From b2df6be531a67723951411b0d843830628ba1ce0 Mon Sep 17 00:00:00 2001
From: Raghavendra Rao Ananta <rananta@quicinc.com>
Date: Fri, 6 Nov 2020 10:34:59 -0800
Subject: [PATCH] ARM: dts: msm: Reorganize the apps_rsc node for Lahaina

Move the 'apps_rsc' node to the beginning of the 'soc'
node such that the rpmh-regulator devices are populated
early in the boot process. As many consumers' probe depend
on these regulator devices, placing 'apps_rsc' at the beginning
would satisfy the consumer devices as soon as they are
populated later in the boot. This way, the drivers no longer
have to wait for the regulator devices to be populated, thus
optimizing the boot performance.

Change-Id: I11f15e625a3383c2936dddab0014a99e940d1c1b
---
 qcom/lahaina.dtsi | 62 +++++++++++++++++++++++------------------------
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 0d190c4bc15a..2612800e8e4c 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -565,6 +565,37 @@
 		method = "smc";
 	};
 
+	apps_rsc: rsc@18200000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x18200000 0x10000>,
+		      <0x18210000 0x10000>,
+		      <0x18220000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0xd00>;
+		qcom,drv-id = <2>;
+		qcom,tcs-config = <ACTIVE_TCS  2>,
+				  <SLEEP_TCS   3>,
+				  <WAKE_TCS    3>,
+				  <CONTROL_TCS 0>;
+
+		apps_bcm_voter: bcm_voter {
+			compatible = "qcom,bcm-voter";
+		};
+
+		system_pm {
+			compatible = "qcom,system-pm";
+		};
+
+		clock_rpmh: qcom,rpmhclk {
+			compatible = "qcom,lahaina-rpmh-clk";
+			#clock-cells = <1>;
+		};
+	};
+
 	slim_aud: slim@3ac0000 {
 		cell-index = <1>;
 		compatible = "qcom,slim-ngd";
@@ -2771,37 +2802,6 @@
 			0x18040060 0x18050060 0x18060060 0x18070060>;
 	};
 
-	apps_rsc: rsc@18200000 {
-		label = "apps_rsc";
-		compatible = "qcom,rpmh-rsc";
-		reg = <0x18200000 0x10000>,
-		      <0x18210000 0x10000>,
-		      <0x18220000 0x10000>;
-		reg-names = "drv-0", "drv-1", "drv-2";
-		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-			    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-		qcom,tcs-offset = <0xd00>;
-		qcom,drv-id = <2>;
-		qcom,tcs-config = <ACTIVE_TCS  2>,
-				  <SLEEP_TCS   3>,
-				  <WAKE_TCS    3>,
-				  <CONTROL_TCS 0>;
-
-		apps_bcm_voter: bcm_voter {
-			compatible = "qcom,bcm-voter";
-		};
-
-		system_pm {
-			compatible = "qcom,system-pm";
-		};
-
-		clock_rpmh: qcom,rpmhclk {
-			compatible = "qcom,lahaina-rpmh-clk";
-			#clock-cells = <1>;
-		};
-	};
-
 	aggre1_noc: interconnect@16e0000 {
 		compatible = "qcom,lahaina-aggre1_noc";
 		reg = <0x016E0000 0x1f180>;