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Merge "msm: kgsl: Print always on counters if HFI timed out"

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qctecmdr 2020-03-22 05:55:57 -07:00 • committed by Gerrit - the friendly Code Review server
commit 20f88c8444
5 changed files with 34 additions and 0 deletions
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6
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -1762,6 +1762,11 @@ static bool a6xx_gmu_scales_bandwidth(struct kgsl_device *device)
return (ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A640);
}
static u64 a6xx_gmu_read_alwayson(struct kgsl_device *device)
{
return a6xx_read_alwayson(ADRENO_DEVICE(device));
}
struct gmu_dev_ops adreno_a6xx_gmudev = {
.load_firmware = a6xx_gmu_load_firmware,
.oob_set = a6xx_gmu_oob_set,
@ -1779,6 +1784,7 @@ struct gmu_dev_ops adreno_a6xx_gmudev = {
.snapshot = a6xx_gmu_snapshot,
.cooperative_reset = a6xx_gmu_cooperative_reset,
.wait_for_active_transition = a6xx_gmu_wait_for_active_transition,
.read_alwayson = a6xx_gmu_read_alwayson,
.gmu2host_intr_mask = HFI_IRQ_MASK,
.gmu_ao_intr_mask = GMU_AO_INT_MASK,
.scales_bandwidth = a6xx_gmu_scales_bandwidth,

6
drivers/gpu/msm/adreno_a6xx_rgmu.c
View file

@ -559,6 +559,11 @@ static void a6xx_rgmu_snapshot(struct kgsl_device *device,
ARRAY_SIZE(a6xx_rgmu_registers) / 2);
}
static u64 a6xx_rgmu_read_alwayson(struct kgsl_device *device)
{
return a6xx_read_alwayson(ADRENO_DEVICE(device));
}
struct gmu_dev_ops adreno_a6xx_rgmudev = {
.load_firmware = a6xx_rgmu_load_firmware,
.oob_set = a6xx_rgmu_oob_set,
@ -573,6 +578,7 @@ struct gmu_dev_ops adreno_a6xx_rgmudev = {
.ifpc_show = a6xx_rgmu_ifpc_show,
.snapshot = a6xx_rgmu_snapshot,
.halt_execution = a6xx_rgmu_halt_execution,
.read_alwayson = a6xx_rgmu_read_alwayson,
.gmu2host_intr_mask = RGMU_OOB_IRQ_MASK,
.gmu_ao_intr_mask = RGMU_AO_IRQ_MASK,
};

10
drivers/gpu/msm/kgsl_gmu_core.c
View file

@ -355,3 +355,13 @@ int gmu_core_dev_wait_for_active_transition(struct kgsl_device *device)
return 0;
}
u64 gmu_core_dev_read_alwayson(struct kgsl_device *device)
{
struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
if (ops && ops->read_alwayson)
return ops->read_alwayson(device);
return 0;
}

2
drivers/gpu/msm/kgsl_gmu_core.h
View file

@ -135,6 +135,7 @@ struct gmu_dev_ops {
void (*halt_execution)(struct kgsl_device *device);
int (*wait_for_active_transition)(struct kgsl_device *device);
bool (*scales_bandwidth)(struct kgsl_device *device);
u64 (*read_alwayson)(struct kgsl_device *device);
const unsigned int gmu2host_intr_mask;
const unsigned int gmu_ao_intr_mask;
};
@ -218,5 +219,6 @@ int gmu_core_dev_ifpc_store(struct kgsl_device *device, unsigned int val);
void gmu_core_dev_prepare_stop(struct kgsl_device *device);
int gmu_core_dev_wait_for_active_transition(struct kgsl_device *device);
void gmu_core_dev_cooperative_reset(struct kgsl_device *device);
u64 gmu_core_dev_read_alwayson(struct kgsl_device *device);
#endif /* __KGSL_GMU_CORE_H */

10
drivers/gpu/msm/kgsl_hfi.c
View file

@ -266,7 +266,12 @@ static int poll_adreno_gmu_reg(struct adreno_device *adreno_dev,
unsigned int mask, unsigned int timeout_ms)
{
unsigned int val;
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct gmu_device *gmu = KGSL_GMU_DEVICE(device);
unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
u64 ao_pre_poll, ao_post_poll;
ao_pre_poll = gmu_core_dev_read_alwayson(device);
while (time_is_after_jiffies(timeout)) {
adreno_read_gmureg(adreno_dev, offset_name, &val);
@ -275,11 +280,16 @@ static int poll_adreno_gmu_reg(struct adreno_device *adreno_dev,
usleep_range(10, 100);
}
ao_post_poll = gmu_core_dev_read_alwayson(device);
/* Check one last time */
adreno_read_gmureg(adreno_dev, offset_name, &val);
if ((val & mask) == expected_val)
return 0;
dev_err(&gmu->pdev->dev, "kgsl hfi poll timeout: always on: %lld ms\n",
div_u64((ao_post_poll - ao_pre_poll) * 52, USEC_PER_SEC));
return -ETIMEDOUT;
}