mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 07:37:31 -04:00
ARM: dts: msm: Add Buses,PCIe,USB and storage devices to SM6150
Add the device tree nodes that describe the PCIe, USB, Buses and storage devices for SM6150 target. Change-Id: Ic77eaa26e00cf577e297064cdca122394e3e0a2f
This commit is contained in:
Nitesh Gupta
parent
0d6f35e3c6
commit
212ccf64f2
12 changed files with 1626 additions and 106 deletions
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@ -27,3 +27,39 @@
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status = "ok"
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};
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&sdhc_1 {
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vdd-supply = <&pm6155_1_l17>;
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qcom,vdd-voltage-level = <2950000 2950000>;
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qcom,vdd-current-level = <0 570000>;
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vdd-io-supply = <&pm6155_1_s4>;
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qcom,vdd-io-always-on;
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qcom,vdd-io-lpm-sup;
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qcom,vdd-io-voltage-level = <1800000 1800000>;
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qcom,vdd-io-current-level = <0 325000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc1_on>;
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pinctrl-1 = <&sdc1_off>;
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status = "ok"
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};
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&sdhc_2 {
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vdd-supply = <&pm6155_1_l10>;
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qcom,vdd-voltage-level = <2950000 2950000>;
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qcom,vdd-current-level = <0 800000>;
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vdd-io-supply = <&pm6155_1_l2>;
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qcom,vdd-io-voltage-level = <1800000 3100000>;
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qcom,vdd-io-current-level = <0 22000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc2_on>;
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pinctrl-1 = <&sdc2_off>;
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cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
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status= "ok"
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};
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@ -1,6 +1,6 @@
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#include <dt-bindings/gpio/gpio.h>
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&qupv3_0 {
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&qupv3_se0_2uart {
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status = "ok"
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};
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@ -27,3 +27,53 @@
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status = "ok"
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};
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&sdhc_1 {
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vdd-supply = <&pm6155_1_l17>;
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qcom,vdd-voltage-level = <2950000 2950000>;
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qcom,vdd-current-level = <0 570000>;
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vdd-io-supply = <&pm6155_1_s4>;
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qcom,vdd-io-always-on;
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qcom,vdd-io-lpm-sup;
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qcom,vdd-io-voltage-level = <1800000 1800000>;
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qcom,vdd-io-current-level = <0 325000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc1_on>;
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pinctrl-1 = <&sdc1_off>;
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status = "ok"
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};
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&sdhc_2 {
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vdd-supply = <&pm6155_1_l10>;
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qcom,vdd-voltage-level = <2950000 2950000>;
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qcom,vdd-current-level = <0 800000>;
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vdd-io-supply = <&pm6155_1_l2>;
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qcom,vdd-io-voltage-level = <1800000 3100000>;
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qcom,vdd-io-current-level = <0 22000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc2_on>;
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pinctrl-1 = <&sdc2_off>;
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cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
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status = "ok"
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};
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&qusb_phy0 {
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qcom,usb-hs-ac-bitmask = <0x30>;
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qcom,usb-hs-ac-value = <0x10>;
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pinctrl-names = "default";
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pinctrl-0 = <&usb0_hs_ac_en_default>;
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};
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&qusb_phy1 {
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qcom,usb-hs-ac-bitmask = <0xc0>;
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qcom,usb-hs-ac-value = <0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&usb1_hs_ac_en_default>;
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};
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248
qcom/sa6155-pcie.dtsi
Normal file
248
qcom/sa6155-pcie.dtsi
Normal file
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@ -0,0 +1,248 @@
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#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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&soc {
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pcie0: qcom,pcie@1c08000 {
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compatible = "qcom,pci-msm";
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cell-index = <0>;
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reg = <0x1c08000 0x4000>,
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<0x1c0e000 0x1000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>,
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<0x40200000 0x100000>,
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<0x40300000 0x1fd00000>;
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reg-names = "parf", "phy", "dm_core", "elbi",
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"iatu", "conf", "io", "bars";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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qcom,phy-sequence = <0x0800 0x01 0x0
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0x0804 0x03 0x0
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0x0034 0x18 0x0
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0x0038 0x10 0x0
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0x0070 0x0f 0x0
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0x00c8 0x01 0x0
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0x0128 0x00 0x0
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0x0144 0xff 0x0
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0x0148 0x1f 0x0
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0x0194 0x06 0x0
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0x0048 0x0f 0x0
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0x0178 0x00 0x0
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0x019c 0x01 0x0
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0x018c 0x20 0x0
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0x0184 0x0a 0x0
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0x00b4 0x20 0x0
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0x000c 0x09 0x0
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0x00ac 0x04 0x0
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0x00d0 0x82 0x0
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0x00e4 0x03 0x0
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0x00e0 0x55 0x0
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0x00dc 0x55 0x0
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0x0054 0x00 0x0
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0x0050 0x0d 0x0
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0x004c 0x04 0x0
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0x0174 0x35 0x0
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0x003c 0x02 0x0
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0x0040 0x1f 0x0
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0x0078 0x04 0x0
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0x0084 0x16 0x0
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0x0090 0x30 0x0
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0x010c 0x00 0x0
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0x0108 0x80 0x0
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0x00a8 0x01 0x0
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0x000c 0x0a 0x0
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0x0010 0x01 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0014 0x02 0x0
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0x0018 0x00 0x0
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0x0024 0x2f 0x0
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0x0028 0x19 0x0
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0x0268 0x45 0x0
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0x0194 0x06 0x0
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0x024c 0x02 0x0
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0x02ac 0x12 0x0
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0x0510 0x1c 0x0
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0x051c 0x14 0x0
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0x04d8 0x01 0x0
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0x04dc 0x00 0x0
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0x04e0 0xdb 0x0
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0x0448 0x4b 0x0
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0x041c 0x04 0x0
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0x0410 0x04 0x0
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0x0074 0x19 0x0
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0x0854 0x04 0x0
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0x09ac 0x00 0x0
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0x08a0 0x40 0x0
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0x09e0 0x00 0x0
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0x09dc 0x40 0x0
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0x09a8 0x00 0x0
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0x08a4 0x40 0x0
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0x08a8 0x73 0x0
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0x09b0 0x07 0x0
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0x09d8 0x99 0x0
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0x0824 0x15 0x0
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0x0828 0x0e 0x0
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0x0800 0x00 0x0
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0x0808 0x03 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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perst-gpio = <&tlmm 101 0>;
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wake-gpio = <&tlmm 100 0>;
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gdsc-vdd-supply = <&pcie_0_gdsc>;
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vreg-1p8-supply = <&L12A>;
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vreg-0p9-supply = <&L5A>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1800000 1800000 24000>;
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qcom,vreg-0p9-voltage-level = <925000 925000 24000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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dma-coherent;
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qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
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RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
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RPMH_REGULATOR_LEVEL_NOM 100000000>;
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interconnect-names = "icc_path";
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interconnects = <&aggre1_noc MASTER_PCIE &mc_virt SLAVE_EBI1>;
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msi-parent = <&pcie0_msi>;
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qcom,no-l0s-supported;
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qcom,no-l1-supported;
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qcom,no-l1ss-supported;
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qcom,no-aux-clk-sync;
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qcom,max-link-speed = <0x2>;
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qcom,ep-latency = <10>;
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qcom,slv-addr-space-size = <0x20000000>;
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qcom,phy-status-offset = <0x974>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x804>;
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qcom,core-preset = <0x77777777>;
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qcom,boot-option = <0x0>;
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linux,pci-domain = <0>;
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qcom,pcie-phy-ver = <2609>;
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qcom,use-19p2mhz-aux-clk;
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qcom,smmu-sid-base = <0x0400>;
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iommu-map = <0x0 &apps_smmu 0x0400 0x1>,
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<0x100 &apps_smmu 0x0401 0x1>,
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<0x200 &apps_smmu 0x0402 0x1>,
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<0x300 &apps_smmu 0x0403 0x1>,
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<0x400 &apps_smmu 0x0404 0x1>,
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<0x500 &apps_smmu 0x0405 0x1>,
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<0x600 &apps_smmu 0x0406 0x1>,
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<0x700 &apps_smmu 0x0407 0x1>,
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<0x800 &apps_smmu 0x0408 0x1>,
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<0x900 &apps_smmu 0x0409 0x1>,
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<0xa00 &apps_smmu 0x040a 0x1>,
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<0xb00 &apps_smmu 0x040b 0x1>,
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<0xc00 &apps_smmu 0x040c 0x1>,
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<0xd00 &apps_smmu 0x040d 0x1>,
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<0xe00 &apps_smmu 0x040e 0x1>,
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<0xf00 &apps_smmu 0x040f 0x1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_PHY_AUX_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_phy_refgen_clk", "pcie_phy_aux_clk";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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pcie_rc0: pcie_rc0 {
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#address-cells = <5>;
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#size-cells = <0>;
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reg = <0 0 0 0 0>;
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pci-ids = "17cb:010a";
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};
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};
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pcie0_msi: qcom,pcie0_msi@17a00040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17a00040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 672 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 673 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 674 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 675 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 676 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 683 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 684 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 685 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 686 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 687 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 689 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 690 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 691 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 692 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 693 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 694 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 695 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 696 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 697 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 698 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 701 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 703 IRQ_TYPE_EDGE_RISING>;
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};
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};
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@ -6,6 +6,27 @@
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compatible = "qcom,sa6155";
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qcom,msm-name = "SA6155";
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qcom,msm-id = <384 0x10000>;
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aliases {
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pci-domain0 = &pcie0; /* PCIe0 domain */
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};
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};
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&qusb_phy0 {
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vdd-supply = <&L5A>;
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vdda18-supply = <&L12A>;
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vdda33-supply = <&L13A>;
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};
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&usb_qmp_phy {
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vdd-supply = <&L5A>;
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core-supply = <&L12A>;
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};
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&qusb_phy1 {
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vdd-supply = <&L5A>;
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vdda18-supply = <&L12A>;
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vdda33-supply = <&L13A>;
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};
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&gcc {
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@ -36,6 +57,7 @@
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compatible = "qcom,sa6155-videocc", "syscon";
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};
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#include "sa6155-pcie.dtsi"
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&slpi_tlmm {
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status = "ok"
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};
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@ -5,6 +5,10 @@
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model = "Qualcomm Technologies, Inc. SA6155P";
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qcom,msm-name = "SA6155P";
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qcom,msm-id = <377 0>, <380 0>;
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aliases {
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pci-domain0 = &pcie0; /* PCIe0 domain */
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};
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};
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/* Delete second instance of pm6155 definitions for APQ version */
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@ -26,6 +30,23 @@
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/delete-node/ bt_wcn3990;
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};
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&qusb_phy0 {
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||||
vdd-supply = <&L5A>;
|
||||
vdda18-supply = <&L12A>;
|
||||
vdda33-supply = <&L13A>;
|
||||
};
|
||||
|
||||
&usb_qmp_phy {
|
||||
vdd-supply = <&L5A>;
|
||||
core-supply = <&L12A>;
|
||||
};
|
||||
|
||||
&qusb_phy1 {
|
||||
vdd-supply = <&L5A>;
|
||||
vdda18-supply = <&L12A>;
|
||||
vdda33-supply = <&L13A>;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
compatible = "qcom,sa6155-gcc", "syscon";
|
||||
/delete-property/ protected-clocks;
|
||||
|
|
@ -54,6 +75,7 @@
|
|||
compatible = "qcom,sa6155-videocc", "syscon";
|
||||
};
|
||||
|
||||
#include "sa6155-pcie.dtsi"
|
||||
&slpi_tlmm {
|
||||
status = "ok"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -842,143 +842,105 @@
|
|||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* SDC pin type */
|
||||
sdc1_clk_on: sdc1_clk_on {
|
||||
config {
|
||||
sdc1_on: sdc1_on {
|
||||
clk {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable; /* NO pull */
|
||||
drive-strength = <16>; /* 16 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_clk_off: sdc1_clk_off {
|
||||
config {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable; /* NO pull */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_cmd_on: sdc1_cmd_on {
|
||||
config {
|
||||
pins = "sdc1_cmd";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_cmd_off: sdc1_cmd_off {
|
||||
config {
|
||||
pins = "sdc1_cmd";
|
||||
num-grp-pins = <1>;
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_data_on: sdc1_data_on {
|
||||
config {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_data_off: sdc1_data_off {
|
||||
config {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_rclk_on: sdc1_rclk_on {
|
||||
config {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down; /* pull down */
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_rclk_off: sdc1_rclk_off {
|
||||
config {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down; /* pull down */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_clk_on: sdc2_clk_on {
|
||||
config {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable; /* NO pull */
|
||||
drive-strength = <16>; /* 16 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_clk_off: sdc2_clk_off {
|
||||
config {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable; /* NO pull */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cmd_on: sdc2_cmd_on {
|
||||
config {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cmd_off: sdc2_cmd_off {
|
||||
config {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_data_on: sdc2_data_on {
|
||||
config {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_data_off: sdc2_data_off {
|
||||
config {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cd_on: cd_on {
|
||||
mux {
|
||||
pins = "gpio99";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio99";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cd_off: cd_off {
|
||||
mux {
|
||||
pins = "gpio99";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio99";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc1_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
rclk {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_off: sdc1_off {
|
||||
clk {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc1_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
rclk {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_on: sdc2_on {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable; /* NO pull */
|
||||
drive-strength = <16>; /* 16 MA */
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
|
||||
sd-cd {
|
||||
pins = "gpio99";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_off: sdc2_off {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable; /* NO pull */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
|
||||
sd-cd {
|
||||
pins = "gpio99";
|
||||
bias-disable; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,18 +1,285 @@
|
|||
#include <dt-bindings/interconnect/qcom,sm6150.h>
|
||||
|
||||
&soc {
|
||||
qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x008c0000 0x6000>;
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
/*
|
||||
* QUPv3 North & South Instances
|
||||
* North 0 : SE 4
|
||||
* North 1 : SE 5
|
||||
* North 2 : SE 6
|
||||
* North 3 : SE 7
|
||||
* South 0 : SE 0
|
||||
* South 1 : SE 1
|
||||
* South 2 : SE 2
|
||||
* South 3 : SE 3
|
||||
*/
|
||||
|
||||
qupv3_se0_2uart: qcom,qup_uart@0x880000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0x0 0x00880000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "ok"
|
||||
};
|
||||
/* QUPv3 South Instances */
|
||||
qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0x8c0000 0x6000>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-bus-ids =
|
||||
<MASTER_QUP_0 SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0xc3 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
/* Debug UART Instance for CDP/MTP platform */
|
||||
qupv3_se0_2uart: qcom,qup_uart@0x880000 {
|
||||
compatible = "qcom,msm-geni-console";
|
||||
reg = <0x880000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_2uart_active>;
|
||||
pinctrl-1 = <&qupv3_se0_2uart_sleep>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I2C */
|
||||
qupv3_se1_i2c: i2c@884000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x884000 0x4000>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_i2c: i2c@888000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x888000 0x4000>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se3_i2c: i2c@88c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x88c000 0x4000>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SPI */
|
||||
qupv3_se2_spi: spi@888000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x888000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se2_spi_sleep>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* QUPv3 North instances */
|
||||
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0xac0000 0x6000>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-bus-ids =
|
||||
<MASTER_BLSP_1 SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0x363 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
|
||||
/* I2C */
|
||||
qupv3_se4_i2c: i2c@a80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_i2c: i2c@a84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_i2c: i2c@a88000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa88000 0x4000>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se7_i2c: i2c@a8c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SPI */
|
||||
qupv3_se4_spi: spi@a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa80000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se4_spi_sleep>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_spi: spi@a88000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa88000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se7_spi: spi@a8c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa8c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se7_spi_sleep>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* HS UART instances. HS UART usecases can be supported on these
|
||||
* instances only.
|
||||
*/
|
||||
qupv3_se7_4uart: qcom,qup_uart@0xa8c000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>,
|
||||
<&qupv3_se7_tx>;
|
||||
pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>,
|
||||
<&qupv3_se7_tx>;
|
||||
interrupts-extended = <&intc GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 13 0>;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,5 +7,237 @@
|
|||
clock-names = "ssc-clk";
|
||||
clocks = <&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
status = "disabled";
|
||||
|
||||
qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
|
||||
qupv3_se8_i2c_active: qupv3_se8_i2c_active {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "func1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
|
||||
qupv3_se9_i2c_active: qupv3_se9_i2c_active {
|
||||
mux {
|
||||
pins = "gpio2", "gpio3";
|
||||
function = "func1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio2", "gpio3";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio2", "gpio3";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
|
||||
qupv3_se10_i2c_active: qupv3_se10_i2c_active {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "func1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio8", "gpio9";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio8", "gpio9";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
|
||||
qupv3_se11_i2c_active: qupv3_se11_i2c_active {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "func3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio16", "gpio17";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio16", "gpio17";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
|
||||
qupv3_se12_i2c_active: qupv3_se12_i2c_active {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "func2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio16", "gpio17";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio16", "gpio17";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
|
||||
qupv3_se13_i2c_active: qupv3_se13_i2c_active {
|
||||
mux {
|
||||
pins = "gpio14", "gpio15";
|
||||
function = "func2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio14", "gpio15";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio14", "gpio15";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio14", "gpio15";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_spi_pins: qupv3_se9_spi_pins {
|
||||
qupv3_se9_spi_active: qupv3_se9_spi_active {
|
||||
mux {
|
||||
pins = "gpio2", "gpio3", "gpio4",
|
||||
"gpio5";
|
||||
function = "func1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio2", "gpio3", "gpio4",
|
||||
"gpio5";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio2", "gpio3", "gpio4",
|
||||
"gpio5";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio2", "gpio3", "gpio4",
|
||||
"gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se10_spi_pins: qupv3_se10_spi_pins {
|
||||
qupv3_se10_spi_active: qupv3_se10_spi_active {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9", "gpio10",
|
||||
"gpio11";
|
||||
function = "func1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio8", "gpio9", "gpio10",
|
||||
"gpio11";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9", "gpio10",
|
||||
"gpio11";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio8", "gpio9", "gpio10",
|
||||
"gpio11";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
164
qcom/sm6150-ssc-qupv3.dtsi
Normal file
164
qcom/sm6150-ssc-qupv3.dtsi
Normal file
|
|
@ -0,0 +1,164 @@
|
|||
#include <dt-bindings/interconnect/qcom,sm6150.h>
|
||||
|
||||
&soc {
|
||||
|
||||
/* QUPv3 SSC Instances */
|
||||
qupv3_2: qcom,qupv3_2_geni_se@626c0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0x626c0000 0x6000>;
|
||||
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-bus-ids =
|
||||
<MASTER_LPASS_ANOC SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0x1783 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
/* I2C */
|
||||
qupv3_se8_i2c: i2c@62680000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x62680000 0x4000>;
|
||||
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE0_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_i2c: i2c@62684000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x62684000 0x4000>;
|
||||
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE1_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se10_i2c: i2c@62688000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x62688000 0x4000>;
|
||||
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE2_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se10_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se11_i2c: i2c@6268c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x6268c000 0x4000>;
|
||||
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE3_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se11_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se12_i2c: i2c@62690000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x62690000 0x4000>;
|
||||
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE4_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se12_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se13_i2c: i2c@62694000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x62694000 0x4000>;
|
||||
interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE5_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se13_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se13_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SPI */
|
||||
qupv3_se9_spi: spi@62684000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x62684000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE1_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
qcom,disable-dma;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se10_spi: spi@62688000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x62688000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE2_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se10_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se10_spi_sleep>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
qcom,disable-dma;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
390
qcom/sm6150-usb.dtsi
Normal file
390
qcom/sm6150-usb.dtsi
Normal file
|
|
@ -0,0 +1,390 @@
|
|||
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
|
||||
#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
|
||||
|
||||
&soc {
|
||||
/* Primary USB port related controller */
|
||||
usb0: ssusb@a600000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0xa600000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
iommus = <&apps_smmu 0x140 0x0>;
|
||||
qcom,iommu-dma = "atomic";
|
||||
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||||
"ss_phy_irq", "dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
|
||||
USB3_GDSC-supply = <&usb30_prim_gdsc>;
|
||||
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"xo", "sleep_clk", "utmi_clk";
|
||||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
|
||||
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
interconnect-names = "usb-ddr", "ddr-usb";
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>;
|
||||
|
||||
dwc3@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0xa600000 0xcd00>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&qusb_phy0>, <&usb_qmp_phy>;
|
||||
tx-fifo-resize;
|
||||
linux,sysdev_is_parent;
|
||||
snps,disable-clk-gating;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x0>;
|
||||
snps,is-utmi-l1-suspend;
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
qcom,usbbam@a704000 {
|
||||
compatible = "qcom,usb-bam-msm";
|
||||
reg = <0xa704000 0x17000>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
|
||||
qcom,usb-bam-num-pipes = <4>;
|
||||
qcom,disable-clk-gating;
|
||||
qcom,usb-bam-override-threshold = <0x4001>;
|
||||
qcom,usb-bam-max-mbps-highspeed = <400>;
|
||||
qcom,usb-bam-max-mbps-superspeed = <3600>;
|
||||
qcom,reset-bam-on-connect;
|
||||
|
||||
qcom,pipe0 {
|
||||
label = "ssusb-qdss-in-0";
|
||||
qcom,usb-bam-mem-type = <2>;
|
||||
qcom,dir = <1>;
|
||||
qcom,pipe-num = <0>;
|
||||
qcom,peer-bam = <0>;
|
||||
qcom,peer-bam-physical-address = <0x6064000>;
|
||||
qcom,src-bam-pipe-index = <0>;
|
||||
qcom,dst-bam-pipe-index = <0>;
|
||||
qcom,data-fifo-offset = <0x0>;
|
||||
qcom,data-fifo-size = <0x1800>;
|
||||
qcom,descriptor-fifo-offset = <0x1800>;
|
||||
qcom,descriptor-fifo-size = <0x800>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Primary USB port related High Speed PHY */
|
||||
qusb_phy0: qusb@88e2000 {
|
||||
compatible = "qcom,qusb2phy";
|
||||
reg = <0x88e2000 0x180>,
|
||||
<0x007801f8 0x4>,
|
||||
<0x01fcb3e4 0x4>;
|
||||
reg-names = "qusb_phy_base",
|
||||
"tune2_efuse_addr",
|
||||
"tcsr_conn_box_spare_0";
|
||||
|
||||
vdd-supply = <&pm6150_l4>;
|
||||
vdda18-supply = <&pm6150_l11>;
|
||||
vdda33-supply = <&pm6150_l17>;
|
||||
qcom,vdd-voltage-level = <0 925000 975000>;
|
||||
qcom,tune2-efuse-bit-pos = <25>;
|
||||
qcom,tune2-efuse-num-bits = <4>;
|
||||
qcom,qusb-phy-init-seq = <0xc8 0x80
|
||||
0xb3 0x84
|
||||
0x83 0x88
|
||||
0xc0 0x8c
|
||||
0x30 0x08
|
||||
0x79 0x0c
|
||||
0x21 0x10
|
||||
0x14 0x9c
|
||||
0x9f 0x1c
|
||||
0x00 0x18>;
|
||||
phy_type = "utmi";
|
||||
qcom,phy-clk-scheme = "cml";
|
||||
qcom,major-rev = <1>;
|
||||
|
||||
/* USB2PHY gets clock directly from CXO pad
|
||||
* connected to differential pin cxo_core_in_1p8_vdda.
|
||||
*/
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_AHB2PHY_WEST_CLK>;
|
||||
clock-names = "ref_clk_src", "cfg_ahb_clk";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
};
|
||||
|
||||
/* Primary USB port related QMP USB PHY */
|
||||
usb_qmp_phy: ssphy@88e6000 {
|
||||
compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
|
||||
reg = <0x88e6000 0x1000>,
|
||||
<0x01fcb244 0x4>;
|
||||
reg-names = "qmp_phy_base",
|
||||
"vls_clamp_reg";
|
||||
|
||||
vdd-supply = <&pm6150_l4>;
|
||||
core-supply = <&pm6150_l11>;
|
||||
qcom,vdd-voltage-level = <0 925000 975000>;
|
||||
qcom,core-voltage-level = <0 1800000 1800000>;
|
||||
qcom,qmp-phy-init-seq =
|
||||
/* <reg_offset, value, delay> */
|
||||
<0xac 0x14 0x00
|
||||
0x34 0x08 0x00
|
||||
0x174 0x30 0x00
|
||||
0x3c 0x06 0x00
|
||||
0xb4 0x00 0x00
|
||||
0xb8 0x08 0x00
|
||||
0x70 0x0f 0x00
|
||||
0x19c 0x01 0x00
|
||||
0x178 0x00 0x00
|
||||
0xd0 0x82 0x00
|
||||
0xdc 0x55 0x00
|
||||
0xe0 0x55 0x00
|
||||
0xe4 0x03 0x00
|
||||
0x78 0x0b 0x00
|
||||
0x84 0x16 0x00
|
||||
0x90 0x28 0x00
|
||||
0x108 0x80 0x00
|
||||
0x10c 0x00 0x00
|
||||
0x184 0x0a 0x00
|
||||
0x4c 0x15 0x00
|
||||
0x50 0x34 0x00
|
||||
0x54 0x00 0x00
|
||||
0xc8 0x00 0x00
|
||||
0x18c 0x00 0x00
|
||||
0xcc 0x00 0x00
|
||||
0x128 0x00 0x00
|
||||
0x0c 0x0a 0x00
|
||||
0x10 0x01 0x00
|
||||
0x1c 0x31 0x00
|
||||
0x20 0x01 0x00
|
||||
0x14 0x00 0x00
|
||||
0x18 0x00 0x00
|
||||
0x24 0xde 0x00
|
||||
0x28 0x07 0x00
|
||||
0x48 0x0f 0x00
|
||||
0x194 0x06 0x00
|
||||
0x100 0x80 0x00
|
||||
0xa8 0x01 0x00
|
||||
0x430 0x0b 0x00
|
||||
0x830 0x0b 0x00
|
||||
0x444 0x00 0x00
|
||||
0x844 0x00 0x00
|
||||
0x43c 0x00 0x00
|
||||
0x83c 0x00 0x00
|
||||
0x440 0x00 0x00
|
||||
0x840 0x00 0x00
|
||||
0x408 0x0a 0x00
|
||||
0x808 0x0a 0x00
|
||||
0x414 0x06 0x00
|
||||
0x814 0x06 0x00
|
||||
0x434 0x75 0x00
|
||||
0x834 0x75 0x00
|
||||
0x4d4 0x02 0x00
|
||||
0x8d4 0x02 0x00
|
||||
0x4d8 0x4e 0x00
|
||||
0x8d8 0x4e 0x00
|
||||
0x4dc 0x18 0x00
|
||||
0x8dc 0x18 0x00
|
||||
0x4f8 0x77 0x00
|
||||
0x8f8 0x77 0x00
|
||||
0x4fc 0x80 0x00
|
||||
0x8fc 0x80 0x00
|
||||
0x4c0 0x0a 0x00
|
||||
0x8c0 0x0a 0x00
|
||||
0x504 0x03 0x00
|
||||
0x904 0x03 0x00
|
||||
0x50c 0x16 0x00
|
||||
0x90c 0x16 0x00
|
||||
0x500 0x00 0x00
|
||||
0x900 0x00 0x00
|
||||
0x564 0x00 0x00
|
||||
0x964 0x00 0x00
|
||||
0x260 0x10 0x00
|
||||
0x660 0x10 0x00
|
||||
0x2a4 0x12 0x00
|
||||
0x6a4 0x12 0x00
|
||||
0x28c 0xc6 0x00
|
||||
0x68c 0xc6 0x00
|
||||
0x244 0x00 0x00
|
||||
0x644 0x00 0x00
|
||||
0x248 0x00 0x00
|
||||
0x648 0x00 0x00
|
||||
0xc0c 0x9f 0x00
|
||||
0xc24 0x17 0x00
|
||||
0xc28 0x0f 0x00
|
||||
0xcc8 0x83 0x00
|
||||
0xcc4 0x02 0x00
|
||||
0xccc 0x09 0x00
|
||||
0xcd0 0xa2 0x00
|
||||
0xcd4 0x85 0x00
|
||||
0xc80 0xd1 0x00
|
||||
0xc84 0x1f 0x00
|
||||
0xc88 0x47 0x00
|
||||
0xcb8 0x75 0x00
|
||||
0xcbc 0x13 0x00
|
||||
0xcb0 0x86 0x00
|
||||
0xca0 0x04 0x00
|
||||
0xc8c 0x44 0x00
|
||||
0xc70 0xe7 0x00
|
||||
0xc74 0x03 0x00
|
||||
0xc78 0x40 0x00
|
||||
0xc7c 0x00 0x00
|
||||
0xdd8 0x88 0x00
|
||||
0xffffffff 0xffffffff 0x00>;
|
||||
|
||||
qcom,qmp-phy-reg-offset =
|
||||
<0xd74 /* USB3_PHY_PCS_STATUS */
|
||||
0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
|
||||
0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
|
||||
0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
|
||||
0xc00 /* USB3_PHY_SW_RESET */
|
||||
0xc08 /* USB3_PHY_START */
|
||||
0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
|
||||
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_AHB2PHY_WEST_CLK>;
|
||||
|
||||
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
||||
"ref_clk", "com_aux_clk", "cfg_ahb_clk";
|
||||
|
||||
resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
|
||||
<&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
|
||||
reset-names = "phy_reset", "phy_phy_reset";
|
||||
};
|
||||
|
||||
usb_nop_phy: usb_nop_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
/* Secondary USB port related controller */
|
||||
usb1: hsusb@a800000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0xa800000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
iommus = <&apps_smmu 0xE0 0x0>;
|
||||
qcom,iommu-dma = "atomic";
|
||||
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||||
"dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
|
||||
qcom,default-mode-host;
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
USB3_GDSC-supply = <&usb20_sec_gdsc>;
|
||||
clocks = <&gcc GCC_USB20_SEC_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
||||
<&gcc GCC_USB20_SEC_SLEEP_CLK>,
|
||||
<&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"xo", "sleep_clk", "utmi_clk";
|
||||
|
||||
resets = <&gcc GCC_USB20_SEC_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <120000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
|
||||
|
||||
interconnect-names = "usb-ddr", "ddr-usb";
|
||||
interconnects = <&aggre1_noc MASTER_USB2 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB2>;
|
||||
|
||||
dwc3@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0xa800000 0xcd00>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&qusb_phy1>, <&usb_nop_phy>;
|
||||
linux,sysdev_is_parent;
|
||||
snps,disable-clk-gating;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x0>;
|
||||
snps,is-utmi-l1-suspend;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
|
||||
/* Secondary USB port related High Speed PHY */
|
||||
qusb_phy1: qusb@88e3000 {
|
||||
compatible = "qcom,qusb2phy";
|
||||
reg = <0x88e3000 0x180>,
|
||||
<0x01fcb3e4 0x4>;
|
||||
reg-names = "qusb_phy_base",
|
||||
"tcsr_conn_box_spare_0";
|
||||
|
||||
vdd-supply = <&pm6150_l4>;
|
||||
vdda18-supply = <&pm6150_l11>;
|
||||
vdda33-supply = <&pm6150_l17>;
|
||||
qcom,vdd-voltage-level = <0 925000 975000>;
|
||||
qcom,qusb-phy-init-seq = <0xc8 0x80
|
||||
0xb3 0x84
|
||||
0x83 0x88
|
||||
0xc0 0x8c
|
||||
0x30 0x08
|
||||
0x79 0x0c
|
||||
0x21 0x10
|
||||
0x14 0x9c
|
||||
0x9f 0x1c
|
||||
0x00 0x18>;
|
||||
phy_type = "utmi";
|
||||
qcom,phy-clk-scheme = "cml";
|
||||
qcom,major-rev = <1>;
|
||||
|
||||
/* USB2PHY gets clock directly from CXO pad
|
||||
* connected to differential pin cxo_core_in_1p8_vdda.
|
||||
*/
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_AHB2PHY_WEST_CLK>;
|
||||
clock-names = "ref_clk_src", "cfg_ahb_clk";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
};
|
||||
|
||||
};
|
||||
127
qcom/sm6150.dtsi
127
qcom/sm6150.dtsi
|
|
@ -28,6 +28,8 @@
|
|||
aliases {
|
||||
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
|
||||
serial0 = &qupv3_se0_2uart;
|
||||
sdhc1 = &sdhc_1;
|
||||
sdhc2 = &sdhc_2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -1720,9 +1722,133 @@
|
|||
hyplog-size-offset = <0x414>;
|
||||
};
|
||||
|
||||
sdhc_1: sdhci@7c4000 {
|
||||
compatible = "qcom,sdhci-msm-v5";
|
||||
reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>;
|
||||
reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
|
||||
|
||||
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
||||
<&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
||||
clock-names = "iface", "core", "ice_core";
|
||||
|
||||
qcom,ice-clk-rates = <300000000 75000000>;
|
||||
|
||||
qcom,devfreq,freq-table = <50000000 200000000>;
|
||||
|
||||
bus-width = <8>;
|
||||
qcom,restore-after-cx-collapse;
|
||||
supports-cqe;
|
||||
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
non-removable;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_1>;
|
||||
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
||||
|
||||
qcom,msm-bus,name = "sdhc1";
|
||||
qcom,msm-bus,num-cases = <6>;
|
||||
qcom,msm-bus,num-paths = <2>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
/* No vote */
|
||||
<0 0>, <0 0>,
|
||||
/* 50 MB/s */
|
||||
<130718 200000>,<133320 133320>,
|
||||
/* 100 MB/s */
|
||||
<130718 200000>,<150000 150000>,
|
||||
/* 200 MB/s */
|
||||
<261438 400000>,<300000 300000>,
|
||||
/* 400 MB/s */
|
||||
<261438 2718822>,<300000 1359411>,
|
||||
/* Max. bandwidth */
|
||||
<1338562 4096000>,<1338562 4096000>;
|
||||
qcom,bus-bw-vectors-bps = <0 50000000 100750000
|
||||
200000000 400000000 4294967295>;
|
||||
|
||||
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
||||
qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
qos0 {
|
||||
mask = <0x3f>;
|
||||
vote = <67>;
|
||||
};
|
||||
|
||||
qos1 {
|
||||
mask = <0xc0>;
|
||||
vote = <67>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc_2: sdhci@8804000 {
|
||||
compatible = "qcom,sdhci-msm-v5";
|
||||
reg = <0x8804000 0x1000>;
|
||||
reg-names = "hc_mem";
|
||||
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
||||
<&gcc GCC_SDCC2_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
|
||||
bus-width = <4>;
|
||||
qcom,restore-after-cx-collapse;
|
||||
|
||||
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
||||
qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>;
|
||||
|
||||
qcom,devfreq,freq-table = <50000000 202000000>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
|
||||
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
||||
|
||||
qcom,msm-bus,name = "sdhc2";
|
||||
qcom,msm-bus,num-cases = <6>;
|
||||
qcom,msm-bus,num-paths = <2>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
/* No vote */
|
||||
<0 0>, <0 0>,
|
||||
/* 25 MB/s */
|
||||
<65360 100000>,<100000 100000>,
|
||||
/* 50 MB/s */
|
||||
<130718 200000>,<133320 133320>,
|
||||
/* 100 MB/s */
|
||||
<261438 200000>,<150000 150000>,
|
||||
/* 200 MB/s */
|
||||
<261438 400000>,<300000 300000>,
|
||||
/* Max. bandwidth */
|
||||
<1338562 4096000>,<1338562 4096000>;
|
||||
qcom,bus-bw-vectors-bps = <0 25000000 50000000
|
||||
100750000 200000000 4294967295>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
qos0 {
|
||||
mask = <0x3f>;
|
||||
vote = <67>;
|
||||
};
|
||||
|
||||
qos1 {
|
||||
mask = <0xc0>;
|
||||
vote = <67>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "sm6150-qupv3.dtsi"
|
||||
#include "sm6150-ssc-qupv3.dtsi"
|
||||
#include "sm6150-pinctrl.dtsi"
|
||||
#include "sm6150-pm.dtsi"
|
||||
#include "sm6150-regulator.dtsi"
|
||||
|
|
@ -1826,3 +1952,4 @@
|
|||
|
||||
#include "msm-arm-smmu-sm6150.dtsi"
|
||||
#include "sm6150-slpi-pinctrl.dtsi"
|
||||
#include "sm6150-usb.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in a new issue