From 21b70e44d7168a0f827d208559d7dee5aa1f1abe Mon Sep 17 00:00:00 2001 From: Nilesh Laad Date: Fri, 27 Jan 2023 09:17:20 +0530 Subject: [PATCH] disp: msm: dp: update pll and catalog sequence Update eDP pll and catalog sequence. Change-Id: Ic7643cdd9d68e28ea7999ebc9d2c1e87aaa8c9d6 Signed-off-by: Nilesh Laad --- msm/dp/dp_catalog_v500.c | 58 +++++++++++++++--------------------- msm/dp/edp_pll_7nm.c | 63 ++++++++++++++++++++++------------------ 2 files changed, 58 insertions(+), 63 deletions(-) diff --git a/msm/dp/dp_catalog_v500.c b/msm/dp/dp_catalog_v500.c index 217c4b7f9f1b..507c5bc31f48 100644 --- a/msm/dp/dp_catalog_v500.c +++ b/msm/dp/dp_catalog_v500.c @@ -40,15 +40,6 @@ enum { TX_DRIVE_MODE_MAX, }; -static u8 const ldo_config[TX_DRIVE_MODE_MAX] = { - 0x81, /* 600mV */ - 0x00, /* off */ - 0x41, /* 650mV */ - 0x00, /* off */ - 0x00, /* off */ - 0x00, /* off */ -}; - static u8 const vm_pre_emphasis [TX_DRIVE_MODE_MAX][MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = { /* pe0, 0 db; pe1, 2.0 db; pe2, 3.6 db; pe3, 6.0 db */ @@ -119,16 +110,16 @@ static u8 const vm_voltage_swing {0x17, 0xFF, 0xFF, 0xFF} /* sw1, 0.45 v */ }, { // DP-only, DP/USB - {0x27, 0x2F, 0x36, 0xFF}, /* sw0, 0.4v */ - {0x31, 0x3E, 0x3F, 0xFF}, /* sw1, 0.6v */ - {0x3A, 0x3F, 0xFF, 0xFF}, /* sw2, 0.8v */ - {0xFF, 0xFF, 0xFF, 0xFF} /* sw3, 1.2 v, optional */ + {0x02, 0x12, 0x16, 0x1A}, /* sw0, 0.4v */ + {0x09, 0x19, 0x1F, 0xFF}, /* sw1, 0.6v */ + {0x10, 0x1F, 0xFF, 0xFF}, /* sw2, 0.8v */ + {0x1F, 0xFF, 0xFF, 0xFF} /* sw3, 1.2 v, optional */ }, { // MiniDP-only - {0x09, 0x17, 0x1F, 0xFF}, /* sw0, 0.4v */ - {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6v */ - {0x1C, 0x1F, 0xFF, 0xFF}, /* sw2, 0.8v */ - {0xFF, 0xFF, 0xFF, 0xFF} /* sw3, 1.2 v, optional */ + {0x07, 0x0F, 0x16, 0x1F}, /* sw0, 0.4v */ + {0x11, 0x1E, 0x1F, 0xFF}, /* sw1, 0.6v */ + {0x16, 0x1F, 0xFF, 0xFF}, /* sw2, 0.8v */ + {0x1F, 0xFF, 0xFF, 0xFF} /* sw3, 1.2 v, optional */ }, }; @@ -162,12 +153,8 @@ static void dp_catalog_aux_setup_v500(struct dp_catalog_aux *aux, revision_id = (dp_read(DP_PHY_REVISION_ID3) & 0xFF) << 8; revision_id |= (dp_read(DP_PHY_REVISION_ID2) & 0xFF); DP_DEBUG("DP phy revision_id: 0x%X\n", revision_id); - if (revision_id > 0x5000) - dp_write(DP_PHY_MODE_V500, 0xfc); - else - dp_write(DP_PHY_MODE, 0xfc); - dp_write(DP_PHY_PD_CTL_V500, 0x7d); + dp_write(DP_PHY_PD_CTL_V500, 0x65); wmb(); /* make sure PD programming happened */ /* Turn on BIAS current for PHY/PLL */ @@ -176,6 +163,20 @@ static void dp_catalog_aux_setup_v500(struct dp_catalog_aux *aux, 0x17); wmb(); /* make sure BIAS programming happened */ + io_data = catalog->io->dp_phy; + dp_write(DP_PHY_PD_CTL_V500, 0x2); + wmb(); /* make sure PD programming happened */ + udelay(1000); + + dp_write(DP_PHY_PD_CTL_V500, 0x7d); + wmb(); /* make sure PD programming happened */ + udelay(1000); + + if (revision_id >= 0x5000) + dp_write(DP_PHY_MODE_V500, 0xfc); + else + dp_write(DP_PHY_MODE, 0xfc); + io_data = catalog->io->dp_phy; /* DP AUX CFG register programming */ for (i = 0; i < PHY_AUX_CFG_MAX; i++) { @@ -353,18 +354,7 @@ static void dp_catalog_ctrl_update_vx_px_v500(struct dp_catalog_ctrl *ctrl, value0 = vm_voltage_swing[index][v_level][p_level]; value1 = vm_pre_emphasis[index][v_level][p_level]; - ldo_cfg = ldo_config[index]; - - /* program default setting first */ - io_data = catalog->io->dp_ln_tx0; - dp_write(TXn_LDO_CONFIG_V500, 0x01); - dp_write(TXn_TX_DRV_LVL_V500, 0x17); - dp_write(TXn_TX_EMP_POST1_LVL_V500, 0x00); - - io_data = catalog->io->dp_ln_tx1; - dp_write(TXn_LDO_CONFIG_V500, 0x01); - dp_write(TXn_TX_DRV_LVL_V500, 0x2A); - dp_write(TXn_TX_EMP_POST1_LVL_V500, 0x20); + ldo_cfg = 0x01; /* Configure host and panel only if both values are allowed */ if (value0 != 0xFF && value1 != 0xFF) { diff --git a/msm/dp/edp_pll_7nm.c b/msm/dp/edp_pll_7nm.c index 13e15c82035a..da26cb657884 100644 --- a/msm/dp/edp_pll_7nm.c +++ b/msm/dp/edp_pll_7nm.c @@ -149,8 +149,8 @@ static int edp_vco_pll_init_db_7nm(struct dp_pll_db *pdb, pdb->div_frac_start3_mode0 = 0x07; pdb->lock_cmp1_mode0 = 0x6f; pdb->lock_cmp2_mode0 = 0x08; - pdb->phy_vco_div = 0x02; - pdb->lock_cmp_en = 0x04; + pdb->phy_vco_div = 0x01; + pdb->lock_cmp_en = 0x08; pdb->ssc_step_size1_mode0 = 0x45; pdb->ssc_step_size2_mode0 = 0x06; break; @@ -279,7 +279,6 @@ static int edp_config_vco_rate_7nm(struct dp_pll *pll, } dp_pll_write(dp_phy, DP_PHY_PD_CTL, 0x7d); - dp_pll_write(dp_phy, DP_PHY_MODE, 0xfc); /* Make sure the PLL register writes are done */ wmb(); @@ -314,7 +313,7 @@ static int edp_config_vco_rate_7nm(struct dp_pll *pll, dp_pll_write(dp_pll, QSERDES_COM_CLK_SEL, 0x30); dp_pll_write(dp_pll, QSERDES_COM_HSCLK_SEL, pdb->hsclk_sel); - dp_pll_write(dp_pll, QSERDES_COM_PLL_IVCO, 0x07); + dp_pll_write(dp_pll, QSERDES_COM_PLL_IVCO, 0x0f); dp_pll_write(dp_pll, QSERDES_COM_LOCK_CMP_EN, pdb->lock_cmp_en); dp_pll_write(dp_pll, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); @@ -350,6 +349,8 @@ static int edp_config_vco_rate_7nm(struct dp_pll *pll, dp_pll_write(dp_pll, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x17); dp_pll_write(dp_pll, QSERDES_COM_CORE_CLK_EN, 0x0f); + dp_pll_write(dp_pll, QSERDES_COM_VCO_TUNE1_MODE0, 0xa0); + dp_pll_write(dp_pll, QSERDES_COM_VCO_TUNE2_MODE0, 0x03); /* Make sure the PHY register writes are done */ wmb(); @@ -482,6 +483,27 @@ static int edp_pll_enable_7nm(struct dp_pll *pll) } dp_pll_write(dp_phy, DP_PHY_CFG, 0x19); + dp_pll_write(dp_ln_tx0, TXn_HIGHZ_DRVR_EN, 0x1f); + dp_pll_write(dp_ln_tx0, TXn_HIGHZ_DRVR_EN, 0x04); + dp_pll_write(dp_ln_tx0, TXn_TX_POL_INV, 0x00); + dp_pll_write(dp_ln_tx1, TXn_HIGHZ_DRVR_EN, 0x1f); + dp_pll_write(dp_ln_tx1, TXn_HIGHZ_DRVR_EN, 0x04); + dp_pll_write(dp_ln_tx1, TXn_TX_POL_INV, 0x00); + dp_pll_write(dp_ln_tx0, TXn_TX_DRV_LVL_OFFSET, 0x10); + dp_pll_write(dp_ln_tx1, TXn_TX_DRV_LVL_OFFSET, 0x10); + dp_pll_write(dp_ln_tx0, + TXn_RES_CODE_LANE_OFFSET_TX0, 0x11); + dp_pll_write(dp_ln_tx0, + TXn_RES_CODE_LANE_OFFSET_TX1, 0x11); + dp_pll_write(dp_ln_tx1, + TXn_RES_CODE_LANE_OFFSET_TX0, 0x11); + dp_pll_write(dp_ln_tx1, + TXn_RES_CODE_LANE_OFFSET_TX1, 0x11); + dp_pll_write(dp_ln_tx0, TXn_TX_EMP_POST1_LVL, 0x10); + dp_pll_write(dp_ln_tx1, TXn_TX_EMP_POST1_LVL, 0x10); + dp_pll_write(dp_ln_tx0, TXn_TX_DRV_LVL, 0x1f); + dp_pll_write(dp_ln_tx1, TXn_TX_DRV_LVL, 0x1f); + /* Make sure the PHY register writes are done */ wmb(); @@ -506,32 +528,15 @@ static int edp_pll_enable_7nm(struct dp_pll *pll) } dp_pll_write(dp_ln_tx0, TXn_HIGHZ_DRVR_EN, drvr_en0); - dp_pll_write(dp_ln_tx0, TXn_TX_POL_INV, 0x00); + dp_pll_write(dp_ln_tx0, TXn_TRANSCEIVER_BIAS_EN, + bias_en0); dp_pll_write(dp_ln_tx1, TXn_HIGHZ_DRVR_EN, drvr_en1); - dp_pll_write(dp_ln_tx1, TXn_TX_POL_INV, 0x00); - dp_pll_write(dp_ln_tx0, TXn_TX_DRV_LVL_OFFSET, 0x10); - dp_pll_write(dp_ln_tx1, TXn_TX_DRV_LVL_OFFSET, 0x10); - dp_pll_write(dp_ln_tx0, - TXn_RES_CODE_LANE_OFFSET_TX0, 0x11); - dp_pll_write(dp_ln_tx0, - TXn_RES_CODE_LANE_OFFSET_TX1, 0x11); - dp_pll_write(dp_ln_tx1, - TXn_RES_CODE_LANE_OFFSET_TX0, 0x11); - dp_pll_write(dp_ln_tx1, - TXn_RES_CODE_LANE_OFFSET_TX1, 0x11); - - dp_pll_write(dp_ln_tx0, TXn_TX_EMP_POST1_LVL, 0x10); - dp_pll_write(dp_ln_tx1, TXn_TX_EMP_POST1_LVL, 0x10); - dp_pll_write(dp_ln_tx0, TXn_TX_DRV_LVL, 0x1f); - dp_pll_write(dp_ln_tx1, TXn_TX_DRV_LVL, 0x1f); + dp_pll_write(dp_ln_tx1, TXn_TRANSCEIVER_BIAS_EN, + bias_en1); /* Make sure the PHY register writes are done */ wmb(); - dp_pll_write(dp_ln_tx0, TXn_TRANSCEIVER_BIAS_EN, - bias_en0); - dp_pll_write(dp_ln_tx1, TXn_TRANSCEIVER_BIAS_EN, - bias_en1); dp_pll_write(dp_phy, DP_PHY_CFG_1, phy_cfg_1); if (!edp_7nm_pll_get_status(pll, PHY_READY)) { @@ -771,7 +776,7 @@ static long edp_pll_vco_div_clk_round(struct clk_hw *hw, unsigned long rate, } static int edp_pll_vco_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) + unsigned long parent_rate) { struct dp_pll *pll = NULL; struct dp_pll_vco_clk *pll_link = NULL; @@ -815,11 +820,11 @@ static const struct clk_ops edp_pll_vco_div_clk_ops = { static struct clk_init_data edp_phy_pll_clks[DP_PLL_NUM_CLKS] = { { - .name = "_phy_pll_link_clk", + .name = "edp_phy_pll_link_clk", .ops = &edp_pll_link_clk_ops, }, { - .name = "_phy_pll_vco_div_clk", + .name = "edp_phy_pll_vco_div_clk", .ops = &edp_pll_vco_div_clk_ops, }, }; @@ -830,7 +835,7 @@ static struct dp_pll_vco_clk *edp_pll_get_clks(struct dp_pll *pll) for (i = 0; i < DP_PLL_NUM_CLKS; i++) { snprintf(pll->pll_clks[i].name, DP_PLL_NAME_MAX_SIZE, - "%s%s", pll->name, edp_phy_pll_clks[i].name); + "%s", edp_phy_pll_clks[i].name); pll->pll_clks[i].init_data.name = pll->pll_clks[i].name; pll->pll_clks[i].init_data.ops = edp_phy_pll_clks[i].ops; pll->pll_clks[i].hw.init = &pll->pll_clks[i].init_data;