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Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6

Browse source 
* master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6: (34 commits)
  PCI: Only build PCI syscalls on architectures that want them
  PCI: limit pci_get_bus_and_slot to domain 0
  PCI: hotplug: acpiphp: avoid acpiphp "cannot get bridge info" PCI hotplug failure
  PCI: hotplug: acpiphp: remove hot plug parameter write to PCI host bridge
  PCI: hotplug: acpiphp: fix slot poweroff problem on systems without _PS3
  PCI: hotplug: pciehp: wait for 1 second after power off slot
  PCI: pci_set_power_state(): check for PM capabilities earlier
  PCI: cpci_hotplug: Convert to use the kthread API
  PCI: add pci_try_set_mwi
  PCI: pcie: remove SPIN_LOCK_UNLOCKED
  PCI: ROUND_UP macro cleanup in drivers/pci
  PCI: remove pci_dac_dma_... APIs
  PCI: pci-x-pci-express-read-control-interfaces cleanups
  PCI: Fix typo in include/linux/pci.h
  PCI: pci_ids, remove double or more empty lines
  PCI: pci_ids, add atheros and 3com_2 vendors
  PCI: pci_ids, reorder some entries
  PCI: i386: traps, change VENDOR to DEVICE
  PCI: ATM: lanai, change VENDOR to DEVICE
  PCI: Change all drivers to use pci_device->revision
  ...
This commit is contained in:
Linus Torvalds 2007-07-12 13:40:57 -07:00
commit 21ba0f88ae
172 changed files with 760 additions and 1401 deletions
Download patch file Download diff file Expand all files Collapse all files

7
drivers/acpi/processor_core.c
View file

@ -115,7 +115,6 @@ struct acpi_processor_errata errata __read_mostly;
static int acpi_processor_errata_piix4(struct pci_dev *dev)
{
u8 rev = 0;
u8 value1 = 0;
u8 value2 = 0;
@ -127,9 +126,7 @@ static int acpi_processor_errata_piix4(struct pci_dev *dev)
* Note that 'dev' references the PIIX4 ACPI Controller.
*/
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
switch (rev) {
switch (dev->revision) {
case 0:
ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found PIIX4 A-step\n"));
break;
@ -147,7 +144,7 @@ static int acpi_processor_errata_piix4(struct pci_dev *dev)
break;
}
switch (rev) {
switch (dev->revision) {
case 0: /* PIIX4 A-step */
case 1: /* PIIX4 B-step */

6
drivers/ata/ata_piix.c
View file

@ -928,20 +928,18 @@ static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
{
struct pci_dev *pdev = NULL;
u16 cfg;
u8 rev;
int no_piix_dma = 0;
while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
{
/* Look for 450NX PXB. Check for problem configurations
A PCI quirk checks bit 6 already */
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
pci_read_config_word(pdev, 0x41, &cfg);
/* Only on the original revision: IDE DMA can hang */
if (rev == 0x00)
if (pdev->revision == 0x00)
no_piix_dma = 1;
/* On all revisions below 5 PXB bus lock must be disabled for IDE */
else if (cfg & (1<<14) && rev < 5)
else if (cfg & (1<<14) && pdev->revision < 5)
no_piix_dma = 2;
}
if (no_piix_dma)

34
drivers/ata/pata_ali.c
View file

@ -455,23 +455,21 @@ static struct ata_port_operations ali_c5_port_ops = {
static void ali_init_chipset(struct pci_dev *pdev)
{
u8 rev, tmp;
u8 tmp;
struct pci_dev *north, *isa_bridge;
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
/*
* The chipset revision selects the driver operations and
* mode data.
*/
if (rev >= 0x20 && rev < 0xC2) {
if (pdev->revision >= 0x20 && pdev->revision < 0xC2) {
/* 1543-E/F, 1543C-C, 1543C-D, 1543C-E */
pci_read_config_byte(pdev, 0x4B, &tmp);
/* Clear CD-ROM DMA write bit */
tmp &= 0x7F;
pci_write_config_byte(pdev, 0x4B, tmp);
} else if (rev >= 0xC2) {
} else if (pdev->revision >= 0xC2) {
/* Enable cable detection logic */
pci_read_config_byte(pdev, 0x4B, &tmp);
pci_write_config_byte(pdev, 0x4B, tmp | 0x08);
@ -483,21 +481,21 @@ static void ali_init_chipset(struct pci_dev *pdev)
/* Configure the ALi bridge logic. For non ALi rely on BIOS.
Set the south bridge enable bit */
pci_read_config_byte(isa_bridge, 0x79, &tmp);
if (rev == 0xC2)
if (pdev->revision == 0xC2)
pci_write_config_byte(isa_bridge, 0x79, tmp | 0x04);
else if (rev > 0xC2 && rev < 0xC5)
else if (pdev->revision > 0xC2 && pdev->revision < 0xC5)
pci_write_config_byte(isa_bridge, 0x79, tmp | 0x02);
}
if (rev >= 0x20) {
if (pdev->revision >= 0x20) {
/*
* CD_ROM DMA on (0x53 bit 0). Enable this even if we want
* to use PIO. 0x53 bit 1 (rev 20 only) - enable FIFO control
* via 0x54/55.
*/
pci_read_config_byte(pdev, 0x53, &tmp);
if (rev <= 0x20)
if (pdev->revision <= 0x20)
tmp &= ~0x02;
if (rev >= 0xc7)
if (pdev->revision >= 0xc7)
tmp |= 0x03;
else
tmp |= 0x01; /* CD_ROM enable for DMA */
@ -579,25 +577,23 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
};
const struct ata_port_info *ppi[] = { NULL, NULL };
u8 rev, tmp;
u8 tmp;
struct pci_dev *isa_bridge;
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
/*
* The chipset revision selects the driver operations and
* mode data.
*/
if (rev < 0x20) {
if (pdev->revision < 0x20) {
ppi[0] = &info_early;
} else if (rev < 0xC2) {
} else if (pdev->revision < 0xC2) {
ppi[0] = &info_20;
} else if (rev == 0xC2) {
} else if (pdev->revision == 0xC2) {
ppi[0] = &info_c2;
} else if (rev == 0xC3) {
} else if (pdev->revision == 0xC3) {
ppi[0] = &info_c3;
} else if (rev == 0xC4) {
} else if (pdev->revision == 0xC4) {
ppi[0] = &info_c4;
} else
ppi[0] = &info_c5;
@ -605,7 +601,7 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
ali_init_chipset(pdev);
isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
if (isa_bridge && rev >= 0x20 && rev < 0xC2) {
if (isa_bridge && pdev->revision >= 0x20 && pdev->revision < 0xC2) {
/* Are we paired with a UDMA capable chip */
pci_read_config_byte(isa_bridge, 0x5E, &tmp);
if ((tmp & 0x1E) == 0x12)

4
drivers/ata/pata_amd.c
View file

@ -623,17 +623,15 @@ static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
const struct ata_port_info *ppi[] = { NULL, NULL };
static int printed_version;
int type = id->driver_data;
u8 rev;
u8 fifo;
if (!printed_version++)
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
pci_read_config_byte(pdev, 0x41, &fifo);
/* Check for AMD7409 without swdma errata and if found adjust type */
if (type == 1 && rev > 0x7)
if (type == 1 && pdev->revision > 0x7)
type = 2;
/* Check for AMD7411 */

2
drivers/ata/pata_cs5530.c
View file

@ -266,7 +266,7 @@ static int cs5530_init_chip(void)
}
pci_set_master(cs5530_0);
pci_set_mwi(cs5530_0);
pci_try_set_mwi(cs5530_0);
/*
* Set PCI CacheLineSize to 16-bytes:

3
drivers/ata/pata_it821x.c
View file

@ -587,8 +587,7 @@ static int it821x_port_start(struct ata_port *ap)
itdev->want[1][1] = ATA_ANY;
itdev->last_device = -1;
pci_read_config_byte(pdev, PCI_REVISION_ID, &conf);
if (conf == 0x10) {
if (pdev->revision == 0x11) {
itdev->timing10 = 1;
/* Need to disable ATAPI DMA for this case */
if (!itdev->smart)

5
drivers/ata/pata_serverworks.c
View file

@ -410,11 +410,8 @@ static int serverworks_fixup_osb4(struct pci_dev *pdev)
static int serverworks_fixup_csb(struct pci_dev *pdev)
{
u8 rev;
u8 btr;
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
/* Third Channel Test */
if (!(PCI_FUNC(pdev->devfn) & 1)) {
struct pci_dev * findev = NULL;
@ -456,7 +453,7 @@ static int serverworks_fixup_csb(struct pci_dev *pdev)
if (!(PCI_FUNC(pdev->devfn) & 1))
btr |= 0x2;
else
btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
pci_write_config_byte(pdev, 0x5A, btr);
return btr;

8
drivers/ata/pata_sis.c
View file

@ -931,9 +931,7 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
if (host != NULL) {
chipset = sets; /* Match found */
if (sets->device == 0x630) { /* SIS630 */
u8 host_rev;
pci_read_config_byte(host, PCI_REVISION_ID, &host_rev);
if (host_rev >= 0x30) /* 630 ET */
if (host->revision >= 0x30) /* 630 ET */
chipset = &sis100_early;
}
break;
@ -977,7 +975,6 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
u16 trueid;
u8 prefctl;
u8 idecfg;
u8 sbrev;
/* Try the second unmasking technique */
pci_read_config_byte(pdev, 0x4a, &idecfg);
@ -990,11 +987,10 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
if (lpc_bridge == NULL)
break;
pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
pci_read_config_byte(pdev, 0x49, &prefctl);
pci_dev_put(lpc_bridge);
if (sbrev == 0x10 && (prefctl & 0x80)) {
if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
chipset = &sis133_early;
break;
}

5
drivers/ata/pata_sl82c105.c
View file

@ -270,7 +270,6 @@ static struct ata_port_operations sl82c105_port_ops = {
static int sl82c105_bridge_revision(struct pci_dev *pdev)
{
struct pci_dev *bridge;
u8 rev;
/*
* The bridge should be part of the same device, but function 0.
@ -292,10 +291,8 @@ static int sl82c105_bridge_revision(struct pci_dev *pdev)
/*
* We need to find function 0's revision, not function 1
*/
pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
pci_dev_put(bridge);
return rev;
return bridge->revision;
}

6
drivers/ata/pata_via.c
View file

@ -506,7 +506,6 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
struct pci_dev *isa = NULL;
const struct via_isa_bridge *config;
static int printed_version;
u8 t;
u8 enable;
u32 timing;
@ -520,9 +519,8 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
!!(config->flags & VIA_BAD_ID),
config->id, NULL))) {
pci_read_config_byte(isa, PCI_REVISION_ID, &t);
if (t >= config->rev_min &&
t <= config->rev_max)
if (isa->revision >= config->rev_min &&
isa->revision <= config->rev_max)
break;
pci_dev_put(isa);
}

20
drivers/ata/sata_mv.c
View file

@ -1765,12 +1765,9 @@ static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
{
u8 rev_id;
int early_5080;
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
if (!early_5080) {
u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
@ -2387,17 +2384,14 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
{
struct pci_dev *pdev = to_pci_dev(host->dev);
struct mv_host_priv *hpriv = host->private_data;
u8 rev_id;
u32 hp_flags = hpriv->hp_flags;
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
switch(board_idx) {
case chip_5080:
hpriv->ops = &mv5xxx_ops;
hp_flags |= MV_HP_GEN_I;
switch (rev_id) {
switch (pdev->revision) {
case 0x1:
hp_flags |= MV_HP_ERRATA_50XXB0;
break;
@ -2417,7 +2411,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
hpriv->ops = &mv5xxx_ops;
hp_flags |= MV_HP_GEN_I;
switch (rev_id) {
switch (pdev->revision) {
case 0x0:
hp_flags |= MV_HP_ERRATA_50XXB0;
break;
@ -2437,7 +2431,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
hpriv->ops = &mv6xxx_ops;
hp_flags |= MV_HP_GEN_II;
switch (rev_id) {
switch (pdev->revision) {
case 0x7:
hp_flags |= MV_HP_ERRATA_60X1B2;
break;
@ -2457,7 +2451,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
hpriv->ops = &mv6xxx_ops;
hp_flags |= MV_HP_GEN_IIE;
switch (rev_id) {
switch (pdev->revision) {
case 0x0:
hp_flags |= MV_HP_ERRATA_XX42A0;
break;
@ -2585,14 +2579,12 @@ static void mv_print_info(struct ata_host *host)
{
struct pci_dev *pdev = to_pci_dev(host->dev);
struct mv_host_priv *hpriv = host->private_data;
u8 rev_id, scc;
u8 scc;
const char *scc_s, *gen;
/* Use this to determine the HW stepping of the chip so we know
* what errata to workaround
*/
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
if (scc == 0)
scc_s = "SCSI";

9
drivers/atm/eni.c
View file

@ -1704,7 +1704,6 @@ static int __devinit eni_do_init(struct atm_dev *dev)
struct pci_dev *pci_dev;
unsigned long real_base;
void __iomem *base;
unsigned char revision;
int error,i,last;
DPRINTK(">eni_init\n");
@ -1715,12 +1714,6 @@ static int __devinit eni_do_init(struct atm_dev *dev)
pci_dev = eni_dev->pci_dev;
real_base = pci_resource_start(pci_dev, 0);
eni_dev->irq = pci_dev->irq;
error = pci_read_config_byte(pci_dev,PCI_REVISION_ID,&revision);
if (error) {
printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%02x\n",
dev->number,error);
return -EINVAL;
}
if ((error = pci_write_config_word(pci_dev,PCI_COMMAND,
PCI_COMMAND_MEMORY |
(eni_dev->asic ? PCI_COMMAND_PARITY | PCI_COMMAND_SERR : 0)))) {
@ -1729,7 +1722,7 @@ static int __devinit eni_do_init(struct atm_dev *dev)
return -EIO;
}
printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d,base=0x%lx,irq=%d,",
dev->number,revision,real_base,eni_dev->irq);
dev->number,pci_dev->revision,real_base,eni_dev->irq);
if (!(base = ioremap_nocache(real_base,MAP_MAX_SIZE))) {
printk("\n");
printk(KERN_ERR DEV_LABEL "(itf %d): can't set up page "

13
drivers/atm/idt77252.c
View file

@ -3679,7 +3679,6 @@ idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
unsigned long membase, srambase;
struct idt77252_dev *card;
struct atm_dev *dev;
ushort revision = 0;
int i, err;
@ -3688,19 +3687,13 @@ idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
return err;
}
if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
err = -ENODEV;
goto err_out_disable_pdev;
}
card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
if (!card) {
printk("idt77252-%d: can't allocate private data\n", index);
err = -ENOMEM;
goto err_out_disable_pdev;
}
card->revision = revision;
card->revision = pcidev->revision;
card->index = index;
card->pcidev = pcidev;
sprintf(card->name, "idt77252-%d", card->index);
@ -3762,8 +3755,8 @@ idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
}
printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
card->name, ((revision > 1) && (revision < 25)) ?
'A' + revision - 1 : '?', membase, srambase,
card->name, ((card->revision > 1) && (card->revision < 25)) ?
'A' + card->revision - 1 : '?', membase, srambase,
card->sramsize / 1024);
if (init_card(dev)) {

11
drivers/atm/iphase.c
View file

@ -2290,7 +2290,6 @@ static int __devinit ia_init(struct atm_dev *dev)
unsigned long real_base;
void __iomem *base;
unsigned short command;
unsigned char revision;
int error, i;
/* The device has been identified and registered. Now we read
@ -2305,16 +2304,14 @@ static int __devinit ia_init(struct atm_dev *dev)
real_base = pci_resource_start (iadev->pci, 0);
iadev->irq = iadev->pci->irq;
if ((error = pci_read_config_word(iadev->pci, PCI_COMMAND,&command))
|| (error = pci_read_config_byte(iadev->pci,
PCI_REVISION_ID,&revision)))
{
error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
if (error) {
printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%x\n",
dev->number,error);
return -EINVAL;
}
IF_INIT(printk(DEV_LABEL "(itf %d): rev.%d,realbase=0x%lx,irq=%d\n",
dev->number, revision, real_base, iadev->irq);)
dev->number, iadev->pci->revision, real_base, iadev->irq);)
/* find mapping size of board */
@ -2353,7 +2350,7 @@ static int __devinit ia_init(struct atm_dev *dev)
return error;
}
IF_INIT(printk(DEV_LABEL " (itf %d): rev.%d,base=%p,irq=%d\n",
dev->number, revision, base, iadev->irq);)
dev->number, iadev->pci->revision, base, iadev->irq);)
/* filling the iphase dev structure */
iadev->mem = iadev->pci_map_size /2;

27
drivers/atm/lanai.c
View file

@ -246,8 +246,8 @@ struct lanai_vcc {
};
enum lanai_type {
lanai2 = PCI_VENDOR_ID_EF_ATM_LANAI2,
lanaihb = PCI_VENDOR_ID_EF_ATM_LANAIHB
lanai2 = PCI_DEVICE_ID_EF_ATM_LANAI2,
lanaihb = PCI_DEVICE_ID_EF_ATM_LANAIHB
};
struct lanai_dev_stats {
@ -293,7 +293,6 @@ struct lanai_dev {
struct atm_vcc *cbrvcc;
int number;
int board_rev;
u8 pci_revision;
/* TODO - look at race conditions with maintence of conf1/conf2 */
/* TODO - transmit locking: should we use _irq not _irqsave? */
/* TODO - organize above in some rational fashion (see <asm/cache.h>) */
@ -1969,14 +1968,6 @@ static int __devinit lanai_pci_start(struct lanai_dev *lanai)
"(itf %d): No suitable DMA available.\n", lanai->number);
return -EBUSY;
}
/* Get the pci revision byte */
result = pci_read_config_byte(pci, PCI_REVISION_ID,
&lanai->pci_revision);
if (result != PCIBIOS_SUCCESSFUL) {
printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
"PCI_REVISION_ID: %d\n", lanai->number, result);
return -EINVAL;
}
result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w);
if (result != PCIBIOS_SUCCESSFUL) {
printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
@ -2254,7 +2245,7 @@ static int __devinit lanai_dev_open(struct atm_dev *atmdev)
lanai_timed_poll_start(lanai);
printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u "
"(%02X-%02X-%02X-%02X-%02X-%02X)\n", lanai->number,
(int) lanai->pci_revision, (unsigned long) lanai->base,
(int) lanai->pci->revision, (unsigned long) lanai->base,
lanai->pci->irq,
atmdev->esi[0], atmdev->esi[1], atmdev->esi[2],
atmdev->esi[3], atmdev->esi[4], atmdev->esi[5]);
@ -2491,7 +2482,7 @@ static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
(unsigned int) lanai->magicno, lanai->num_vci);
if (left-- == 0)
return sprintf(page, "revision: board=%d, pci_if=%d\n",
lanai->board_rev, (int) lanai->pci_revision);
lanai->board_rev, (int) lanai->pci->revision);
if (left-- == 0)
return sprintf(page, "EEPROM ESI: "
"%02X:%02X:%02X:%02X:%02X:%02X\n",
@ -2631,14 +2622,8 @@ static int __devinit lanai_init_one(struct pci_dev *pci,
}
static struct pci_device_id lanai_pci_tbl[] = {
{
PCI_VENDOR_ID_EF, PCI_VENDOR_ID_EF_ATM_LANAI2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
},
{
PCI_VENDOR_ID_EF, PCI_VENDOR_ID_EF_ATM_LANAIHB,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
},
{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },
{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },
{ 0, } /* terminal entry */
};
MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);

6
drivers/atm/zatm.c
View file

@ -1182,7 +1182,6 @@ static int __devinit zatm_init(struct atm_dev *dev)
struct zatm_dev *zatm_dev;
struct pci_dev *pci_dev;
unsigned short command;
unsigned char revision;
int error,i,last;
unsigned long t0,t1,t2;
@ -1192,8 +1191,7 @@ static int __devinit zatm_init(struct atm_dev *dev)
pci_dev = zatm_dev->pci_dev;
zatm_dev->base = pci_resource_start(pci_dev, 0);
zatm_dev->irq = pci_dev->irq;
if ((error = pci_read_config_word(pci_dev,PCI_COMMAND,&command)) ||
(error = pci_read_config_byte(pci_dev,PCI_REVISION_ID,&revision))) {
if ((error = pci_read_config_word(pci_dev,PCI_COMMAND,&command))) {
printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%02x\n",
dev->number,error);
return -EINVAL;
@ -1206,7 +1204,7 @@ static int __devinit zatm_init(struct atm_dev *dev)
}
eprom_get_esi(dev);
printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d,base=0x%x,irq=%d,",
dev->number,revision,zatm_dev->base,zatm_dev->irq);
dev->number,pci_dev->revision,zatm_dev->base,zatm_dev->irq);
/* reset uPD98401 */
zout(0,SWR);
while (!(zin(GSR) & uPD98401_INT_IND));

4
drivers/char/agp/amd-k7-agp.c
View file

@ -462,9 +462,7 @@ static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
* erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
* With this lot disabled, we should prevent lockups. */
if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
u8 revision=0;
pci_read_config_byte(pdev, PCI_REVISION_ID, &revision);
if (revision == 0x10 || revision == 0x11) {
if (pdev->revision == 0x10 || pdev->revision == 0x11) {
agp_bridge->flags = AGP_ERRATA_FASTWRITES;
agp_bridge->flags |= AGP_ERRATA_SBA;
agp_bridge->flags |= AGP_ERRATA_1X;

6
drivers/char/agp/amd64-agp.c
View file

@ -367,10 +367,8 @@ static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
{
char *revstring;
u8 rev_id;
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
switch (rev_id) {
switch (pdev->revision) {
case 0x01: revstring="A0"; break;
case 0x02: revstring="A1"; break;
case 0x11: revstring="B0"; break;
@ -386,7 +384,7 @@ static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data
* Work around errata.
* Chips before B2 stepping incorrectly reporting v3.5
*/
if (rev_id < 0x13) {
if (pdev->revision < 0x13) {
printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
bridge->major_version = 3;
bridge->minor_version = 0;

5
drivers/clocksource/acpi_pm.c
View file

@ -105,14 +105,11 @@ static inline void acpi_pm_need_workaround(void)
*/
static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
{
u8 rev;
if (acpi_pm_good)
return;
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
/* the bug has been fixed in PIIX4M */
if (rev < 3) {
if (dev->revision < 3) {
printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
" Due to workarounds for a bug,\n"
"* this clock source is slow. Consider trying"

3
drivers/i2c/busses/i2c-viapro.c
View file

@ -397,8 +397,7 @@ found:
case PCI_DEVICE_ID_VIA_82C686_4:
/* The VT82C686B (rev 0x40) does support I2C block
transactions, but the VT82C686A (rev 0x30) doesn't */
if (!pci_read_config_byte(pdev, PCI_REVISION_ID, &temp)
&& temp >= 0x40)
if (pdev->revision >= 0x40)
vt596_features |= FEATURE_I2CBLOCK;
break;
}

2
drivers/ide/pci/alim15x3.c
View file

@ -508,7 +508,7 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c
u8 tmpbyte;
struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision);
m5229_revision = dev->revision;
isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);

8
drivers/ide/pci/amd74xx.c
View file

@ -123,8 +123,7 @@ static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
amd_print("Driver Version: 2.13");
amd_print("South Bridge: %s", pci_name(bmide_dev));
pci_read_config_byte(dev, PCI_REVISION_ID, &t);
amd_print("Revision: IDE %#x", t);
amd_print("Revision: IDE %#x", dev->revision);
amd_print("Highest DMA rate: UDMA%s", amd_dma[fls(amd_config->udma_mask) - 1]);
amd_print("BM-DMA base: %#lx", amd_base);
@ -312,8 +311,7 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch
*/
if (amd_config->flags & AMD_CHECK_SWDMA) {
pci_read_config_byte(dev, PCI_REVISION_ID, &t);
if (t <= 7)
if (dev->revision <= 7)
amd_config->flags |= AMD_BAD_SWDMA;
}
@ -383,7 +381,7 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch
pci_read_config_byte(dev, PCI_REVISION_ID, &t);
printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
amd_chipset->name, pci_name(dev), t,
amd_chipset->name, pci_name(dev), dev->revision,
amd_dma[fls(amd_config->udma_mask) - 1]);
/*

9
drivers/ide/pci/cmd64x.c
View file

@ -88,7 +88,6 @@ static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
u8 reg72 = 0, reg73 = 0; /* primary */
u8 reg7a = 0, reg7b = 0; /* secondary */
u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
u8 rev = 0;
p += sprintf(p, "\nController: %d\n", index);
p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
@ -103,9 +102,8 @@ static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
(void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
/* PCI0643/6 originally didn't have the primary channel enable bit */
(void) pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
(dev->device == PCI_DEVICE_ID_CMD_646 && rev < 3))
(dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3))
reg51 |= CNTRL_ENA_1ST;
p += sprintf(p, "---------------- Primary Channel "
@ -604,14 +602,11 @@ static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d)
static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
{
u8 rev = 0;
/*
* The original PCI0646 didn't have the primary channel enable bit,
* it appeared starting with PCI0646U (i.e. revision ID 3).
*/
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
if (rev < 3)
if (dev->revision < 3)
d->enablebits[0].reg = 0;
return ide_setup_pci_device(dev, d);

2
drivers/ide/pci/cs5530.c
View file

@ -236,7 +236,7 @@ static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const ch
*/
pci_set_master(cs5530_0);
pci_set_mwi(cs5530_0);
pci_try_set_mwi(cs5530_0);
/*
* Set PCI CacheLineSize to 16-bytes:

20
drivers/ide/pci/hpt366.c
View file

@ -1413,11 +1413,9 @@ static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d
static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
{
struct hpt_info *info;
u8 rev = 0, mcr1 = 0;
u8 mcr1 = 0;
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
if (rev > 1) {
if (dev->revision > 1) {
d->name = "HPT371N";
info = &hpt371n;
@ -1442,11 +1440,8 @@ static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
{
struct hpt_info *info;
u8 rev = 0;
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
if (rev > 1) {
if (dev->revision > 1) {
d->name = "HPT372N";
info = &hpt372n;
@ -1460,11 +1455,8 @@ static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d
static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
{
struct hpt_info *info;
u8 rev = 0;
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
if (rev > 1) {
if (dev->revision > 1) {
d->name = "HPT302N";
info = &hpt302n;
@ -1478,7 +1470,7 @@ static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
{
struct pci_dev *dev2;
u8 rev = 0;
u8 rev = dev->revision;
static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
"HPT370", "HPT370A", "HPT372",
"HPT372N" };
@ -1489,8 +1481,6 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
if (PCI_FUNC(dev->devfn) & 1)
return -ENODEV;
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
switch (rev) {
case 0:
case 1:

6
drivers/ide/pci/piix.c
View file

@ -572,18 +572,16 @@ static void __devinit piix_check_450nx(void)
{
struct pci_dev *pdev = NULL;
u16 cfg;
u8 rev;
while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
{
/* Look for 450NX PXB. Check for problem configurations
A PCI quirk checks bit 6 already */
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
pci_read_config_word(pdev, 0x41, &cfg);
/* Only on the original revision: IDE DMA can hang */
if(rev == 0x00)
if (pdev->revision == 0x00)
no_piix_dma = 1;
/* On all revisions below 5 PXB bus lock must be disabled for IDE */
else if(cfg & (1<<14) && rev < 5)
else if (cfg & (1<<14) && pdev->revision < 5)
no_piix_dma = 2;
}
if(no_piix_dma)

13
drivers/ide/pci/serverworks.c
View file

@ -55,7 +55,6 @@ static const char *svwks_bad_ata100[] = {
NULL
};
static u8 svwks_revision = 0;
static struct pci_dev *isa_dev;
static int check_in_drive_lists (ide_drive_t *drive, const char **list)
@ -71,9 +70,6 @@ static u8 svwks_udma_filter(ide_drive_t *drive)
struct pci_dev *dev = HWIF(drive)->pci_dev;
u8 mask = 0;
if (!svwks_revision)
pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
return 0x1f;
if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
@ -88,9 +84,9 @@ static u8 svwks_udma_filter(ide_drive_t *drive)
return 0;
/* Check the OSB4 DMA33 enable bit */
return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
} else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
return 0x07;
} else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
} else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
u8 btr = 0, mode;
pci_read_config_byte(dev, 0x5A, &btr);
mode = btr & 0x3;
@ -234,9 +230,6 @@ static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const cha
unsigned int reg;
u8 btr;
/* save revision id to determine DMA capability */
pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
/* force Master Latency Timer value to 64 PCICLKs */
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
@ -315,7 +308,7 @@ static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const cha
if (!(PCI_FUNC(dev->devfn) & 1))
btr |= 0x2;
else
btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
pci_write_config_byte(dev, 0x5A, btr);
}
/* Setup HT1000 SouthBridge Controller - Single Channel Only */

8
drivers/ide/pci/sis5513.c
View file

@ -659,9 +659,7 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
/* Special case for SiS630 : 630S/ET is ATA_100a */
if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
u8 hostrev;
pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
if (hostrev >= 0x30)
if (host->revision >= 0x30)
chipset_family = ATA_100a;
}
pci_dev_put(host);
@ -702,7 +700,6 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
u16 trueid;
u8 prefctl;
u8 idecfg;
u8 sbrev;
pci_read_config_byte(dev, 0x4a, &idecfg);
pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
@ -712,11 +709,10 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
if (trueid == 0x5517) { /* SiS 961/961B */
lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
pci_read_config_byte(dev, 0x49, &prefctl);
pci_dev_put(lpc_bridge);
if (sbrev == 0x10 && (prefctl & 0x80)) {
if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
chipset_family = ATA_133a;
} else {

4
drivers/ide/pci/sl82c105.c
View file

@ -338,7 +338,6 @@ static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
{
struct pci_dev *bridge;
u8 rev;
/*
* The bridge should be part of the same device, but function 0.
@ -360,10 +359,9 @@ static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
/*
* We need to find function 0's revision, not function 1
*/
pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
pci_dev_put(bridge);
return rev;
return bridge->revision;
}
/*

9
drivers/ide/pci/via82cxxx.c
View file

@ -237,16 +237,14 @@ static int via82cxxx_ide_dma_check (ide_drive_t *drive)
static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
struct via_isa_bridge *via_config;
u8 t;
for (via_config = via_isa_bridges; via_config->id; via_config++)
if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
!!(via_config->flags & VIA_BAD_ID),
via_config->id, NULL))) {
pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
if (t >= via_config->rev_min &&
t <= via_config->rev_max)
if ((*isa)->revision >= via_config->rev_min &&
(*isa)->revision <= via_config->rev_max)
break;
pci_dev_put(*isa);
}
@ -404,10 +402,9 @@ static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const
* Print the boot message.
*/
pci_read_config_byte(isa, PCI_REVISION_ID, &t);
printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
"controller on pci%s\n",
via_config->name, t,
via_config->name, isa->revision,
via_config->udma_mask ? "U" : "MW",
via_dma[via_config->udma_mask ?
(fls(via_config->udma_mask) - 1) : 0],

9
drivers/infiniband/hw/ipath/ipath_driver.c
View file

@ -270,7 +270,6 @@ static int __devinit ipath_init_one(struct pci_dev *pdev,
struct ipath_devdata *dd;
unsigned long long addr;
u32 bar0 = 0, bar1 = 0;
u8 rev;
dd = ipath_alloc_devdata(pdev);
if (IS_ERR(dd)) {
@ -432,13 +431,7 @@ static int __devinit ipath_init_one(struct pci_dev *pdev,
dd->ipath_deviceid = ent->device; /* save for later use */
dd->ipath_vendorid = ent->vendor;
ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
if (ret) {
ipath_dev_err(dd, "Failed to read PCI revision ID unit "
"%u: err %d\n", dd->ipath_unit, -ret);
goto bail_regions; /* shouldn't ever happen */
}
dd->ipath_pcirev = rev;
dd->ipath_pcirev = pdev->revision;
#if defined(__powerpc__)
/* There isn't a generic way to specify writethrough mappings */

4
drivers/isdn/hisax/bkm_a8.c
View file

@ -287,7 +287,6 @@ setup_sct_quadro(struct IsdnCard *card)
#ifdef CONFIG_PCI
struct IsdnCardState *cs = card->cs;
char tmp[64];
u_char pci_rev_id;
u_int found = 0;
u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
@ -335,8 +334,7 @@ setup_sct_quadro(struct IsdnCard *card)
}
#ifdef ATTEMPT_PCI_REMAPPING
/* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
pci_read_config_byte(dev_a8, PCI_REVISION_ID, &pci_rev_id);
if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
if ((pci_ioaddr1 & 0x80) && (dev_a8->revision == 1)) {
printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);

4
drivers/media/radio/radio-gemtek-pci.c
View file

@ -94,7 +94,6 @@ struct gemtek_pci_card {
u32 iobase;
u32 length;
u8 chiprev;
u16 model;
u32 current_frequency;
@ -415,7 +414,6 @@ static int __devinit gemtek_pci_probe( struct pci_dev *pci_dev, const struct pci
goto err_pci;
}
pci_read_config_byte( pci_dev, PCI_REVISION_ID, &card->chiprev );
pci_read_config_word( pci_dev, PCI_SUBSYSTEM_ID, &card->model );
pci_set_drvdata( pci_dev, card );
@ -436,7 +434,7 @@ static int __devinit gemtek_pci_probe( struct pci_dev *pci_dev, const struct pci
gemtek_pci_mute( card );
printk( KERN_INFO "Gemtek PCI Radio (rev. %d) found at 0x%04x-0x%04x.\n",
card->chiprev, card->iobase, card->iobase + card->length - 1 );
pci_dev->revision, card->iobase, card->iobase + card->length - 1 );
return 0;

4
drivers/media/video/meye.c
View file

@ -1809,7 +1809,6 @@ static int __devinit meye_probe(struct pci_dev *pcidev,
{
int ret = -EBUSY;
unsigned long mchip_adr;
u8 revision;
if (meye.mchip_dev != NULL) {
printk(KERN_ERR "meye: only one device allowed!\n");
@ -1885,7 +1884,6 @@ static int __devinit meye_probe(struct pci_dev *pcidev,
goto outreqirq;
}
pci_read_config_byte(meye.mchip_dev, PCI_REVISION_ID, &revision);
pci_write_config_byte(meye.mchip_dev, PCI_CACHE_LINE_SIZE, 8);
pci_write_config_byte(meye.mchip_dev, PCI_LATENCY_TIMER, 64);
@ -1939,7 +1937,7 @@ static int __devinit meye_probe(struct pci_dev *pcidev,
printk(KERN_INFO "meye: Motion Eye Camera Driver v%s.\n",
MEYE_DRIVER_VERSION);
printk(KERN_INFO "meye: mchip KL5A72002 rev. %d, base %lx, irq %d\n",
revision, mchip_adr, meye.mchip_irq);
meye.mchip_dev->revision, mchip_adr, meye.mchip_irq);
return 0;

7
drivers/net/8139cp.c
View file

@ -1799,7 +1799,6 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
void __iomem *regs;
resource_size_t pciaddr;
unsigned int addr_len, i, pci_using_dac;
u8 pci_rev;
#ifndef MODULE
static int version_printed;
@ -1807,13 +1806,11 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
printk("%s", version);
#endif
pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
dev_err(&pdev->dev,
"This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
pdev->vendor, pdev->device, pci_rev);
pdev->vendor, pdev->device, pdev->revision);
dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
return -ENODEV;
}

7
drivers/net/8139too.c
View file

@ -931,7 +931,6 @@ static int __devinit rtl8139_init_one (struct pci_dev *pdev,
int i, addr_len, option;
void __iomem *ioaddr;
static int board_idx = -1;
u8 pci_rev;
assert (pdev != NULL);
assert (ent != NULL);
@ -949,13 +948,11 @@ static int __devinit rtl8139_init_one (struct pci_dev *pdev,
}
#endif
pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
dev_info(&pdev->dev,
"This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
pdev->vendor, pdev->device, pci_rev);
pdev->vendor, pdev->device, pdev->revision);
dev_info(&pdev->dev,
"Use the \"8139cp\" driver for improved performance and stability.\n");
}

1
drivers/net/atl1/atl1.h
View file

@ -210,7 +210,6 @@ struct atl1_hw {
u16 phy_spd_default;
u16 dev_rev;
u8 revision_id;
/* spi flash */
u8 flash_vendor;

4
drivers/net/atl1/atl1_main.c
View file

@ -118,10 +118,6 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
{
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
struct pci_dev *pdev = adapter->pdev;
/* PCI config space info */
pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
hw->max_frame_size = netdev->mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;

5
drivers/net/bnx2.c
View file

@ -6736,10 +6736,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_8132_BRIDGE,
amd_8132))) {
u8 rev;
pci_read_config_byte(amd_8132, PCI_REVISION_ID, &rev);
if (rev >= 0x10 && rev <= 0x13) {
if (amd_8132->revision >= 0x10 &&
amd_8132->revision <= 0x13) {
disable_msi = 1;
pci_dev_put(amd_8132);
break;

12
drivers/net/cassini.c
View file

@ -3422,21 +3422,19 @@ done:
static void cas_check_pci_invariants(struct cas *cp)
{
struct pci_dev *pdev = cp->pdev;
u8 rev;
cp->cas_flags = 0;
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
(pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
if (rev >= CAS_ID_REVPLUS)
if (pdev->revision >= CAS_ID_REVPLUS)
cp->cas_flags |= CAS_FLAG_REG_PLUS;
if (rev < CAS_ID_REVPLUS02u)
if (pdev->revision < CAS_ID_REVPLUS02u)
cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
/* Original Cassini supports HW CSUM, but it's not
* enabled by default as it can trigger TX hangs.
*/
if (rev < CAS_ID_REV2)
if (pdev->revision < CAS_ID_REV2)
cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
} else {
/* Only sun has original cassini chips. */
@ -4919,13 +4917,13 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
pci_cmd &= ~PCI_COMMAND_SERR;
pci_cmd |= PCI_COMMAND_PARITY;
pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
if (pci_set_mwi(pdev))
if (pci_try_set_mwi(pdev))
printk(KERN_WARNING PFX "Could not enable MWI for %s\n",
pci_name(pdev));
/*
* On some architectures, the default cache line size set
* by pci_set_mwi reduces perforamnce. We have to increase
* by pci_try_set_mwi reduces perforamnce. We have to increase
* it for this case. To start, we'll print some configuration
* data.
*/

3
drivers/net/dl2k.c
View file

@ -250,7 +250,6 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
np->an_enable = 1;
mii_set_media (dev);
}
pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
err = register_netdev (dev);
if (err)
@ -879,7 +878,7 @@ receive_packet (struct net_device *dev)
skb->protocol = eth_type_trans (skb, dev);
#if 0
/* Checksum done by hw, but csum value unavailable. */
if (np->pci_rev_id >= 0x0c &&
if (np->pdev->pci_rev_id >= 0x0c &&
!(frame_status & (TCPError | UDPError | IPError))) {
skb->ip_summed = CHECKSUM_UNNECESSARY;
}

1
drivers/net/dl2k.h
View file

@ -668,7 +668,6 @@ struct netdev_private {
unsigned int rx_flow:1; /* Rx flow control enable */
unsigned int phy_media:1; /* 1: fiber, 0: copper */
unsigned int link_status:1; /* Current link status */
unsigned char pci_rev_id; /* PCI revision ID */
struct netdev_desc *last_tx; /* Last Tx descriptor used. */
unsigned long cur_rx, old_rx; /* Producer/consumer ring indices */
unsigned long cur_tx, old_tx;

8
drivers/net/e100.c
View file

@ -583,7 +583,6 @@ struct nic {
u32 rx_tco_frames;
u32 rx_over_length_errors;
u8 rev_id;
u16 leds;
u16 eeprom_wc;
u16 eeprom[256];
@ -937,9 +936,8 @@ static void e100_get_defaults(struct nic *nic)
struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
if(nic->mac == mac_unknown)
nic->mac = mac_82557_D100_A;
@ -1279,7 +1277,7 @@ static void e100_setup_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb
if (nic->flags & ich)
goto noloaducode;
/* Search for ucode match against h/w rev_id */
/* Search for ucode match against h/w revision */
for (opts = ucode_opts; opts->mac; opts++) {
int i;
u32 *ucode = opts->ucode;
@ -2238,7 +2236,7 @@ static void e100_get_regs(struct net_device *netdev,
u32 *buff = p;
int i;
regs->version = (1 << 24) | nic->rev_id;
regs->version = (1 << 24) | nic->pdev->revision;
buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
ioread8(&nic->csr->scb.cmd_lo) << 16 |
ioread16(&nic->csr->scb.status);

3
drivers/net/e1000/e1000_main.c
View file

@ -1266,8 +1266,7 @@ e1000_sw_init(struct e1000_adapter *adapter)
hw->device_id = pdev->device;
hw->subsystem_vendor_id = pdev->subsystem_vendor;
hw->subsystem_id = pdev->subsystem_device;
pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
hw->revision_id = pdev->revision;
pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);

4
drivers/net/forcedeth.c
View file

@ -5084,15 +5084,13 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
np->wolenabled = 0;
if (id->driver_data & DEV_HAS_POWER_CNTRL) {
u8 revision_id;
pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
/* take phy and nic out of low power mode */
powerstate = readl(base + NvRegPowerState2);
powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
revision_id >= 0xA3)
pci_dev->revision >= 0xA3)
powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
writel(powerstate, base + NvRegPowerState2);
}

7
drivers/net/netxen/netxen_nic_main.c
View file

@ -54,8 +54,6 @@ static char netxen_nic_driver_string[] = "NetXen Network Driver version "
#define NETXEN_ADAPTER_UP_MAGIC 777
#define NETXEN_NIC_PEG_TUNE 0
u8 nx_p2_id = NX_P2_C0;
#define DMA_32BIT_MASK 0x00000000ffffffffULL
#define DMA_35BIT_MASK 0x00000007ffffffffULL
@ -307,8 +305,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
goto err_out_disable_pdev;
pci_set_master(pdev);
pci_read_config_byte(pdev, PCI_REVISION_ID, &nx_p2_id);
if (nx_p2_id == NX_P2_C1 &&
if (pdev->revision == NX_P2_C1 &&
(pci_set_dma_mask(pdev, DMA_35BIT_MASK) == 0) &&
(pci_set_consistent_dma_mask(pdev, DMA_35BIT_MASK) == 0)) {
pci_using_dac = 1;
@ -552,7 +549,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task);
adapter->ahw.pdev = pdev;
adapter->proc_cmd_buf_counter = 0;
adapter->ahw.revision_id = nx_p2_id;
adapter->ahw.revision_id = pdev->revision;
/* make sure Window == 1 */
netxen_nic_pci_change_crbwindow(adapter, 1);

25
drivers/net/s2io.c
View file

@ -1135,7 +1135,7 @@ static int init_nic(struct s2io_nic *nic)
* SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
*/
if ((nic->device_type == XFRAME_I_DEVICE) &&
(get_xena_rev_id(nic->pdev) < 4))
(nic->pdev->revision < 4))
writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
val64 = readq(&bar0->tx_fifo_partition_0);
@ -1873,7 +1873,7 @@ static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
herc = (sp->device_type == XFRAME_II_DEVICE);
if (flag == FALSE) {
if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
if ((!herc && (sp->pdev->revision >= 4)) || herc) {
if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
ret = 1;
} else {
@ -1881,7 +1881,7 @@ static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
ret = 1;
}
} else {
if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
if ((!herc && (sp->pdev->revision >= 4)) || herc) {
if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
ADAPTER_STATUS_RMAC_PCC_IDLE))
ret = 1;
@ -7075,23 +7075,6 @@ static void s2io_link(struct s2io_nic * sp, int link)
sp->start_time = jiffies;
}
/**
* get_xena_rev_id - to identify revision ID of xena.
* @pdev : PCI Dev structure
* Description:
* Function to identify the Revision ID of xena.
* Return value:
* returns the revision ID of the device.
*/
static int get_xena_rev_id(struct pci_dev *pdev)
{
u8 id = 0;
int ret;
ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
return id;
}
/**
* s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
* @sp : private member of the device structure, which is a pointer to the
@ -7550,7 +7533,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
s2io_vpd_read(sp);
DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
sp->product_name, get_xena_rev_id(sp->pdev));
sp->product_name, pdev->revision);
DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
s2io_driver_version);
DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "

1
drivers/net/s2io.h
View file

@ -1033,7 +1033,6 @@ static void s2io_set_link(struct work_struct *work);
static int s2io_set_swapper(struct s2io_nic * sp);
static void s2io_card_down(struct s2io_nic *nic);
static int s2io_card_up(struct s2io_nic *nic);
static int get_xena_rev_id(struct pci_dev *pdev);
static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
int bit_state);
static int s2io_add_isr(struct s2io_nic * sp);

2
drivers/net/starfire.c
View file

@ -740,7 +740,7 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
pci_set_master(pdev);
/* enable MWI -- it vastly improves Rx performance on sparc64 */
pci_set_mwi(pdev);
pci_try_set_mwi(pdev);
#ifdef ZEROCOPY
/* Starfire can do TCP/UDP checksumming */

7
drivers/net/sundance.c
View file

@ -397,7 +397,6 @@ struct netdev_private {
unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
struct pci_dev *pci_dev;
void __iomem *base;
unsigned char pci_rev_id;
};
/* The station address location in the EEPROM. */
@ -544,8 +543,6 @@ static int __devinit sundance_probe1 (struct pci_dev *pdev,
dev->change_mtu = &change_mtu;
pci_set_drvdata(pdev, dev);
pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
i = register_netdev(dev);
if (i)
goto err_out_unmap_rx;
@ -828,7 +825,7 @@ static int netdev_open(struct net_device *dev)
iowrite8(100, ioaddr + RxDMAPollPeriod);
iowrite8(127, ioaddr + TxDMAPollPeriod);
/* Fix DFE-580TX packet drop issue */
if (np->pci_rev_id >= 0x14)
if (np->pci_dev->revision >= 0x14)
iowrite8(0x01, ioaddr + DebugCtrl1);
netif_start_queue(dev);
@ -1194,7 +1191,7 @@ static irqreturn_t intr_handler(int irq, void *dev_instance)
hw_frame_id = ioread8(ioaddr + TxFrameId);
}
if (np->pci_rev_id >= 0x14) {
if (np->pci_dev->revision >= 0x14) {
spin_lock(&np->lock);
for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
int entry = np->dirty_tx % TX_RING_SIZE;

8
drivers/net/sunhme.c
View file

@ -3095,12 +3095,8 @@ static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
#ifdef CONFIG_SPARC
hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
if (hp->hm_revision == 0xff) {
unsigned char prev;
pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
hp->hm_revision = 0xc0 | (prev & 0x0f);
}
if (hp->hm_revision == 0xff)
hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
#else
/* works with this on non-sparc hosts */
hp->hm_revision = 0x20;

6
drivers/net/tg3.c
View file

@ -10551,11 +10551,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
continue;
}
if (pci_id->rev != PCI_ANY_ID) {
u8 rev;
pci_read_config_byte(bridge, PCI_REVISION_ID,
&rev);
if (rev > pci_id->rev)
if (bridge->revision > pci_id->rev)
continue;
}
if (bridge->subordinate &&

5
drivers/net/tlan.c
View file

@ -533,7 +533,6 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
struct net_device *dev;
TLanPrivateInfo *priv;
u8 pci_rev;
u16 device_id;
int reg, rc = -ENODEV;
@ -577,8 +576,6 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
goto err_out_free_dev;
}
pci_read_config_byte ( pdev, PCI_REVISION_ID, &pci_rev);
for ( reg= 0; reg <= 5; reg ++ ) {
if (pci_resource_flags(pdev, reg) & IORESOURCE_IO) {
pci_io_base = pci_resource_start(pdev, reg);
@ -595,7 +592,7 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
dev->base_addr = pci_io_base;
dev->irq = pdev->irq;
priv->adapterRev = pci_rev;
priv->adapterRev = pdev->revision;
pci_set_master(pdev);
pci_set_drvdata(pdev, dev);

8
drivers/net/tulip/de4x5.c
View file

@ -2134,7 +2134,7 @@ srom_search(struct net_device *dev, struct pci_dev *pdev)
u_short vendor, status;
u_int irq = 0, device;
u_long iobase = 0; /* Clear upper 32 bits in Alphas */
int i, j, cfrv;
int i, j;
struct de4x5_private *lp = netdev_priv(dev);
struct list_head *walk;
@ -2150,7 +2150,6 @@ srom_search(struct net_device *dev, struct pci_dev *pdev)
/* Get the chip configuration revision register */
pb = this_dev->bus->number;
pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv);
/* Set the device number information */
lp->device = PCI_SLOT(this_dev->devfn);
@ -2158,7 +2157,8 @@ srom_search(struct net_device *dev, struct pci_dev *pdev)
/* Set the chipset information */
if (is_DC2114x) {
device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
? DC21142 : DC21143);
}
lp->chipset = device;
@ -2254,7 +2254,7 @@ static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
}
/* Get the chip configuration revision register */
pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv);
lp->cfrv = pdev->revision;
/* Set the device number information */
lp->device = dev_num;

26
drivers/net/tulip/dmfe.c
View file

@ -181,11 +181,12 @@
udelay(5);
#define __CHK_IO_SIZE(pci_id, dev_rev) \
(( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? \
(( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
DM9102A_IO_SIZE: DM9102_IO_SIZE)
#define CHK_IO_SIZE(pci_dev, dev_rev) \
(__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev))
#define CHK_IO_SIZE(pci_dev) \
(__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
(pci_dev)->revision))
/* Sten Check */
#define DEVICE net_device
@ -205,7 +206,7 @@ struct rx_desc {
struct dmfe_board_info {
u32 chip_id; /* Chip vendor/Device ID */
u32 chip_revision; /* Chip revision */
u8 chip_revision; /* Chip revision */
struct DEVICE *next_dev; /* next device */
struct pci_dev *pdev; /* PCI device */
spinlock_t lock;
@ -359,7 +360,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
{
struct dmfe_board_info *db; /* board information structure */
struct net_device *dev;
u32 dev_rev, pci_pmr;
u32 pci_pmr;
int i, err;
DMFE_DBUG(0, "dmfe_init_one()", 0);
@ -392,10 +393,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
goto err_out_disable;
}
/* Read Chip revision */
pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
err = -ENODEV;
goto err_out_disable;
@ -433,7 +431,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
db->chip_id = ent->driver_data;
db->ioaddr = pci_resource_start(pdev, 0);
db->chip_revision = dev_rev;
db->chip_revision = pdev->revision;
db->wol_mode = 0;
db->pdev = pdev;
@ -455,7 +453,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
pci_read_config_dword(pdev, 0x50, &pci_pmr);
pci_pmr &= 0x70000;
if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
db->chip_type = 1; /* DM9102A E3 */
else
db->chip_type = 0;
@ -553,7 +551,7 @@ static int dmfe_open(struct DEVICE *dev)
/* CR6 operation mode decision */
if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
(db->chip_revision >= 0x02000030) ) {
(db->chip_revision >= 0x30) ) {
db->cr6_data |= DMFE_TXTH_256;
db->cr0_data = CR0_DEFAULT;
db->dm910x_chk_mode=4; /* Enter the normal mode */
@ -1199,9 +1197,9 @@ static void dmfe_timer(unsigned long data)
tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
if ( ((db->chip_id == PCI_DM9102_ID) &&
(db->chip_revision == 0x02000030)) ||
(db->chip_revision == 0x30)) ||
((db->chip_id == PCI_DM9132_ID) &&
(db->chip_revision == 0x02000010)) ) {
(db->chip_revision == 0x10)) ) {
/* DM9102A Chip */
if (tmp_cr12 & 2)
link_ok = 0;

15
drivers/net/tulip/tulip_core.c
View file

@ -1155,7 +1155,7 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
/* set or disable MWI in the standard PCI command bit.
* Check for the case where mwi is desired but not available
*/
if (csr0 & MWI) pci_set_mwi(pdev);
if (csr0 & MWI) pci_try_set_mwi(pdev);
else pci_clear_mwi(pdev);
/* read result from hardware (in case bit refused to enable) */
@ -1238,7 +1238,6 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
};
static int last_irq;
static int multiport_cnt; /* For four-port boards w/one EEPROM */
u8 chip_rev;
int i, irq;
unsigned short sum;
unsigned char *ee_data;
@ -1274,10 +1273,8 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
{
u32 dev_rev;
/* Read Chip revision */
pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
if(dev_rev < 0x02000030)
if (pdev->revision < 0x02000030)
{
printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
return -ENODEV;
@ -1360,8 +1357,6 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
if (!ioaddr)
goto err_out_free_res;
pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev);
/*
* initialize private data structure 'tp'
* it is zeroed and aligned in alloc_etherdev
@ -1382,7 +1377,7 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
tp->flags = tulip_tbl[chip_idx].flags;
tp->pdev = pdev;
tp->base_addr = ioaddr;
tp->revision = chip_rev;
tp->revision = pdev->revision;
tp->csr0 = csr0;
spin_lock_init(&tp->lock);
spin_lock_init(&tp->mii_lock);
@ -1399,7 +1394,7 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
tulip_mwi_config (pdev, dev);
#else
/* MWI is broken for DC21143 rev 65... */
if (chip_idx == DC21143 && chip_rev == 65)
if (chip_idx == DC21143 && pdev->revision == 65)
tp->csr0 &= ~MWI;
#endif
@ -1640,7 +1635,7 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
#else
"Port"
#endif
" %#llx,", dev->name, chip_name, chip_rev,
" %#llx,", dev->name, chip_name, pdev->revision,
(unsigned long long) pci_resource_start(pdev, TULIP_BAR));
pci_set_drvdata(pdev, dev);

5
drivers/net/tulip/xircom_cb.c
View file

@ -205,7 +205,6 @@ static int __devinit xircom_probe(struct pci_dev *pdev, const struct pci_device_
{
struct net_device *dev = NULL;
struct xircom_private *private;
unsigned char chip_rev;
unsigned long flags;
unsigned short tmp16;
enter("xircom_probe");
@ -224,8 +223,6 @@ static int __devinit xircom_probe(struct pci_dev *pdev, const struct pci_device_
pci_read_config_word (pdev,PCI_STATUS, &tmp16);
pci_write_config_word (pdev, PCI_STATUS,tmp16);
pci_read_config_byte(pdev, PCI_REVISION_ID, &chip_rev);
if (!request_region(pci_resource_start(pdev, 0), 128, "xircom_cb")) {
printk(KERN_ERR "xircom_probe: failed to allocate io-region\n");
return -ENODEV;
@ -286,7 +283,7 @@ static int __devinit xircom_probe(struct pci_dev *pdev, const struct pci_device_
goto reg_fail;
}
printk(KERN_INFO "%s: Xircom cardbus revision %i at irq %i \n", dev->name, chip_rev, pdev->irq);
printk(KERN_INFO "%s: Xircom cardbus revision %i at irq %i \n", dev->name, pdev->revision, pdev->irq);
/* start the transmitter to get a heartbeat */
/* TODO: send 2 dummy packets here */
transceiver_voodoo(private);

4
drivers/net/tulip/xircom_tulip_cb.c
View file

@ -524,7 +524,6 @@ static int __devinit xircom_init_one(struct pci_dev *pdev, const struct pci_devi
int chip_idx = id->driver_data;
long ioaddr;
int i;
u8 chip_rev;
/* when built into the kernel, we only print version if device is found */
#ifndef MODULE
@ -620,9 +619,8 @@ static int __devinit xircom_init_one(struct pci_dev *pdev, const struct pci_devi
if (register_netdev(dev))
goto err_out_cleardev;
pci_read_config_byte(pdev, PCI_REVISION_ID, &chip_rev);
printk(KERN_INFO "%s: %s rev %d at %#3lx,",
dev->name, xircom_tbl[chip_idx].chip_name, chip_rev, ioaddr);
dev->name, xircom_tbl[chip_idx].chip_name, pdev->revision, ioaddr);
for (i = 0; i < 6; i++)
printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
printk(", IRQ %d.\n", dev->irq);

7
drivers/net/typhoon.c
View file

@ -2267,12 +2267,6 @@ need_resume:
typhoon_resume(pdev);
return -EBUSY;
}
static int
typhoon_enable_wake(struct pci_dev *pdev, pci_power_t state, int enable)
{
return pci_enable_wake(pdev, state, enable);
}
#endif
static int __devinit
@ -2636,7 +2630,6 @@ static struct pci_driver typhoon_driver = {
#ifdef CONFIG_PM
.suspend = typhoon_suspend,
.resume = typhoon_resume,
.enable_wake = typhoon_enable_wake,
#endif
};

13
drivers/net/via-rhine.c
View file

@ -622,7 +622,6 @@ static int __devinit rhine_init_one(struct pci_dev *pdev,
struct net_device *dev;
struct rhine_private *rp;
int i, rc;
u8 pci_rev;
u32 quirks;
long pioaddr;
long memaddr;
@ -642,27 +641,25 @@ static int __devinit rhine_init_one(struct pci_dev *pdev,
printk(version);
#endif
pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
io_size = 256;
phy_id = 0;
quirks = 0;
name = "Rhine";
if (pci_rev < VTunknown0) {
if (pdev->revision < VTunknown0) {
quirks = rqRhineI;
io_size = 128;
}
else if (pci_rev >= VT6102) {
else if (pdev->revision >= VT6102) {
quirks = rqWOL | rqForceReset;
if (pci_rev < VT6105) {
if (pdev->revision < VT6105) {
name = "Rhine II";
quirks |= rqStatusWBRace; /* Rhine-II exclusive */
}
else {
phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
if (pci_rev >= VT6105_B0)
if (pdev->revision >= VT6105_B0)
quirks |= rq6patterns;
if (pci_rev < VT6105M)
if (pdev->revision < VT6105M)
name = "Rhine III";
else
name = "Rhine III (Management Adapter)";

3
drivers/net/via-velocity.c
View file

@ -890,8 +890,7 @@ static void __devinit velocity_init_info(struct pci_dev *pdev,
static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev)
{
if (pci_read_config_byte(pdev, PCI_REVISION_ID, &vptr->rev_id) < 0)
return -EIO;
vptr->rev_id = pdev->revision;
pci_set_master(pdev);

4
drivers/net/wan/pc300_drv.c
View file

@ -3439,7 +3439,6 @@ static int __devinit
cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
static int first_time = 1;
ucchar cpc_rev_id;
int err, eeprom_outdated = 0;
ucshort device_id;
pc300_t *card;
@ -3480,7 +3479,6 @@ cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
card->hw.falcsize = pci_resource_len(pdev, 4);
card->hw.plxphys = pci_resource_start(pdev, 5);
card->hw.plxsize = pci_resource_len(pdev, 5);
pci_read_config_byte(pdev, PCI_REVISION_ID, &cpc_rev_id);
switch (device_id) {
case PCI_DEVICE_ID_PC300_RX_1:
@ -3498,7 +3496,7 @@ cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
}
#ifdef PC300_DEBUG_PCI
printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
printk("rev_id=%d) IRQ%d\n", cpc_rev_id, card->hw.irq);
printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
"ctladdr=0x%08lx falcaddr=0x%08lx\n",
card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,

2
drivers/net/wan/pc300too.c
View file

@ -311,7 +311,6 @@ static int __devinit pc300_pci_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
card_t *card;
u8 rev_id;
u32 __iomem *p;
int i;
u32 ramsize;
@ -366,7 +365,6 @@ static int __devinit pc300_pci_init_one(struct pci_dev *pdev,
return -ENOMEM;
}
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
pci_resource_len(pdev, 3) < 16384) {

2
drivers/net/wan/pci200syn.c
View file

@ -289,7 +289,6 @@ static int __devinit pci200_pci_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
card_t *card;
u8 rev_id;
u32 __iomem *p;
int i;
u32 ramsize;
@ -330,7 +329,6 @@ static int __devinit pci200_pci_init_one(struct pci_dev *pdev,
return -ENOMEM;
}
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
pci_resource_len(pdev, 3) < 16384) {

6
drivers/net/wireless/bcm43xx/bcm43xx_main.c
View file

@ -3741,10 +3741,8 @@ static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
&bcm->board_type);
if (err)
goto err_iounmap;
err = bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
&bcm->board_revision);
if (err)
goto err_iounmap;
bcm->board_revision = bcm->pci_dev->revision;
err = bcm43xx_chipset_attach(bcm);
if (err)

2
drivers/net/wireless/hostap/hostap_pci.c
View file

@ -453,8 +453,6 @@ static struct pci_driver prism2_pci_drv_id = {
.suspend = prism2_pci_suspend,
.resume = prism2_pci_resume,
#endif /* CONFIG_PM */
/* Linux 2.4.6 added save_state and enable_wake that are not used here
*/
};

3
drivers/net/wireless/hostap/hostap_plx.c
View file

@ -613,9 +613,6 @@ static struct pci_driver prism2_plx_drv_id = {
.id_table = prism2_plx_id_table,
.probe = prism2_plx_probe,
.remove = prism2_plx_remove,
.suspend = NULL,
.resume = NULL,
.enable_wake = NULL
};

4
drivers/net/wireless/prism54/islpci_hotplug.c
View file

@ -87,7 +87,6 @@ static struct pci_driver prism54_driver = {
.remove = prism54_remove,
.suspend = prism54_suspend,
.resume = prism54_resume,
/* .enable_wake ; we don't support this yet */
};
/******************************************************************************
@ -167,8 +166,7 @@ prism54_probe(struct pci_dev *pdev, const struct pci_device_id *id)
pci_set_master(pdev);
/* enable MWI */
if (!pci_set_mwi(pdev))
printk(KERN_INFO "%s: pci_set_mwi(pdev) succeeded\n", DRV_NAME);
pci_try_set_mwi(pdev);
/* setup the network device interface and its structure */
if (!(ndev = islpci_setup(pdev))) {

4
drivers/pci/Makefile
View file

@ -41,9 +41,7 @@ obj-$(CONFIG_ACPI) += pci-acpi.o
# Cardbus & CompactPCI use setup-bus
obj-$(CONFIG_HOTPLUG) += setup-bus.o
ifndef CONFIG_X86
obj-y += syscall.o
endif
obj-$(CONFIG_PCI_SYSCALL) += syscall.o
ifeq ($(CONFIG_PCI_DEBUG),y)
EXTRA_CFLAGS += -DDEBUG

1
drivers/pci/hotplug/acpiphp.h
View file

@ -211,6 +211,7 @@ typedef int (*acpiphp_callback)(struct acpiphp_slot *slot, void *data);
extern int acpiphp_enable_slot (struct acpiphp_slot *slot);
extern int acpiphp_disable_slot (struct acpiphp_slot *slot);
extern int acpiphp_eject_slot (struct acpiphp_slot *slot);
extern u8 acpiphp_get_power_status (struct acpiphp_slot *slot);
extern u8 acpiphp_get_attention_status (struct acpiphp_slot *slot);
extern u8 acpiphp_get_latch_status (struct acpiphp_slot *slot);

6
drivers/pci/hotplug/acpiphp_core.c
View file

@ -156,11 +156,15 @@ static int enable_slot(struct hotplug_slot *hotplug_slot)
static int disable_slot(struct hotplug_slot *hotplug_slot)
{
struct slot *slot = hotplug_slot->private;
int retval;
dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
/* disable the specified slot */
return acpiphp_disable_slot(slot->acpi_slot);
retval = acpiphp_disable_slot(slot->acpi_slot);
if (!retval)
retval = acpiphp_eject_slot(slot->acpi_slot);
return retval;
}

53
drivers/pci/hotplug/acpiphp_glue.c
View file

@ -1282,7 +1282,7 @@ static unsigned int get_slot_status(struct acpiphp_slot *slot)
/**
* acpiphp_eject_slot - physically eject the slot
*/
static int acpiphp_eject_slot(struct acpiphp_slot *slot)
int acpiphp_eject_slot(struct acpiphp_slot *slot)
{
acpi_status status;
struct acpiphp_func *func;
@ -1368,6 +1368,9 @@ static void program_hpp(struct pci_dev *dev, struct acpiphp_bridge *bridge)
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
return;
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
return;
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
bridge->hpp.t0->cache_line_size);
pci_write_config_byte(dev, PCI_LATENCY_TIMER,
@ -1502,6 +1505,37 @@ static void handle_bridge_insertion(acpi_handle handle, u32 type)
* ACPI event handlers
*/
static acpi_status
count_sub_bridges(acpi_handle handle, u32 lvl, void *context, void **rv)
{
int *count = (int *)context;
struct acpiphp_bridge *bridge;
bridge = acpiphp_handle_to_bridge(handle);
if (bridge)
(*count)++;
return AE_OK ;
}
static acpi_status
check_sub_bridges(acpi_handle handle, u32 lvl, void *context, void **rv)
{
struct acpiphp_bridge *bridge;
char objname[64];
struct acpi_buffer buffer = { .length = sizeof(objname),
.pointer = objname };
bridge = acpiphp_handle_to_bridge(handle);
if (bridge) {
acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
dbg("%s: re-enumerating slots under %s\n",
__FUNCTION__, objname);
acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
acpiphp_check_bridge(bridge);
}
return AE_OK ;
}
/**
* handle_hotplug_event_bridge - handle ACPI event on bridges
*
@ -1519,6 +1553,7 @@ static void handle_hotplug_event_bridge(acpi_handle handle, u32 type, void *cont
struct acpi_buffer buffer = { .length = sizeof(objname),
.pointer = objname };
struct acpi_device *device;
int num_sub_bridges = 0;
if (acpi_bus_get_device(handle, &device)) {
/* This bridge must have just been physically inserted */
@ -1527,7 +1562,12 @@ static void handle_hotplug_event_bridge(acpi_handle handle, u32 type, void *cont
}
bridge = acpiphp_handle_to_bridge(handle);
if (!bridge) {
if (type == ACPI_NOTIFY_BUS_CHECK) {
acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, ACPI_UINT32_MAX,
count_sub_bridges, &num_sub_bridges, NULL);
}
if (!bridge && !num_sub_bridges) {
err("cannot get bridge info\n");
return;
}
@ -1538,7 +1578,14 @@ static void handle_hotplug_event_bridge(acpi_handle handle, u32 type, void *cont
case ACPI_NOTIFY_BUS_CHECK:
/* bus re-enumerate */
dbg("%s: Bus check notify on %s\n", __FUNCTION__, objname);
acpiphp_check_bridge(bridge);
if (bridge) {
dbg("%s: re-enumerating slots under %s\n",
__FUNCTION__, objname);
acpiphp_check_bridge(bridge);
}
if (num_sub_bridges)
acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
ACPI_UINT32_MAX, check_sub_bridges, NULL, NULL);
break;
case ACPI_NOTIFY_DEVICE_CHECK:

66
drivers/pci/hotplug/cpci_hotplug_core.c
View file

@ -35,6 +35,7 @@
#include <linux/smp_lock.h>
#include <asm/atomic.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include "cpci_hotplug.h"
#define DRIVER_AUTHOR "Scott Murray <[email protected]>"
@ -59,9 +60,8 @@ static int slots;
static atomic_t extracting;
int cpci_debug;
static struct cpci_hp_controller *controller;
static struct semaphore event_semaphore; /* mutex for process loop (up if something to process) */
static struct semaphore thread_exit; /* guard ensure thread has exited before calling it quits */
static int thread_finished = 1;
static struct task_struct *cpci_thread;
static int thread_finished;
static int enable_slot(struct hotplug_slot *slot);
static int disable_slot(struct hotplug_slot *slot);
@ -357,9 +357,7 @@ cpci_hp_intr(int irq, void *data)
controller->ops->disable_irq();
/* Trigger processing by the event thread */
dbg("Signal event_semaphore");
up(&event_semaphore);
dbg("exited cpci_hp_intr");
wake_up_process(cpci_thread);
return IRQ_HANDLED;
}
@ -521,17 +519,12 @@ event_thread(void *data)
{
int rc;
lock_kernel();
daemonize("cpci_hp_eventd");
unlock_kernel();
dbg("%s - event thread started", __FUNCTION__);
while (1) {
dbg("event thread sleeping");
down_interruptible(&event_semaphore);
dbg("event thread woken, thread_finished = %d",
thread_finished);
if (thread_finished || signal_pending(current))
set_current_state(TASK_INTERRUPTIBLE);
schedule();
if (kthread_should_stop())
break;
do {
rc = check_slots();
@ -541,18 +534,17 @@ event_thread(void *data)
} else if (rc < 0) {
dbg("%s - error checking slots", __FUNCTION__);
thread_finished = 1;
break;
goto out;
}
} while (atomic_read(&extracting) && !thread_finished);
if (thread_finished)
} while (atomic_read(&extracting) && !kthread_should_stop());
if (kthread_should_stop())
break;
/* Re-enable ENUM# interrupt */
dbg("%s - re-enabling irq", __FUNCTION__);
controller->ops->enable_irq();
}
dbg("%s - event thread signals exit", __FUNCTION__);
up(&thread_exit);
out:
return 0;
}
@ -562,12 +554,8 @@ poll_thread(void *data)
{
int rc;
lock_kernel();
daemonize("cpci_hp_polld");
unlock_kernel();
while (1) {
if (thread_finished || signal_pending(current))
if (kthread_should_stop() || signal_pending(current))
break;
if (controller->ops->query_enum()) {
do {
@ -578,48 +566,36 @@ poll_thread(void *data)
} else if (rc < 0) {
dbg("%s - error checking slots", __FUNCTION__);
thread_finished = 1;
break;
goto out;
}
} while (atomic_read(&extracting) && !thread_finished);
} while (atomic_read(&extracting) && !kthread_should_stop());
}
msleep(100);
}
dbg("poll thread signals exit");
up(&thread_exit);
out:
return 0;
}
static int
cpci_start_thread(void)
{
int pid;
/* initialize our semaphores */
init_MUTEX_LOCKED(&event_semaphore);
init_MUTEX_LOCKED(&thread_exit);
thread_finished = 0;
if (controller->irq)
pid = kernel_thread(event_thread, NULL, 0);
cpci_thread = kthread_run(event_thread, NULL, "cpci_hp_eventd");
else
pid = kernel_thread(poll_thread, NULL, 0);
if (pid < 0) {
cpci_thread = kthread_run(poll_thread, NULL, "cpci_hp_polld");
if (IS_ERR(cpci_thread)) {
err("Can't start up our thread");
return -1;
return PTR_ERR(cpci_thread);
}
dbg("Our thread pid = %d", pid);
thread_finished = 0;
return 0;
}
static void
cpci_stop_thread(void)
{
kthread_stop(cpci_thread);
thread_finished = 1;
dbg("thread finish command given");
if (controller->irq)
up(&event_semaphore);
dbg("wait for thread to exit");
down(&thread_exit);
}
int

2
drivers/pci/hotplug/cpci_hotplug_pci.c
View file

@ -45,8 +45,6 @@ extern int cpci_debug;
#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)
#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME , ## arg)
#define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
u8 cpci_get_attention_status(struct slot* slot)
{

12
drivers/pci/hotplug/cpqphp_core.c
View file

@ -796,7 +796,6 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
u8 num_of_slots = 0;
u8 hp_slot = 0;
u8 device;
u8 rev;
u8 bus_cap;
u16 temp_word;
u16 vendor_id;
@ -823,9 +822,8 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
dbg("Vendor ID: %x\n", vendor_id);
rc = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
dbg("revision: %d\n", rev);
if (rc || ((vendor_id == PCI_VENDOR_ID_COMPAQ) && (!rev))) {
dbg("revision: %d\n", pdev->revision);
if ((vendor_id == PCI_VENDOR_ID_COMPAQ) && (!pdev->revision)) {
err(msg_HPC_rev_error);
rc = -ENODEV;
goto err_disable_device;
@ -836,7 +834,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
* For Intel, each SSID bit identifies a PHP capability.
* Also Intel HPC's may have RID=0.
*/
if ((rev > 2) || (vendor_id == PCI_VENDOR_ID_INTEL)) {
if ((pdev->revision > 2) || (vendor_id == PCI_VENDOR_ID_INTEL)) {
// TODO: This code can be made to support non-Compaq or Intel subsystem IDs
rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vid);
if (rc) {
@ -870,7 +868,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
switch (subsystem_vid) {
case PCI_VENDOR_ID_COMPAQ:
if (rev >= 0x13) { /* CIOBX */
if (pdev->revision >= 0x13) { /* CIOBX */
ctrl->push_flag = 1;
ctrl->slot_switch_type = 1;
ctrl->push_button = 1;
@ -1075,7 +1073,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
memcpy(ctrl->pci_bus, pdev->bus, sizeof(*ctrl->pci_bus));
ctrl->bus = pdev->bus->number;
ctrl->rev = rev;
ctrl->rev = pdev->revision;
dbg("bus device function rev: %d %d %d %d\n", ctrl->bus,
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), ctrl->rev);

1
drivers/pci/hotplug/pciehp.h
View file

@ -103,6 +103,7 @@ struct controller {
u8 cap_base;
struct timer_list poll_timer;
volatile int cmd_busy;
spinlock_t lock;
};
#define INT_BUTTON_IGNORE 0

12
drivers/pci/hotplug/pciehp_ctrl.c
View file

@ -197,6 +197,12 @@ static void set_slot_off(struct controller *ctrl, struct slot * pslot)
__FUNCTION__);
return;
}
/*
* After turning power off, we must wait for at least
* 1 second before taking any action that relies on
* power having been removed from the slot/adapter.
*/
msleep(1000);
}
}
@ -615,6 +621,12 @@ int pciehp_disable_slot(struct slot *p_slot)
mutex_unlock(&p_slot->ctrl->crit_sect);
return -EINVAL;
}
/*
* After turning power off, we must wait for at least
* 1 second before taking any action that relies on
* power having been removed from the slot/adapter.
*/
msleep(1000);
}
ret = remove_board(p_slot);

191
drivers/pci/hotplug/pciehp_hpc.c
View file

@ -275,11 +275,19 @@ static inline int pcie_wait_cmd(struct controller *ctrl)
return retval;
}
static int pcie_write_cmd(struct slot *slot, u16 cmd)
/**
* pcie_write_cmd - Issue controller command
* @slot: slot to which the command is issued
* @cmd: command value written to slot control register
* @mask: bitmask of slot control register to be modified
*/
static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
{
struct controller *ctrl = slot->ctrl;
int retval = 0;
u16 slot_status;
u16 slot_ctrl;
unsigned long flags;
DBG_ENTER_ROUTINE
@ -299,17 +307,29 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd)
__FUNCTION__);
}
ctrl->cmd_busy = 1;
retval = pciehp_writew(ctrl, SLOTCTRL, (cmd | CMD_CMPL_INTR_ENABLE));
spin_lock_irqsave(&ctrl->lock, flags);
retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (retval) {
err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
goto out;
err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
goto out_spin_unlock;
}
slot_ctrl &= ~mask;
slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
ctrl->cmd_busy = 1;
retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
if (retval)
err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
out_spin_unlock:
spin_unlock_irqrestore(&ctrl->lock, flags);
/*
* Wait for command completion.
*/
retval = pcie_wait_cmd(ctrl);
if (!retval)
retval = pcie_wait_cmd(ctrl);
out:
mutex_unlock(&ctrl->ctrl_lock);
DBG_LEAVE_ROUTINE
@ -502,25 +522,20 @@ static int hpc_get_emi_status(struct slot *slot, u8 *status)
static int hpc_toggle_emi(struct slot *slot)
{
struct controller *ctrl = slot->ctrl;
u16 slot_cmd = 0;
u16 slot_ctrl;
int rc = 0;
u16 slot_cmd;
u16 cmd_mask;
int rc;
DBG_ENTER_ROUTINE
rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (rc) {
err("%s : hp_register_read_word SLOT_CTRL failed\n",
__FUNCTION__);
return rc;
slot_cmd = EMI_CTRL;
cmd_mask = EMI_CTRL;
if (!pciehp_poll_mode) {
slot_cmd = slot_cmd | HP_INTR_ENABLE;
cmd_mask = cmd_mask | HP_INTR_ENABLE;
}
slot_cmd = (slot_ctrl | EMI_CTRL);
if (!pciehp_poll_mode)
slot_cmd = slot_cmd | HP_INTR_ENABLE;
pcie_write_cmd(slot, slot_cmd);
rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
slot->last_emi_toggle = get_seconds();
DBG_LEAVE_ROUTINE
return rc;
@ -529,35 +544,32 @@ static int hpc_toggle_emi(struct slot *slot)
static int hpc_set_attention_status(struct slot *slot, u8 value)
{
struct controller *ctrl = slot->ctrl;
u16 slot_cmd = 0;
u16 slot_ctrl;
int rc = 0;
u16 slot_cmd;
u16 cmd_mask;
int rc;
DBG_ENTER_ROUTINE
rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (rc) {
err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
return rc;
}
cmd_mask = ATTN_LED_CTRL;
switch (value) {
case 0 : /* turn off */
slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
slot_cmd = 0x00C0;
break;
case 1: /* turn on */
slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
slot_cmd = 0x0040;
break;
case 2: /* turn blink */
slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
slot_cmd = 0x0080;
break;
default:
return -1;
}
if (!pciehp_poll_mode)
slot_cmd = slot_cmd | HP_INTR_ENABLE;
if (!pciehp_poll_mode) {
slot_cmd = slot_cmd | HP_INTR_ENABLE;
cmd_mask = cmd_mask | HP_INTR_ENABLE;
}
pcie_write_cmd(slot, slot_cmd);
rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
dbg("%s: SLOTCTRL %x write cmd %x\n",
__FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
@ -570,21 +582,18 @@ static void hpc_set_green_led_on(struct slot *slot)
{
struct controller *ctrl = slot->ctrl;
u16 slot_cmd;
u16 slot_ctrl;
int rc = 0;
u16 cmd_mask;
DBG_ENTER_ROUTINE
rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (rc) {
err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
return;
slot_cmd = 0x0100;
cmd_mask = PWR_LED_CTRL;
if (!pciehp_poll_mode) {
slot_cmd = slot_cmd | HP_INTR_ENABLE;
cmd_mask = cmd_mask | HP_INTR_ENABLE;
}
slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
if (!pciehp_poll_mode)
slot_cmd = slot_cmd | HP_INTR_ENABLE;
pcie_write_cmd(slot, slot_cmd);
pcie_write_cmd(slot, slot_cmd, cmd_mask);
dbg("%s: SLOTCTRL %x write cmd %x\n",
__FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
@ -596,22 +605,18 @@ static void hpc_set_green_led_off(struct slot *slot)
{
struct controller *ctrl = slot->ctrl;
u16 slot_cmd;
u16 slot_ctrl;
int rc = 0;
u16 cmd_mask;
DBG_ENTER_ROUTINE
rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (rc) {
err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
return;
slot_cmd = 0x0300;
cmd_mask = PWR_LED_CTRL;
if (!pciehp_poll_mode) {
slot_cmd = slot_cmd | HP_INTR_ENABLE;
cmd_mask = cmd_mask | HP_INTR_ENABLE;
}
slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
if (!pciehp_poll_mode)
slot_cmd = slot_cmd | HP_INTR_ENABLE;
pcie_write_cmd(slot, slot_cmd);
pcie_write_cmd(slot, slot_cmd, cmd_mask);
dbg("%s: SLOTCTRL %x write cmd %x\n",
__FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
@ -623,22 +628,18 @@ static void hpc_set_green_led_blink(struct slot *slot)
{
struct controller *ctrl = slot->ctrl;
u16 slot_cmd;
u16 slot_ctrl;
int rc = 0;
u16 cmd_mask;
DBG_ENTER_ROUTINE
rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (rc) {
err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
return;
slot_cmd = 0x0200;
cmd_mask = PWR_LED_CTRL;
if (!pciehp_poll_mode) {
slot_cmd = slot_cmd | HP_INTR_ENABLE;
cmd_mask = cmd_mask | HP_INTR_ENABLE;
}
slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
if (!pciehp_poll_mode)
slot_cmd = slot_cmd | HP_INTR_ENABLE;
pcie_write_cmd(slot, slot_cmd);
pcie_write_cmd(slot, slot_cmd, cmd_mask);
dbg("%s: SLOTCTRL %x write cmd %x\n",
__FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
@ -669,7 +670,8 @@ static int hpc_power_on_slot(struct slot * slot)
{
struct controller *ctrl = slot->ctrl;
u16 slot_cmd;
u16 slot_ctrl, slot_status;
u16 cmd_mask;
u16 slot_status;
int retval = 0;
DBG_ENTER_ROUTINE
@ -692,23 +694,23 @@ static int hpc_power_on_slot(struct slot * slot)
}
}
retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (retval) {
err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
return retval;
}
slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
slot_cmd = POWER_ON;
cmd_mask = PWR_CTRL;
/* Enable detection that we turned off at slot power-off time */
if (!pciehp_poll_mode)
if (!pciehp_poll_mode) {
slot_cmd = slot_cmd |
PWR_FAULT_DETECT_ENABLE |
MRL_DETECT_ENABLE |
PRSN_DETECT_ENABLE |
HP_INTR_ENABLE;
cmd_mask = cmd_mask |
PWR_FAULT_DETECT_ENABLE |
MRL_DETECT_ENABLE |
PRSN_DETECT_ENABLE |
HP_INTR_ENABLE;
}
retval = pcie_write_cmd(slot, slot_cmd);
retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
if (retval) {
err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
@ -726,21 +728,15 @@ static int hpc_power_off_slot(struct slot * slot)
{
struct controller *ctrl = slot->ctrl;
u16 slot_cmd;
u16 slot_ctrl;
u16 cmd_mask;
int retval = 0;
DBG_ENTER_ROUTINE
dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (retval) {
err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
return retval;
}
slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
slot_cmd = POWER_OFF;
cmd_mask = PWR_CTRL;
/*
* If we get MRL or presence detect interrupts now, the isr
* will notice the sticky power-fault bit too and issue power
@ -748,14 +744,19 @@ static int hpc_power_off_slot(struct slot * slot)
* of command completions, since the power-fault bit remains on
* till the slot is powered on again.
*/
if (!pciehp_poll_mode)
if (!pciehp_poll_mode) {
slot_cmd = (slot_cmd &
~PWR_FAULT_DETECT_ENABLE &
~MRL_DETECT_ENABLE &
~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
cmd_mask = cmd_mask |
PWR_FAULT_DETECT_ENABLE |
MRL_DETECT_ENABLE |
PRSN_DETECT_ENABLE |
HP_INTR_ENABLE;
}
retval = pcie_write_cmd(slot, slot_cmd);
retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
if (retval) {
err("%s: Write command failed!\n", __FUNCTION__);
return -1;
@ -775,6 +776,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
u16 temp_word;
int hp_slot = 0; /* only 1 slot per PCI Express port */
int rc = 0;
unsigned long flags;
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
@ -794,10 +796,12 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
/* Mask Hot-plug Interrupt Enable */
if (!pciehp_poll_mode) {
spin_lock_irqsave(&ctrl->lock, flags);
rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
if (rc) {
err("%s: Cannot read SLOT_CTRL register\n",
__FUNCTION__);
spin_unlock_irqrestore(&ctrl->lock, flags);
return IRQ_NONE;
}
@ -808,8 +812,10 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
if (rc) {
err("%s: Cannot write to SLOTCTRL register\n",
__FUNCTION__);
spin_unlock_irqrestore(&ctrl->lock, flags);
return IRQ_NONE;
}
spin_unlock_irqrestore(&ctrl->lock, flags);
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
@ -859,10 +865,12 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
}
/* Unmask Hot-plug Interrupt Enable */
if (!pciehp_poll_mode) {
spin_lock_irqsave(&ctrl->lock, flags);
rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
if (rc) {
err("%s: Cannot read SLOTCTRL register\n",
__FUNCTION__);
spin_unlock_irqrestore(&ctrl->lock, flags);
return IRQ_NONE;
}
@ -873,8 +881,10 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
if (rc) {
err("%s: Cannot write to SLOTCTRL register\n",
__FUNCTION__);
spin_unlock_irqrestore(&ctrl->lock, flags);
return IRQ_NONE;
}
spin_unlock_irqrestore(&ctrl->lock, flags);
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
@ -1237,6 +1247,7 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
mutex_init(&ctrl->crit_sect);
mutex_init(&ctrl->ctrl_lock);
spin_lock_init(&ctrl->lock);
/* setup wait queue */
init_waitqueue_head(&ctrl->queue);

8
drivers/pci/pci-acpi.c
View file

@ -55,8 +55,6 @@ acpi_query_osc (
status = acpi_evaluate_object(handle, "_OSC", &input, &output);
if (ACPI_FAILURE (status)) {
printk(KERN_DEBUG
"Evaluate _OSC Set fails. Status = 0x%04x\n", status);
*ret_status = status;
return status;
}
@ -124,11 +122,9 @@ acpi_run_osc (
in_params[3].buffer.pointer = (u8 *)context;
status = acpi_evaluate_object(handle, "_OSC", &input, &output);
if (ACPI_FAILURE (status)) {
printk(KERN_DEBUG
"Evaluate _OSC Set fails. Status = 0x%04x\n", status);
if (ACPI_FAILURE (status))
return status;
}
out_obj = output.pointer;
if (out_obj->type != ACPI_TYPE_BUFFER) {
printk(KERN_DEBUG

11
drivers/pci/pci-sysfs.c
View file

@ -603,6 +603,11 @@ static struct bin_attribute pcie_config_attr = {
.write = pci_write_config,
};
int __attribute__ ((weak)) pcibios_add_platform_entries(struct pci_dev *dev)
{
return 0;
}
int __must_check pci_create_sysfs_dev_files (struct pci_dev *pdev)
{
struct bin_attribute *rom_attr = NULL;
@ -642,10 +647,14 @@ int __must_check pci_create_sysfs_dev_files (struct pci_dev *pdev)
}
}
/* add platform-specific attributes */
pcibios_add_platform_entries(pdev);
if (pcibios_add_platform_entries(pdev))
goto err_rom_file;
return 0;
err_rom_file:
if (pci_resource_len(pdev, PCI_ROM_RESOURCE))
sysfs_remove_bin_file(&pdev->dev.kobj, rom_attr);
err_rom:
kfree(rom_attr);
err_resource_files:

200
drivers/pci/pci.c
View file

@ -406,6 +406,13 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
return 0;
/* find PCI PM capability in list */
pm = pci_find_capability(dev, PCI_CAP_ID_PM);
/* abort if the device doesn't support PM capabilities */
if (!pm)
return -EIO;
/* Validate current state:
* Can enter D0 from any state, but if we can only go deeper
* to sleep if we're already in a low power state
@ -418,13 +425,6 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
return 0; /* we're already there */
/* find PCI PM capability in list */
pm = pci_find_capability(dev, PCI_CAP_ID_PM);
/* abort if the device doesn't support PM capabilities */
if (!pm)
return -EIO;
pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
printk(KERN_DEBUG
@ -1186,6 +1186,11 @@ int pci_set_mwi(struct pci_dev *dev)
return 0;
}
int pci_try_set_mwi(struct pci_dev *dev)
{
return 0;
}
void pci_clear_mwi(struct pci_dev *dev)
{
}
@ -1242,9 +1247,7 @@ pci_set_cacheline_size(struct pci_dev *dev)
* pci_set_mwi - enables memory-write-invalidate PCI transaction
* @dev: the PCI device for which MWI is enabled
*
* Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
* and then calls @pcibios_set_mwi to do the needed arch specific
* operations or a generic mwi-prep function.
* Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
*
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
*/
@ -1260,7 +1263,8 @@ pci_set_mwi(struct pci_dev *dev)
pci_read_config_word(dev, PCI_COMMAND, &cmd);
if (! (cmd & PCI_COMMAND_INVALIDATE)) {
pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
pci_name(dev));
cmd |= PCI_COMMAND_INVALIDATE;
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
@ -1268,6 +1272,21 @@ pci_set_mwi(struct pci_dev *dev)
return 0;
}
/**
* pci_try_set_mwi - enables memory-write-invalidate PCI transaction
* @dev: the PCI device for which MWI is enabled
*
* Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
* Callers are not required to check the return value.
*
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
*/
int pci_try_set_mwi(struct pci_dev *dev)
{
int rc = pci_set_mwi(dev);
return rc;
}
/**
* pci_clear_mwi - disables Memory-Write-Invalidate for device dev
* @dev: the PCI device to disable
@ -1374,6 +1393,164 @@ pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
}
#endif
/**
* pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
* @dev: PCI device to query
*
* Returns mmrbc: maximum designed memory read count in bytes
* or appropriate error value.
*/
int pcix_get_max_mmrbc(struct pci_dev *dev)
{
int err, cap;
u32 stat;
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (!cap)
return -EINVAL;
err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
if (err)
return -EINVAL;
return (stat & PCI_X_STATUS_MAX_READ) >> 12;
}
EXPORT_SYMBOL(pcix_get_max_mmrbc);
/**
* pcix_get_mmrbc - get PCI-X maximum memory read byte count
* @dev: PCI device to query
*
* Returns mmrbc: maximum memory read count in bytes
* or appropriate error value.
*/
int pcix_get_mmrbc(struct pci_dev *dev)
{
int ret, cap;
u32 cmd;
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (!cap)
return -EINVAL;
ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
if (!ret)
ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
return ret;
}
EXPORT_SYMBOL(pcix_get_mmrbc);
/**
* pcix_set_mmrbc - set PCI-X maximum memory read byte count
* @dev: PCI device to query
* @mmrbc: maximum memory read count in bytes
* valid values are 512, 1024, 2048, 4096
*
* If possible sets maximum memory read byte count, some bridges have erratas
* that prevent this.
*/
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
{
int cap, err = -EINVAL;
u32 stat, cmd, v, o;
if (mmrbc < 512 || mmrbc > 4096 || (mmrbc & (mmrbc-1)))
goto out;
v = ffs(mmrbc) - 10;
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (!cap)
goto out;
err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
if (err)
goto out;
if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
return -E2BIG;
err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
if (err)
goto out;
o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
if (o != v) {
if (v > o && dev->bus &&
(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
return -EIO;
cmd &= ~PCI_X_CMD_MAX_READ;
cmd |= v << 2;
err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
}
out:
return err;
}
EXPORT_SYMBOL(pcix_set_mmrbc);
/**
* pcie_get_readrq - get PCI Express read request size
* @dev: PCI device to query
*
* Returns maximum memory read request in bytes
* or appropriate error value.
*/
int pcie_get_readrq(struct pci_dev *dev)
{
int ret, cap;
u16 ctl;
cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (!cap)
return -EINVAL;
ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
if (!ret)
ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
return ret;
}
EXPORT_SYMBOL(pcie_get_readrq);
/**
* pcie_set_readrq - set PCI Express maximum memory read request
* @dev: PCI device to query
* @count: maximum memory read count in bytes
* valid values are 128, 256, 512, 1024, 2048, 4096
*
* If possible sets maximum read byte count
*/
int pcie_set_readrq(struct pci_dev *dev, int rq)
{
int cap, err = -EINVAL;
u16 ctl, v;
if (rq < 128 || rq > 4096 || (rq & (rq-1)))
goto out;
v = (ffs(rq) - 8) << 12;
cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (!cap)
goto out;
err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
if (err)
goto out;
if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
ctl &= ~PCI_EXP_DEVCTL_READRQ;
ctl |= v;
err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
}
out:
return err;
}
EXPORT_SYMBOL(pcie_set_readrq);
/**
* pci_select_bars - Make BAR mask from the type of resource
* @dev: the PCI device for which BAR mask is made
@ -1442,6 +1619,7 @@ EXPORT_SYMBOL(pci_release_selected_regions);
EXPORT_SYMBOL(pci_request_selected_regions);
EXPORT_SYMBOL(pci_set_master);
EXPORT_SYMBOL(pci_set_mwi);
EXPORT_SYMBOL(pci_try_set_mwi);
EXPORT_SYMBOL(pci_clear_mwi);
EXPORT_SYMBOL_GPL(pci_intx);
EXPORT_SYMBOL(pci_set_dma_mask);

2
drivers/pci/pcie/aer/Kconfig
View file

@ -4,7 +4,7 @@
config PCIEAER
boolean "Root Port Advanced Error Reporting support"
depends on PCIEPORTBUS && ACPI
depends on PCIEPORTBUS
default y
help
This enables PCI Express Root Port Advanced Error Reporting

3
drivers/pci/pcie/aer/Makefile
View file

@ -4,5 +4,6 @@
obj-$(CONFIG_PCIEAER) += aerdriver.o
aerdriver-objs := aerdrv_errprint.o aerdrv_core.o aerdrv.o aerdrv_acpi.o
aerdriver-objs := aerdrv_errprint.o aerdrv_core.o aerdrv.o
aerdriver-$(CONFIG_ACPI) += aerdrv_acpi.o

2
drivers/pci/pcie/aer/aerdrv.c
View file

@ -157,7 +157,7 @@ static struct aer_rpc* aer_alloc_rpc(struct pcie_device *dev)
* Initialize Root lock access, e_lock, to Root Error Status Reg,
* Root Error ID Reg, and Root error producer/consumer index.
*/
rpc->e_lock = SPIN_LOCK_UNLOCKED;
spin_lock_init(&rpc->e_lock);
rpc->rpd = dev;
INIT_WORK(&rpc->dpc_handler, aer_isr);

14
drivers/pci/pcie/aer/aerdrv.h
View file

@ -19,10 +19,6 @@
#define AER_ERROR_MASK 0x001fffff
#define AER_ERROR(d) (d & AER_ERROR_MASK)
#define OSC_METHOD_RUN_SUCCESS 0
#define OSC_METHOD_NOT_SUPPORTED 1
#define OSC_METHOD_RUN_FAILURE 2
/* Root Error Status Register Bits */
#define ROOT_ERR_STATUS_MASKS 0x0f
@ -121,6 +117,14 @@ extern void aer_delete_rootport(struct aer_rpc *rpc);
extern int aer_init(struct pcie_device *dev);
extern void aer_isr(struct work_struct *work);
extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
extern int aer_osc_setup(struct pci_dev *dev);
#ifdef CONFIG_ACPI
extern int aer_osc_setup(struct pcie_device *pciedev);
#else
static inline int aer_osc_setup(struct pcie_device *pciedev)
{
return 0;
}
#endif
#endif //_AERDRV_H_

40
drivers/pci/pcie/aer/aerdrv_acpi.c
View file

@ -20,19 +20,18 @@
/**
* aer_osc_setup - run ACPI _OSC method
* @pciedev: pcie_device which AER is being enabled on
*
* Return:
* Zero if success. Nonzero for otherwise.
* @return: Zero on success. Nonzero otherwise.
*
* Invoked when PCIE bus loads AER service driver. To avoid conflict with
* BIOS AER support requires BIOS to yield AER control to OS native driver.
**/
int aer_osc_setup(struct pci_dev *dev)
int aer_osc_setup(struct pcie_device *pciedev)
{
int retval = OSC_METHOD_RUN_SUCCESS;
acpi_status status;
acpi_handle handle = DEVICE_ACPI_HANDLE(&dev->dev);
struct pci_dev *pdev = dev;
acpi_status status = AE_NOT_FOUND;
struct pci_dev *pdev = pciedev->port;
acpi_handle handle = DEVICE_ACPI_HANDLE(&pdev->dev);
struct pci_bus *parent;
while (!handle) {
@ -50,19 +49,20 @@ int aer_osc_setup(struct pci_dev *dev)
pdev = parent->self;
}
if (!handle)
return OSC_METHOD_NOT_SUPPORTED;
pci_osc_support_set(OSC_EXT_PCI_CONFIG_SUPPORT);
status = pci_osc_control_set(handle, OSC_PCI_EXPRESS_AER_CONTROL |
OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
if (ACPI_FAILURE(status)) {
if (status == AE_SUPPORT)
retval = OSC_METHOD_NOT_SUPPORTED;
else
retval = OSC_METHOD_RUN_FAILURE;
if (handle) {
pci_osc_support_set(OSC_EXT_PCI_CONFIG_SUPPORT);
status = pci_osc_control_set(handle,
OSC_PCI_EXPRESS_AER_CONTROL |
OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
}
return retval;
}
if (ACPI_FAILURE(status)) {
printk(KERN_DEBUG "AER service couldn't init device %s - %s\n",
pciedev->device.bus_id,
(status == AE_SUPPORT || status == AE_NOT_FOUND) ?
"no _OSC support" : "Run ACPI _OSC fails");
return -1;
}
return 0;
}

34
drivers/pci/pcie/aer/aerdrv_core.c
View file

@ -22,8 +22,6 @@
#include <linux/errno.h>
#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/acpi.h>
#include <linux/pci-acpi.h>
#include <linux/delay.h>
#include "aerdrv.h"
@ -119,6 +117,21 @@ int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
return 0;
}
int pci_cleanup_aer_correct_error_status(struct pci_dev *dev)
{
int pos;
u32 status;
pos = pci_find_aer_capability(dev);
if (!pos)
return -EIO;
pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &status);
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, status);
return 0;
}
static int find_device_iter(struct device *device, void *data)
{
struct pci_dev *dev;
@ -733,20 +746,8 @@ void aer_delete_rootport(struct aer_rpc *rpc)
**/
int aer_init(struct pcie_device *dev)
{
int status;
/* Run _OSC Method */
status = aer_osc_setup(dev->port);
if(status != OSC_METHOD_RUN_SUCCESS) {
printk(KERN_DEBUG "%s: AER service init fails - %s\n",
__FUNCTION__,
(status == OSC_METHOD_NOT_SUPPORTED) ?
"No ACPI _OSC support" : "Run ACPI _OSC fails");
if (!forceload)
return status;
}
if (aer_osc_setup(dev) && !forceload)
return -ENXIO;
return AER_SUCCESS;
}
@ -755,4 +756,5 @@ EXPORT_SYMBOL_GPL(pci_find_aer_capability);
EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status);
EXPORT_SYMBOL_GPL(pci_cleanup_aer_correct_error_status);

3
drivers/pci/probe.c
View file

@ -654,7 +654,7 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass
pcibios_assign_all_busses() ? " " :
" (try 'pci=assign-busses')");
printk(KERN_WARNING "Please report the result to "
"linux-kernel to fix this permanently\n");
"<[email protected]> to fix this permanently\n");
}
bus = bus->parent;
}
@ -700,6 +700,7 @@ static int pci_setup_device(struct pci_dev * dev)
dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
dev->revision = class & 0xff;
class >>= 8; /* upper 3 bytes */
dev->class = class;
class >>= 8;

1
drivers/pci/proc.c
View file

@ -480,7 +480,6 @@ static int __init pci_proc_init(void)
__initcall(pci_proc_init);
#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pci_proc_attach_device);
EXPORT_SYMBOL(pci_proc_detach_bus);
#endif

30
drivers/pci/quirks.c
View file

@ -587,10 +587,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_v
*/
static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
{
u8 rev;
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
if (rev >= 0x02) {
if (dev->revision >= 0x02) {
printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
}
@ -610,13 +607,12 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
#define AMD8131_NIOAMODE_BIT 0
static void quirk_amd_8131_ioapic(struct pci_dev *dev)
{
unsigned char revid, tmp;
unsigned char tmp;
if (nr_ioapics == 0)
return;
pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
pci_read_config_byte( dev, AMD8131_MISC, &tmp);
tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
@ -627,6 +623,22 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
#endif /* CONFIG_X86_IO_APIC */
/*
* Some settings of MMRBC can lead to data corruption so block changes.
* See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
*/
static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
{
unsigned char revid;
pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
if (dev->subordinate && revid <= 0x12) {
printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X "
"MMRBC\n", revid);
dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
/*
* FIXME: it is questionable that quirk_via_acpi
@ -843,10 +855,8 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, qu
static void quirk_disable_pxb(struct pci_dev *pdev)
{
u16 config;
u8 rev;
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
if (rev != 0x04) /* Only C0 requires this */
if (pdev->revision != 0x04) /* Only C0 requires this */
return;
pci_read_config_word(pdev, 0x40, &config);
if (config & (1<<6)) {

7
drivers/pci/search.c
View file

@ -139,12 +139,14 @@ struct pci_dev * pci_get_slot(struct pci_bus *bus, unsigned int devfn)
}
/**
* pci_get_bus_and_slot - locate PCI device from a given PCI slot
* pci_get_bus_and_slot - locate PCI device from a given PCI bus & slot
* @bus: number of PCI bus on which desired PCI device resides
* @devfn: encodes number of PCI slot in which the desired PCI
* device resides and the logical device number within that slot
* in case of multi-function devices.
*
* Note: the bus/slot search is limited to PCI domain (segment) 0.
*
* Given a PCI bus and slot/function number, the desired PCI device
* is located in system global list of PCI devices. If the device
* is found, a pointer to its data structure is returned. If no
@ -157,7 +159,8 @@ struct pci_dev * pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
struct pci_dev *dev = NULL;
while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
if (dev->bus->number == bus && dev->devfn == devfn)
if (pci_domain_nr(dev->bus) == 0 &&
(dev->bus->number == bus && dev->devfn == devfn))
return dev;
}
return NULL;

8
drivers/pci/setup-bus.c
View file

@ -34,8 +34,6 @@
#define DBG(x...)
#endif
#define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
static void pbus_assign_resources_sorted(struct pci_bus *bus)
{
struct pci_dev *dev;
@ -310,7 +308,7 @@ static void pbus_size_io(struct pci_bus *bus)
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
size = (size & 0xff) + ((size & ~0xffUL) << 2);
#endif
size = ROUND_UP(size + size1, 4096);
size = ALIGN(size + size1, 4096);
if (!size) {
b_res->flags = 0;
return;
@ -378,11 +376,11 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
if (!align)
min_align = align1;
else if (ROUND_UP(align + min_align, min_align) < align1)
else if (ALIGN(align + min_align, min_align) < align1)
min_align = align1 >> 1;
align += aligns[order];
}
size = ROUND_UP(size, min_align);
size = ALIGN(size, min_align);
if (!size) {
b_res->flags = 0;
return 1;

20
drivers/pci/syscall.c
View file

@ -23,14 +23,14 @@ sys_pciconfig_read(unsigned long bus, unsigned long dfn,
u8 byte;
u16 word;
u32 dword;
long err, cfg_ret;
long err;
long cfg_ret;
err = -EPERM;
if (!capable(CAP_SYS_ADMIN))
goto error;
return -EPERM;
err = -ENODEV;
dev = pci_find_slot(bus, dfn);
dev = pci_get_bus_and_slot(bus, dfn);
if (!dev)
goto error;
@ -66,7 +66,8 @@ sys_pciconfig_read(unsigned long bus, unsigned long dfn,
case 4:
err = put_user(dword, (unsigned int __user *)buf);
break;
};
}
pci_dev_put(dev);
return err;
error:
@ -83,7 +84,8 @@ error:
case 4:
put_user(-1, (unsigned int __user *)buf);
break;
};
}
pci_dev_put(dev);
return err;
}
@ -101,7 +103,7 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
dev = pci_find_slot(bus, dfn);
dev = pci_get_bus_and_slot(bus, dfn);
if (!dev)
return -ENODEV;
@ -137,8 +139,8 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
default:
err = -EINVAL;
break;
};
}
unlock_kernel();
pci_dev_put(dev);
return err;
}

9
drivers/scsi/aic94xx/aic94xx_init.c
View file

@ -223,13 +223,8 @@ static int __devinit asd_common_setup(struct asd_ha_struct *asd_ha)
{
int err, i;
err = pci_read_config_byte(asd_ha->pcidev, PCI_REVISION_ID,
&asd_ha->revision_id);
if (err) {
asd_printk("couldn't read REVISION ID register of %s\n",
pci_name(asd_ha->pcidev));
goto Err;
}
asd_ha->revision_id = asd_ha->pcidev->revision;
err = -ENODEV;
if (asd_ha->revision_id < AIC9410_DEV_REV_B0) {
asd_printk("%s is revision %s (%X), which is not supported\n",

22
drivers/scsi/ipr.c
View file

@ -5373,18 +5373,12 @@ static const u16 ipr_blocked_processors[] = {
**/
static int ipr_invalid_adapter(struct ipr_ioa_cfg *ioa_cfg)
{
u8 rev_id;
int i;
if (ioa_cfg->type == 0x5702) {
if (pci_read_config_byte(ioa_cfg->pdev, PCI_REVISION_ID,
&rev_id) == PCIBIOS_SUCCESSFUL) {
if (rev_id < 4) {
for (i = 0; i < ARRAY_SIZE(ipr_blocked_processors); i++){
if (__is_processor(ipr_blocked_processors[i]))
return 1;
}
}
if ((ioa_cfg->type == 0x5702) && (ioa_cfg->pdev->revision < 4)) {
for (i = 0; i < ARRAY_SIZE(ipr_blocked_processors); i++){
if (__is_processor(ipr_blocked_processors[i]))
return 1;
}
}
return 0;
@ -7541,13 +7535,7 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev,
else
ioa_cfg->transop_timeout = IPR_OPERATIONAL_TIMEOUT;
rc = pci_read_config_byte(pdev, PCI_REVISION_ID, &ioa_cfg->revid);
if (rc != PCIBIOS_SUCCESSFUL) {
dev_err(&pdev->dev, "Failed to read PCI revision ID\n");
rc = -EIO;
goto out_scsi_host_put;
}
ioa_cfg->revid = pdev->revision;
ipr_regs_pci = pci_resource_start(pdev, 0);

9
drivers/scsi/ips.c
View file

@ -7148,7 +7148,6 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
uint32_t mem_addr;
uint32_t io_len;
uint32_t mem_len;
uint8_t revision_id;
uint8_t bus;
uint8_t func;
uint8_t irq;
@ -7227,12 +7226,6 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
}
}
/* get the revision ID */
if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) {
IPS_PRINTK(KERN_WARNING, pci_dev, "Can't get revision id.\n");
return -1;
}
subdevice_id = pci_dev->subsystem_device;
/* found a controller */
@ -7258,7 +7251,7 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
ha->mem_ptr = mem_ptr;
ha->ioremap_ptr = ioremap_ptr;
ha->host_num = (uint32_t) index;
ha->revision_id = revision_id;
ha->revision_id = pci_dev->revision;
ha->slot_num = PCI_SLOT(pci_dev->devfn);
ha->device_id = pci_dev->device;
ha->subdevice_id = subdevice_id;

5
drivers/scsi/lpfc/lpfc_init.c
View file

@ -1578,10 +1578,7 @@ lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
INIT_LIST_HEAD(&phba->fc_nodes);
pci_set_master(pdev);
retval = pci_set_mwi(pdev);
if (retval)
dev_printk(KERN_WARNING, &pdev->dev,
"Warning: pci_set_mwi returned %d\n", retval);
pci_try_set_mwi(pdev);
if (pci_set_dma_mask(phba->pcidev, DMA_64BIT_MASK) != 0)
if (pci_set_dma_mask(phba->pcidev, DMA_32BIT_MASK) != 0)

10
drivers/scsi/nsp32.c
View file

@ -3487,15 +3487,6 @@ static int nsp32_resume(struct pci_dev *pdev)
return 0;
}
/* Enable wake event */
static int nsp32_enable_wake(struct pci_dev *pdev, pci_power_t state, int enable)
{
struct Scsi_Host *host = pci_get_drvdata(pdev);
nsp32_msg(KERN_INFO, "pci-enable_wake: stub, pdev=0x%p, enable=%d, slot=%s, host=0x%p", pdev, enable, pci_name(pdev), host);
return 0;
}
#endif
/************************************************************************
@ -3571,7 +3562,6 @@ static struct pci_driver nsp32_driver = {
#ifdef CONFIG_PM
.suspend = nsp32_suspend,
.resume = nsp32_resume,
.enable_wake = nsp32_enable_wake,
#endif
};

2
drivers/scsi/qla2xxx/qla_init.c
View file

@ -296,7 +296,7 @@ qla24xx_pci_config(scsi_qla_host_t *ha)
d &= ~PCI_ROM_ADDRESS_ENABLE;
pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d);
pci_read_config_word(ha->pdev, PCI_REVISION_ID, &ha->chip_revision);
ha->chip_revision = ha->pdev->revision;
/* Get PCI bus information. */
spin_lock_irqsave(&ha->hardware_lock, flags);

2
drivers/serial/jsm/jsm_driver.c
View file

@ -88,7 +88,7 @@ static int jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
spin_lock_init(&brd->bd_intr_lock);
/* store which revision we have */
pci_read_config_byte(pdev, PCI_REVISION_ID, &brd->rev);
brd->rev = pdev->revision;
brd->irq = pdev->irq;

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