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clk: imx7d: create clocks behind rawnand clock gate
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <[email protected]> Tested-by: Fabio Estevam <[email protected]> Acked-by: Han Xu <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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2 changed files with 7 additions and 3 deletions
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@ -450,5 +450,7 @@
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#define IMX7D_CLK_ARM 437
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#define IMX7D_CKIL 438
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#define IMX7D_OCOTP_CLK 439
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#define IMX7D_CLK_END 440
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#define IMX7D_NAND_RAWNAND_CLK 440
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#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
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#define IMX7D_CLK_END 442
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#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
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