mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 21:54:34 -04:00
Merge "ARM: dts: msm: Add all clock controller and gdsc nodes for scshrike"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
2300427621
6 changed files with 823 additions and 0 deletions
47
qcom/sa8195-gdsc.dtsi
Normal file
47
qcom/sa8195-gdsc.dtsi
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
#include "sm8150-gdsc.dtsi"
|
||||
|
||||
&soc {
|
||||
/* GDSCs in Global CC */
|
||||
pcie_2_gdsc: qcom,gdsc@19d004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x19d004 0x4>;
|
||||
regulator-name = "pcie_2_gdsc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie_3_gdsc: qcom,gdsc@1a3004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x1a3004 0x4>;
|
||||
regulator-name = "pcie_3_gdsc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_card_2_gdsc: qcom,gdsc@1a2004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x1a2004 0x4>;
|
||||
regulator-name = "ufs_card_2_gdsc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb30_mp_gdsc: qcom,gdsc@1a6004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x1a6004 0x4>;
|
||||
regulator-name = "usb30_mp_gdsc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* GDSCs in Camera CC */
|
||||
ife_2_gdsc: qcom,gdsc@ad0f004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xad0f004 0x4>;
|
||||
regulator-name = "ife_2_gdsc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ife_3_gdsc: qcom,gdsc@ad0f070 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xad0f070 0x4>;
|
||||
regulator-name = "ife_3_gdsc";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -59,4 +59,13 @@
|
|||
/delete-node/ refgen;
|
||||
};
|
||||
|
||||
&camcc {
|
||||
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
};
|
||||
|
||||
&gpu_gx_gdsc {
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
};
|
||||
|
||||
#include "sa8195p-regulator.dtsi"
|
||||
|
|
|
|||
84
qcom/sa8195-smp2p.dtsi
Normal file
84
qcom/sa8195-smp2p.dtsi
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
&soc {
|
||||
|
||||
qcom,smp2p-modem {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <435>, <428>;
|
||||
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,ipc = <&apcs 0 14>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <1>;
|
||||
|
||||
modem_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
modem_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-adsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <443>, <429>;
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,ipc = <&apcs 0 10>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <2>;
|
||||
|
||||
adsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
adsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-dsps {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <481>, <430>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,ipc = <&apcs 0 26>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <3>;
|
||||
|
||||
dsps_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
dsps_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-cdsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <94>, <432>;
|
||||
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,ipc = <&apcs 0 6>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <5>;
|
||||
|
||||
cdsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
cdsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -7,3 +7,7 @@
|
|||
qcom,msm-id = <405 0x20000>;
|
||||
};
|
||||
|
||||
&scc {
|
||||
vdd_scc_cx-supply = <&VDD_SCC_CX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,3 +6,28 @@
|
|||
qcom,msm-id = <340 0x20000>;
|
||||
};
|
||||
|
||||
/delete-node/ &ufs_card_gdsc;
|
||||
|
||||
&camcc {
|
||||
compatible = "qcom,scshrike-camcc-v2", "syscon";
|
||||
};
|
||||
|
||||
&dispcc {
|
||||
compatible = "qcom,scshrike-dispcc-v2", "syscon";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
compatible = "qcom,scshrike-gcc-v2", "syscon";
|
||||
};
|
||||
|
||||
&npucc {
|
||||
compatible = "qcom,sm8150-npucc-v2", "syscon";
|
||||
};
|
||||
|
||||
&scc {
|
||||
compatible = "qcom,sa8195-scc-v2", "syscon";
|
||||
};
|
||||
|
||||
&videocc {
|
||||
compatible = "qcom,sm8150-videocc-v2", "syscon";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,3 +1,11 @@
|
|||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,camcc-scshrike.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-scshrike.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-scshrike.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,npucc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,scc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interconnect/qcom,scshrike.h>
|
||||
|
|
@ -579,6 +587,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
xo_board: xo-board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <38400000>;
|
||||
clock-output-names = "xo_board";
|
||||
};
|
||||
|
||||
sleep_clk: sleep-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32000>;
|
||||
clock-output-names = "sleep_clk";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-imem@146bf000 {
|
||||
compatible = "qcom,msm-imem";
|
||||
reg = <0x146bf000 0x1000>;
|
||||
|
|
@ -654,6 +678,12 @@
|
|||
compatible = "qcom,bcm-voter";
|
||||
};
|
||||
|
||||
rpmhcc: clock-controller {
|
||||
compatible = "qcom,sm8150-rpmh-clk";
|
||||
#clock-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
system_pm {
|
||||
compatible = "qcom,system-pm";
|
||||
};
|
||||
|
|
@ -763,6 +793,439 @@
|
|||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
qmp_aop: qcom,qmp-aop@c300000 {
|
||||
compatible = "qcom,qmp-mbox";
|
||||
reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
|
||||
reg-names = "msgram", "irq-reg-base";
|
||||
qcom,irq-mask = <0x1>;
|
||||
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "aop";
|
||||
qcom,early-boot;
|
||||
priority = <0>;
|
||||
mbox-desc-offset = <0x0>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
aopcc: qcom,aopcc@0 {
|
||||
compatible = "qcom,aop-qmp-clk";
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "qdss_clk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,scshrike-gcc", "syscon";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names =
|
||||
"bi_tcxo",
|
||||
"bi_tcxo_ao",
|
||||
"sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
scc: clock-controller@2b10000 {
|
||||
compatible = "qcom,sa8195-scc";
|
||||
reg = <0x2b10000 0x30000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpucc: clock-controller@2c90000 {
|
||||
compatible = "qcom,scshrike-gpucc", "syscon";
|
||||
reg = <0x2c90000 0x9000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
npucc: clock-controller@9910000 {
|
||||
compatible = "qcom,sm8150-npucc", "syscon";
|
||||
reg = <0x9910000 0x10000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_gdsc-supply = <&npu_core_gdsc>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
|
||||
<&gcc GCC_NPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_NPU_AXI_CLK>;
|
||||
clock-names =
|
||||
"bi_tcxo",
|
||||
"gcc_npu_gpll0_div_clk_src",
|
||||
"gcc_npu_gpll0_clk_src",
|
||||
"gcc_npu_axi_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
videocc: clock-controller@ab00000 {
|
||||
compatible = "qcom,sm8150-videocc", "syscon";
|
||||
reg = <0xab00000 0x10000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names =
|
||||
"cfg_ahb_clk",
|
||||
"bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
camcc: clock-controller@ad00000 {
|
||||
compatible = "qcom,scshrike-camcc", "syscon";
|
||||
reg = <0xad00000 0x20000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names =
|
||||
"cfg_ahb_clk",
|
||||
"bi_tcxo",
|
||||
"sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
dispcc: clock-controller@af00000 {
|
||||
compatible = "qcom,scshrike-dispcc", "syscon";
|
||||
reg = <0xaf00000 0x20000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names =
|
||||
"cfg_ahb_clk",
|
||||
"bi_tcxo",
|
||||
"sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
apsscc: syscon@182a0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x182a0000 0x1c>;
|
||||
};
|
||||
|
||||
mccc: syscon@90b0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x90b0000 0x54>;
|
||||
};
|
||||
|
||||
debugcc: debug-clock-controller@0 {
|
||||
compatible = "qcom,scshrike-debugcc";
|
||||
qcom,gcc = <&gcc>;
|
||||
qcom,videocc = <&videocc>;
|
||||
qcom,camcc = <&camcc>;
|
||||
qcom,dispcc = <&dispcc>;
|
||||
qcom,npucc = <&npucc>;
|
||||
qcom,gpucc = <&gpucc>;
|
||||
qcom,apsscc = <&apsscc>;
|
||||
qcom,mccc = <&mccc>;
|
||||
clock-names = "xo_clk_src";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
tcsr_mutex_block: syscon@1f40000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1f40000 0x20000>;
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock@1f40000 {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
syscon = <&tcsr_mutex_block 0 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
smem: qcom,smem@8600000 {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_region>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
apcs: syscon@17c0000c {
|
||||
compatible = "syscon";
|
||||
reg = <0x17c0000c 0x4>;
|
||||
};
|
||||
|
||||
apss_shared: mailbox@17c00000 {
|
||||
compatible = "qcom,sm8150-apss-shared";
|
||||
reg = <0x17c00000 0x1000>;
|
||||
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
sp_scsr: mailbox@188501c {
|
||||
compatible = "qcom,sm8150-spcs-global";
|
||||
reg = <0x188501c 0x4>;
|
||||
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
sp_scsr_block: syscon@1880000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1880000 0x10000>;
|
||||
};
|
||||
|
||||
intsp: qcom,qsee_irq {
|
||||
compatible = "qcom,sm8150-qsee-irq";
|
||||
|
||||
syscon = <&sp_scsr_block>;
|
||||
interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 349 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-names = "sp_ipc0",
|
||||
"sp_ipc1";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
qcom,qsee_irq_bridge {
|
||||
compatible = "qcom,qsee-ipc-irq-bridge";
|
||||
|
||||
qcom,qsee-ipc-irq-spss {
|
||||
qcom,dev-name = "qsee_ipc_irq_spss";
|
||||
label = "spss";
|
||||
interrupt-parent = <&intsp>;
|
||||
interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,glink {
|
||||
compatible = "qcom,glink";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
glink_modem: modem {
|
||||
qcom,remote-pid = <1>;
|
||||
transport = "smem";
|
||||
mboxes = <&apss_shared 12>;
|
||||
mbox-names = "mpss_smem";
|
||||
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "modem";
|
||||
qcom,glink-label = "mpss";
|
||||
|
||||
qcom,modem_qrtr {
|
||||
qcom,glink-channels = "IPCRTR";
|
||||
qcom,low-latency;
|
||||
qcom,intents = <0x800 5
|
||||
0x2000 3
|
||||
0x4400 2>;
|
||||
};
|
||||
|
||||
qcom,msm_fastrpc_rpmsg {
|
||||
compatible = "qcom,msm-fastrpc-rpmsg";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
};
|
||||
|
||||
qcom,modem_glink_ssr {
|
||||
qcom,glink-channels = "glink_ssr";
|
||||
qcom,notify-edges = <&glink_adsp>,
|
||||
<&glink_slpi>,
|
||||
<&glink_cdsp>,
|
||||
<&glink_spss>;
|
||||
};
|
||||
};
|
||||
|
||||
glink_adsp: adsp {
|
||||
qcom,remote-pid = <2>;
|
||||
transport = "smem";
|
||||
mboxes = <&apss_shared 8>;
|
||||
mbox-names = "adsp_smem";
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "adsp";
|
||||
qcom,glink-label = "lpass";
|
||||
cpu-affinity = <1 2>;
|
||||
|
||||
qcom,adsp_qrtr {
|
||||
qcom,glink-channels = "IPCRTR";
|
||||
qcom,intents = <0x800 5
|
||||
0x2000 3
|
||||
0x4400 2>;
|
||||
};
|
||||
|
||||
qcom,apr_tal_rpmsg {
|
||||
qcom,glink-channels = "apr_audio_svc";
|
||||
qcom,intents = <0x200 20>;
|
||||
};
|
||||
|
||||
qcom,msm_fastrpc_rpmsg {
|
||||
compatible = "qcom,msm-fastrpc-rpmsg";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
};
|
||||
|
||||
qcom,adsp_glink_ssr {
|
||||
qcom,glink-channels = "glink_ssr";
|
||||
qcom,notify-edges = <&glink_modem>,
|
||||
<&glink_slpi>,
|
||||
<&glink_cdsp>;
|
||||
};
|
||||
};
|
||||
|
||||
glink_slpi: dsps {
|
||||
qcom,remote-pid = <3>;
|
||||
transport = "smem";
|
||||
mboxes = <&apss_shared 24>;
|
||||
mbox-names = "dsps_smem";
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "slpi";
|
||||
qcom,glink-label = "dsps";
|
||||
|
||||
qcom,slpi_qrtr {
|
||||
qcom,glink-channels = "IPCRTR";
|
||||
qcom,low-latency;
|
||||
qcom,intents = <0x800 5
|
||||
0x2000 3
|
||||
0x4400 2>;
|
||||
};
|
||||
|
||||
qcom,msm_fastrpc_rpmsg {
|
||||
compatible = "qcom,msm-fastrpc-rpmsg";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
};
|
||||
|
||||
qcom,slpi_glink_ssr {
|
||||
qcom,glink-channels = "glink_ssr";
|
||||
qcom,notify-edges = <&glink_modem>,
|
||||
<&glink_adsp>,
|
||||
<&glink_cdsp>;
|
||||
};
|
||||
};
|
||||
|
||||
glink_cdsp: cdsp {
|
||||
qcom,remote-pid = <5>;
|
||||
transport = "smem";
|
||||
mboxes = <&apss_shared 4>;
|
||||
mbox-names = "cdsp_smem";
|
||||
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "cdsp";
|
||||
qcom,glink-label = "cdsp";
|
||||
|
||||
qcom,cdsp_qrtr {
|
||||
qcom,glink-channels = "IPCRTR";
|
||||
qcom,intents = <0x800 5
|
||||
0x2000 3
|
||||
0x4400 2>;
|
||||
};
|
||||
|
||||
qcom,msm_fastrpc_rpmsg {
|
||||
compatible = "qcom,msm-fastrpc-rpmsg";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
};
|
||||
|
||||
qcom,cdsp_glink_ssr {
|
||||
qcom,glink-channels = "glink_ssr";
|
||||
qcom,notify-edges = <&glink_modem>,
|
||||
<&glink_adsp>,
|
||||
<&glink_slpi>;
|
||||
};
|
||||
};
|
||||
|
||||
glink_spss: spss {
|
||||
qcom,remote-pid = <8>;
|
||||
transport = "spss";
|
||||
mboxes = <&sp_scsr 0>;
|
||||
mbox-names = "spss_spss";
|
||||
interrupt-parent = <&intsp>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
reg = <0x1885008 0x8>,
|
||||
<0x1885010 0x4>;
|
||||
reg-names = "qcom,spss-addr",
|
||||
"qcom,spss-size";
|
||||
|
||||
label = "spss";
|
||||
qcom,glink-label = "spss";
|
||||
|
||||
qcom,spss_glink_ssr {
|
||||
qcom,glink-channels = "glink_ssr";
|
||||
qcom,notify-edges = <&glink_modem>;
|
||||
};
|
||||
};
|
||||
|
||||
glink_spi_xprt_wdsp: wdsp {
|
||||
qcom,remote-pid = <10>;
|
||||
transport = "spi";
|
||||
tx-descriptors = <0x12000 0x12004>;
|
||||
rx-descriptors = <0x1200c 0x12010>;
|
||||
|
||||
label = "wdsp";
|
||||
qcom,glink-label = "wdsp";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,glinkpkt {
|
||||
compatible = "qcom,glinkpkt";
|
||||
|
||||
qcom,glinkpkt-at-mdm0 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DS";
|
||||
qcom,glinkpkt-dev-name = "at_mdm0";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-apr-apps2 {
|
||||
qcom,glinkpkt-edge = "adsp";
|
||||
qcom,glinkpkt-ch-name = "apr_apps2";
|
||||
qcom,glinkpkt-dev-name = "apr_apps2";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data40-cntl {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
||||
qcom,glinkpkt-dev-name = "smdcntl8";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data1 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA1";
|
||||
qcom,glinkpkt-dev-name = "smd7";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data4 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA4";
|
||||
qcom,glinkpkt-dev-name = "smd8";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data11 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA11";
|
||||
qcom,glinkpkt-dev-name = "smd11";
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x00ac0000 0x6000>;
|
||||
|
|
@ -784,3 +1247,194 @@
|
|||
#include "sdmshrike-pinctrl.dtsi"
|
||||
#include "sa8195-regulator.dtsi"
|
||||
#include "sm8150-pm.dtsi"
|
||||
#include "sa8195-smp2p.dtsi"
|
||||
#include "sa8195-gdsc.dtsi"
|
||||
|
||||
&emac_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&pcie_0_gdsc {
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&pcie_1_gdsc {
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&pcie_2_gdsc {
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&pcie_3_gdsc {
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ufs_card_2_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ufs_card_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ufs_phy_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&usb30_mp_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&usb30_prim_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&usb30_sec_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&bps_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ife_0_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ife_1_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ife_2_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ife_3_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ipe_0_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ipe_1_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&titan_top_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mdss_core_gdsc {
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&gpu_cx_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&gpu_gx_gdsc {
|
||||
parent-supply = <&VDD_GFX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&npu_core_gdsc {
|
||||
clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mvs0_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mvs1_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mvsc_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MMCX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue