diff --git a/hw/qca6750/v1/lithium_top_reg.h b/hw/qca6750/v1/lithium_top_reg.h index f1ca3294736c..415b1d02a13c 100644 --- a/hw/qca6750/v1/lithium_top_reg.h +++ b/hw/qca6750/v1/lithium_top_reg.h @@ -21,6 +21,7 @@ ////////////////////////////////////////////////////////////////////////////// // **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!! ////////////////////////////////////////////////////////////////////////////// +// // // RCS File : -USE CVS LOG- // Revision : -USE CVS LOG- @@ -26661,29 +26662,23 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_RXTD_ABTCF_CONFIG_L (0x003A2668) #define PHYA_RXTD_ABTCF_CONFIG_L___RWC QCSR_REG_RW -#define PHYA_RXTD_ABTCF_CONFIG_L___POR 0x00000078 +#define PHYA_RXTD_ABTCF_CONFIG_L___POR 0x00440C78 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_BACKOFF_LOW___POR 0x08 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_RISING_EDGE_THR_LOW___POR 0x103 #define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___POR 0x03C #define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___POR 0x0 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_BACKOFF_LOW___M 0x07F80000 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_BACKOFF_LOW___S 19 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_RISING_EDGE_THR_LOW___M 0x0007FC00 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_RISING_EDGE_THR_LOW___S 10 #define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___M 0x000003FE #define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___S 1 #define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___M 0x00000001 #define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___S 0 -#define PHYA_RXTD_ABTCF_CONFIG_L___M 0x000003FF +#define PHYA_RXTD_ABTCF_CONFIG_L___M 0x07FFFFFF #define PHYA_RXTD_ABTCF_CONFIG_L___S 0 -#define PHYA_RXTD_ABTCF_CONFIG_2_L (0x003A2670) -#define PHYA_RXTD_ABTCF_CONFIG_2_L___RWC QCSR_REG_RW -#define PHYA_RXTD_ABTCF_CONFIG_2_L___POR 0x00001103 -#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___POR 0x08 -#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___POR 0x103 -#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___M 0x0001FE00 -#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___S 9 -#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___M 0x000001FF -#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___S 0 -#define PHYA_RXTD_ABTCF_CONFIG_2_L___M 0x0001FFFF -#define PHYA_RXTD_ABTCF_CONFIG_2_L___S 0 - -#define PHYA_RXTD_ECTE_CONFIG_L (0x003A2678) +#define PHYA_RXTD_ECTE_CONFIG_L (0x003A2670) #define PHYA_RXTD_ECTE_CONFIG_L___RWC QCSR_REG_RW #define PHYA_RXTD_ECTE_CONFIG_L___POR 0x001EF780 #define PHYA_RXTD_ECTE_CONFIG_L__ECTE_DETECT_THRESH___POR 0x3DE @@ -40116,12 +40111,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_PHYRF_RXCORR_CTRL_1_L (0x00480120) #define PHYA_PHYRF_RXCORR_CTRL_1_L___RWC QCSR_REG_RW #define PHYA_PHYRF_RXCORR_CTRL_1_L___POR 0x00000400 -#define PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_SPARE1___POR 0x0 #define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___POR 0x0 #define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_CENTER_TAP___POR 0x4 #define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_USE_ONETAP___POR 0x0 -#define PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___M 0x01000000 -#define PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___S 24 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_SPARE1___M 0x01000000 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_SPARE1___S 24 #define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___M 0x00010000 #define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___S 16 #define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_CENTER_TAP___M 0x00000F00 @@ -42725,53 +42720,53 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___M 0xFFFFFFFF #define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n(n) (0x00481AA8+0x8*(n)) -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_nMIN 0 -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_nMAX 0 -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_ELEM 1 -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___RWC QCSR_REG_RW -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___POR 0x00000000 -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___POR 0x0000 -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___M 0x00003FFF -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___M 0x00003FFF -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0 (0x00481AA8) -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0___RWC QCSR_REG_RW -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0__MEM_ADDR___M 0x00003FFF -#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0__MEM_ADDR___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n(n) (0x00481AA8+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n__MEM_ADDR_DUMMY___POR 0x0000 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n__MEM_ADDR_DUMMY___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n__MEM_ADDR_DUMMY___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_0 (0x00481AA8) +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_0__MEM_ADDR_DUMMY___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_DUMMY_L_0__MEM_ADDR_DUMMY___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n(n) (0x00481AB0+0x8*(n)) -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_nMIN 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_nMAX 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_ELEM 1 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___RWC QCSR_REG_RW -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___POR 0x00000000 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___POR 0x00000000 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___M 0xFFFFFFFF -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___M 0xFFFFFFFF -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0 (0x00481AB0) -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0___RWC QCSR_REG_RW -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0__MEM_DATA_L32___M 0xFFFFFFFF -#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0__MEM_DATA_L32___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n(n) (0x00481AB0+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n___POR 0xDEADC0DE +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n__MEM_DATA_L32_DUMMY___POR 0xDEADC0DE +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n__MEM_DATA_L32_DUMMY___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n__MEM_DATA_L32_DUMMY___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_0 (0x00481AB0) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_0__MEM_DATA_L32_DUMMY___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_L_0__MEM_DATA_L32_DUMMY___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n(n) (0x00481AB4+0x8*(n)) -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_nMIN 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_nMAX 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_ELEM 1 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___RWC QCSR_REG_RW -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___POR 0x00000000 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___POR 0x00000000 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___M 0xFFFFFFFF -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___M 0xFFFFFFFF -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___S 0 -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0 (0x00481AB4) -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0___RWC QCSR_REG_RW -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0__MEM_DATA_U32___M 0xFFFFFFFF -#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0__MEM_DATA_U32___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n(n) (0x00481AB4+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n___POR 0xDEADC0DE +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n__MEM_DATA_U32_DUMMY___POR 0xDEADC0DE +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n__MEM_DATA_U32_DUMMY___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n__MEM_DATA_U32_DUMMY___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_0 (0x00481AB4) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_0__MEM_DATA_U32_DUMMY___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_DUMMY_U_0__MEM_DATA_U32_DUMMY___S 0 #define PHYA_PHYRF_PHYDBG_MODE_L (0x00481AD0) #define PHYA_PHYRF_PHYDBG_MODE_L___RWC QCSR_REG_RW @@ -43626,6 +43621,54 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_PHYRF_TS_TIMER1_CTRL_1_L___M 0x00000001 #define PHYA_PHYRF_TS_TIMER1_CTRL_1_L___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n(n) (0x00489C98+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___POR 0x0000 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0 (0x00489C98) +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0__MEM_ADDR___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0__MEM_ADDR___S 0 + +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n(n) (0x00489CA0+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0 (0x00489CA0) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0__MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0__MEM_DATA_L32___S 0 + +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n(n) (0x00489CA4+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0 (0x00489CA4) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0__MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0__MEM_DATA_U32___S 0 + #define PHYA_PHYRF_PAPRD_CTRL_L_B0 (0x00490000) #define PHYA_PHYRF_PAPRD_CTRL_L_B0___RWC QCSR_REG_RW #define PHYA_PHYRF_PAPRD_CTRL_L_B0___POR 0x001F8000 @@ -80379,17 +80422,23 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG (0x005D4040) #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___POR 0x00000001 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___POR 0x00000007 #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_BT___POR 0x1 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_CH1___POR 0x1 #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___M 0x00008000 #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___S 15 #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___M 0x00004000 #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___S 14 -#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___M 0x00000001 -#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___S 0 -#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___M 0x0000C001 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_BT___M 0x00000004 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_BT___S 2 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_CH0___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_CH0___S 1 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_CH1___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL_CH1___S 0 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___M 0x0000C007 #define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___S 0 #define PHYA_IRON2G_RFA_AON_AOA (0x005D4044) @@ -80458,39 +80507,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_RO_PM___M 0x0001FFFF #define PHYA_IRON2G_RFA_AON_RO_PM___S 0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC (0x005D4050) -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC___POR 0x00000000 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___POR 0x00 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___POR 0x0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___M 0x80000000 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___S 31 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___M 0x40000000 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___S 30 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___M 0x20000000 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___S 29 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___M 0x1FC00000 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___S 22 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___M 0x00008000 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___S 15 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___M 0x00004000 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___S 14 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___M 0x00002000 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___S 13 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___M 0x00000018 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___S 3 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___M 0x00000001 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___S 0 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC___M 0xFFC0E019 -#define PHYA_IRON2G_RFA_AON_WL_BT_CONC___S 0 - #define PHYA_IRON2G_RFA_AON_ATB (0x005D4054) #define PHYA_IRON2G_RFA_AON_ATB___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_AON_ATB___POR 0x00000000 @@ -81402,21 +81418,19 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G (0x005D4114) #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___POR 0x00A000A0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___POR 0x00800080 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH0_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH0___POR 0x1 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___POR 0x0 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___POR 0x1 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH1_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH1___POR 0x1 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___POR 0x1 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___S 30 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH0_OVS___M 0x30000000 @@ -81429,8 +81443,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH0___S 23 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___M 0x00400000 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___S 22 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___M 0x00200000 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___S 21 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___M 0x0000C000 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___S 14 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH1_OVS___M 0x00003000 @@ -81443,28 +81455,24 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH1___S 7 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___M 0x00000040 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___S 6 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___M 0x00000020 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___S 5 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___M 0xFFE0FFE0 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___S 5 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___S 6 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G (0x005D4118) #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___POR 0x00A000A0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___POR 0x00800080 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH0_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH0___POR 0x1 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___POR 0x0 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___POR 0x1 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH1_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH1___POR 0x1 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___POR 0x1 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___S 30 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH0_OVS___M 0x30000000 @@ -81477,8 +81485,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH0___S 23 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___M 0x00400000 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___S 22 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___M 0x00200000 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___S 21 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___M 0x0000C000 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___S 14 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH1_OVS___M 0x00003000 @@ -81491,10 +81497,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH1___S 7 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___M 0x00000040 #define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___S 6 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___M 0x00000020 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___S 5 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___M 0xFFE0FFE0 -#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___S 5 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___S 6 #define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G (0x005D411C) #define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___RWC QCSR_REG_RW @@ -81787,6 +81791,30 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___M 0xFFFFF000 #define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM (0x005D413C) +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM___POR 0x03608000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__LDO_REFGEN_WL_SYNTH0_SDM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_REFGEN_WL_SYNTH0_SDM_ISEL_IR12P5___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_REFGEN_WL_SYNTH0_SDM_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__LDO_WL_SYNTH0_SDM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_WL_SYNTH0_SDM_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_WL_SYNTH0_SDM_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__LDO_REFGEN_WL_SYNTH0_SDM_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__LDO_REFGEN_WL_SYNTH0_SDM_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_REFGEN_WL_SYNTH0_SDM_ISEL_IR12P5___M 0x07000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_REFGEN_WL_SYNTH0_SDM_ISEL_IR12P5___S 24 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_REFGEN_WL_SYNTH0_SDM_ISEL_IC25___M 0x00E00000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_REFGEN_WL_SYNTH0_SDM_ISEL_IC25___S 21 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__LDO_WL_SYNTH0_SDM_EN_OVS___M 0x00180000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__LDO_WL_SYNTH0_SDM_EN_OVS___S 19 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_WL_SYNTH0_SDM_BYPASS___M 0x00040000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_WL_SYNTH0_SDM_BYPASS___S 18 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_WL_SYNTH0_SDM_OTA_CUR___M 0x00038000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM__D_LDO_WL_SYNTH0_SDM_OTA_CUR___S 15 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM___M 0xC7FF8000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH0_SDM___S 15 + #define PHYA_IRON2G_RFA_AON_TOP_0 (0x005D4140) #define PHYA_IRON2G_RFA_AON_TOP_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_AON_TOP_0___POR 0x31848948 @@ -81903,27 +81931,21 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS (0x005D414C) #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___POR 0x16000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___POR 0x00000000 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___POR 0x0 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___POR 0x1 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___POR 0x1 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___POR 0x1 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___M 0x40000000 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___S 30 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___M 0x20000000 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___S 29 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___M 0x10000000 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___S 28 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___M 0x04000000 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___S 26 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___M 0x02000000 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___S 25 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___M 0x01000000 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___S 24 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___M 0x77000000 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___S 24 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___M 0x66000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___S 25 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV (0x005D4150) #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___RWC QCSR_REG_RW @@ -81934,10 +81956,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH1_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH0_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH0_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH0_OVS___S 30 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH1_OVS___M 0x30000000 @@ -81950,16 +81968,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH0_OVS___S 22 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___M 0x00300000 #define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___S 20 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___S 18 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___S 16 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___S 14 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___S 12 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___M 0xFFFFF000 -#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___S 12 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___M 0xFFF00000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___S 20 #define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0 (0x005D4154) #define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___RWC QCSR_REG_RW @@ -82258,24 +82268,42 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT (0x005D41A8) #define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___RWC QCSR_REG_RO #define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___POR 0x00000000 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___M 0x80000000 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___S 31 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___M 0x40000000 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___S 30 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___M 0x20000000 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___S 29 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___M 0x10000000 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___S 28 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___M 0x0F000000 -#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___S 24 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN_5G___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN_5G___S 31 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN_5G___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN_5G___S 30 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL_5G___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL_5G___S 29 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN_5G___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN_5G___S 28 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN_2G___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN_2G___S 27 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN_2G___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN_2G___S 26 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL_2G___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL_2G___S 25 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN_2G___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN_2G___S 24 #define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___M 0xFF000000 #define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___S 24 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT_XO (0x005D41AC) +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT_XO___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT_XO___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT_XO__RO_DCLK_COUNT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT_XO__RO_DCLK_COUNT___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT_XO__RO_DCLK_COUNT___S 24 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT_XO___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT_XO___S 24 + #define PHYA_IRON2G_RFA_AON_SYNTH_CFG (0x005D41C0) #define PHYA_IRON2G_RFA_AON_SYNTH_CFG___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_AON_SYNTH_CFG___POR 0x80000000 @@ -82306,79 +82334,136 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV (0x005D41C4) #define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___POR 0x00000000 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_2G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_2G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_2G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_5G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_5G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_5G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH0_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___POR 0x0 #define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___S 26 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___S 24 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___S 22 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___M 0xFFC00000 -#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___S 22 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_2G_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_2G_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_2G_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_2G_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_2G_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_2G_OVS___S 26 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_5G_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_5G_OVS___S 24 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_5G_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_5G_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_5G_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_5G_OVS___S 20 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH0_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH0_OVS___S 18 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___S 16 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___S 14 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG (0x005D41C8) -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___POR 0x00000000 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___POR 0x0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___M 0xE0000000 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___S 29 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___M 0x10000000 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___S 28 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___M 0x08000000 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___S 27 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___M 0x04000000 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___S 26 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___M 0x0000C000 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___S 14 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___M 0x00002000 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___S 13 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___M 0x00001000 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___S 12 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___M 0x00000800 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___S 11 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___M 0x00000400 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___S 10 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___M 0x00000200 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___S 9 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___M 0x000000C0 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___S 6 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___M 0x00000020 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___S 5 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___M 0x00000010 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___S 4 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___M 0x00000008 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___S 3 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___M 0x00000004 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___S 2 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___M 0x00000002 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___S 1 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___M 0xFC00FEFE -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___S 1 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0 (0x005D41C8) +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_CST_SYNTH_WSI_SW_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_MAIN_SYN_EN_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_EN_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_SEL_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_CST_SYNTH_WSI_SW_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_MAIN_SYN_EN_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_EN_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_SEL_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_CST_SYNTH_WSI_SW_5G___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_CST_SYNTH_WSI_SW_5G___S 29 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_MAIN_SYN_EN_5G___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_MAIN_SYN_EN_5G___S 28 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_EN_5G___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_EN_5G___S 27 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_SEL_5G___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_SEL_5G___S 26 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_CST_SYNTH_WSI_SW_2G___M 0x00E00000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_CST_SYNTH_WSI_SW_2G___S 21 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_MAIN_SYN_EN_2G___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_MAIN_SYN_EN_2G___S 20 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_EN_2G___M 0x00080000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_EN_2G___S 19 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_SEL_2G___M 0x00040000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0__RO_RFA_LP_SYN_SEL_2G___S 18 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0___M 0xFCFC0000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG0___S 18 -#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG (0x005D41CC) +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1 (0x005D41CC) +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_LP2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_LP2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_LP2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_LP5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_LP5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_LP5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_2G___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_2G___S 30 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_2G___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_2G___S 29 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_2G___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_2G___S 28 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_LP2G___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_LP2G___S 26 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_LP2G___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_LP2G___S 25 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_LP2G___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_LP2G___S 24 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_5G___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_5G___S 22 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_5G___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_5G___S 21 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_5G___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_5G___S 20 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_LP5G___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_CST_SYNTH_RES_CTRL_LP5G___S 18 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_LP5G___M 0x00020000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RES_EN_LP5G___S 17 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_LP5G___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_EN_LP5G___S 16 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH0___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH0___S 10 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH0___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH0___S 9 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH0___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH0___S 8 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH1___S 6 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH1___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH1___S 5 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH1___M 0x00000010 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH1___S 4 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH2___M 0x00000004 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_RESTORE_WL_SYNTH2___S 2 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH2___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_EN_WL_SYNTH2___S 1 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH2___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1__RO_SYN_CAL_DONE_WL_SYNTH2___S 0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1___M 0xFFFF0777 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG1___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG (0x005D41D0) #define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___RWC QCSR_REG_RO #define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___POR 0x00000000 #define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH0___POR 0x0 @@ -82440,9 +82525,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0 (0x005D4244) #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___POR 0xC0000000 -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___POR 0x1 -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XLNA_CFG_2G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XLNA_CFG_2G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XTRSW_CFG_2G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___M 0x80000000 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___S 31 @@ -82455,9 +82540,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1 (0x005D4248) #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___POR 0xC0000000 -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___POR 0x1 -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XLNA_CFG_2G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XLNA_CFG_2G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XTRSW_CFG_2G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___M 0x80000000 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___S 31 @@ -82470,9 +82555,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0 (0x005D424C) #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___POR 0xC0000000 -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___POR 0x1 -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XLNA_CFG_5G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XLNA_CFG_5G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XTRSW_CFG_5G_CH0___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___M 0x80000000 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___S 31 @@ -82485,9 +82570,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1 (0x005D4250) #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___POR 0xC0000000 -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___POR 0x1 -#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XLNA_CFG_5G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XLNA_CFG_5G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XTRSW_CFG_5G_CH1___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___M 0x80000000 #define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___S 31 @@ -83122,37 +83207,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1 (0x005D42AC) #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___POR 0x00000000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_18___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_17___POR 0x0 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___POR 0x0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___M 0x03000000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___S 24 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___M 0x00C00000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___S 22 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___M 0x00300000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___S 20 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___M 0x000C0000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___S 18 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___M 0x00030000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___S 16 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___M 0x0000C000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___S 14 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___M 0x00003000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___S 12 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___M 0x00000C00 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___S 10 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___M 0x00000300 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___S 8 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___M 0x000000C0 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___S 6 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_18___M 0x00000030 @@ -83161,16 +83219,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_17___S 2 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___M 0x00000003 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___S 0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___M 0x000000FF #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___S 0 #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG (0x005D42B0) #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___POR 0x00000000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___POR 0x00000000 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___POR 0x00000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___M 0x000FFFFF #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___S 0 -#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___M 0x000FFFFF #define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___S 0 #define PHYA_IRON2G_RFA_AON_COEX_COEX (0x005D42C0) @@ -84064,7 +84122,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH0_OV___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH1_OV___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___POR 0x0 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_LOGEN_VREF_OV___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_VREF_OV___POR 0x0 @@ -84123,8 +84180,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH1_OV___S 6 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___M 0x00000020 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___S 5 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___M 0x00000010 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___S 4 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___M 0x00000008 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___S 3 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_LOGEN_VREF_OV___M 0x00000004 @@ -84133,7 +84188,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_VREF_OV___S 1 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_VREF_OV___M 0x00000001 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_VREF_OV___S 0 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___M 0xFFFFFFEF #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___S 0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3 (0x005D448C) @@ -84164,6 +84219,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_WL_BBPLL_OV___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_BTFMPLL_OV___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH0_SDM_VREF_OV___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH2_VREF_OV___M 0x80000000 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH2_VREF_OV___S 31 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_REFGEN_VREF_OV___M 0x40000000 @@ -84214,14 +84270,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_BTFMPLL_OV___S 8 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___M 0x00000080 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___S 7 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___M 0xFFFFFF80 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___S 7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH0_SDM_VREF_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH0_SDM_VREF_OV___S 6 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___S 6 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL (0x005D4490) #define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___POR 0x30000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___POR 0x70000000 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_SEL_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_SEL_OVD___POR 0x7 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_OUT_FREQ_SEL_OVD___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___M 0x80000000 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___S 31 @@ -84345,7 +84403,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0 (0x005D44A8) #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___POR 0x81446800 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___POR 0x81446880 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___POR 0x8 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_VSEL_OVD___POR 0x1 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_ICTRL_OVD___POR 0x2 @@ -84353,6 +84411,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_BWSEL_OVD___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_VSEL_OVD___POR 0x3 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH0_SDM_VREF_OVD___POR 0x4 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___M 0xF0000000 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___S 28 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_VSEL_OVD___M 0x0F000000 @@ -84367,8 +84426,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_VSEL_OVD___S 13 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___M 0x00001E00 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___S 9 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___M 0xFFFFFE00 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___S 9 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH0_SDM_VREF_OVD___M 0x000001E0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH0_SDM_VREF_OVD___S 5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___S 5 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1 (0x005D44AC) #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___RWC QCSR_REG_RW @@ -84432,14 +84493,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3 (0x005D44B4) #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___POR 0xBB000444 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___POR 0xBB000044 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_2G_CH1_OVD___POR 0xB #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_5G_CH1_OVD___POR 0xB #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH0_OVD___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH0_OVD___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH1_OVD___POR 0x0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___POR 0x4 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___POR 0x4 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___POR 0x4 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_2G_CH1_OVD___M 0xF0000000 @@ -84454,13 +84514,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH1_OVD___S 15 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___M 0x00007000 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___S 12 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___M 0x00000F00 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___S 8 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___M 0x000000F0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___S 4 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___M 0x0000000F #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___S 0 -#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___M 0xFFFFF0FF #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___S 0 #define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4 (0x005D44B8) @@ -84996,6 +85054,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___POR 0x00000000 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_TCXO_EN___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH0___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_EN___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_BTFMPLL___POR 0x0 @@ -85010,6 +85071,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_TCXO_EN___S 31 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___M 0x40000000 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH2___M 0x00030000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH2___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH1___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH1___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH0___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_MODE_WL_SYNTH0___S 12 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___M 0x00000800 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___S 11 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_EN___M 0x00000400 @@ -85030,7 +85097,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL_VALID___S 3 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL___M 0x00000007 #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL___S 0 -#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___M 0xC0000FFF +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___M 0xC003FFFF #define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___S 0 #define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0 (0x005D4830) @@ -85200,7 +85267,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL (0x005D4848) #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___POR 0x000018A0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___POR 0x00001800 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OVD___POR 0x00 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OV___POR 0x0 @@ -85211,8 +85278,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_DIFF_EN___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_CLK_DRV___POR 0x3 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___POR 0x1 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_2G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_5G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_LP2G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_LP5G_REFCLK_FREQ___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___M 0x80000000 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___S 31 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OVD___M 0x3F000000 @@ -85233,12 +85302,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_CLK_DRV___S 11 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___M 0x00000600 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___S 9 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___M 0x00000180 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___S 7 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___M 0x00000060 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___S 5 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___M 0xBFFFFFE0 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_2G_REFCLK_FREQ___M 0x00000180 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_2G_REFCLK_FREQ___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_5G_REFCLK_FREQ___M 0x00000060 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_5G_REFCLK_FREQ___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_LP2G_REFCLK_FREQ___M 0x00000018 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_LP2G_REFCLK_FREQ___S 3 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_LP5G_REFCLK_FREQ___M 0x00000006 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_LP5G_REFCLK_FREQ___S 1 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___M 0xBFFFFFFE +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___S 1 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL (0x005D484C) #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___RWC QCSR_REG_RW @@ -85253,7 +85326,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_DIFF_EN___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_CLK_DRV___POR 0x3 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_2G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_5G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_LP2G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_LP5G_REFCLK_FREQ___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OV___M 0x80000000 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OV___S 31 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OVD___M 0x3F000000 @@ -85274,14 +85350,20 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_CLK_DRV___S 11 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___M 0x00000600 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___S 9 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___M 0x00000180 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___S 7 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___M 0xBFFFFF80 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_2G_REFCLK_FREQ___M 0x00000180 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_2G_REFCLK_FREQ___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_5G_REFCLK_FREQ___M 0x00000060 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_5G_REFCLK_FREQ___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_LP2G_REFCLK_FREQ___M 0x00000018 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_LP2G_REFCLK_FREQ___S 3 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_LP5G_REFCLK_FREQ___M 0x00000006 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_LP5G_REFCLK_FREQ___S 1 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___M 0xBFFFFFFE +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___S 1 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL (0x005D4850) #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___POR 0x00001880 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___POR 0x00001800 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OVD___POR 0x00 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OV___POR 0x0 @@ -85292,7 +85374,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_DIFF_EN___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_CLK_DRV___POR 0x3 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_2G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_5G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_LP2G_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_LP5G_REFCLK_FREQ___POR 0x0 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___M 0x80000000 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___S 31 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OVD___M 0x3F000000 @@ -85313,10 +85398,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_CLK_DRV___S 11 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___M 0x00000600 #define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___S 9 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___M 0x00000180 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___S 7 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___M 0xBFFFFF80 -#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_2G_REFCLK_FREQ___M 0x00000180 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_2G_REFCLK_FREQ___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_5G_REFCLK_FREQ___M 0x00000060 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_5G_REFCLK_FREQ___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_LP2G_REFCLK_FREQ___M 0x00000018 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_LP2G_REFCLK_FREQ___S 3 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_LP5G_REFCLK_FREQ___M 0x00000006 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_LP5G_REFCLK_FREQ___S 1 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___M 0xBFFFFFFE +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___S 1 #define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL (0x005D4854) #define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___RWC QCSR_REG_RW @@ -85957,2057 +86048,1382 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___M 0x0000001F #define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0 (0x005D6000) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___POR 0x0221D532 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___POR 0x004 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___POR 0x21D532 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___M 0x007FFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1 (0x005D6004) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___M 0x000003F0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2 (0x005D6008) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___POR 0x0042AAAA -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___POR 0x42AAAA -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___M 0x08000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___M 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___M 0x01000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___M 0x00FFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___M 0x0FFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3 (0x005D600C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___POR 0x55000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___POR 0x0AA -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___S 23 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0 (0x005D6010) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___POR 0x116C2599 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___POR 0x9 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___M 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___M 0x00E00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___S 21 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___M 0x001C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___M 0x00000F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___M 0x000000F0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___M 0x00000008 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___M 0x00000004 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1 (0x005D6014) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___POR 0x80680000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___M 0x08000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___M 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___M 0x01000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___M 0x00E00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___S 21 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___M 0x00100000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___M 0x00080000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___M 0x00007C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___M 0x000003E0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___M 0x0000001F -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___M 0xFFF87FFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2 (0x005D6018) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___POR 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___POR 0x400 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___M 0x07FF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___M 0x07FFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0 (0x005D601C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1 (0x005D6020) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___M 0x00004000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___M 0x00002000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___M 0xFFFF7FFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2 (0x005D6024) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___M 0x20000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___M 0x10000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___M 0x08000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___M 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___M 0x01000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___M 0x00004000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___M 0x00002000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___M 0x00000F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___M 0xFF0FFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3 (0x005D6028) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___S 23 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4 (0x005D602C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___POR 0x000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___M 0x007FFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___M 0x007FFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5 (0x005D6030) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___POR 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6 (0x005D6034) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___M 0x0001F800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___M 0x0001FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0 (0x005D6040) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___POR 0x44A43E4A -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___M 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___M 0x20000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___M 0x10000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___M 0x00380000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___M 0x00000380 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___M 0x00000070 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___M 0x0000000C -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___M 0xFCFFFFFE -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___S 1 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1 (0x005D6044) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___POR 0xB4208000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___POR 0x08 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___POR 0x08 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___M 0xFFFF8000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___S 15 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS (0x005D6048) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___M 0x20000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___M 0xFF000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___S 24 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2 (0x005D604C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___M 0xFE000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___S 25 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0 (0x005D6050) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1 (0x005D6054) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2 (0x005D6058) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3 (0x005D605C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4 (0x005D6060) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5 (0x005D6064) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6 (0x005D6068) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7 (0x005D606C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8 (0x005D6070) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9 (0x005D6074) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10 (0x005D6078) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11 (0x005D607C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12 (0x005D6080) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13 (0x005D6084) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14 (0x005D6088) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15 (0x005D608C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16 (0x005D6090) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17 (0x005D6094) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18 (0x005D6098) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19 (0x005D609C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20 (0x005D60A0) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21 (0x005D60A4) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22 (0x005D60A8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23 (0x005D60AC) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24 (0x005D60B0) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25 (0x005D60B4) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26 (0x005D60B8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27 (0x005D60BC) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28 (0x005D60C0) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29 (0x005D60C4) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30 (0x005D60C8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31 (0x005D60CC) -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST (0x005D6100) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___POR 0x06C0F998 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___POR 0xC -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___M 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___M 0x00004000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___M 0x00002000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___M 0x000000C0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___M 0x00000038 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___M 0xFFFFFFF8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___S 3 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0 (0x005D6104) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___M 0x07FF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___M 0xC7FF07FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1 (0x005D6108) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___POR 0x7FFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2 (0x005D610C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___POR 0x7FFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3 (0x005D6110) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4 (0x005D6114) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5 (0x005D6118) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6 (0x005D611C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0 (0x005D6140) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___POR 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___M 0x00038000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___M 0x00000600 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___M 0x00000180 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___M 0x00000060 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___M 0x00000018 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___M 0x00000006 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___M 0xFFFFFFFE -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___S 1 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1 (0x005D6144) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___M 0x00000030 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___M 0x0000000C -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___M 0x00000003 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2 (0x005D6148) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___M 0xFFFFFF00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___S 8 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3 (0x005D614C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___M 0x00000030 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4 (0x005D6150) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___M 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___M 0x00007FC0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___M 0xE00FFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5 (0x005D6154) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___M 0xFF3FFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6 (0x005D6158) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___POR 0x00001C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___M 0x00018000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___M 0x00007000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___M 0x00000200 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___M 0x00000100 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___M 0x3F01FFE0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___S 5 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7 (0x005D615C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___M 0xFF000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___S 24 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8 (0x005D6160) -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___POR 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___M 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___M 0x18000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___S 23 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0 (0x005D6180) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___POR 0xAF682022 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___POR 0x22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1 (0x005D6184) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___POR 0x8F669A44 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___POR 0x44 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2 (0x005D6188) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___POR 0x6F859677 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___POR 0x77 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3 (0x005D618C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___POR 0x6F851499 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___POR 0x99 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4 (0x005D6190) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___POR 0xAF6820AA -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5 (0x005D6194) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___POR 0x8F669ADD -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6 (0x005D6198) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___POR 0x6F8596EE -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7 (0x005D619C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___POR 0x6F8514FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0 (0x005D61A8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___POR 0x10120F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___POR 0x020 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___POR 0x048 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___POR 0x078 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___M 0x007FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___M 0x00003FE0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___M 0xFFFFFFE0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___S 5 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1 (0x005D61AC) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___POR 0x5C3EE7A0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___POR 0x0B8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___POR 0x0FB -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___POR 0x13D -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___M 0x007FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___M 0x00003FE0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___M 0xFFFFFFE0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___S 5 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2 (0x005D61B0) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___POR 0xBE800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___POR 0x17D -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___M 0x00000080 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___M 0x00000070 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___M 0x00000008 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___M 0x00000004 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___M 0xFF8000FE -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___S 1 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3 (0x005D61B4) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4 (0x005D61B8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___M 0x1C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___M 0xFFFFC000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___S 14 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0 (0x005D61C0) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___POR 0x00068000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___M 0x10000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___M 0x01000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___M 0x00800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___M 0x000E0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___M 0x00004000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___M 0x00002000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___M 0x11CFF800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___S 11 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1 (0x005D61C4) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___POR 0x0000301B -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___M 0x00007000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___M 0x00000038 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___M 0x00000007 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___M 0x0000703F -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2 (0x005D61C8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___POR 0x6D860000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___M 0xFF8E0002 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___S 1 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3 (0x005D61CC) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___POR 0x00300001 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___M 0x00308003 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4 (0x005D61D0) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___M 0x03E00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___S 21 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___M 0x00100000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___M 0x000E0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___M 0xE3FE0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___S 17 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5 (0x005D61D4) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6 (0x005D61D8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7 (0x005D61DC) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___POR 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___M 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___M 0x3C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___M 0x01E00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___S 21 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___S 21 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0 (0x005D61E0) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___M 0x00070000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___M 0x00003800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___M 0x00000700 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___M 0x000000F0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___M 0x0000000F -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1 (0x005D61E4) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___M 0x00000003 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___M 0xE0000003 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8 (0x005D61E8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___POR 0x1CA2B95C -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___POR 0xC -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___POR 0xC -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___M 0x0E000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___M 0x003C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___M 0x00020000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___M 0x0001E000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___M 0x00000100 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___M 0x000000F0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9 (0x005D61EC) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___POR 0x1C7C6000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___M 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___M 0xFFFFFC00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___S 10 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10 (0x005D61F0) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___POR 0x2210000F -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___M 0x00100000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___M 0x00020000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___M 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___M 0x0000000E -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___M 0xFF1F800F -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11 (0x005D61F4) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___POR 0x03000018 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___M 0x00080000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___M 0x00007800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___M 0x00000010 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___M 0x00000007 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___M 0x0FFFF81F -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12 (0x005D61F8) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___POR 0x007FF7FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___POR 0x7FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___POR 0x7FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___M 0x00800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___M 0x007FF000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___M 0x00FFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13 (0x005D61FC) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___POR 0x007FF7FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___POR 0x7FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___POR 0x7FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___M 0x00800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___M 0x007FF000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___M 0x00FFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0 (0x005D6240) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___POR 0x091B0C00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___POR 0x12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0 (0x005D6244) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___POR 0x67850000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1 (0x005D6248) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___POR 0x212B8640 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___POR 0x02 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1 (0x005D624C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___POR 0x38410000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2 (0x005D6250) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___POR 0x091B0C40 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___POR 0x12 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2 (0x005D6254) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___POR 0x67850000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3 (0x005D6258) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___POR 0x212B8640 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___POR 0x02 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3 (0x005D625C) -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___POR 0x38410000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL (0x005D6280) -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___POR 0x10000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___M 0x08000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___M 0x06000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___M 0x01800000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___M 0xFF800003 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO (0x005D6288) -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___M 0x00000007 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___M 0x00000007 -#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0 (0x005D6000) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0___POR 0x0221D532 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0__NBNA___POR 0x004 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0__NF___POR 0x21D532 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0__NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0__NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0__NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0__NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1 (0x005D6004) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__SD_NF_OFFSET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BSTARGET_OFS_COARSE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BSTARGET_OFS_FINE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BS_COARSE_FINE_BDRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__SD_NF_OFFSET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__SD_NF_OFFSET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BSTARGET_OFS_COARSE___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BSTARGET_OFS_FINE___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BSTARGET_OFS_FINE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1__BS_COARSE_FINE_BDRY___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2 (0x005D6008) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2___POR 0x0042AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DELTA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_BASE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DELTA___POR 0x42AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DELTA_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DELTA_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_BASE_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_BASE_SEL___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DIS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DIS___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_START___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_START___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DELTA___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2__FC_DELTA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH3 (0x005D600C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH3___POR 0x55000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH3__FC_DELTA_SUB___POR 0x0AA +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH3__FC_DELTA_SUB___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH3__FC_DELTA_SUB___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_CH3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0 (0x005D6010) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0___POR 0x116C2599 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSTART___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSMODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BKSHFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSETT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSWAIT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSAMPLE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__LPF_VTUNEMON_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_RFCNT_OUT_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__RFCNTEN_DLY_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_VMID_NON_HB___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_VMID_HB___POR 0x9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__NF0B___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__D_DTIM_FBDIV4_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__DISABLE_LPF_TMR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSTART___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSTART___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSMODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSMODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BKSHFT___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BKSHFT___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSETT___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSETT___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSWAIT___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSWAIT___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSAMPLE___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BSSAMPLE___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__LPF_VTUNEMON_TMR___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__LPF_VTUNEMON_TMR___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_RFCNT_OUT_TIME___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__RFCNTEN_DLY_DIS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__RFCNTEN_DLY_DIS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_VMID_NON_HB___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_VMID_NON_HB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_VMID_HB___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_VMID_HB___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_CLBS_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__BS_CLBS_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__NF0B___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__NF0B___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__D_DTIM_FBDIV4_SEL___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__DISABLE_LPF_TMR___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0__DISABLE_LPF_TMR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1 (0x005D6014) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1___POR 0x80680000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDM_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDMOGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__BSTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SD_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__D_PLLMD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__BS_OVCAL_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__PLL_SLIP_DET_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__RESTORE_BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST2_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST1_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST0_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDM_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDM_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDMOGAIN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDMOGAIN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__BSTESTEN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__BSTESTEN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDTESTEN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SDTESTEN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SD_RESET___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__SD_RESET___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__D_PLLMD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__D_PLLMD___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__BS_OVCAL_BDRY___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__BS_OVCAL_BDRY___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__PLL_SLIP_DET_RESET___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__PLL_SLIP_DET_RESET___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__RESTORE_BS_CLBS_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__RESTORE_BS_CLBS_EN___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST2_SEL___M 0x00007C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST2_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST1_SEL___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST1_SEL___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST0_SEL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1__DTEST0_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1___M 0xFFF87FFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2 (0x005D6018) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2__IVCOBK___POR 0x400 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2__TSTCNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2__IVCOBK___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2__IVCOBK___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2__TSTCNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2__TSTCNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0 (0x005D601C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0__RO_BSTARGET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0__RO_BSCOUNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0__RO_BSTARGET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0__RO_BSTARGET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0__RO_BSCOUNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0__RO_BSCOUNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1 (0x005D6020) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_VC_2HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_VC_2LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BIST_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_FVCOBK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_VC_2HI___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_VC_2HI___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_VC_2LO___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_VC_2LO___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BIST_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BIST_ON___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_BSON___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_FVCOBK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1__RO_FVCOBK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1___M 0xFFFF7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2 (0x005D6024) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_EN_REC_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_ANY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_ANY_TX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_CLBS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_TX_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK_DET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_DLL_LOCKED___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_BS_VMID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_CHAN_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_EN___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_EN_REC_LO___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_SYN_EN_REC_LO___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_ANY_RX_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_ANY_RX_EN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_ANY_TX_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_ANY_TX_EN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_CLBS_ON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_CLBS_ON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_TX_MASK___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_TX_MASK___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK_DET___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK_DET___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_DLL_LOCKED___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_DLL_LOCKED___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_NON_DTIM_5G___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_NON_DTIM_5G___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_BS_VMID___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_BS_VMID___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_CHAN_IDX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2__RO_CHAN_IDX___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2___M 0xFF0FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3 (0x005D6028) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3__RO_NBNA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3__RO_NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3__RO_NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS4 (0x005D602C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS4__RO_NF___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS4__RO_NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS4__RO_NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS4___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS5 (0x005D6030) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS5___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS5__CLBS_QS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS5__CLBS_QS_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS5__CLBS_QS_EN___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS5___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_BS5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6 (0x005D6034) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6__BANK_DBG_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6__RO_INIT_BANK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6__BANK_DBG_OFFSET___M 0x0001F800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6__BANK_DBG_OFFSET___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6__RO_INIT_BANK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6__RO_INIT_BANK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_BS6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0 (0x005D6040) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0___POR 0x44A43E4A +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_VC___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_TX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_RX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_COMP_REPEAT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SMPL_RATE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MAX_STEP___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_STEPSIZE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_HYBRID_BDRY___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SETTIME___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SAMPLE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MASK_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_PSYNC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_VC___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_VC___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_TX___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_TX___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_RX___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_RX___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MODE___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MODE___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_COMP_REPEAT___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SMPL_RATE___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SMPL_RATE___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MAX_STEP___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MAX_STEP___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_STEPSIZE___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_STEPSIZE___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_HYBRID_BDRY___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SETTIME___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SETTIME___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SAMPLE___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_SAMPLE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MASK_SEL___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_MASK_SEL___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_PSYNC_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0__CLBS_PSYNC_EN___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0___M 0xFCFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1 (0x005D6044) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1___POR 0xB4208000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_INC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_DEC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_BDRY___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_INC___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_DEC___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1__CLBS_SAMPLE_RESTORE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS1___S 15 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS (0x005D6048) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_OFF_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_NON_DTIM_5G___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_NON_DTIM_5G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_OFF_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_CLBS___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2 (0x005D604C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_LIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_LIN_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2__CLBS_LIN_EN___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS2___S 25 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_0 (0x005D6050) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_0___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_0__CLBS_LIN_OFFSET_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_0___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_1 (0x005D6054) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_1__CLBS_LIN_OFFSET_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_1___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_2 (0x005D6058) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_2___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_2__CLBS_LIN_OFFSET_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_2___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_3 (0x005D605C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_3___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_3__CLBS_LIN_OFFSET_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_3___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_4 (0x005D6060) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_4___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_4__CLBS_LIN_OFFSET_4___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_4___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_5 (0x005D6064) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_5___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_5__CLBS_LIN_OFFSET_5___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_5___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_6 (0x005D6068) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_6___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_6__CLBS_LIN_OFFSET_6___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_6___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_7 (0x005D606C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_7___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_7__CLBS_LIN_OFFSET_7___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_7___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_8 (0x005D6070) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_8___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_8__CLBS_LIN_OFFSET_8___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_8___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_9 (0x005D6074) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_9___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_9__CLBS_LIN_OFFSET_9___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_9___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_10 (0x005D6078) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_10___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_10__CLBS_LIN_OFFSET_10___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_10___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_11 (0x005D607C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_11___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_11__CLBS_LIN_OFFSET_11___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_11___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_12 (0x005D6080) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_12___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_12__CLBS_LIN_OFFSET_12___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_12___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_13 (0x005D6084) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_13___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_13__CLBS_LIN_OFFSET_13___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_13___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_14 (0x005D6088) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_14___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_14__CLBS_LIN_OFFSET_14___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_14___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_15 (0x005D608C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_15___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_15__CLBS_LIN_OFFSET_15___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_15___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_16 (0x005D6090) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_16___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_16__CLBS_LIN_OFFSET_16___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_16___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_17 (0x005D6094) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_17___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_17__CLBS_LIN_OFFSET_17___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_17___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_18 (0x005D6098) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_18___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_18__CLBS_LIN_OFFSET_18___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_18___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_19 (0x005D609C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_19___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_19__CLBS_LIN_OFFSET_19___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_19___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_20 (0x005D60A0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_20___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_20__CLBS_LIN_OFFSET_20___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_20___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_21 (0x005D60A4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_21___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_21__CLBS_LIN_OFFSET_21___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_21___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_22 (0x005D60A8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_22___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_22__CLBS_LIN_OFFSET_22___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_22___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_23 (0x005D60AC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_23___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_23__CLBS_LIN_OFFSET_23___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_23___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_24 (0x005D60B0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_24___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_24__CLBS_LIN_OFFSET_24___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_24___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_25 (0x005D60B4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_25___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_25__CLBS_LIN_OFFSET_25___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_25___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_26 (0x005D60B8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_26___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_26__CLBS_LIN_OFFSET_26___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_26___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_27 (0x005D60BC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_27___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_27__CLBS_LIN_OFFSET_27___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_27___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_28 (0x005D60C0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_28___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_28__CLBS_LIN_OFFSET_28___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_28___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_29 (0x005D60C4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_29___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_29__CLBS_LIN_OFFSET_29___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_29___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_30 (0x005D60C8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_30___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_30__CLBS_LIN_OFFSET_30___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_30___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_31 (0x005D60CC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_31___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_31__CLBS_LIN_OFFSET_31___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_CLBS_31___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST (0x005D6100) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST___POR 0x06C0F998 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOM___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOH___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_VCO_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_NDIV_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_RFCNT_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_RFCNT_OUT_TIME___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__NDIV_BIST_TIME___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_MODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_MODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOM___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOM___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOH___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOH___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOL___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_VCO_BIST___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_VCO_BIST___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_NDIV_BIST___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_NDIV_BIST___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_RFCNT_BIST___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__EN_RFCNT_BIST___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_RFCNT_OUT_TIME___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_TIME___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_TIME___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_WAIT___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__BIST_WAIT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__NDIV_BIST_TIME___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST__NDIV_BIST_TIME___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_BIST___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0 (0x005D6104) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_BIST_PASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_BIST_OVERLAP___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_BIST_MONO___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_BIST_PASS___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_BIST_OVERLAP___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_BIST_OVERLAP___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_BIST_MONO___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0__RO_BIST_MONO___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0___M 0xC7FF07FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1 (0x005D6108) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2 (0x005D610C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3 (0x005D6110) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3__RO_MIN_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3__RO_MAX_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3__RO_MIN_BANK_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3__RO_MAX_BANK_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4 (0x005D6114) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_MID_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5 (0x005D6118) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5__RO_RFCNT_BIST_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6 (0x005D611C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_BIST6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0 (0x005D6140) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0___POR 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__ATOP_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SDM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__EN_DCLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VC_2HI_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VC_2LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SYN_EN_REC_LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__FASTCH_TMR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__FASTCH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_OUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__PRES_RSTB_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VCON_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__DLL_LOCKED_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__ATOP_ISO_DIS_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SDM_EN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SDM_EN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__EN_DCLK___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__EN_DCLK___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VC_2HI_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VC_2HI_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VC_2LO_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VC_2LO_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SYN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SYN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__SYN_EN_REC_LO_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__FASTCH_TMR___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__FASTCH_TMR___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__FASTCH_SEL___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__FASTCH_SEL___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_OUT_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__RFCNT_OUT_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__PRES_RSTB_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__PRES_RSTB_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VCON_SW_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__VCON_SW_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__DLL_LOCKED_OVS___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0__DLL_LOCKED_OVS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1 (0x005D6144) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__VMID_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PRECH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LPF_VCMON_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__BIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__CP_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LDO_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LDO_PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__HB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LPVCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__VMID_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__VMID_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PRECH_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PRECH_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PFD_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PFD_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__CP_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__CP_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PRNDIV_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__PRNDIV_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LPF_VCMON_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LPF_VCMON_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__BIAS_FC_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__BIAS_FC_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__CP_FC_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__CP_FC_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__VCO_FC_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__VCO_FC_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LDO_VCO_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LDO_VCO_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LDO_PFD_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LDO_PFD_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__HB_VCO_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__HB_VCO_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LPVCO_DIV2_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1__LPVCO_DIV2_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC1___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2 (0x005D6148) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__LOBUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__LOBUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__BUF_EN_TX_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__LOBUF_CH0_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__LOBUF_CH0_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__LOBUF_CH1_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__LOBUF_CH1_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__BUF_EN_TX_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2__BUF_EN_TX_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC2___S 26 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3 (0x005D614C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__SYN_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__SYN_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__ANY_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__ANY_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__CHAN_IDX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__CHAN_IDX_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__SYN_MODE_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__SYN_MODE_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__SYN_MODE_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__SYN_MODE_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__ANY_TX_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__ANY_TX_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__ANY_RX_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__ANY_RX_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__CHAN_IDX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__CHAN_IDX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__CHAN_IDX_OVD___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3__CHAN_IDX_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3___M 0xE00FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC3___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC4 (0x005D6150) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC4___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC4__FASTCH_TMR_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC4__FASTCH_TMR_RESTORE___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC4__FASTCH_TMR_RESTORE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC4___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5 (0x005D6154) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__ENBR_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__ENBF_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__SD_ISO_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__SD_PRESET_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__VC_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__ENBR_IN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__ENBR_IN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__ENBF_IN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__ENBF_IN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__SD_ISO_L_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__SD_ISO_L_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__SD_PRESET_L_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__SD_PRESET_L_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__VC_ISO_DIS_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5__VC_ISO_DIS_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC5___S 22 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6 (0x005D6158) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6__VCON_SW_LEG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6__VCON_SW_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6__VCON_SW_LEG___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6__VCON_SW_LEG___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6__VCON_SW_OPT___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6__VCON_SW_OPT___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_PC6___S 29 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0 (0x005D6180) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0___POR 0xB0A00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__KVCO_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__IBIAS_0___POR 0x10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__LDO_VCO_VREG_0___POR 0xA +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__LOGEN_CAP_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__KVCO_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__KVCO_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__IBIAS_0___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__IBIAS_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__LDO_VCO_VREG_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNE_0___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNEB_0___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0__LOGEN_CAP_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCOMUX_0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0 (0x005D61A8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__HB_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__DTIM_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_SEL_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_SEL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_GATE_DIS___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__KVCO_GATE_DIS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__HB_GATE_DIS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__HB_GATE_DIS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__DTIM_GATE_DIS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0__DTIM_GATE_DIS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0___M 0x000000FE +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_KVCO0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1 (0x005D61AC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_KVCO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_IBIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_LDO_VCO_VREG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_VCO_CMTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_VCO_CMTUNEB___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_LOGEN_CAP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_KVCO___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_KVCO___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_IBIAS___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_IBIAS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_LDO_VCO_VREG___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_LDO_VCO_VREG___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_VCO_CMTUNE___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_VCO_CMTUNE___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_VCO_CMTUNEB___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_VCO_CMTUNEB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_LOGEN_CAP___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1__RO_LOGEN_CAP___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO2 (0x005D61B0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO2__RO_KVCO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO2__RO_KVCO_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO2__RO_KVCO_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_KVCO2___S 29 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0 (0x005D61C0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0___POR 0x3C65C300 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_OTACUR___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_CP_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_FBDIV_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_BYPASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_BYPASS___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_ISEL_IC25___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_ISEL_IC25___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_OTACUR___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_VCO_OTACUR___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_CP_ISEL_IC25___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_CP_ISEL_IC25___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_BYPASS___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_BYPASS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_VREG___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_VREG___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_OTACUR___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_OTACUR___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_LKRON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_LKRON___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_ISEL_IC25___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_PFD_ISEL_IC25___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_FBDIV_LKRON___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0__D_LDO_FBDIV_LKRON___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0___M 0xFEFFFF80 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC0___S 7 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1 (0x005D61C4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1___POR 0x3E022070 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_BIAS_IC50___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCOBUFREG_BIAS_IC12P5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_ISRC_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_PMRR_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_LKR_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_SUPFILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_NBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_PBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_DRAINSW_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_LOW_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_BIAS_IC50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_BIAS_IC50___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCOBUFREG_BIAS_IC12P5___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCOBUFREG_BIAS_IC12P5___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_ISRC_BYPASS___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_ISRC_BYPASS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_PMRR_BIAS___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_VCO_PMRR_BIAS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_DEGEN_PROG___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_DEGEN_PROG___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_LKR_DEGEN_PROG___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_LKR_DEGEN_PROG___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_SUPFILT_RES___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_SUPFILT_RES___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_NBIAS_RSEL___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_NBIAS_RSEL___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_PBIAS_RSEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_PBIAS_RSEL___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_ISEL_IR25___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_ISEL_IR25___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_DRAINSW_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_DRAINSW_EN___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_LOW_BIAS___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1__D_CP_LOW_BIAS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC1___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2 (0x005D61C8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2___POR 0xF0760000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_PFD_HI_LK_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_LPF_C1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_VREF_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_BIAS_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_PINVC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_VCMON_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_SPARE_BIAS_IC25_FIXED___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_SPARE_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_PFD_HI_LK_MODE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_PFD_HI_LK_MODE___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_LPF_C1___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_LPF_C1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_VREF_FILT_RES___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_VREF_FILT_RES___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_BIAS_FILT_RES___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_BIAS_FILT_RES___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_PINVC___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_PINVC___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_VCMON_ISEL_IC25___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_VCMON_ISEL_IC25___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_SPARE_BIAS_IC25_FIXED___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_SPARE_BIAS_IC25_FIXED___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_SPARE_ISEL_IC25___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2__D_SPARE_ISEL_IC25___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2___M 0xFFFE0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC2___S 17 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3 (0x005D61CC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__D_VCO_TST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__D_VCO_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__SYN_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__D_VCO_TST_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__D_VCO_TST_EN___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__D_VCO_ATB_SEL___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__D_VCO_ATB_SEL___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__SYN_ATB_SEL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3__SYN_ATB_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC4 (0x005D61D0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC4__D_SYN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC4__D_SYN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC4__D_SYN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC5 (0x005D61D4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC5__D_SYN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC5__D_SYN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC5__D_SYN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6 (0x005D61D8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__CLBS_LPF_VREF_ADJ_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_LO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_LO_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_HI_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_HI_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__CLBS_LPF_VREF_ADJ_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__CLBS_LPF_VREF_ADJ_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_LO_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_LO_OV___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_LO_OVD___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_LO_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_HI_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_HI_OV___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_HI_OVD___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6__LPF_VREF_HI_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC6___S 21 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7 (0x005D61DC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7___POR 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7__BANK_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7__BANK_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7__BANK_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7__BANK_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7__BANK_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7__BANK_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7___M 0x00FFF000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_AC7___S 12 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0 (0x005D61E0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_RFCNT_SEL_BSC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_PFDCP_CPI___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_CP_LEAKER___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_C2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_C3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_R1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_R2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_RFCNT_SEL_BSC___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_PFDCP_CPI___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_PFDCP_CPI___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_CP_LEAKER___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_CP_LEAKER___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_C2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_C2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_C3___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_C3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_R1___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_R1___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_R2___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_R2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_LO___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_LO___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_HI___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_HI___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC1 (0x005D61E4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC1__RO_BAND___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC1__RO_BAND___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC1__RO_BAND___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC1___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2 (0x005D6240) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2___POR 0x06190C80 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__PFDCP_CPI_2___POR 0x0C +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__CP_LEAKER_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_C2_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_C3_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_R1_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_R2_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__RFCNT_SEL_BSC_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__PFDCP_CPI_2___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__CP_LEAKER_2___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__CP_LEAKER_2___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_C2_2___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_C2_2___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_C3_2___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_C3_2___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_R1_2___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_R1_2___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_R2_2___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2__LPF_R2_2___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX_2___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2 (0x005D6244) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2___POR 0x45630000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_BANDMUX1_2___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL (0x005D6280) +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_REFBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_REFDIV_EN_OVS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_RESET_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PSYNC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PCAL_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_REFBUF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_REFDIV_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_REFDIV_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_OV___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_OVD___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_RESET_OVS___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PAL_FLAG_RESET_OVS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PSYNC_START___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PSYNC_START___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PCAL_START___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL__PCAL_START___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL___M 0xFF800003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_PAL___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LO (0x005D6288) +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LO___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LO___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LO__RO_LO_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LO__RO_LO_FREQ___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LO__RO_LO_FREQ___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LO___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LO___S 0 #define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0 (0x005D6800) #define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___RWC QCSR_REG_RW @@ -88994,8 +88410,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_DRV_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0 @@ -89020,10 +88434,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH0_EN_OVS___S 14 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___S 8 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___S 6 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_DRV_EN_OVS___M 0x00000030 @@ -89032,7 +88442,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_LB_MODE_EN_OVS___S 2 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_HB_MODE_EN_OVS___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___M 0xFFFFF0FF #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___S 0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4 (0x005D6950) @@ -89107,6 +88517,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_SEL_6G_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__FASTCH_TMR_RESTORE___POR 0x1 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1 @@ -89122,6 +88533,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_CORE_EN_OVS___S 26 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_SEL_6G_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_SEL_6G_OVS___S 22 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___M 0x00018000 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___S 15 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__FASTCH_TMR_RESTORE___M 0x00007000 @@ -89140,7 +88553,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_CORE_EN_OPT___S 6 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_OBUF_EN_OPT___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___M 0x3F01FFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___M 0x3FC1FFE0 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___S 5 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7 (0x005D695C) @@ -89182,6 +88595,87 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___M 0xFF800000 #define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0 (0x005D6964) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_LDO_LOGEN_2GDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_LOBIAS_2GDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LOBUF_TLINE0_2G_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LOBUF_TLINE1_2G_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_POSTBUF_2G_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_EN_LPSYN_CALPATH_BUF_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VCO_FASTCH_2G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VCO_2G_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__SEL_5G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__SEL_2G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VDD12CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__CPLDORFB_2G_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LDO_VCOBUF_EN_2G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LDO_VCO_EN_2G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_PREBUF_2G_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_CORE_2G_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_LDO_LOGEN_2GDIV_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_LDO_LOGEN_2GDIV_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_LOBIAS_2GDIV_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_LOBIAS_2GDIV_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LOBUF_TLINE0_2G_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LOBUF_TLINE0_2G_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LOBUF_TLINE1_2G_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LOBUF_TLINE1_2G_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_POSTBUF_2G_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_POSTBUF_2G_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_EN_LPSYN_CALPATH_BUF_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__WL_EN_LPSYN_CALPATH_BUF_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VCO_FASTCH_2G_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VCO_FASTCH_2G_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VCO_2G_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VCO_2G_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__SEL_5G_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__SEL_5G_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__SEL_2G_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__SEL_2G_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VDD12CP_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__VDD12CP_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__CPLDORFB_2G_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__CPLDORFB_2G_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LDO_VCOBUF_EN_2G_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LDO_VCOBUF_EN_2G_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LDO_VCO_EN_2G_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LDO_VCO_EN_2G_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_PREBUF_2G_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_PREBUF_2G_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_CORE_2G_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0__LODIV2_CORE_2G_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1 (0x005D6968) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1__WL_LOBIAS_FASTCH_2GDIV_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1__VCO_DUALCORE_2G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1__WL_LOBIAS_FASTCH_2GDIV_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1__WL_LOBIAS_FASTCH_2GDIV_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1__VCO_DUALCORE_2G_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1__VCO_DUALCORE_2G_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M1___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2 (0x005D696C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_OBUF_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_IBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_CORE_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_OBUF_EN_OPT___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_OBUF_EN_OPT___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_IBUF_EN_OPT___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_IBUF_EN_OPT___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_CORE_EN_OPT___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2__LB_LODIV2_CORE_EN_OPT___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC_M2___S 29 + #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0 (0x005D6980) #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___POR 0xAF682022 @@ -89374,6 +88868,30 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8 (0x005D69A0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8___POR 0x70A00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__KVCO_8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__IBIAS_8___POR 0x10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__LDO_VCO_VREG_8___POR 0xA +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__VCO_CMTUNE_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__VCO_CMTUNEB_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__LOGEN_CAP_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__KVCO_8___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__KVCO_8___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__IBIAS_8___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__IBIAS_8___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__LDO_VCO_VREG_8___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__LDO_VCO_VREG_8___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__VCO_CMTUNE_8___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__VCO_CMTUNE_8___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__VCO_CMTUNEB_8___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__VCO_CMTUNEB_8___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__LOGEN_CAP_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8__LOGEN_CAP_8___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_8___S 0 + #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0 (0x005D69A8) #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___POR 0x10120F00 @@ -89415,9 +88933,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_TH6___M 0xFF800000 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_TH6___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___M 0x00000080 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___M 0x000000F0 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___S 4 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_GATE_DIS___M 0x00000008 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_GATE_DIS___S 3 @@ -89425,7 +88943,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__HB_GATE_DIS___S 2 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___M 0x00000002 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___M 0xFF8000FE +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___M 0xFF8001FE #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___S 1 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3 (0x005D69B4) @@ -89459,16 +88977,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00 #define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___M 0x1C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___M 0xFFFFC000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x0007E000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___M 0xFFFFE000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___S 13 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0 (0x005D69C0) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___RWC QCSR_REG_RW @@ -89660,9 +89178,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_LPF_R2_6G___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_LPF_R2_6G___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___M 0x00000007 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___M 0xE0000003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___M 0xE0000007 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___S 0 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8 (0x005D69E8) @@ -89703,10 +89221,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9 (0x005D69EC) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___POR 0x1C7C6000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___POR 0x007C6000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_LKRON___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___POR 0x7 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_CAPSEL___POR 0x3 @@ -89720,8 +89237,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_LKRON___S 31 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___S 26 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___S 25 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000 @@ -89740,12 +89255,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_CPLVL_BYPASS___S 12 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LOBIAS_BWRSEL___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___M 0xC3FFFC00 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___S 10 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10 (0x005D69F0) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___POR 0x2210000F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___POR 0x22100001 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___POR 0x2 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE_6G___POR 0x1 @@ -89753,7 +89268,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_NBIAS_RSEL___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_PBIAS_RSEL___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___POR 0x7 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___POR 0x1 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___M 0xF0000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___S 28 @@ -89769,11 +89283,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_PBIAS_RSEL___S 16 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___M 0x00008000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___M 0x0000000E -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___S 1 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___M 0x00000001 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___M 0xFF1F800F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___M 0xFF1F8001 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___S 0 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11 (0x005D69F4) @@ -89845,40 +89357,151 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___M 0x00FFFFFF #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC14 (0x005D6A00) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC14__BA_SEL_AX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC14__BA_SEL_AX___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC14__BA_SEL_AX___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC14___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC14___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0 (0x005D6A04) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0___POR 0x14000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCOBUF_DUM_2G_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCO_ISRC_BYPASS_2G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCO_DUALSW_2G_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_WL_PD_LODIV2_POSTBUF___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_WL_PD_LPSYN_CALPATH_BUF___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCOBUF_DUM_2G_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCOBUF_DUM_2G_EN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCO_ISRC_BYPASS_2G___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCO_ISRC_BYPASS_2G___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCO_DUALSW_2G_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_VCO_DUALSW_2G_EN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_WL_PD_LODIV2_POSTBUF___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_WL_PD_LODIV2_POSTBUF___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_WL_PD_LPSYN_CALPATH_BUF___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0__D_WL_PD_LPSYN_CALPATH_BUF___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M0___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1 (0x005D6A08) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1___POR 0x440700B0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_VREG_2G___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_OTACUR_2G___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_BYP_2G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_VRES09_2G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_VRES07_2G___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_OTACUR_2G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_BYP_2G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_BYP_2GDIV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_LKRON_2GDIV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_OTACUR_2GDIV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_VREF_2GDIV___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_VREG_2G___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_VREG_2G___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_OTACUR_2G___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_OTACUR_2G___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_BYP_2G___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCOBUF_BYP_2G___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_VRES09_2G___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_VRES09_2G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_VRES07_2G___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_VRES07_2G___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_OTACUR_2G___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_OTACUR_2G___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_BYP_2G___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_LDO_VCO_BYP_2G___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_BYP_2GDIV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_BYP_2GDIV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_LKRON_2GDIV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_LKRON_2GDIV___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_OTACUR_2GDIV___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_OTACUR_2GDIV___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_VREF_2GDIV___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1__D_WL_LDO_LOGEN_VREF_2GDIV___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1___M 0xFFFFFFF0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M1___S 4 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M2 (0x005D6A0C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M2__D_WL_LOBIAS_BWRSEL_2GDIV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M2__D_WL_LOBIAS_BWRSEL_2GDIV___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M2__D_WL_LOBIAS_BWRSEL_2GDIV___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M2___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M2___S 30 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3 (0x005D6A10) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANK_2G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANK_2G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANKA_2G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANKA_2G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANK_2G_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANK_2G_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANK_2G_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANK_2G_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANKA_2G_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANKA_2G_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANKA_2G_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3__BANKA_2G_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4 (0x005D6A14) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4__BAND_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4__BAND_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4__BAND_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4__BAND_OV___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4__BAND_OVD___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4__BAND_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC_M4___S 0 + #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0 (0x005D6A40) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___POR 0x091B0C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___POR 0x061F2190 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___POR 0x0C #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C1_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___POR 0x2 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___POR 0x2 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___S 29 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___S 23 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___M 0x00780000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C1_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C1_0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___M 0x000003C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___S 3 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0 (0x005D6A44) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___POR 0x67850000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___POR 0x45630000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x3 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___S 28 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000 @@ -89892,13 +89515,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1 (0x005D6A48) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___POR 0x212B8640 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___POR 0x02 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___POR 0x091F6188 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C1_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___POR 0x6 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___POR 0x6 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___POR 0x1 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___S 29 @@ -89906,24 +89530,26 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___S 23 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___M 0x00780000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C1_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C1_1___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___M 0x000003C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___S 3 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1 (0x005D6A4C) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___POR 0x38410000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x5 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___S 28 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000 @@ -89935,60 +89561,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___M 0xFFFF0000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2 (0x005D6A50) -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___POR 0x091B0C40 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___POR 0x12 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2 (0x005D6A54) -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___POR 0x67850000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3 (0x005D6A58) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3 (0x005D6A50) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___POR 0x212B8640 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___POR 0x02 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___POR 0x091F6188 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C1_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___POR 0x6 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___POR 0x6 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___POR 0x1 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___S 29 @@ -89996,24 +89578,26 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___S 23 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___M 0x00780000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C1_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C1_3___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___M 0x000003C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3 (0x005D6A5C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3 (0x005D6A54) #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___POR 0x38410000 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x5 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___S 28 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000 @@ -90025,6 +89609,150 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___M 0xFFFF0000 #define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4 (0x005D6A58) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4___POR 0x061F2190 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__RFCNT_SEL_BSC_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__PFDCP_CPI_4___POR 0x0C +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__CP_LEAKER_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C1_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C2_4___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C3_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_R1_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_R2_4___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__RFCNT_SEL_BSC_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__RFCNT_SEL_BSC_4___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__PFDCP_CPI_4___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__PFDCP_CPI_4___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__CP_LEAKER_4___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__CP_LEAKER_4___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C1_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C1_4___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C2_4___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C2_4___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C3_4___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_C3_4___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_R1_4___M 0x000003C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_R1_4___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_R2_4___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4__LPF_R2_4___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_4___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4 (0x005D6A5C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4___POR 0x45630000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_LO_4___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_HI_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_LO_CLBS_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_HI_CLBS_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_LO_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_LO_4___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_HI_4___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_HI_4___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_LO_CLBS_4___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_LO_CLBS_4___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_HI_CLBS_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4__LPF_VREF_HI_CLBS_4___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_4___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5 (0x005D6A60) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5___POR 0x091F6188 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__RFCNT_SEL_BSC_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__PFDCP_CPI_5___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__CP_LEAKER_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C1_5___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C2_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C3_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_R1_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_R2_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__RFCNT_SEL_BSC_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__RFCNT_SEL_BSC_5___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__PFDCP_CPI_5___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__PFDCP_CPI_5___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__CP_LEAKER_5___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__CP_LEAKER_5___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C1_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C1_5___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C2_5___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C2_5___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C3_5___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_C3_5___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_R1_5___M 0x000003C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_R1_5___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_R2_5___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5__LPF_R2_5___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_5___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5 (0x005D6A64) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_LO_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_HI_5___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_LO_CLBS_5___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_HI_CLBS_5___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_LO_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_LO_5___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_HI_5___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_HI_5___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_LO_CLBS_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_LO_CLBS_5___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_HI_CLBS_5___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5__LPF_VREF_HI_CLBS_5___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_5___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7 (0x005D6A68) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7___POR 0x091F6188 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__RFCNT_SEL_BSC_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__PFDCP_CPI_7___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__CP_LEAKER_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C1_7___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C2_7___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C3_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_R1_7___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_R2_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__RFCNT_SEL_BSC_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__RFCNT_SEL_BSC_7___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__PFDCP_CPI_7___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__PFDCP_CPI_7___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__CP_LEAKER_7___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__CP_LEAKER_7___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C1_7___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C1_7___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C2_7___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C2_7___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C3_7___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_C3_7___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_R1_7___M 0x000003C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_R1_7___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_R2_7___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7__LPF_R2_7___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_7___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7 (0x005D6A6C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_LO_7___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_HI_7___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_LO_CLBS_7___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_HI_CLBS_7___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_LO_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_LO_7___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_HI_7___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_HI_7___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_LO_CLBS_7___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_LO_CLBS_7___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_HI_CLBS_7___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7__LPF_VREF_HI_CLBS_7___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_7___S 16 + #define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL (0x005D6A80) #define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___POR 0x10000000 @@ -90061,2057 +89789,2057 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___M 0x00000007 #define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0 (0x005D7000) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___POR 0x0221D532 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___POR 0x004 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___POR 0x21D532 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___M 0x007FFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1 (0x005D7004) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___M 0x000003F0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2 (0x005D7008) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___POR 0x0042AAAA -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___POR 0x42AAAA -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___M 0x08000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___M 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___M 0x01000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___M 0x00FFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___M 0x0FFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3 (0x005D700C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___POR 0x55000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___POR 0x0AA -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___S 23 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0 (0x005D7010) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___POR 0x116C2599 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___POR 0x9 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___M 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___M 0x00E00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___S 21 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___M 0x001C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___M 0x00000F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___M 0x000000F0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___M 0x00000008 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___M 0x00000004 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1 (0x005D7014) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___POR 0x80680000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___M 0x08000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___M 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___M 0x01000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___M 0x00E00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___S 21 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___M 0x00100000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___M 0x00080000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___M 0x00007C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___M 0x000003E0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___M 0x0000001F -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___M 0xFFF87FFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2 (0x005D7018) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___POR 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___POR 0x400 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___M 0x07FF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___M 0x07FFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0 (0x005D701C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1 (0x005D7020) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___M 0x00004000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___M 0x00002000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___M 0xFFFF7FFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2 (0x005D7024) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___M 0x20000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___M 0x10000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___M 0x08000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___M 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___M 0x01000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___M 0x00004000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___M 0x00002000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___M 0x00000F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___M 0xFF0FFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3 (0x005D7028) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___S 23 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4 (0x005D702C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___POR 0x000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___M 0x007FFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___M 0x007FFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5 (0x005D7030) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___POR 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6 (0x005D7034) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___M 0x0001F800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___M 0x0001FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0 (0x005D7040) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___POR 0x44A43E4A -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___M 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___M 0x20000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___M 0x10000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___M 0x00380000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___M 0x00000380 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___M 0x00000070 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___M 0x0000000C -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___M 0xFCFFFFFE -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___S 1 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1 (0x005D7044) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___POR 0xB4208000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___POR 0x08 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___POR 0x08 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___M 0xFFFF8000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___S 15 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS (0x005D7048) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___M 0x20000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___M 0xFF000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___S 24 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2 (0x005D704C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___M 0xFE000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___S 25 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0 (0x005D7050) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1 (0x005D7054) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2 (0x005D7058) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3 (0x005D705C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4 (0x005D7060) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5 (0x005D7064) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6 (0x005D7068) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7 (0x005D706C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8 (0x005D7070) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9 (0x005D7074) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10 (0x005D7078) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11 (0x005D707C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12 (0x005D7080) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13 (0x005D7084) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14 (0x005D7088) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15 (0x005D708C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16 (0x005D7090) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17 (0x005D7094) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18 (0x005D7098) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19 (0x005D709C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20 (0x005D70A0) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21 (0x005D70A4) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22 (0x005D70A8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23 (0x005D70AC) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24 (0x005D70B0) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25 (0x005D70B4) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___POR 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26 (0x005D70B8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27 (0x005D70BC) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___POR 0x50000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28 (0x005D70C0) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___POR 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29 (0x005D70C4) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30 (0x005D70C8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31 (0x005D70CC) -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___POR 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___S 28 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST (0x005D7100) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___POR 0x06C0F998 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___POR 0xC -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___M 0x70000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___M 0x00004000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___M 0x00002000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___M 0x000000C0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___M 0x00000038 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___M 0xFFFFFFF8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___S 3 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0 (0x005D7104) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___M 0x07FF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___M 0xC7FF07FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1 (0x005D7108) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___POR 0x7FFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2 (0x005D710C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___POR 0x7FFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3 (0x005D7110) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4 (0x005D7114) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5 (0x005D7118) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6 (0x005D711C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0 (0x005D7140) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___POR 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___M 0x00038000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___M 0x00000600 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___M 0x00000180 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___M 0x00000060 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___M 0x00000018 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___M 0x00000006 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___M 0xFFFFFFFE -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___S 1 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1 (0x005D7144) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___M 0x00000030 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___M 0x0000000C -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___M 0x00000003 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2 (0x005D7148) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___M 0xFFFFFF00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___S 8 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3 (0x005D714C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___M 0x00000030 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4 (0x005D7150) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___POR 0x000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___M 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___M 0x00007FC0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___M 0xE00FFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5 (0x005D7154) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___M 0xFF3FFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6 (0x005D7158) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___POR 0x00001C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___M 0x00018000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___M 0x00007000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___M 0x00000200 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___M 0x00000100 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___M 0x3F01FFE0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___S 5 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7 (0x005D715C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___M 0x0C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___M 0x03000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___M 0xFF000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___S 24 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8 (0x005D7160) -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___POR 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___M 0x60000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___M 0x18000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___S 23 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0 (0x005D7180) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___POR 0xAF682022 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___POR 0x22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1 (0x005D7184) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___POR 0x8F669A44 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___POR 0x44 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2 (0x005D7188) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___POR 0x6F859677 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___POR 0x77 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3 (0x005D718C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___POR 0x6F851499 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___POR 0x99 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4 (0x005D7190) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___POR 0xAF6820AA -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5 (0x005D7194) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___POR 0x8F669ADD -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6 (0x005D7198) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___POR 0x6F8596EE -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7 (0x005D719C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___POR 0x6F8514FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___POR 0x0F -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0 (0x005D71A8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___POR 0x10120F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___POR 0x020 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___POR 0x048 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___POR 0x078 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___M 0x007FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___M 0x00003FE0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___M 0xFFFFFFE0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___S 5 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1 (0x005D71AC) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___POR 0x5C3EE7A0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___POR 0x0B8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___POR 0x0FB -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___POR 0x13D -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___M 0x007FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___M 0x00003FE0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___S 5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___M 0xFFFFFFE0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___S 5 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2 (0x005D71B0) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___POR 0xBE800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___POR 0x17D -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___M 0xFF800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___M 0x00000080 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___S 7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___M 0x00000070 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___M 0x00000008 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___M 0x00000004 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___S 2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___M 0xFF8000FE -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___S 1 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3 (0x005D71B4) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___M 0x1F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___M 0x000000FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4 (0x005D71B8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___M 0x1C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___M 0xFFFFC000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___S 14 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0 (0x005D71C0) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___POR 0x00068000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___M 0x10000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___M 0x01000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___M 0x00800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___M 0x000E0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___M 0x00004000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___M 0x00002000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___M 0x11CFF800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___S 11 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1 (0x005D71C4) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___POR 0x0000301B -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___M 0x00007000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___M 0x00000038 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___M 0x00000007 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___M 0x0000703F -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2 (0x005D71C8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___POR 0x6D860000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___M 0xFF8E0002 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___S 1 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3 (0x005D71CC) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___POR 0x00300001 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___M 0x00308003 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4 (0x005D71D0) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___M 0x03E00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___S 21 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___M 0x00100000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___M 0x000E0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___M 0xE3FE0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___S 17 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5 (0x005D71D4) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6 (0x005D71D8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7 (0x005D71DC) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___POR 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___M 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___M 0x3C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___M 0x01E00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___S 21 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___S 21 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0 (0x005D71E0) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___POR 0x00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___M 0x00070000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___M 0x0000C000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___S 14 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___M 0x00003800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___M 0x00000700 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___M 0x000000F0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___M 0x0000000F -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1 (0x005D71E4) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___M 0x00000003 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___M 0xE0000003 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8 (0x005D71E8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___POR 0x1CA2B95C -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___POR 0xC -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___POR 0xC -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___M 0x0E000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___M 0x003C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___M 0x00020000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___M 0x0001E000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___M 0x00000100 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___S 8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___M 0x000000F0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___M 0xFFFFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9 (0x005D71EC) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___POR 0x1C7C6000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___S 31 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___S 26 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___M 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___S 10 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___M 0xFFFFFC00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___S 10 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10 (0x005D71F0) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___POR 0x2210000F -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___M 0x00100000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___M 0x000C0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___S 18 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___M 0x00020000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___S 17 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___M 0x00010000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___M 0x00008000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___M 0x0000000E -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___M 0xFF1F800F -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11 (0x005D71F4) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___POR 0x03000018 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___M 0x00C00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___S 22 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___M 0x00300000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___M 0x00080000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___M 0x00007800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___M 0x00000010 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___S 4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___S 3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___M 0x00000007 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___M 0x0FFFF81F -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12 (0x005D71F8) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___POR 0x007FF7FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___POR 0x7FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___POR 0x7FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___M 0x00800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___M 0x007FF000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___M 0x00FFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13 (0x005D71FC) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___POR 0x007FF7FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___POR 0x7FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___POR 0x7FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___M 0x00800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___M 0x007FF000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___S 12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___M 0x00000800 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___S 11 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___M 0x000007FF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___M 0x00FFFFFF -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0 (0x005D7240) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___POR 0x091B0C00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___POR 0x12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0 (0x005D7244) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___POR 0x67850000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1 (0x005D7248) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___POR 0x212B8640 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___POR 0x02 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1 (0x005D724C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___POR 0x38410000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2 (0x005D7250) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___POR 0x091B0C40 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___POR 0x12 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2 (0x005D7254) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___POR 0x67850000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3 (0x005D7258) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___POR 0x212B8640 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___POR 0x02 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___POR 0x5 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___POR 0x7 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___S 29 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___M 0x00780000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___S 19 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___M 0x00078000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___S 15 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___M 0x00006000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___S 13 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___M 0x00001E00 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___S 9 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___M 0x000001C0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___S 6 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___S 6 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3 (0x005D725C) -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___POR 0x38410000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___S 24 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S 20 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S 16 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___S 16 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL (0x005D7280) -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___POR 0x10000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___POR 0x1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___S 30 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___M 0x30000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___S 28 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___M 0x08000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___S 27 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___M 0x06000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___S 25 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___M 0x01800000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___S 23 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___M 0x00000002 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___S 1 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___M 0x00000001 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___M 0xFF800003 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___S 0 - -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO (0x005D7288) -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___RWC QCSR_REG_RO -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___POR 0x00000000 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___POR 0x0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___M 0x00000007 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___S 0 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___M 0x00000007 -#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0 (0x005D7000) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0___POR 0x0221D532 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0__NBNA___POR 0x004 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0__NF___POR 0x21D532 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0__NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0__NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0__NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0__NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1 (0x005D7004) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__SD_NF_OFFSET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BSTARGET_OFS_COARSE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BSTARGET_OFS_FINE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BS_COARSE_FINE_BDRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__SD_NF_OFFSET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__SD_NF_OFFSET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BSTARGET_OFS_COARSE___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BSTARGET_OFS_FINE___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BSTARGET_OFS_FINE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1__BS_COARSE_FINE_BDRY___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2 (0x005D7008) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2___POR 0x0042AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DELTA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_BASE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DELTA___POR 0x42AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DELTA_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DELTA_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_BASE_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_BASE_SEL___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DIS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DIS___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_START___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_START___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DELTA___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2__FC_DELTA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH3 (0x005D700C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH3___POR 0x55000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH3__FC_DELTA_SUB___POR 0x0AA +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH3__FC_DELTA_SUB___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH3__FC_DELTA_SUB___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_CH3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0 (0x005D7010) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0___POR 0x116C2599 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSTART___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSMODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BKSHFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSETT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSWAIT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSAMPLE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__LPF_VTUNEMON_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_RFCNT_OUT_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__RFCNTEN_DLY_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_VMID_NON_HB___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_VMID_HB___POR 0x9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__NF0B___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__D_DTIM_FBDIV4_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__DISABLE_LPF_TMR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSTART___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSTART___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSMODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSMODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BKSHFT___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BKSHFT___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSETT___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSETT___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSWAIT___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSWAIT___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSAMPLE___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BSSAMPLE___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__LPF_VTUNEMON_TMR___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__LPF_VTUNEMON_TMR___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_RFCNT_OUT_TIME___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__RFCNTEN_DLY_DIS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__RFCNTEN_DLY_DIS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_VMID_NON_HB___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_VMID_NON_HB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_VMID_HB___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_VMID_HB___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_CLBS_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__BS_CLBS_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__NF0B___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__NF0B___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__D_DTIM_FBDIV4_SEL___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__DISABLE_LPF_TMR___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0__DISABLE_LPF_TMR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1 (0x005D7014) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1___POR 0x80680000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDM_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDMOGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__BSTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SD_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__D_PLLMD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__BS_OVCAL_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__PLL_SLIP_DET_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__RESTORE_BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST2_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST1_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST0_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDM_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDM_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDMOGAIN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDMOGAIN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__BSTESTEN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__BSTESTEN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDTESTEN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SDTESTEN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SD_RESET___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__SD_RESET___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__D_PLLMD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__D_PLLMD___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__BS_OVCAL_BDRY___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__BS_OVCAL_BDRY___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__PLL_SLIP_DET_RESET___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__PLL_SLIP_DET_RESET___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__RESTORE_BS_CLBS_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__RESTORE_BS_CLBS_EN___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST2_SEL___M 0x00007C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST2_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST1_SEL___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST1_SEL___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST0_SEL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1__DTEST0_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1___M 0xFFF87FFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2 (0x005D7018) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2__IVCOBK___POR 0x400 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2__TSTCNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2__IVCOBK___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2__IVCOBK___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2__TSTCNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2__TSTCNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0 (0x005D701C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0__RO_BSTARGET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0__RO_BSCOUNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0__RO_BSTARGET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0__RO_BSTARGET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0__RO_BSCOUNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0__RO_BSCOUNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1 (0x005D7020) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_VC_2HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_VC_2LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BIST_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_FVCOBK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSDELTA_B0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_VC_2HI___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_VC_2HI___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_VC_2LO___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_VC_2LO___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BIST_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BIST_ON___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_BSON___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_FVCOBK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1__RO_FVCOBK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1___M 0xFFFF7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2 (0x005D7024) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_EN_REC_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_ANY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_ANY_TX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_CLBS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_TX_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK_DET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_DLL_LOCKED___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_BS_VMID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_CHAN_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_EN___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_EN_REC_LO___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_SYN_EN_REC_LO___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_ANY_RX_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_ANY_RX_EN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_ANY_TX_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_ANY_TX_EN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_CLBS_ON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_CLBS_ON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_TX_MASK___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_TX_MASK___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK_DET___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK_DET___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_PLL_LOCK___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_DLL_LOCKED___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_DLL_LOCKED___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_NON_DTIM_5G___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_NON_DTIM_5G___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_BS_VMID___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_BS_VMID___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_CHAN_IDX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2__RO_CHAN_IDX___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2___M 0xFF0FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3 (0x005D7028) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3__RO_NBNA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3__RO_NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3__RO_NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6WL_SYNTH_BS3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS4 (0x005D702C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS4__RO_NF___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS4__RO_NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS4__RO_NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS4___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS5 (0x005D7030) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS5___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS5__CLBS_QS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS5__CLBS_QS_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS5__CLBS_QS_EN___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS5___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_BS5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6 (0x005D7034) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6__BANK_DBG_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6__RO_INIT_BANK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6__BANK_DBG_OFFSET___M 0x0001F800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6__BANK_DBG_OFFSET___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6__RO_INIT_BANK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6__RO_INIT_BANK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_BS6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0 (0x005D7040) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0___POR 0x44A43E4A +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_VC___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_TX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_RX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_COMP_REPEAT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SMPL_RATE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MAX_STEP___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_STEPSIZE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_HYBRID_BDRY___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SETTIME___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SAMPLE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MASK_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_PSYNC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_VC___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_VC___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_TX___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_TX___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_RX___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_ENABLE_RX___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MODE___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MODE___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_COMP_REPEAT___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SMPL_RATE___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SMPL_RATE___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MAX_STEP___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MAX_STEP___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_STEPSIZE___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_STEPSIZE___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_HYBRID_BDRY___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SETTIME___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SETTIME___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SAMPLE___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_SAMPLE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MASK_SEL___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_MASK_SEL___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_PSYNC_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0__CLBS_PSYNC_EN___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0___M 0xFCFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1 (0x005D7044) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1___POR 0xB4208000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_INC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_DEC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_BDRY___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_INC___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_OVSKIP_DEC___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1__CLBS_SAMPLE_RESTORE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS1___S 15 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS (0x005D7048) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_OFF_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_NON_DTIM_5G___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_NON_DTIM_5G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS__RO_CLBS_OFF_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_CLBS___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2 (0x005D704C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_LIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_OFF_SEL_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_LIN_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2__CLBS_LIN_EN___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS2___S 25 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_0 (0x005D7050) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_0___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_0__CLBS_LIN_OFFSET_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_0___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_1 (0x005D7054) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_1__CLBS_LIN_OFFSET_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_1___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_2 (0x005D7058) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_2___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_2__CLBS_LIN_OFFSET_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_2___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_3 (0x005D705C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_3___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_3__CLBS_LIN_OFFSET_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_3___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_4 (0x005D7060) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_4___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_4__CLBS_LIN_OFFSET_4___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_4___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_5 (0x005D7064) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_5___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_5__CLBS_LIN_OFFSET_5___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_5___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_6 (0x005D7068) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_6___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_6__CLBS_LIN_OFFSET_6___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_6___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_7 (0x005D706C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_7___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_7__CLBS_LIN_OFFSET_7___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_7___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_8 (0x005D7070) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_8___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_8__CLBS_LIN_OFFSET_8___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_8___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_9 (0x005D7074) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_9___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_9__CLBS_LIN_OFFSET_9___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_9___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_10 (0x005D7078) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_10___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_10__CLBS_LIN_OFFSET_10___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_10___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_11 (0x005D707C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_11___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_11__CLBS_LIN_OFFSET_11___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_11___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_12 (0x005D7080) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_12___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_12__CLBS_LIN_OFFSET_12___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_12___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_13 (0x005D7084) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_13___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_13__CLBS_LIN_OFFSET_13___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_13___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_14 (0x005D7088) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_14___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_14__CLBS_LIN_OFFSET_14___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_14___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_15 (0x005D708C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_15___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_15__CLBS_LIN_OFFSET_15___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_15___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_16 (0x005D7090) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_16___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_16__CLBS_LIN_OFFSET_16___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_16___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_17 (0x005D7094) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_17___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_17__CLBS_LIN_OFFSET_17___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_17___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_18 (0x005D7098) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_18___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_18__CLBS_LIN_OFFSET_18___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_18___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_19 (0x005D709C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_19___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_19__CLBS_LIN_OFFSET_19___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_19___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_20 (0x005D70A0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_20___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_20__CLBS_LIN_OFFSET_20___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_20___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_21 (0x005D70A4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_21___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_21__CLBS_LIN_OFFSET_21___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_21___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_22 (0x005D70A8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_22___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_22__CLBS_LIN_OFFSET_22___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_22___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_23 (0x005D70AC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_23___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_23__CLBS_LIN_OFFSET_23___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_23___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_24 (0x005D70B0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_24___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_24__CLBS_LIN_OFFSET_24___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_24___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_25 (0x005D70B4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_25___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_25__CLBS_LIN_OFFSET_25___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_25___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_26 (0x005D70B8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_26___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_26__CLBS_LIN_OFFSET_26___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_26___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_27 (0x005D70BC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_27___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_27__CLBS_LIN_OFFSET_27___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_27___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_28 (0x005D70C0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_28___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_28__CLBS_LIN_OFFSET_28___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_28___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_29 (0x005D70C4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_29___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_29__CLBS_LIN_OFFSET_29___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_29___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_30 (0x005D70C8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_30___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_30__CLBS_LIN_OFFSET_30___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_30___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_31 (0x005D70CC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_31___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_31__CLBS_LIN_OFFSET_31___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_CLBS_31___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST (0x005D7100) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST___POR 0x06C0F998 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOM___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOH___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_VCO_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_NDIV_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_RFCNT_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_RFCNT_OUT_TIME___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__NDIV_BIST_TIME___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_MODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_MODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOM___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOM___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOH___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOH___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOL___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_VMID_KVCOL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_VCO_BIST___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_VCO_BIST___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_NDIV_BIST___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_NDIV_BIST___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_RFCNT_BIST___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__EN_RFCNT_BIST___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_RFCNT_OUT_TIME___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_TIME___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_TIME___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_WAIT___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__BIST_WAIT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__NDIV_BIST_TIME___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST__NDIV_BIST_TIME___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_BIST___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0 (0x005D7104) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_BIST_PASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_BIST_OVERLAP___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_BIST_MONO___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_BIST_PASS___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_BIST_OVERLAP___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_BIST_OVERLAP___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_BIST_MONO___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0__RO_BIST_MONO___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0___M 0xC7FF07FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1 (0x005D7108) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1__RO_OVERLAP_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2 (0x005D710C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2__RO_MONO_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3 (0x005D7110) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3__RO_MIN_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3__RO_MAX_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3__RO_MIN_BANK_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3__RO_MAX_BANK_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4 (0x005D7114) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4__RO_ONEBANK_MID_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5 (0x005D7118) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5__RO_RFCNT_BIST_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6 (0x005D711C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_BIST6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0 (0x005D7140) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0___POR 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__ATOP_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SDM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__EN_DCLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VC_2HI_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VC_2LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SYN_EN_REC_LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__FASTCH_TMR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__FASTCH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_OUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__PRES_RSTB_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VCON_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__DLL_LOCKED_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__ATOP_ISO_DIS_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SDM_EN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SDM_EN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__EN_DCLK___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__EN_DCLK___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VC_2HI_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VC_2HI_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VC_2LO_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VC_2LO_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SYN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SYN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__SYN_EN_REC_LO_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__FASTCH_TMR___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__FASTCH_TMR___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__FASTCH_SEL___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__FASTCH_SEL___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_OUT_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__RFCNT_OUT_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__PRES_RSTB_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__PRES_RSTB_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VCON_SW_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__VCON_SW_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__DLL_LOCKED_OVS___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0__DLL_LOCKED_OVS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1 (0x005D7144) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__VMID_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PRECH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LPF_VCMON_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__BIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__CP_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_VCOBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_FBDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__VMID_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__VMID_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PRECH_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PRECH_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PFD_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PFD_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__CP_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__CP_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__BIAS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__BIAS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PRNDIV_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__PRNDIV_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LPF_VCMON_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LPF_VCMON_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__BIAS_FC_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__BIAS_FC_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__CP_FC_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__CP_FC_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__VCO_FC_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__VCO_FC_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_VCOBUF_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_VCO_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_VCO_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_LOGEN_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_PFD_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_PFD_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_CP_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_CP_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_FBDIV_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1__LDO_FBDIV_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2 (0x005D7148) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOMIX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOAMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__VC_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_VCO_EN_6G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_MODE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_MODE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_VCO_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_VCO_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOGEN_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOGEN_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOGEN_DIV2_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOMIX_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOMIX_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOAMP_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOAMP_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOBUF_CH0_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOBUF_CH1_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOSYNC_RX_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_LOSYNC_TX_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__VC_ISO_DIS_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__VC_ISO_DIS_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_VCO_EN_6G_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2__HB_VCO_EN_6G_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC2___S 8 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3 (0x005D714C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_FBN_BUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_BUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_BUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_DRV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_MODE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_MODE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_LOGEN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_LOGEN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_LOGEN_DRV_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_FBN_BUF_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_BUF_CH0_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LB_BUF_CH1_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LDO_DTIM_VCO_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__LDO_DTIM_VCO_FC_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_PRNDIV_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_DRV_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_DRV_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_LB_MODE_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3__DTIM_HB_MODE_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4 (0x005D7150) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__SYN_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__SYN_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__ANY_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__ANY_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__CHAN_IDX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__CHAN_IDX_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__SYN_MODE_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__SYN_MODE_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__SYN_MODE_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__SYN_MODE_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__ANY_TX_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__ANY_TX_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__ANY_RX_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__ANY_RX_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__CHAN_IDX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__CHAN_IDX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__CHAN_IDX_OVD___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4__CHAN_IDX_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4___M 0xE00FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC4___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5 (0x005D7154) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LDO_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LDO_CPLVL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LOBIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LOBIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LDO_VCO_FC_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LDO_VCO_FC_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LDO_CPLVL_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LDO_CPLVL_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LOBIAS_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LOBIAS_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LOBIAS_FC_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__LOBIAS_FC_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2LATCH_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2OBUF_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_IBUF_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_CORE_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LODIV2_OBUF_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_DIV2_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5___M 0xFF3FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC5___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6 (0x005D7158) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6___POR 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__VCO_VARAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__FASTCH_TMR_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LOMIX_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LOAMP_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_PREBUF_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_CORE_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__LB_LODIV2_POSTBUF_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__VCO_VARAC_EN_OVS___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__VCO_VARAC_EN_OVS___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__FASTCH_TMR_RESTORE___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__FASTCH_TMR_RESTORE___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2LATCH_EN_OPT___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2OBUF_EN_OPT___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LOMIX_EN_OPT___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LOMIX_EN_OPT___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LOAMP_EN_OPT___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LOAMP_EN_OPT___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_IBUF_EN_OPT___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_CORE_EN_OPT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6__HB_LODIV2_OBUF_EN_OPT___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6___M 0x3F01FFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC6___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7 (0x005D715C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__ENBR_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__ENBF_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__SD_ISO_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__SD_PRESET_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__ENBR_IN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__ENBR_IN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__ENBF_IN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__ENBF_IN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__SD_ISO_L_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__SD_ISO_L_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__SD_PRESET_L_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7__SD_PRESET_L_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC7___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8 (0x005D7160) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__VCON_SW_LEG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__VCON_SW_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__SEL_6G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__VCON_SW_LEG___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__VCON_SW_LEG___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__VCON_SW_OPT___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__VCON_SW_OPT___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__SEL_6G_OVS___M 0x18000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__SEL_6G_OVS___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__FC_HB_LOGEN_DIV_OV___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8__FC_HB_LOGEN_DIV_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_PC8___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0 (0x005D7180) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0___POR 0xAF682022 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__KVCO_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__IBIAS_0___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__LOGEN_CAP_0___POR 0x22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__KVCO_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__KVCO_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__IBIAS_0___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__IBIAS_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__LDO_VCO_VREG_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNE_0___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__VCO_CMTUNEB_0___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0__LOGEN_CAP_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1 (0x005D7184) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1___POR 0x8F669A44 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__KVCO_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__IBIAS_1___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__LOGEN_CAP_1___POR 0x44 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__KVCO_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__KVCO_1___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__IBIAS_1___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__IBIAS_1___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__LDO_VCO_VREG_1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__VCO_CMTUNE_1___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__VCO_CMTUNEB_1___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1__LOGEN_CAP_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2 (0x005D7188) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2___POR 0x6F859677 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__KVCO_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__IBIAS_2___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__LOGEN_CAP_2___POR 0x77 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__KVCO_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__KVCO_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__IBIAS_2___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__IBIAS_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__LDO_VCO_VREG_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__VCO_CMTUNE_2___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__VCO_CMTUNEB_2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2__LOGEN_CAP_2___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3 (0x005D718C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3___POR 0x6F851499 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__KVCO_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__IBIAS_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__LOGEN_CAP_3___POR 0x99 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__KVCO_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__KVCO_3___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__IBIAS_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__IBIAS_3___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__LDO_VCO_VREG_3___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__VCO_CMTUNE_3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__VCO_CMTUNEB_3___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3__LOGEN_CAP_3___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4 (0x005D7190) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4___POR 0xAF6820AA +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__KVCO_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__IBIAS_4___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__KVCO_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__KVCO_4___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__IBIAS_4___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__IBIAS_4___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__LDO_VCO_VREG_4___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__VCO_CMTUNE_4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__VCO_CMTUNEB_4___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4__LOGEN_CAP_4___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5 (0x005D7194) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5___POR 0x8F669ADD +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__KVCO_5___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__IBIAS_5___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__KVCO_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__KVCO_5___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__IBIAS_5___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__IBIAS_5___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__LDO_VCO_VREG_5___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__VCO_CMTUNE_5___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__VCO_CMTUNEB_5___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5__LOGEN_CAP_5___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6 (0x005D7198) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6___POR 0x6F8596EE +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__KVCO_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__IBIAS_6___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__KVCO_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__KVCO_6___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__IBIAS_6___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__IBIAS_6___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__LDO_VCO_VREG_6___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__VCO_CMTUNE_6___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__VCO_CMTUNEB_6___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6__LOGEN_CAP_6___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7 (0x005D719C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7___POR 0x6F8514FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__KVCO_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__IBIAS_7___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__KVCO_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__KVCO_7___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__IBIAS_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__IBIAS_7___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__LDO_VCO_VREG_7___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__VCO_CMTUNE_7___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__VCO_CMTUNEB_7___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7__LOGEN_CAP_7___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCOMUX_7___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0 (0x005D71A8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0___POR 0x10120F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH0___POR 0x020 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH1___POR 0x048 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH2___POR 0x078 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH0___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH1___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH1___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH2___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0__KVCO_TH2___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO0___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1 (0x005D71AC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1___POR 0x5C3EE7A0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH3___POR 0x0B8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH4___POR 0x0FB +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH5___POR 0x13D +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH3___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH4___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH5___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1__KVCO_TH5___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO1___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2 (0x005D71B0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2___POR 0xBE800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_TH6___POR 0x17D +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__HB_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__DTIM_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_TH6___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_TH6___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_SEL_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_SEL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_GATE_DIS___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__KVCO_GATE_DIS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__HB_GATE_DIS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__HB_GATE_DIS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__DTIM_GATE_DIS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2__DTIM_GATE_DIS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2___M 0xFF8000FE +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_KVCO2___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3 (0x005D71B4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_KVCO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_IBIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_LDO_VCO_VREG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_VCO_CMTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_VCO_CMTUNEB___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_LOGEN_CAP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_KVCO___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_KVCO___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_IBIAS___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_IBIAS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_LDO_VCO_VREG___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_VCO_CMTUNE___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_VCO_CMTUNE___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_VCO_CMTUNEB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_LOGEN_CAP___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3__RO_LOGEN_CAP___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4 (0x005D71B8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_KVCO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_KVCO_6G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_KVCO_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_KVCO_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_KVCO_6G___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_KVCO_6G___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_VCO_CMTUNE_6G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4__RO_VCO_CMTUNEB_6G___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_KVCO4___S 14 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0 (0x005D71C0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0___POR 0x00068000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_CP_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_VCO_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_PFD_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_FBDIV_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_VREF___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_LEAK___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_CP_LOW_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_PINVC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_PFD_C_FILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_FBDIV_C_FILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_CP_BYPASS___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_CP_BYPASS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_VCO_BYPASS___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_VCO_BYPASS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_PFD_BYPASS___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_PFD_BYPASS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_FBDIV_BYPASS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_VREF___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_VREF___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_BYPASS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_LEAK___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_LOGEN_LEAK___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_CP_LOW_BIAS___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_CP_LOW_BIAS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_PINVC___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_PINVC___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_PFD_C_FILT___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_PFD_C_FILT___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0__D_LDO_FBDIV_C_FILT___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0___M 0x11CFF800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC0___S 11 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1 (0x005D71C4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1___POR 0x0000301B +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_CP_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_SPARE_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_SPARE_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_CP_ISEL_IR25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_CP_ISEL_IR25___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_SPARE_ISEL_IR25___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_SPARE_ISEL_IR25___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_SPARE_ISEL_IC25___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1__D_SPARE_ISEL_IC25___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1___M 0x0000703F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2 (0x005D71C8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2___POR 0x6D860000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_CP_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_VCMON_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_SEL_IC_IPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_PFD_ISEL_IC25___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_CP_ISEL_IC25___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_VCMON_ISEL_IC25___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_VCMON_ISEL_IC25___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_LDO_FBDIV_ISEL_IC25___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_SEL_IC_IPT___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2__D_SEL_IC_IPT___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2___M 0xFF8E0002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC2___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3 (0x005D71CC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3___POR 0x00300001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_LB_LOBUF_DRVSTR___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_VCO_ISRC_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_PFD_HI_LK_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_LB_LOBUF_DRVSTR___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_VCO_ISRC_BYPASS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_VCO_ISRC_BYPASS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_PFD_HI_LK_MODE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3__D_PFD_HI_LK_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3___M 0x00308003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4 (0x005D71D0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_HB_VCO_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__SYN_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_VCO_TST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_HB_VARAC_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_HB_VCO_ATB_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__SYN_ATB_SEL___M 0x03E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__SYN_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_VCO_TST_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_VCO_TST_EN___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_HB_VARAC_BIAS___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4__D_HB_VARAC_BIAS___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4___M 0xE3FE0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC4___S 17 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC5 (0x005D71D4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC5__D_SYN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC5__D_SYN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC6 (0x005D71D8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC6__D_SYN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC6__D_SYN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7 (0x005D71DC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_LO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_LO_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_HI_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_HI_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__CLBS_LPF_VREF_ADJ_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_LO_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_LO_OV___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_LO_OVD___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_LO_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_HI_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_HI_OV___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_HI_OVD___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7__LPF_VREF_HI_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC7___S 21 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0 (0x005D71E0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_RFCNT_SEL_BSC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_PFDCP_CPI___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_CP_LEAKER___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_C2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_C3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_R1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_R2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_RFCNT_SEL_BSC___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_PFDCP_CPI___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_PFDCP_CPI___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_CP_LEAKER___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_CP_LEAKER___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_C2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_C2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_C3___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_C3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_R1___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_R1___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_R2___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_R2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_LO___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_LO___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_HI___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0__RO_LPF_VREF_HI___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1 (0x005D71E4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1__RO_LPF_R2_6G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1__RO_BAND___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1__RO_LPF_R2_6G___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1__RO_LPF_R2_6G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1__RO_BAND___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1__RO_BAND___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1___M 0xE0000003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8 (0x005D71E8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8___POR 0x1CA2B95C +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCOBUF_VREG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCO_OTACUR___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_CP_VREG___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCOBUF_VREG___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCO_OTACUR___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCO_OTACUR___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_VCOBUF_OTACUR___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_CP_VREG___M 0x003C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_CP_VREG___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_SEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_VREG___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_VREG___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_OTACUR___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_PFD_OTACUR___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_SEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_VREG___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_VREG___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8__D_LDO_FBDIV_OTACUR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC8___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9 (0x005D71EC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9___POR 0x107C6000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_FBDIV_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_VREG___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_OTACUR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_MERGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_CPLVL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LOBIAS_BWRSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_LKRON___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_LKRON___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_FBDIV_LKRON___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_FBDIV_LKRON___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_VREG___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_VREG___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_LKRON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_LKRON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_LOGEN_OTACUR___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_CAPSEL___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_CAPSEL___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_FBDIV_CAPSEL___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_VCOBUF_BYPASS___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_MERGE___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_PFD_MERGE___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_VCO_ISEL_IC25___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LDO_CPLVL_BYPASS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LOBIAS_BWRSEL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9__D_LOBIAS_BWRSEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC9___S 10 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10 (0x005D71F0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10___POR 0x2210000F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_VCO_DUALCORE_6G___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_SUPFILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_NBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_PBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_LDO_MERGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_LPF_C1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_VCO_DUALCORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_DEGEN_PROG___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_DEGEN_PROG___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_LKR_DEGEN_PROG___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_VCO_DUALCORE_6G___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_VCO_DUALCORE_6G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_SUPFILT_RES___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_SUPFILT_RES___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_NBIAS_RSEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_NBIAS_RSEL___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_PBIAS_RSEL___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_PBIAS_RSEL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_LDO_MERGE___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_CP_LDO_MERGE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_LPF_C1___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_LPF_C1___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_VCO_DUALCORE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10__D_VCO_DUALCORE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10___M 0xFF1F800F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC10___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11 (0x005D71F4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11___POR 0x03000018 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_HB_LOAMP_CUR___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LOBUF_DRV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_VREF_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_BIAS_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCO_VRES09___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCO_VRES07___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_CP_DRAINSW_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_HB_LOGEN_DIV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_HB_LOAMP_CUR___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_HB_LOAMP_CUR___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LOBUF_DRV___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LOBUF_DRV___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_VREF_FILT_RES___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_VREF_FILT_RES___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_BIAS_FILT_RES___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_BIAS_FILT_RES___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCO_VRES09___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCO_VRES09___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCO_VRES07___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCO_VRES07___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_CP_DRAINSW_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_CP_DRAINSW_EN___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_LB_VCOBUF_DUMLOAD_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_HB_LOGEN_DIV___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11__D_HB_LOGEN_DIV___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11___M 0x0FFFF81F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC11___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12 (0x005D71F8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANK_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANK_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANKA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANKA_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANK_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANK_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANK_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANK_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANKA_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANKA_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANKA_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12__BANKA_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC12___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13 (0x005D71FC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANK_6G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANK_6G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANKA_6G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANKA_6G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANK_6G_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANK_6G_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANK_6G_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANK_6G_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANKA_6G_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANKA_6G_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANKA_6G_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13__BANKA_6G_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_AC13___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0 (0x005D7240) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0___POR 0x091B0C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__PFDCP_CPI_0___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__CP_LEAKER_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_C2_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_C3_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_R1_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_R2_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__RFCNT_SEL_BSC_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__PFDCP_CPI_0___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__CP_LEAKER_0___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__CP_LEAKER_0___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_C2_0___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_C2_0___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_C3_0___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_C3_0___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_R1_0___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_R1_0___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_R2_0___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0__LPF_R2_0___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_0___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0 (0x005D7244) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_LO_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_HI_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_0___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1 (0x005D7248) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1___POR 0x212B8640 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__PFDCP_CPI_1___POR 0x02 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__CP_LEAKER_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_C2_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_C3_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_R1_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_R2_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__RFCNT_SEL_BSC_1___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__PFDCP_CPI_1___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__CP_LEAKER_1___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__CP_LEAKER_1___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_C2_1___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_C2_1___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_C3_1___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_C3_1___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_R1_1___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_R1_1___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_R2_1___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1__LPF_R2_1___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_1___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1 (0x005D724C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1___POR 0x38410000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_LO_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_HI_1___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_1___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2 (0x005D7250) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2___POR 0x091B0C40 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__PFDCP_CPI_2___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__CP_LEAKER_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_C2_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_C3_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_R1_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_R2_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__RFCNT_SEL_BSC_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__PFDCP_CPI_2___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__CP_LEAKER_2___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__CP_LEAKER_2___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_C2_2___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_C2_2___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_C3_2___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_C3_2___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_R1_2___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_R1_2___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_R2_2___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2__LPF_R2_2___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_2___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2 (0x005D7254) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_2___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3 (0x005D7258) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3___POR 0x212B8640 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__PFDCP_CPI_3___POR 0x02 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__CP_LEAKER_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_C2_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_C3_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_R1_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_R2_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__RFCNT_SEL_BSC_3___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__PFDCP_CPI_3___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__CP_LEAKER_3___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__CP_LEAKER_3___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_C2_3___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_C2_3___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_C3_3___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_C3_3___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_R1_3___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_R1_3___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_R2_3___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3__LPF_R2_3___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX_3___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3 (0x005D725C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3___POR 0x38410000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_LO_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_HI_3___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_BANDMUX1_3___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL (0x005D7280) +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_REFBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_REFDIV_EN_OVS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_RESET_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PSYNC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PCAL_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_REFBUF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_REFDIV_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_REFDIV_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_OV___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_OVD___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_RESET_OVS___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PAL_FLAG_RESET_OVS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PSYNC_START___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PSYNC_START___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PCAL_START___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL__PCAL_START___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL___M 0xFF800003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_PAL___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LO (0x005D7288) +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LO___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LO___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LO__RO_LO_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LO__RO_LO_FREQ___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LO__RO_LO_FREQ___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LO___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LO___S 0 #define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00 (0x005D7C00) #define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___RWC QCSR_REG_RW @@ -94420,6 +94148,2373 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LPO2M (0x005DA000) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LPO2M___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LPO2M___POR 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___POR 0x8 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LPO2M___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LPO2M___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LFRC (0x005DA004) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LFRC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LFRC___POR 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___POR 0x80 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LFRC___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LFRC___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_HFRC (0x005DA008) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_HFRC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_HFRC___POR 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___POR 0x8 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_HFRC___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_HFRC___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_0 (0x005DA00C) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_0___POR 0x000000AF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___POR 0xAF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_1 (0x005DA010) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_1___POR 0x0000005C +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___POR 0x5C +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_2 (0x005DA014) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_2___POR 0x00000076 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___POR 0x76 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_3 (0x005DA018) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_3___POR 0x0000005C +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___POR 0x5C +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_CORE_LDO08AO_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0 (0x005DA01C) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___POR 0x000000AF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___POR 0xAF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1 (0x005DA020) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___POR 0x0000003D +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___POR 0x3D +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_0 (0x005DA024) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___POR 0x0000009F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___POR 0x9F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_1 (0x005DA028) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___POR 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___POR 0x20 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_2 (0x005DA02C) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___POR 0x00000076 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___POR 0x76 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_3 (0x005DA030) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___POR 0x00000089 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___POR 0x89 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_0 (0x005DA034) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___POR 0x000000AF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___POR 0xAF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_1 (0x005DA038) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___POR 0x0000003D +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___POR 0x3D +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_2 (0x005DA03C) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___POR 0x000000AF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___POR 0xAF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_3 (0x005DA040) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___POR 0x000000AF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___POR 0xAF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_4 (0x005DA044) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___POR 0x000000AF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___POR 0xAF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0 (0x005DA048) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___POR 0x0000009F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___POR 0x9F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1 (0x005DA04C) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___POR 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___POR 0x20 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_0 (0x005DA050) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___POR 0x0000009F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___POR 0x9F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_1 (0x005DA054) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___POR 0x0000009F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___POR 0x9F +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_0 (0x005DA058) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___POR 0x00000039 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___POR 0x39 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_1 (0x005DA05C) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___POR 0x00000039 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___POR 0x39 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0 (0x005DA060) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___POR 0x000000C6 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___POR 0xC6 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1 (0x005DA064) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___POR 0x000000C6 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___POR 0xC6 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_0 (0x005DA068) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___POR 0x00000079 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___POR 0x79 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_1 (0x005DA06C) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___POR 0x00000079 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___POR 0x79 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0 (0x005DA070) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___POR 0x00000086 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___POR 0x86 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1 (0x005DA074) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___POR 0x00000086 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___POR 0x86 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREA (0x005DA078) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREA___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREA___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREA___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREB (0x005DA07C) +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREB___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREB___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_OTP_TRIM_PMU_SPAREB___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_SVS (0x005DA080) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_SVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_SVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_SVS___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_LSVS (0x005DA084) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_LSVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_LSVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_LSVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_AO_LSVS___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_SVS (0x005DA088) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_SVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_SVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_SVS___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_L1 (0x005DA08C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_L1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_L1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_L1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLCX_L1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_SVS (0x005DA090) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_SVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_SVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_SVS___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_LSVS (0x005DA094) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_LSVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_LSVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_LSVS___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_LSVS___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_L1 (0x005DA098) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_L1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_L1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_L1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_WLMX_L1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREA (0x005DA09C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREA___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREA___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREA___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREB (0x005DA0A0) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREB___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREB___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_OTP_TRIM_PMU_SPAREB___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER (0x005DA0C0) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_VER___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M (0x005DA0C4) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___M 0x0000000C +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LPO2M___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC (0x005DA0C8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_LFRC_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__D_LFRC_DIV2_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_BYPASS___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_BYPASS___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_LFRC_DIS___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_LFRC_DIS___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___M 0x00000030 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__D_LFRC_DIV2_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC__D_LFRC_DIV2_EN___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC___M 0x000000F8 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LFRC___S 3 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC (0x005DA0CC) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC__CORE_SPAREB___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC__CORE_SPAREB___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC__CORE_SPAREB___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___M 0x00000030 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_HFRC___S 4 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET (0x005DA0D0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_SPARE4___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_SPARE4___M 0x0000003C +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_SPARE4___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___M 0x00000003 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDOAO_SET___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE (0x005DA0D4) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_CORE___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG0 (0x005DA0D8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG0__CORE_ATB_REG0___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG0__CORE_ATB_REG0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG0__CORE_ATB_REG0___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG1 (0x005DA0DC) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG1__CORE_ATB_REG1___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG1__CORE_ATB_REG1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG1__CORE_ATB_REG1___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG2 (0x005DA0E0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG2__CORE_ATB_REG2___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG2__CORE_ATB_REG2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG2__CORE_ATB_REG2___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG3 (0x005DA0E4) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG3__CORE_ATB_REG3___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG3__CORE_ATB_REG3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG3__CORE_ATB_REG3___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG4 (0x005DA0E8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG4__CORE_ATB_REG4___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG4__CORE_ATB_REG4___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG4__CORE_ATB_REG4___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG4___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_ATB_REG4___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST (0x005DA0EC) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST__CORE_DTEST1_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST__CORE_DTEST0_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST__CORE_DTEST1_CFG___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST__CORE_DTEST1_CFG___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST__CORE_DTEST0_CFG___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST__CORE_DTEST0_CFG___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTEST___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2 (0x005DA0F0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2___POR 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_SPARE2___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_SPARE2___M 0x00000078 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_SPARE2___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_LDO08AO_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3 (0x005DA0F4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3___M 0x00000033 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_LDO08AO_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_0 (0x005DA0F8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_1 (0x005DA0FC) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_2 (0x005DA100) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_3 (0x005DA104) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_CORE_DTESTO_IGNORE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_0 (0x005DA108) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_1 (0x005DA10C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_2 (0x005DA110) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_3 (0x005DA114) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_0 (0x005DA118) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_1 (0x005DA11C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_2 (0x005DA120) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_3 (0x005DA124) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_CORE_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2 (0x005DA128) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3 (0x005DA12C) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0 (0x005DA130) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1 (0x005DA134) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2 (0x005DA138) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2__BTCMX_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BTCMX_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3 (0x005DA13C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0 (0x005DA140) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1 (0x005DA144) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2 (0x005DA148) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3 (0x005DA14C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0 (0x005DA150) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1 (0x005DA154) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2 (0x005DA158) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3 (0x005DA15C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2 (0x005DA160) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3 (0x005DA164) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0 (0x005DA168) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1 (0x005DA16C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2 (0x005DA170) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2__WLCX_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLCX_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3 (0x005DA174) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_0 (0x005DA178) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_1 (0x005DA17C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_2 (0x005DA180) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_3 (0x005DA184) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_0 (0x005DA188) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_1 (0x005DA18C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_2 (0x005DA190) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_3 (0x005DA194) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2 (0x005DA198) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3 (0x005DA19C) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0 (0x005DA1A0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1 (0x005DA1A4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2 (0x005DA1A8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2__WLMX_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_WLMX_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3 (0x005DA1AC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_0 (0x005DA1B0) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_1 (0x005DA1B4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_2 (0x005DA1B8) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_3 (0x005DA1BC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_0 (0x005DA1C0) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_1 (0x005DA1C4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_2 (0x005DA1C8) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_3 (0x005DA1CC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2 (0x005DA1D0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3 (0x005DA1D4) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0 (0x005DA1D8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1 (0x005DA1DC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2 (0x005DA1E0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2__RFACMN_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFACMN_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3 (0x005DA1E4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0 (0x005DA1E8) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1 (0x005DA1EC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2 (0x005DA1F0) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3 (0x005DA1F4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0 (0x005DA1F8) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1 (0x005DA1FC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2 (0x005DA200) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3 (0x005DA204) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2 (0x005DA208) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3 (0x005DA20C) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0 (0x005DA210) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1 (0x005DA214) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2 (0x005DA218) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2__RFA08_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA08_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3 (0x005DA21C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_0 (0x005DA220) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_1 (0x005DA224) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_2 (0x005DA228) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_3 (0x005DA22C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_0 (0x005DA230) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_1 (0x005DA234) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_2 (0x005DA238) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_3 (0x005DA23C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2 (0x005DA240) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3 (0x005DA244) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0 (0x005DA248) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0___POR 0x00000084 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1 (0x005DA24C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2 (0x005DA250) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2__RFA12_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA12_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3 (0x005DA254) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_0 (0x005DA258) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_1 (0x005DA25C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_2 (0x005DA260) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_3 (0x005DA264) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_0 (0x005DA268) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_1 (0x005DA26C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_2 (0x005DA270) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_3 (0x005DA274) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2 (0x005DA278) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3 (0x005DA27C) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0 (0x005DA280) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1 (0x005DA284) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2 (0x005DA288) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2__PCIE09_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE09_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3 (0x005DA28C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0 (0x005DA290) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1 (0x005DA294) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2 (0x005DA298) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3 (0x005DA29C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0 (0x005DA2A0) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1 (0x005DA2A4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2 (0x005DA2A8) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3 (0x005DA2AC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2 (0x005DA2B0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3 (0x005DA2B4) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0 (0x005DA2B8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0___POR 0x00000084 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1 (0x005DA2BC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2 (0x005DA2C0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2__RFA17_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_RFA17_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3 (0x005DA2C4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_0 (0x005DA2C8) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_1 (0x005DA2CC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_2 (0x005DA2D0) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_3 (0x005DA2D4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_0 (0x005DA2D8) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_1 (0x005DA2DC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_2 (0x005DA2E0) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_3 (0x005DA2E4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2 (0x005DA2E8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3 (0x005DA2EC) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0 (0x005DA2F0) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0___POR 0x00000084 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1 (0x005DA2F4) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2 (0x005DA2F8) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_SPARE6___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_BYPASS___S 5 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2__PCIE18_LIMIT___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_PCIE18_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3 (0x005DA2FC) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0 (0x005DA300) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1 (0x005DA304) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2 (0x005DA308) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3 (0x005DA30C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0 (0x005DA310) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1 (0x005DA314) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2 (0x005DA318) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3 (0x005DA31C) +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1 (0x005DA320) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__WL_EN_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__BT_EN_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__WL_EN_08AO_OVR___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__WL_EN_08AO_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__BT_EN_08AO_OVR___M 0x00000030 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__BT_EN_08AO_OVR___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___M 0x0000000C +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___M 0x00000003 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2 (0x005DA324) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__QOW_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__OK_VDD08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__QOW_08AO_OVR___M 0x000000C0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__QOW_08AO_OVR___S 6 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__OK_VDD08AO_OVR___M 0x00000030 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__OK_VDD08AO_OVR___S 4 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___M 0x0000000C +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___S 2 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___M 0x00000003 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_MISC_OVR_2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG1 (0x005DA328) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG1___POR 0x00000005 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG1__D_BG_TCOMP_TRIM___POR 0x05 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG1__D_BG_TCOMP_TRIM___M 0x0000003F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG1__D_BG_TCOMP_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG1___M 0x0000003F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG1___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG2 (0x005DA32C) +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG2___POR 0x0000002C +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG2__D_BG_IR_TRIM___POR 0x2C +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG2__D_BG_IR_TRIM___M 0x0000003F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG2__D_BG_IR_TRIM___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG2___M 0x0000003F +#define PHYA_IRON2G_RFA_PMU_TEST_PMU_BG2___S 0 + +#define PHYA_IRON2G_RFA_PMU_TEST_SPARE (0x005DA334) +#define PHYA_IRON2G_RFA_PMU_TEST_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_PMU_TEST_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_PMU_TEST_SPARE__D_PMU_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_PMU_TEST_SPARE__D_PMU_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_SPARE__D_PMU_SPARE___S 0 +#define PHYA_IRON2G_RFA_PMU_TEST_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_PMU_TEST_SPARE___S 0 + #define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS (0x005DC000) #define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___POR 0x00000444 @@ -95137,7 +97232,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___M 0x00000004 #define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___S 2 -#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS (0x005DC064) +#define PHYA_IRON2G_RFA_BT_MTOP_XPA_OFF_STATE (0x005DC064) +#define PHYA_IRON2G_RFA_BT_MTOP_XPA_OFF_STATE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_XPA_OFF_STATE___POR 0x00000002 +#define PHYA_IRON2G_RFA_BT_MTOP_XPA_OFF_STATE__XPA_GAIN_OFF___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_XPA_OFF_STATE__XPA_GAIN_OFF___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_XPA_OFF_STATE__XPA_GAIN_OFF___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_XPA_OFF_STATE___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_XPA_OFF_STATE___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS (0x005DC068) #define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH0_TO_CT_OVS___POR 0x0 @@ -95167,7 +97271,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___M 0xF0777777 #define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL (0x005DC068) +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL (0x005DC06C) #define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___RWC QCSR_REG_RO #define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL__RO_BTD_TXRF_GAINSTEP___POR 0x0 @@ -95176,12 +97280,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___M 0x0000000F #define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0 (0x005DC06C) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0 (0x005DC070) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__TX_CLASS0___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__IPA_GAIN0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__BBF_GAIN0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___POR 0x00560002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__TX_CLASS0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__IPA_GAIN0___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__BBF_GAIN0___POR 0x10 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__UPC_GAIN0___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__DA_GAIN0___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__XPA_GAIN0___POR 0x2 @@ -95200,12 +97304,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1 (0x005DC070) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1 (0x005DC074) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__TX_CLASS1___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__IPA_GAIN1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__BBF_GAIN1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___POR 0x00568002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__TX_CLASS1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__IPA_GAIN1___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__BBF_GAIN1___POR 0x14 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__UPC_GAIN1___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__DA_GAIN1___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__XPA_GAIN1___POR 0x2 @@ -95224,12 +97328,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2 (0x005DC074) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2 (0x005DC078) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__TX_CLASS2___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__IPA_GAIN2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__BBF_GAIN2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___POR 0x00576002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__TX_CLASS2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__IPA_GAIN2___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__BBF_GAIN2___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__UPC_GAIN2___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__DA_GAIN2___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__XPA_GAIN2___POR 0x2 @@ -95248,14 +97352,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3 (0x005DC078) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3 (0x005DC07C) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__IPA_GAIN3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__BBF_GAIN3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___POR 0x00576006 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__IPA_GAIN3___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__BBF_GAIN3___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__UPC_GAIN3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__DA_GAIN3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__DA_GAIN3___POR 0x01 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__XPA_GAIN3___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___S 23 @@ -95272,14 +97376,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4 (0x005DC07C) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4 (0x005DC080) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__IPA_GAIN4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__BBF_GAIN4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___POR 0x0057601A +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__IPA_GAIN4___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__BBF_GAIN4___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__UPC_GAIN4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__DA_GAIN4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__DA_GAIN4___POR 0x06 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__XPA_GAIN4___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___S 23 @@ -95296,14 +97400,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5 (0x005DC080) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5 (0x005DC084) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__IPA_GAIN5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__BBF_GAIN5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___POR 0x0057602E +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__IPA_GAIN5___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__BBF_GAIN5___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__UPC_GAIN5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__DA_GAIN5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__DA_GAIN5___POR 0x0B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__XPA_GAIN5___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___S 23 @@ -95320,14 +97424,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6 (0x005DC084) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6 (0x005DC088) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__IPA_GAIN6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__BBF_GAIN6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___POR 0x006F602A +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__IPA_GAIN6___POR 0x1B +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__BBF_GAIN6___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__UPC_GAIN6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__DA_GAIN6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__DA_GAIN6___POR 0x0A #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__XPA_GAIN6___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___S 23 @@ -95344,14 +97448,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7 (0x005DC088) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7 (0x005DC08C) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__IPA_GAIN7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__BBF_GAIN7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___POR 0x00EF603E +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__IPA_GAIN7___POR 0x1B +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__BBF_GAIN7___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__UPC_GAIN7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__DA_GAIN7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__DA_GAIN7___POR 0x0F #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__XPA_GAIN7___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___S 23 @@ -95368,14 +97472,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8 (0x005DC08C) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8 (0x005DC090) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___POR 0x00000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__IPA_GAIN8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__BBF_GAIN8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___POR 0x016F6052 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__IPA_GAIN8___POR 0x1B +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__BBF_GAIN8___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__UPC_GAIN8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__DA_GAIN8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__DA_GAIN8___POR 0x14 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__XPA_GAIN8___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___S 23 @@ -95392,14 +97496,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9 (0x005DC090) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9 (0x005DC094) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___POR 0x00000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__IPA_GAIN9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__BBF_GAIN9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___POR 0x016F607E +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__IPA_GAIN9___POR 0x1B +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__BBF_GAIN9___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__UPC_GAIN9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__DA_GAIN9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__DA_GAIN9___POR 0x1F #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__XPA_GAIN9___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___S 23 @@ -95416,14 +97520,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10 (0x005DC094) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10 (0x005DC098) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___POR 0x00800002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___POR 0x1 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__IPA_GAIN10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__BBF_GAIN10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___POR 0x01A3605A +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___POR 0x3 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__IPA_GAIN10___POR 0x08 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__BBF_GAIN10___POR 0x1B #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__UPC_GAIN10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__DA_GAIN10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__DA_GAIN10___POR 0x16 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__XPA_GAIN10___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___S 23 @@ -95440,14 +97544,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11 (0x005DC098) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11 (0x005DC09C) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___POR 0x00800002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___POR 0x1 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__IPA_GAIN11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__BBF_GAIN11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___POR 0x019FC05E +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___POR 0x3 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__IPA_GAIN11___POR 0x07 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__BBF_GAIN11___POR 0x1E #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__UPC_GAIN11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__DA_GAIN11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__DA_GAIN11___POR 0x17 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__XPA_GAIN11___POR 0x2 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___M 0x01800000 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___S 23 @@ -95464,12 +97568,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12 (0x005DC09C) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12 (0x005DC0A0) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__TX_CLASS12___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__IPA_GAIN12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__BBF_GAIN12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___POR 0x0054E002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__TX_CLASS12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__IPA_GAIN12___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__BBF_GAIN12___POR 0x07 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__UPC_GAIN12___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__DA_GAIN12___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__XPA_GAIN12___POR 0x2 @@ -95488,12 +97592,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13 (0x005DC0A0) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13 (0x005DC0A4) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__TX_CLASS13___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__IPA_GAIN13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__BBF_GAIN13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___POR 0x00544002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__TX_CLASS13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__IPA_GAIN13___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__BBF_GAIN13___POR 0x02 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__UPC_GAIN13___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__DA_GAIN13___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__XPA_GAIN13___POR 0x2 @@ -95512,12 +97616,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14 (0x005DC0A4) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14 (0x005DC0A8) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__TX_CLASS14___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__IPA_GAIN14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__BBF_GAIN14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___POR 0x00548002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__TX_CLASS14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__IPA_GAIN14___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__BBF_GAIN14___POR 0x04 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__UPC_GAIN14___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__DA_GAIN14___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__XPA_GAIN14___POR 0x2 @@ -95536,12 +97640,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___M 0x01FFFFFF #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___S 0 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15 (0x005DC0A8) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15 (0x005DC0AC) #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___POR 0x01000002 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__TX_CLASS15___POR 0x2 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__IPA_GAIN15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__BBF_GAIN15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___POR 0x00554002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__TX_CLASS15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__IPA_GAIN15___POR 0x15 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__BBF_GAIN15___POR 0x0A #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__UPC_GAIN15___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__DA_GAIN15___POR 0x00 #define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__XPA_GAIN15___POR 0x2 @@ -95655,9 +97759,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0 (0x005DC814) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___POR 0x00000101 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___POR 0x01 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___M 0x0000001F @@ -95667,9 +97771,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1 (0x005DC818) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___POR 0x00000102 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___POR 0x02 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___M 0x0000001F @@ -95679,9 +97783,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2 (0x005DC81C) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___POR 0x00000103 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___POR 0x03 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___M 0x0000001F @@ -95691,9 +97795,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3 (0x005DC820) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___POR 0x00000104 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___POR 0x04 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___M 0x0000001F @@ -95703,9 +97807,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4 (0x005DC824) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___POR 0x00000105 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___POR 0x05 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___M 0x0000001F @@ -95715,9 +97819,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5 (0x005DC828) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___POR 0x00000106 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___POR 0x06 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___M 0x0000001F @@ -95727,9 +97831,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6 (0x005DC82C) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___POR 0x00000107 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___POR 0x07 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___M 0x0000001F @@ -95739,9 +97843,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7 (0x005DC830) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___POR 0x00000201 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___POR 0x01 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___M 0x0000001F @@ -95751,9 +97855,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8 (0x005DC834) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___POR 0x00000202 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___POR 0x02 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___M 0x0000001F @@ -95763,9 +97867,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9 (0x005DC838) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___POR 0x00000203 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___POR 0x03 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___M 0x0000001F @@ -95775,9 +97879,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10 (0x005DC83C) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___POR 0x00000204 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___POR 0x04 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___M 0x0000001F @@ -95787,9 +97891,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11 (0x005DC840) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___POR 0x00000205 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___POR 0x05 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___M 0x0000001F @@ -95799,9 +97903,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12 (0x005DC844) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___POR 0x00000206 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___POR 0x06 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___M 0x0000001F @@ -95811,9 +97915,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13 (0x005DC848) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___POR 0x00000207 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___POR 0x07 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___M 0x0000001F @@ -95823,9 +97927,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14 (0x005DC84C) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___POR 0x00000303 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___POR 0x03 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___M 0x0000001F @@ -95835,9 +97939,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15 (0x005DC850) #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___POR 0x00000304 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___POR 0x04 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___M 0x00000F00 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___S 8 #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___M 0x0000001F @@ -95845,6 +97949,198 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___M 0x00000F1F #define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16 (0x005DC854) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16___POR 0x00000305 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16__RCF_GAIN_CODE_16___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16__RCF_PC_CODE_16___POR 0x05 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16__RCF_GAIN_CODE_16___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16__RCF_GAIN_CODE_16___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16__RCF_PC_CODE_16___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16__RCF_PC_CODE_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17 (0x005DC858) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17___POR 0x00000306 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17__RCF_GAIN_CODE_17___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17__RCF_PC_CODE_17___POR 0x06 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17__RCF_GAIN_CODE_17___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17__RCF_GAIN_CODE_17___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17__RCF_PC_CODE_17___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17__RCF_PC_CODE_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18 (0x005DC85C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18___POR 0x00000307 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18__RCF_GAIN_CODE_18___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18__RCF_PC_CODE_18___POR 0x07 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18__RCF_GAIN_CODE_18___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18__RCF_GAIN_CODE_18___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18__RCF_PC_CODE_18___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18__RCF_PC_CODE_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19 (0x005DC860) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19___POR 0x00000308 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19__RCF_GAIN_CODE_19___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19__RCF_PC_CODE_19___POR 0x08 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19__RCF_GAIN_CODE_19___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19__RCF_GAIN_CODE_19___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19__RCF_PC_CODE_19___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19__RCF_PC_CODE_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20 (0x005DC864) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20___POR 0x00000309 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20__RCF_GAIN_CODE_20___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20__RCF_PC_CODE_20___POR 0x09 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20__RCF_GAIN_CODE_20___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20__RCF_GAIN_CODE_20___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20__RCF_PC_CODE_20___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20__RCF_PC_CODE_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21 (0x005DC868) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21___POR 0x0000030A +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21__RCF_GAIN_CODE_21___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21__RCF_PC_CODE_21___POR 0x0A +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21__RCF_GAIN_CODE_21___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21__RCF_GAIN_CODE_21___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21__RCF_PC_CODE_21___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21__RCF_PC_CODE_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22 (0x005DC86C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22___POR 0x0000030B +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22__RCF_GAIN_CODE_22___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22__RCF_PC_CODE_22___POR 0x0B +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22__RCF_GAIN_CODE_22___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22__RCF_GAIN_CODE_22___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22__RCF_PC_CODE_22___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22__RCF_PC_CODE_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23 (0x005DC870) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23___POR 0x0000030C +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23__RCF_GAIN_CODE_23___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23__RCF_PC_CODE_23___POR 0x0C +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23__RCF_GAIN_CODE_23___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23__RCF_GAIN_CODE_23___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23__RCF_PC_CODE_23___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23__RCF_PC_CODE_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24 (0x005DC874) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24___POR 0x0000030D +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24__RCF_GAIN_CODE_24___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24__RCF_PC_CODE_24___POR 0x0D +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24__RCF_GAIN_CODE_24___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24__RCF_GAIN_CODE_24___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24__RCF_PC_CODE_24___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24__RCF_PC_CODE_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25 (0x005DC878) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25___POR 0x0000030E +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25__RCF_GAIN_CODE_25___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25__RCF_PC_CODE_25___POR 0x0E +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25__RCF_GAIN_CODE_25___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25__RCF_GAIN_CODE_25___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25__RCF_PC_CODE_25___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25__RCF_PC_CODE_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26 (0x005DC87C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26___POR 0x0000030F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26__RCF_GAIN_CODE_26___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26__RCF_PC_CODE_26___POR 0x0F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26__RCF_GAIN_CODE_26___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26__RCF_GAIN_CODE_26___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26__RCF_PC_CODE_26___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26__RCF_PC_CODE_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27 (0x005DC880) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27___POR 0x00000310 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27__RCF_GAIN_CODE_27___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27__RCF_PC_CODE_27___POR 0x10 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27__RCF_GAIN_CODE_27___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27__RCF_GAIN_CODE_27___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27__RCF_PC_CODE_27___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27__RCF_PC_CODE_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28 (0x005DC884) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28___POR 0x00000311 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28__RCF_GAIN_CODE_28___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28__RCF_PC_CODE_28___POR 0x11 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28__RCF_GAIN_CODE_28___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28__RCF_GAIN_CODE_28___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28__RCF_PC_CODE_28___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28__RCF_PC_CODE_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29 (0x005DC888) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29___POR 0x00000312 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29__RCF_GAIN_CODE_29___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29__RCF_PC_CODE_29___POR 0x12 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29__RCF_GAIN_CODE_29___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29__RCF_GAIN_CODE_29___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29__RCF_PC_CODE_29___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29__RCF_PC_CODE_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30 (0x005DC88C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30___POR 0x00000313 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30__RCF_GAIN_CODE_30___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30__RCF_PC_CODE_30___POR 0x13 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30__RCF_GAIN_CODE_30___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30__RCF_GAIN_CODE_30___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30__RCF_PC_CODE_30___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30__RCF_PC_CODE_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31 (0x005DC890) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31___POR 0x00000314 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31__RCF_GAIN_CODE_31___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31__RCF_PC_CODE_31___POR 0x14 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31__RCF_GAIN_CODE_31___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31__RCF_GAIN_CODE_31___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31__RCF_PC_CODE_31___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31__RCF_PC_CODE_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_31___S 0 + #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0 (0x005DCC00) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___POR 0x70008884 @@ -95908,7 +98204,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET (0x005DCC08) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2 (0x005DCC08) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX1_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX1_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX1_EN___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX0_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX0_EN___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_EN___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_CTRL___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_CTRL___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET (0x005DCC0C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___POR 0x0 @@ -95950,7 +98264,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___M 0x0007FBFB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0 (0x005DCC0C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0 (0x005DCC10) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___POR 0x0 @@ -95986,7 +98300,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___M 0x0FFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1 (0x005DCC10) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1 (0x005DCC14) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___POR 0x0 @@ -96016,9 +98330,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___M 0x07FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2 (0x005DCC14) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2 (0x005DCC18) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_FE_RFIO_CAP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_BOOST_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___POR 0x0 @@ -96033,6 +98349,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_FE_RFIO_CAP_EN_OVS___M 0x60000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_FE_RFIO_CAP_EN_OVS___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_BOOST_OVS___M 0x18000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_BOOST_OVS___S 27 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___M 0x04000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___M 0x03800000 @@ -96061,12 +98381,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___S 5 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___M 0x0000001F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___M 0x7FFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3 (0x005DCC18) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3 (0x005DCC1C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___POR 0x0 @@ -96077,6 +98399,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OV___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OVD___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OVD___S 28 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___M 0x08000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___S 27 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___M 0x07000000 @@ -96097,24 +98423,21 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___M 0x000003FF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___M 0x7FFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4 (0x005DCC1C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4 (0x005DCC20) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___POR 0x000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___POR 0x000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___M 0x80000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___S 31 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___M 0x7C000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2___M 0x7C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___M 0x01000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___S 24 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___M 0x00FFC000 @@ -96127,17 +98450,20 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___S 2 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___M 0x00000003 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___M 0xFDFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___M 0x7DFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5 (0x005DCC20) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5 (0x005DCC24) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_LP_CORE_XFRM_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXMIX_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_LP_CORE_XFRM_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_LP_CORE_XFRM_OVS___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___M 0x00000300 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___S 8 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___M 0x000000C0 @@ -96148,18 +98474,42 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___S 2 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___M 0x00000003 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___M 0x00000FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL (0x005DCC24) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6 (0x005DCC28) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OV___S 11 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OVD___M 0x000007C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6___M 0x00000FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL (0x005DCC2C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OV___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OVD___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OVD___S 18 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x00020000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S 17 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x0001F000 @@ -96172,25 +98522,28 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S 5 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x0000001F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___M 0x0003FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___M 0x001FFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL (0x005DCC2C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL (0x005DCC30) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RO #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_TX_CLASS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_TX_CLASS___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_TX_CLASS___S 24 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___M 0x0001F000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___S 12 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___M 0x000007C0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___S 6 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___M 0x0000001F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___M 0x0001F7DF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___M 0x0301F7DF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0 (0x005DCC30) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0 (0x005DCC34) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___POR 0x00 @@ -96202,7 +98555,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1 (0x005DCC34) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1 (0x005DCC38) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___POR 0x00 @@ -96214,7 +98567,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2 (0x005DCC38) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2 (0x005DCC3C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___POR 0x00 @@ -96226,7 +98579,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3 (0x005DCC3C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3 (0x005DCC40) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___POR 0x00 @@ -96238,7 +98591,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4 (0x005DCC40) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4 (0x005DCC44) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___POR 0x00 @@ -96250,7 +98603,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5 (0x005DCC44) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5 (0x005DCC48) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___POR 0x00 @@ -96262,7 +98615,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6 (0x005DCC48) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6 (0x005DCC4C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___POR 0x00 @@ -96274,7 +98627,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7 (0x005DCC4C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7 (0x005DCC50) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___POR 0x00 @@ -96286,7 +98639,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8 (0x005DCC50) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8 (0x005DCC54) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___POR 0x00 @@ -96298,7 +98651,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9 (0x005DCC54) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9 (0x005DCC58) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___POR 0x00 @@ -96310,7 +98663,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10 (0x005DCC58) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10 (0x005DCC5C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___POR 0x00 @@ -96322,7 +98675,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11 (0x005DCC5C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11 (0x005DCC60) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___POR 0x00 @@ -96334,7 +98687,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12 (0x005DCC60) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12 (0x005DCC64) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___POR 0x00 @@ -96346,7 +98699,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13 (0x005DCC64) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13 (0x005DCC68) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___POR 0x00 @@ -96358,7 +98711,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14 (0x005DCC68) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14 (0x005DCC6C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___POR 0x00 @@ -96370,7 +98723,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15 (0x005DCC6C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15 (0x005DCC70) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___POR 0x00 @@ -96382,15 +98735,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0 (0x005DCC70) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0 (0x005DCC74) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___POR 0x02407007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CTUNE_0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CELL_EN_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CELL_EN_0___POR 0x007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___M 0x00700000 @@ -96406,15 +98759,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1 (0x005DCC74) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1 (0x005DCC78) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___POR 0x0240700C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CTUNE_1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CELL_EN_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CELL_EN_1___POR 0x00C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___M 0x00700000 @@ -96430,15 +98783,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2 (0x005DCC78) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2 (0x005DCC7C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___POR 0x0240700E +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CTUNE_2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CELL_EN_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CELL_EN_2___POR 0x00E #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___M 0x00700000 @@ -96454,15 +98807,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3 (0x005DCC7C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3 (0x005DCC80) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___POR 0x0240700F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CTUNE_3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CELL_EN_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CELL_EN_3___POR 0x00F #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___M 0x00700000 @@ -96478,15 +98831,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4 (0x005DCC80) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4 (0x005DCC84) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___POR 0x02407015 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CTUNE_4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CELL_EN_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CELL_EN_4___POR 0x015 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___M 0x00700000 @@ -96502,15 +98855,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5 (0x005DCC84) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5 (0x005DCC88) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___POR 0x02407017 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CTUNE_5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CELL_EN_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CELL_EN_5___POR 0x017 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___M 0x00700000 @@ -96526,15 +98879,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6 (0x005DCC88) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6 (0x005DCC8C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___POR 0x0240701A +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CTUNE_6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CELL_EN_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CELL_EN_6___POR 0x01A #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___M 0x00700000 @@ -96550,15 +98903,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7 (0x005DCC8C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7 (0x005DCC90) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___POR 0x02407024 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CTUNE_7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CELL_EN_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CELL_EN_7___POR 0x024 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___M 0x00700000 @@ -96574,15 +98927,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8 (0x005DCC90) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8 (0x005DCC94) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___POR 0x02407028 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CTUNE_8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CELL_EN_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CELL_EN_8___POR 0x028 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___M 0x00700000 @@ -96598,15 +98951,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9 (0x005DCC94) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9 (0x005DCC98) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___POR 0x0240702B +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CTUNE_9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CELL_EN_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CELL_EN_9___POR 0x02B #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___M 0x00700000 @@ -96622,15 +98975,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10 (0x005DCC98) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10 (0x005DCC9C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___POR 0x02407033 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CTUNE_10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CELL_EN_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CELL_EN_10___POR 0x033 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___M 0x00700000 @@ -96646,15 +98999,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11 (0x005DCC9C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11 (0x005DCCA0) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___POR 0x02407037 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CTUNE_11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CELL_EN_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CELL_EN_11___POR 0x037 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___M 0x00700000 @@ -96670,15 +99023,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12 (0x005DCCA0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12 (0x005DCCA4) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___POR 0x0240703C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CTUNE_12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CELL_EN_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CELL_EN_12___POR 0x03C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___M 0x00700000 @@ -96694,15 +99047,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13 (0x005DCCA4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13 (0x005DCCA8) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___POR 0x0240704A +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CTUNE_13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CELL_EN_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CELL_EN_13___POR 0x04A #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___M 0x00700000 @@ -96718,15 +99071,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14 (0x005DCCA8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14 (0x005DCCAC) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___POR 0x02407054 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CTUNE_14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CELL_EN_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CELL_EN_14___POR 0x054 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___M 0x00700000 @@ -96742,15 +99095,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15 (0x005DCCAC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15 (0x005DCCB0) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___POR 0x0240705A +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CTUNE_15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CELL_EN_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CELL_EN_15___POR 0x05A #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___M 0x00700000 @@ -96766,14 +99119,397 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0 (0x005DCCB0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16 (0x005DCCB4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16___POR 0x0240706B +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_IBIAS_LOWER_LIM_16___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_ISLOPE_16___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CTUNE_16___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CAS_BIAS_16___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CASOFF_BIAS_16___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CELL_EN_16___POR 0x06B +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_IBIAS_LOWER_LIM_16___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_IBIAS_LOWER_LIM_16___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_ISLOPE_16___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_ISLOPE_16___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CTUNE_16___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CTUNE_16___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CAS_BIAS_16___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CAS_BIAS_16___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CASOFF_BIAS_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CASOFF_BIAS_16___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CELL_EN_16___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16__DA_CELL_EN_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17 (0x005DCCB8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17___POR 0x02407078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_IBIAS_LOWER_LIM_17___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_ISLOPE_17___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CTUNE_17___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CAS_BIAS_17___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CASOFF_BIAS_17___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CELL_EN_17___POR 0x078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_IBIAS_LOWER_LIM_17___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_IBIAS_LOWER_LIM_17___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_ISLOPE_17___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_ISLOPE_17___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CTUNE_17___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CTUNE_17___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CAS_BIAS_17___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CAS_BIAS_17___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CASOFF_BIAS_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CASOFF_BIAS_17___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CELL_EN_17___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17__DA_CELL_EN_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18 (0x005DCCBC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18___POR 0x02407089 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_IBIAS_LOWER_LIM_18___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_ISLOPE_18___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CTUNE_18___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CAS_BIAS_18___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CASOFF_BIAS_18___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CELL_EN_18___POR 0x089 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_IBIAS_LOWER_LIM_18___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_IBIAS_LOWER_LIM_18___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_ISLOPE_18___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_ISLOPE_18___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CTUNE_18___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CTUNE_18___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CAS_BIAS_18___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CAS_BIAS_18___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CASOFF_BIAS_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CASOFF_BIAS_18___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CELL_EN_18___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18__DA_CELL_EN_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19 (0x005DCCC0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19___POR 0x02407092 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_IBIAS_LOWER_LIM_19___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_ISLOPE_19___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CTUNE_19___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CAS_BIAS_19___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CASOFF_BIAS_19___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CELL_EN_19___POR 0x092 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_IBIAS_LOWER_LIM_19___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_IBIAS_LOWER_LIM_19___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_ISLOPE_19___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_ISLOPE_19___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CTUNE_19___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CTUNE_19___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CAS_BIAS_19___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CAS_BIAS_19___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CASOFF_BIAS_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CASOFF_BIAS_19___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CELL_EN_19___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19__DA_CELL_EN_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20 (0x005DCCC4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20___POR 0x024070A0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_IBIAS_LOWER_LIM_20___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_ISLOPE_20___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CTUNE_20___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CAS_BIAS_20___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CASOFF_BIAS_20___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CELL_EN_20___POR 0x0A0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_IBIAS_LOWER_LIM_20___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_IBIAS_LOWER_LIM_20___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_ISLOPE_20___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_ISLOPE_20___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CTUNE_20___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CTUNE_20___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CAS_BIAS_20___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CAS_BIAS_20___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CASOFF_BIAS_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CASOFF_BIAS_20___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CELL_EN_20___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20__DA_CELL_EN_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21 (0x005DCCC8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21___POR 0x02407096 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_IBIAS_LOWER_LIM_21___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_ISLOPE_21___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CTUNE_21___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CAS_BIAS_21___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CASOFF_BIAS_21___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CELL_EN_21___POR 0x096 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_IBIAS_LOWER_LIM_21___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_IBIAS_LOWER_LIM_21___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_ISLOPE_21___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_ISLOPE_21___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CTUNE_21___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CTUNE_21___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CAS_BIAS_21___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CAS_BIAS_21___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CASOFF_BIAS_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CASOFF_BIAS_21___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CELL_EN_21___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21__DA_CELL_EN_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22 (0x005DCCCC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22___POR 0x024070AD +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_IBIAS_LOWER_LIM_22___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_ISLOPE_22___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CTUNE_22___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CAS_BIAS_22___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CASOFF_BIAS_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CELL_EN_22___POR 0x0AD +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_IBIAS_LOWER_LIM_22___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_IBIAS_LOWER_LIM_22___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_ISLOPE_22___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_ISLOPE_22___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CTUNE_22___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CTUNE_22___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CAS_BIAS_22___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CAS_BIAS_22___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CASOFF_BIAS_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CASOFF_BIAS_22___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CELL_EN_22___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22__DA_CELL_EN_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23 (0x005DCCD0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23___POR 0x024070B4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_IBIAS_LOWER_LIM_23___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_ISLOPE_23___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CTUNE_23___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CAS_BIAS_23___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CASOFF_BIAS_23___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CELL_EN_23___POR 0x0B4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_IBIAS_LOWER_LIM_23___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_IBIAS_LOWER_LIM_23___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_ISLOPE_23___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_ISLOPE_23___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CTUNE_23___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CTUNE_23___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CAS_BIAS_23___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CAS_BIAS_23___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CASOFF_BIAS_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CASOFF_BIAS_23___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CELL_EN_23___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23__DA_CELL_EN_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24 (0x005DCCD4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24___POR 0x024070C8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_IBIAS_LOWER_LIM_24___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_ISLOPE_24___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CTUNE_24___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CAS_BIAS_24___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CASOFF_BIAS_24___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CELL_EN_24___POR 0x0C8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_IBIAS_LOWER_LIM_24___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_IBIAS_LOWER_LIM_24___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_ISLOPE_24___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_ISLOPE_24___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CTUNE_24___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CTUNE_24___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CAS_BIAS_24___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CAS_BIAS_24___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CASOFF_BIAS_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CASOFF_BIAS_24___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CELL_EN_24___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24__DA_CELL_EN_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25 (0x005DCCD8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25___POR 0x024070DC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_IBIAS_LOWER_LIM_25___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_ISLOPE_25___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CTUNE_25___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CAS_BIAS_25___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CASOFF_BIAS_25___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CELL_EN_25___POR 0x0DC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_IBIAS_LOWER_LIM_25___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_IBIAS_LOWER_LIM_25___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_ISLOPE_25___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_ISLOPE_25___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CTUNE_25___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CTUNE_25___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CAS_BIAS_25___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CAS_BIAS_25___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CASOFF_BIAS_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CASOFF_BIAS_25___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CELL_EN_25___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25__DA_CELL_EN_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26 (0x005DCCDC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26___POR 0x024070E6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_IBIAS_LOWER_LIM_26___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_ISLOPE_26___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CTUNE_26___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CAS_BIAS_26___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CASOFF_BIAS_26___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CELL_EN_26___POR 0x0E6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_IBIAS_LOWER_LIM_26___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_IBIAS_LOWER_LIM_26___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_ISLOPE_26___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_ISLOPE_26___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CTUNE_26___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CTUNE_26___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CAS_BIAS_26___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CAS_BIAS_26___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CASOFF_BIAS_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CASOFF_BIAS_26___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CELL_EN_26___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26__DA_CELL_EN_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27 (0x005DCCE0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27___POR 0x024070FB +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_IBIAS_LOWER_LIM_27___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_ISLOPE_27___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CTUNE_27___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CAS_BIAS_27___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CASOFF_BIAS_27___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CELL_EN_27___POR 0x0FB +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_IBIAS_LOWER_LIM_27___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_IBIAS_LOWER_LIM_27___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_ISLOPE_27___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_ISLOPE_27___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CTUNE_27___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CTUNE_27___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CAS_BIAS_27___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CAS_BIAS_27___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CASOFF_BIAS_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CASOFF_BIAS_27___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CELL_EN_27___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27__DA_CELL_EN_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28 (0x005DCCE4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28___POR 0x02407118 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_IBIAS_LOWER_LIM_28___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_ISLOPE_28___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CTUNE_28___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CAS_BIAS_28___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CASOFF_BIAS_28___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CELL_EN_28___POR 0x118 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_IBIAS_LOWER_LIM_28___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_IBIAS_LOWER_LIM_28___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_ISLOPE_28___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_ISLOPE_28___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CTUNE_28___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CTUNE_28___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CAS_BIAS_28___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CAS_BIAS_28___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CASOFF_BIAS_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CASOFF_BIAS_28___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CELL_EN_28___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28__DA_CELL_EN_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29 (0x005DCCE8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29___POR 0x02407140 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_IBIAS_LOWER_LIM_29___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_ISLOPE_29___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CTUNE_29___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CAS_BIAS_29___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CASOFF_BIAS_29___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CELL_EN_29___POR 0x140 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_IBIAS_LOWER_LIM_29___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_IBIAS_LOWER_LIM_29___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_ISLOPE_29___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_ISLOPE_29___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CTUNE_29___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CTUNE_29___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CAS_BIAS_29___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CAS_BIAS_29___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CASOFF_BIAS_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CASOFF_BIAS_29___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CELL_EN_29___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29__DA_CELL_EN_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30 (0x005DCCEC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30___POR 0x02407190 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_IBIAS_LOWER_LIM_30___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_ISLOPE_30___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CTUNE_30___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CAS_BIAS_30___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CASOFF_BIAS_30___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CELL_EN_30___POR 0x190 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_IBIAS_LOWER_LIM_30___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_IBIAS_LOWER_LIM_30___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_ISLOPE_30___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_ISLOPE_30___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CTUNE_30___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CTUNE_30___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CAS_BIAS_30___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CAS_BIAS_30___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CASOFF_BIAS_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CASOFF_BIAS_30___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CELL_EN_30___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30__DA_CELL_EN_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31 (0x005DCCF0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31___POR 0x024071FD +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_IBIAS_LOWER_LIM_31___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_ISLOPE_31___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CTUNE_31___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CAS_BIAS_31___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CASOFF_BIAS_31___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CELL_EN_31___POR 0x1FD +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_IBIAS_LOWER_LIM_31___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_IBIAS_LOWER_LIM_31___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_ISLOPE_31___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_ISLOPE_31___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CTUNE_31___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CTUNE_31___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CAS_BIAS_31___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CAS_BIAS_31___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CASOFF_BIAS_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CASOFF_BIAS_31___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CELL_EN_31___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31__DA_CELL_EN_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_31___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0 (0x005DCCF4) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___POR 0x000005E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___POR 0x02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___M 0x000001C0 @@ -96782,19 +99518,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1 (0x005DCCB4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1 (0x005DCCF8) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___POR 0x000005E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___POR 0x02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___M 0x000001C0 @@ -96803,19 +99536,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2 (0x005DCCB8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2 (0x005DCCFC) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___POR 0x000005E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___POR 0x02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___M 0x000001C0 @@ -96824,19 +99554,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3 (0x005DCCBC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3 (0x005DCD00) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___POR 0x000005E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___POR 0x02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___M 0x000001C0 @@ -96845,19 +99572,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4 (0x005DCCC0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4 (0x005DCD04) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___POR 0x000007E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___M 0x000001C0 @@ -96866,19 +99590,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5 (0x005DCCC4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5 (0x005DCD08) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___POR 0x000007E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___M 0x000001C0 @@ -96887,19 +99608,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6 (0x005DCCC8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6 (0x005DCD0C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___POR 0x000007E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___M 0x000001C0 @@ -96908,19 +99626,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7 (0x005DCCCC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7 (0x005DCD10) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___POR 0x000007E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___M 0x000001C0 @@ -96929,19 +99644,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8 (0x005DCCD0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8 (0x005DCD14) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___POR 0x000009E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___POR 0x04 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___M 0x000001C0 @@ -96950,19 +99662,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9 (0x005DCCD4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9 (0x005DCD18) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___POR 0x00000DE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___POR 0x06 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___M 0x000001C0 @@ -96971,19 +99680,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10 (0x005DCCD8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10 (0x005DCD1C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___POR 0x000015E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___POR 0x0A +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___M 0x000001C0 @@ -96992,19 +99698,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11 (0x005DCCDC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11 (0x005DCD20) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___POR 0x000019E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___POR 0x0C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___M 0x000001C0 @@ -97013,19 +99716,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12 (0x005DCCE0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12 (0x005DCD24) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___POR 0x000019E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___POR 0x0C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___M 0x000001C0 @@ -97034,19 +99734,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13 (0x005DCCE4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13 (0x005DCD28) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___POR 0x00001DE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___POR 0x0E +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___M 0x000001C0 @@ -97055,19 +99752,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14 (0x005DCCE8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14 (0x005DCD2C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___POR 0x00001FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___POR 0x0F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___M 0x000001C0 @@ -97076,19 +99770,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15 (0x005DCCEC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15 (0x005DCD30) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___POR 0x000025E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___POR 0x12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___M 0x000001C0 @@ -97097,30 +99788,319 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0 (0x005DCCF0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16 (0x005DCD34) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16___POR 0x000031E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_CELL_AUX_EN_16___POR 0x18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_CAS_BIAS_AUX_16___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_ILEVEL_16___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_ILEVEL_COARSE_16___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_CELL_AUX_EN_16___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_CELL_AUX_EN_16___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_CAS_BIAS_AUX_16___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_CAS_BIAS_AUX_16___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_ILEVEL_16___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_ILEVEL_16___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_ILEVEL_COARSE_16___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16__DA_ILEVEL_COARSE_16___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_16___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17 (0x005DCD38) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17___POR 0x00003FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_CELL_AUX_EN_17___POR 0x1F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_CAS_BIAS_AUX_17___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_ILEVEL_17___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_ILEVEL_COARSE_17___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_CELL_AUX_EN_17___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_CELL_AUX_EN_17___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_CAS_BIAS_AUX_17___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_CAS_BIAS_AUX_17___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_ILEVEL_17___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_ILEVEL_17___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_ILEVEL_COARSE_17___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17__DA_ILEVEL_COARSE_17___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_17___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18 (0x005DCD3C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18___POR 0x000055E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_CELL_AUX_EN_18___POR 0x2A +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_CAS_BIAS_AUX_18___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_ILEVEL_18___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_ILEVEL_COARSE_18___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_CELL_AUX_EN_18___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_CELL_AUX_EN_18___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_CAS_BIAS_AUX_18___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_CAS_BIAS_AUX_18___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_ILEVEL_18___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_ILEVEL_18___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_ILEVEL_COARSE_18___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18__DA_ILEVEL_COARSE_18___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_18___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19 (0x005DCD40) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19___POR 0x000055E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_CELL_AUX_EN_19___POR 0x2A +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_CAS_BIAS_AUX_19___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_ILEVEL_19___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_ILEVEL_COARSE_19___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_CELL_AUX_EN_19___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_CELL_AUX_EN_19___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_CAS_BIAS_AUX_19___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_CAS_BIAS_AUX_19___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_ILEVEL_19___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_ILEVEL_19___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_ILEVEL_COARSE_19___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19__DA_ILEVEL_COARSE_19___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_19___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20 (0x005DCD44) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20___POR 0x000067E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_CELL_AUX_EN_20___POR 0x33 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_CAS_BIAS_AUX_20___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_ILEVEL_20___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_ILEVEL_COARSE_20___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_CELL_AUX_EN_20___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_CELL_AUX_EN_20___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_CAS_BIAS_AUX_20___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_CAS_BIAS_AUX_20___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_ILEVEL_20___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_ILEVEL_20___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_ILEVEL_COARSE_20___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20__DA_ILEVEL_COARSE_20___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_20___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21 (0x005DCD48) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21___POR 0x000079E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_CELL_AUX_EN_21___POR 0x3C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_CAS_BIAS_AUX_21___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_ILEVEL_21___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_ILEVEL_COARSE_21___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_CELL_AUX_EN_21___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_CELL_AUX_EN_21___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_CAS_BIAS_AUX_21___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_CAS_BIAS_AUX_21___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_ILEVEL_21___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_ILEVEL_21___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_ILEVEL_COARSE_21___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21__DA_ILEVEL_COARSE_21___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_21___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22 (0x005DCD4C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_CELL_AUX_EN_22___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_CAS_BIAS_AUX_22___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_ILEVEL_22___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_ILEVEL_COARSE_22___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_CELL_AUX_EN_22___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_CELL_AUX_EN_22___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_CAS_BIAS_AUX_22___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_CAS_BIAS_AUX_22___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_ILEVEL_22___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_ILEVEL_22___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_ILEVEL_COARSE_22___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22__DA_ILEVEL_COARSE_22___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_22___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23 (0x005DCD50) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_CELL_AUX_EN_23___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_CAS_BIAS_AUX_23___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_ILEVEL_23___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_ILEVEL_COARSE_23___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_CELL_AUX_EN_23___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_CELL_AUX_EN_23___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_CAS_BIAS_AUX_23___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_CAS_BIAS_AUX_23___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_ILEVEL_23___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_ILEVEL_23___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_ILEVEL_COARSE_23___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23__DA_ILEVEL_COARSE_23___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_23___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24 (0x005DCD54) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_CELL_AUX_EN_24___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_CAS_BIAS_AUX_24___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_ILEVEL_24___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_ILEVEL_COARSE_24___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_CELL_AUX_EN_24___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_CELL_AUX_EN_24___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_CAS_BIAS_AUX_24___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_CAS_BIAS_AUX_24___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_ILEVEL_24___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_ILEVEL_24___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_ILEVEL_COARSE_24___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24__DA_ILEVEL_COARSE_24___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_24___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25 (0x005DCD58) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_CELL_AUX_EN_25___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_CAS_BIAS_AUX_25___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_ILEVEL_25___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_ILEVEL_COARSE_25___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_CELL_AUX_EN_25___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_CELL_AUX_EN_25___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_CAS_BIAS_AUX_25___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_CAS_BIAS_AUX_25___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_ILEVEL_25___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_ILEVEL_25___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_ILEVEL_COARSE_25___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25__DA_ILEVEL_COARSE_25___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_25___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26 (0x005DCD5C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_CELL_AUX_EN_26___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_CAS_BIAS_AUX_26___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_ILEVEL_26___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_ILEVEL_COARSE_26___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_CELL_AUX_EN_26___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_CELL_AUX_EN_26___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_CAS_BIAS_AUX_26___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_CAS_BIAS_AUX_26___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_ILEVEL_26___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_ILEVEL_26___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_ILEVEL_COARSE_26___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26__DA_ILEVEL_COARSE_26___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_26___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27 (0x005DCD60) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_CELL_AUX_EN_27___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_CAS_BIAS_AUX_27___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_ILEVEL_27___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_ILEVEL_COARSE_27___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_CELL_AUX_EN_27___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_CELL_AUX_EN_27___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_CAS_BIAS_AUX_27___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_CAS_BIAS_AUX_27___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_ILEVEL_27___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_ILEVEL_27___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_ILEVEL_COARSE_27___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27__DA_ILEVEL_COARSE_27___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_27___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28 (0x005DCD64) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_CELL_AUX_EN_28___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_CAS_BIAS_AUX_28___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_ILEVEL_28___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_ILEVEL_COARSE_28___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_CELL_AUX_EN_28___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_CELL_AUX_EN_28___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_CAS_BIAS_AUX_28___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_CAS_BIAS_AUX_28___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_ILEVEL_28___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_ILEVEL_28___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_ILEVEL_COARSE_28___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28__DA_ILEVEL_COARSE_28___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_28___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29 (0x005DCD68) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_CELL_AUX_EN_29___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_CAS_BIAS_AUX_29___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_ILEVEL_29___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_ILEVEL_COARSE_29___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_CELL_AUX_EN_29___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_CELL_AUX_EN_29___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_CAS_BIAS_AUX_29___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_CAS_BIAS_AUX_29___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_ILEVEL_29___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_ILEVEL_29___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_ILEVEL_COARSE_29___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29__DA_ILEVEL_COARSE_29___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_29___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30 (0x005DCD6C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_CELL_AUX_EN_30___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_CAS_BIAS_AUX_30___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_ILEVEL_30___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_ILEVEL_COARSE_30___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_CELL_AUX_EN_30___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_CELL_AUX_EN_30___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_CAS_BIAS_AUX_30___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_CAS_BIAS_AUX_30___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_ILEVEL_30___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_ILEVEL_30___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_ILEVEL_COARSE_30___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30__DA_ILEVEL_COARSE_30___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_30___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31 (0x005DCD70) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_CELL_AUX_EN_31___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_CAS_BIAS_AUX_31___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_ILEVEL_31___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_ILEVEL_COARSE_31___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_CELL_AUX_EN_31___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_CELL_AUX_EN_31___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_CAS_BIAS_AUX_31___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_CAS_BIAS_AUX_31___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_ILEVEL_31___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_ILEVEL_31___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_ILEVEL_COARSE_31___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31__DA_ILEVEL_COARSE_31___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_31___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0 (0x005DCD74) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_BOOST_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__FE_RFIO_CAP_EN_0___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_BOOST_0___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_BOOST_0___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__FE_RFIO_CAP_EN_0___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__FE_RFIO_CAP_EN_0___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___M 0x00000380 @@ -97129,28 +100109,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1 (0x005DCCF4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1 (0x005DCD78) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_BOOST_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__FE_RFIO_CAP_EN_1___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_BOOST_1___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_BOOST_1___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__FE_RFIO_CAP_EN_1___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__FE_RFIO_CAP_EN_1___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___M 0x00000380 @@ -97159,28 +100142,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2 (0x005DCCF8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2 (0x005DCD7C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_BOOST_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__FE_RFIO_CAP_EN_2___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_BOOST_2___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_BOOST_2___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__FE_RFIO_CAP_EN_2___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__FE_RFIO_CAP_EN_2___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___M 0x00000380 @@ -97189,28 +100175,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3 (0x005DCCFC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3 (0x005DCD80) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_BOOST_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__FE_RFIO_CAP_EN_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_BOOST_3___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_BOOST_3___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__FE_RFIO_CAP_EN_3___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__FE_RFIO_CAP_EN_3___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___M 0x00000380 @@ -97219,28 +100208,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4 (0x005DCD00) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4 (0x005DCD84) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_BOOST_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__FE_RFIO_CAP_EN_4___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_BOOST_4___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_BOOST_4___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__FE_RFIO_CAP_EN_4___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__FE_RFIO_CAP_EN_4___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___M 0x00000380 @@ -97249,28 +100241,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5 (0x005DCD04) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5 (0x005DCD88) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_BOOST_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__FE_RFIO_CAP_EN_5___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_BOOST_5___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_BOOST_5___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__FE_RFIO_CAP_EN_5___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__FE_RFIO_CAP_EN_5___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___M 0x00000380 @@ -97279,28 +100274,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6 (0x005DCD08) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6 (0x005DCD8C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_BOOST_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__FE_RFIO_CAP_EN_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_BOOST_6___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_BOOST_6___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__FE_RFIO_CAP_EN_6___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__FE_RFIO_CAP_EN_6___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___M 0x00000380 @@ -97309,28 +100307,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7 (0x005DCD0C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7 (0x005DCD90) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___POR 0x1A8C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_BOOST_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__FE_RFIO_CAP_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_BOOST_7___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_BOOST_7___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__FE_RFIO_CAP_EN_7___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__FE_RFIO_CAP_EN_7___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___M 0x00000380 @@ -97339,28 +100340,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8 (0x005DCD10) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8 (0x005DCD94) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___POR 0x128C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_BOOST_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__FE_RFIO_CAP_EN_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_BOOST_8___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_BOOST_8___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__FE_RFIO_CAP_EN_8___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__FE_RFIO_CAP_EN_8___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___M 0x00000380 @@ -97369,28 +100373,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9 (0x005DCD14) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9 (0x005DCD98) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___POR 0x0A8C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_BOOST_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__FE_RFIO_CAP_EN_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_BOOST_9___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_BOOST_9___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__FE_RFIO_CAP_EN_9___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__FE_RFIO_CAP_EN_9___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___M 0x00000380 @@ -97399,28 +100406,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10 (0x005DCD18) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10 (0x005DCD9C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_BOOST_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__FE_RFIO_CAP_EN_10___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_BOOST_10___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_BOOST_10___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__FE_RFIO_CAP_EN_10___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__FE_RFIO_CAP_EN_10___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___M 0x00000380 @@ -97429,28 +100439,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11 (0x005DCD1C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11 (0x005DCDA0) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___POR 0x028C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_BOOST_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__FE_RFIO_CAP_EN_11___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_BOOST_11___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_BOOST_11___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__FE_RFIO_CAP_EN_11___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__FE_RFIO_CAP_EN_11___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___M 0x00000380 @@ -97459,28 +100472,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12 (0x005DCD20) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12 (0x005DCDA4) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___POR 0x428C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_BOOST_12___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__FE_RFIO_CAP_EN_12___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_BOOST_12___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_BOOST_12___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__FE_RFIO_CAP_EN_12___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__FE_RFIO_CAP_EN_12___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___M 0x00000380 @@ -97489,28 +100505,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13 (0x005DCD24) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13 (0x005DCDA8) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_BOOST_13___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__FE_RFIO_CAP_EN_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_BOOST_13___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_BOOST_13___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__FE_RFIO_CAP_EN_13___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__FE_RFIO_CAP_EN_13___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___M 0x00000380 @@ -97519,28 +100538,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14 (0x005DCD28) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14 (0x005DCDAC) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_BOOST_14___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__FE_RFIO_CAP_EN_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_BOOST_14___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_BOOST_14___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__FE_RFIO_CAP_EN_14___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__FE_RFIO_CAP_EN_14___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___M 0x00000380 @@ -97549,28 +100571,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15 (0x005DCD2C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15 (0x005DCDB0) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___POR 0x5A8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_BOOST_15___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__FE_RFIO_CAP_EN_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_BOOST_15___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_BOOST_15___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__FE_RFIO_CAP_EN_15___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__FE_RFIO_CAP_EN_15___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___M 0x00000380 @@ -97579,16 +100604,544 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0 (0x005DCD30) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16 (0x005DCDB4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16___POR 0x568C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_IBIAS_BOOST_16___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__FE_RFIO_CAP_EN_16___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_IBIAS_LOWER_LIM_16___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_ISLOPE_16___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_ILEVEL_16___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX1_16___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX0_16___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_16___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CASOFF_BIAS_16___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_IBIAS_BOOST_16___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_IBIAS_BOOST_16___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__FE_RFIO_CAP_EN_16___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__FE_RFIO_CAP_EN_16___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_IBIAS_LOWER_LIM_16___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_IBIAS_LOWER_LIM_16___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_ISLOPE_16___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_ISLOPE_16___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_ILEVEL_16___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_ILEVEL_16___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX1_16___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX1_16___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX0_16___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX0_16___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_16___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CAS_BIAS_16___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CASOFF_BIAS_16___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16__PA_CASOFF_BIAS_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17 (0x005DCDB8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_IBIAS_BOOST_17___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__FE_RFIO_CAP_EN_17___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_IBIAS_LOWER_LIM_17___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_ISLOPE_17___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_ILEVEL_17___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX1_17___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX0_17___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_17___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CASOFF_BIAS_17___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_IBIAS_BOOST_17___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_IBIAS_BOOST_17___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__FE_RFIO_CAP_EN_17___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__FE_RFIO_CAP_EN_17___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_IBIAS_LOWER_LIM_17___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_IBIAS_LOWER_LIM_17___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_ISLOPE_17___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_ISLOPE_17___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_ILEVEL_17___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_ILEVEL_17___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX1_17___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX1_17___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX0_17___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX0_17___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_17___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CAS_BIAS_17___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CASOFF_BIAS_17___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17__PA_CASOFF_BIAS_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18 (0x005DCDBC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18___POR 0x4E8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_IBIAS_BOOST_18___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__FE_RFIO_CAP_EN_18___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_IBIAS_LOWER_LIM_18___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_ISLOPE_18___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_ILEVEL_18___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX1_18___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX0_18___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_18___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CASOFF_BIAS_18___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_IBIAS_BOOST_18___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_IBIAS_BOOST_18___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__FE_RFIO_CAP_EN_18___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__FE_RFIO_CAP_EN_18___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_IBIAS_LOWER_LIM_18___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_IBIAS_LOWER_LIM_18___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_ISLOPE_18___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_ISLOPE_18___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_ILEVEL_18___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_ILEVEL_18___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX1_18___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX1_18___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX0_18___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX0_18___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_18___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CAS_BIAS_18___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CASOFF_BIAS_18___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18__PA_CASOFF_BIAS_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19 (0x005DCDC0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19___POR 0x4A8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_IBIAS_BOOST_19___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__FE_RFIO_CAP_EN_19___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_IBIAS_LOWER_LIM_19___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_ISLOPE_19___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_ILEVEL_19___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX1_19___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX0_19___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_19___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CASOFF_BIAS_19___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_IBIAS_BOOST_19___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_IBIAS_BOOST_19___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__FE_RFIO_CAP_EN_19___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__FE_RFIO_CAP_EN_19___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_IBIAS_LOWER_LIM_19___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_IBIAS_LOWER_LIM_19___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_ISLOPE_19___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_ISLOPE_19___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_ILEVEL_19___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_ILEVEL_19___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX1_19___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX1_19___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX0_19___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX0_19___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_19___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CAS_BIAS_19___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CASOFF_BIAS_19___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19__PA_CASOFF_BIAS_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20 (0x005DCDC4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20___POR 0x468C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_IBIAS_BOOST_20___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__FE_RFIO_CAP_EN_20___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_IBIAS_LOWER_LIM_20___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_ISLOPE_20___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_ILEVEL_20___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX1_20___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX0_20___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_20___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CASOFF_BIAS_20___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_IBIAS_BOOST_20___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_IBIAS_BOOST_20___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__FE_RFIO_CAP_EN_20___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__FE_RFIO_CAP_EN_20___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_IBIAS_LOWER_LIM_20___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_IBIAS_LOWER_LIM_20___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_ISLOPE_20___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_ISLOPE_20___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_ILEVEL_20___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_ILEVEL_20___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX1_20___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX1_20___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX0_20___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX0_20___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_20___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CAS_BIAS_20___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CASOFF_BIAS_20___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20__PA_CASOFF_BIAS_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21 (0x005DCDC8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21___POR 0x428C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_IBIAS_BOOST_21___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__FE_RFIO_CAP_EN_21___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_IBIAS_LOWER_LIM_21___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_ISLOPE_21___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_ILEVEL_21___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX1_21___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX0_21___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_21___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CASOFF_BIAS_21___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_IBIAS_BOOST_21___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_IBIAS_BOOST_21___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__FE_RFIO_CAP_EN_21___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__FE_RFIO_CAP_EN_21___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_IBIAS_LOWER_LIM_21___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_IBIAS_LOWER_LIM_21___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_ISLOPE_21___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_ISLOPE_21___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_ILEVEL_21___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_ILEVEL_21___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX1_21___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX1_21___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX0_21___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX0_21___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_21___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CAS_BIAS_21___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CASOFF_BIAS_21___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21__PA_CASOFF_BIAS_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22 (0x005DCDCC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22___POR 0x428C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_IBIAS_BOOST_22___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__FE_RFIO_CAP_EN_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_IBIAS_LOWER_LIM_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_ISLOPE_22___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_ILEVEL_22___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX1_22___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX0_22___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_22___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CASOFF_BIAS_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_IBIAS_BOOST_22___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_IBIAS_BOOST_22___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__FE_RFIO_CAP_EN_22___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__FE_RFIO_CAP_EN_22___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_IBIAS_LOWER_LIM_22___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_IBIAS_LOWER_LIM_22___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_ISLOPE_22___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_ISLOPE_22___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_ILEVEL_22___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_ILEVEL_22___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX1_22___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX1_22___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX0_22___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX0_22___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_22___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CAS_BIAS_22___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CASOFF_BIAS_22___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22__PA_CASOFF_BIAS_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23 (0x005DCDD0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_IBIAS_BOOST_23___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__FE_RFIO_CAP_EN_23___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_IBIAS_LOWER_LIM_23___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_ISLOPE_23___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_ILEVEL_23___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX1_23___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX0_23___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_23___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CASOFF_BIAS_23___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_IBIAS_BOOST_23___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_IBIAS_BOOST_23___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__FE_RFIO_CAP_EN_23___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__FE_RFIO_CAP_EN_23___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_IBIAS_LOWER_LIM_23___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_IBIAS_LOWER_LIM_23___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_ISLOPE_23___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_ISLOPE_23___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_ILEVEL_23___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_ILEVEL_23___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX1_23___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX1_23___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX0_23___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX0_23___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_23___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CAS_BIAS_23___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CASOFF_BIAS_23___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23__PA_CASOFF_BIAS_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24 (0x005DCDD4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_IBIAS_BOOST_24___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__FE_RFIO_CAP_EN_24___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_IBIAS_LOWER_LIM_24___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_ISLOPE_24___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_ILEVEL_24___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX1_24___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX0_24___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_24___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CASOFF_BIAS_24___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_IBIAS_BOOST_24___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_IBIAS_BOOST_24___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__FE_RFIO_CAP_EN_24___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__FE_RFIO_CAP_EN_24___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_IBIAS_LOWER_LIM_24___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_IBIAS_LOWER_LIM_24___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_ISLOPE_24___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_ISLOPE_24___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_ILEVEL_24___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_ILEVEL_24___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX1_24___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX1_24___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX0_24___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX0_24___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_24___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CAS_BIAS_24___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CASOFF_BIAS_24___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24__PA_CASOFF_BIAS_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25 (0x005DCDD8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25___POR 0x428C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_IBIAS_BOOST_25___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__FE_RFIO_CAP_EN_25___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_IBIAS_LOWER_LIM_25___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_ISLOPE_25___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_ILEVEL_25___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX1_25___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX0_25___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_25___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CASOFF_BIAS_25___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_IBIAS_BOOST_25___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_IBIAS_BOOST_25___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__FE_RFIO_CAP_EN_25___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__FE_RFIO_CAP_EN_25___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_IBIAS_LOWER_LIM_25___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_IBIAS_LOWER_LIM_25___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_ISLOPE_25___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_ISLOPE_25___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_ILEVEL_25___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_ILEVEL_25___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX1_25___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX1_25___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX0_25___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX0_25___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_25___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CAS_BIAS_25___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CASOFF_BIAS_25___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25__PA_CASOFF_BIAS_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26 (0x005DCDDC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26___POR 0x468C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_IBIAS_BOOST_26___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__FE_RFIO_CAP_EN_26___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_IBIAS_LOWER_LIM_26___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_ISLOPE_26___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_ILEVEL_26___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX1_26___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX0_26___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_26___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CASOFF_BIAS_26___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_IBIAS_BOOST_26___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_IBIAS_BOOST_26___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__FE_RFIO_CAP_EN_26___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__FE_RFIO_CAP_EN_26___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_IBIAS_LOWER_LIM_26___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_IBIAS_LOWER_LIM_26___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_ISLOPE_26___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_ISLOPE_26___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_ILEVEL_26___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_ILEVEL_26___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX1_26___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX1_26___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX0_26___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX0_26___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_26___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CAS_BIAS_26___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CASOFF_BIAS_26___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26__PA_CASOFF_BIAS_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27 (0x005DCDE0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27___POR 0x4A8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_IBIAS_BOOST_27___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__FE_RFIO_CAP_EN_27___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_IBIAS_LOWER_LIM_27___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_ISLOPE_27___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_ILEVEL_27___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX1_27___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX0_27___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_27___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CASOFF_BIAS_27___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_IBIAS_BOOST_27___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_IBIAS_BOOST_27___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__FE_RFIO_CAP_EN_27___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__FE_RFIO_CAP_EN_27___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_IBIAS_LOWER_LIM_27___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_IBIAS_LOWER_LIM_27___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_ISLOPE_27___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_ISLOPE_27___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_ILEVEL_27___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_ILEVEL_27___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX1_27___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX1_27___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX0_27___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX0_27___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_27___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CAS_BIAS_27___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CASOFF_BIAS_27___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27__PA_CASOFF_BIAS_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28 (0x005DCDE4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28___POR 0x4E8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_IBIAS_BOOST_28___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__FE_RFIO_CAP_EN_28___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_IBIAS_LOWER_LIM_28___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_ISLOPE_28___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_ILEVEL_28___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX1_28___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX0_28___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_28___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CASOFF_BIAS_28___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_IBIAS_BOOST_28___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_IBIAS_BOOST_28___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__FE_RFIO_CAP_EN_28___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__FE_RFIO_CAP_EN_28___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_IBIAS_LOWER_LIM_28___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_IBIAS_LOWER_LIM_28___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_ISLOPE_28___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_ISLOPE_28___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_ILEVEL_28___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_ILEVEL_28___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX1_28___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX1_28___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX0_28___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX0_28___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_28___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CAS_BIAS_28___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CASOFF_BIAS_28___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28__PA_CASOFF_BIAS_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29 (0x005DCDE8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_IBIAS_BOOST_29___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__FE_RFIO_CAP_EN_29___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_IBIAS_LOWER_LIM_29___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_ISLOPE_29___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_ILEVEL_29___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX1_29___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX0_29___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_29___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CASOFF_BIAS_29___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_IBIAS_BOOST_29___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_IBIAS_BOOST_29___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__FE_RFIO_CAP_EN_29___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__FE_RFIO_CAP_EN_29___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_IBIAS_LOWER_LIM_29___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_IBIAS_LOWER_LIM_29___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_ISLOPE_29___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_ISLOPE_29___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_ILEVEL_29___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_ILEVEL_29___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX1_29___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX1_29___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX0_29___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX0_29___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_29___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CAS_BIAS_29___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CASOFF_BIAS_29___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29__PA_CASOFF_BIAS_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30 (0x005DCDEC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30___POR 0x568C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_IBIAS_BOOST_30___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__FE_RFIO_CAP_EN_30___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_IBIAS_LOWER_LIM_30___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_ISLOPE_30___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_ILEVEL_30___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX1_30___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX0_30___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_30___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CASOFF_BIAS_30___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_IBIAS_BOOST_30___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_IBIAS_BOOST_30___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__FE_RFIO_CAP_EN_30___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__FE_RFIO_CAP_EN_30___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_IBIAS_LOWER_LIM_30___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_IBIAS_LOWER_LIM_30___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_ISLOPE_30___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_ISLOPE_30___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_ILEVEL_30___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_ILEVEL_30___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX1_30___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX1_30___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX0_30___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX0_30___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_30___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CAS_BIAS_30___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CASOFF_BIAS_30___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30__PA_CASOFF_BIAS_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31 (0x005DCDF0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31___POR 0x5A8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_IBIAS_BOOST_31___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__FE_RFIO_CAP_EN_31___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_IBIAS_LOWER_LIM_31___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_ISLOPE_31___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_ILEVEL_31___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX1_31___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX0_31___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_31___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CASOFF_BIAS_31___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_IBIAS_BOOST_31___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_IBIAS_BOOST_31___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__FE_RFIO_CAP_EN_31___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__FE_RFIO_CAP_EN_31___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_IBIAS_LOWER_LIM_31___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_IBIAS_LOWER_LIM_31___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_ISLOPE_31___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_ISLOPE_31___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_ILEVEL_31___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_ILEVEL_31___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX1_31___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX1_31___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX0_31___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX0_31___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_31___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CAS_BIAS_31___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CASOFF_BIAS_31___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31__PA_CASOFF_BIAS_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_31___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0 (0x005DCDF4) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_FB_0___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___POR 0x00401007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___POR 0x001 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___POR 0x001 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_FB_0___POR 0x001 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___M 0x003FF000 @@ -97600,13 +101153,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1 (0x005DCD34) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1 (0x005DCDF8) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_FB_1___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___POR 0x00C0300F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___POR 0x003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___POR 0x003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_FB_1___POR 0x003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___M 0x003FF000 @@ -97618,13 +101171,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2 (0x005DCD38) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2 (0x005DCDFC) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_FB_2___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___POR 0x01C0701F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___POR 0x007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___POR 0x007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_FB_2___POR 0x007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___M 0x003FF000 @@ -97636,13 +101189,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3 (0x005DCD3C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3 (0x005DCE00) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_FB_3___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___POR 0x03C0F03F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___POR 0x00F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___POR 0x00F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_FB_3___POR 0x00F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___M 0x003FF000 @@ -97654,13 +101207,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4 (0x005DCD40) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4 (0x005DCE04) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_FB_4___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___POR 0x07C1F07F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___POR 0x01F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___POR 0x01F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_FB_4___POR 0x01F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___M 0x003FF000 @@ -97672,13 +101225,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5 (0x005DCD44) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5 (0x005DCE08) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_FB_5___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___POR 0x0FC3F0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___POR 0x03F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___POR 0x03F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_FB_5___POR 0x03F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___M 0x003FF000 @@ -97690,13 +101243,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6 (0x005DCD48) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6 (0x005DCE0C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_FB_6___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___POR 0x1FC7F1FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___POR 0x07F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___POR 0x07F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_FB_6___POR 0x07F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___M 0x003FF000 @@ -97708,13 +101261,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7 (0x005DCD4C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7 (0x005DCE10) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_FB_7___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___POR 0x3FCFF3FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_FB_7___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___M 0x003FF000 @@ -97726,13 +101279,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8 (0x005DCD50) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8 (0x005DCE14) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_FB_8___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___POR 0x3FCFF3FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_FB_8___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___M 0x003FF000 @@ -97744,13 +101297,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9 (0x005DCD54) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9 (0x005DCE18) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_FB_9___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___POR 0x3FCFF3FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_FB_9___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___M 0x003FF000 @@ -97762,13 +101315,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10 (0x005DCD58) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10 (0x005DCE1C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_FB_10___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___POR 0x3FCFF3FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_FB_10___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___M 0x003FF000 @@ -97780,13 +101333,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11 (0x005DCD5C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11 (0x005DCE20) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_FB_11___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_FB_11___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___M 0x003FF000 @@ -97798,12 +101351,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12 (0x005DCD60) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12 (0x005DCE24) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN0_12___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_FB_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___POR 0x80200800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN0_12___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_FB_12___POR 0x200 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___S 22 @@ -97816,13 +101369,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13 (0x005DCD64) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13 (0x005DCE28) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_FB_13___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___POR 0x80200801 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_FB_13___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___M 0x003FF000 @@ -97834,13 +101387,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14 (0x005DCD68) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14 (0x005DCE2C) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_FB_14___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___POR 0x80200802 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_FB_14___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___POR 0x2 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___M 0x003FF000 @@ -97852,13 +101405,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15 (0x005DCD6C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15 (0x005DCE30) #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_FB_15___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_FB_15___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___M 0x003FF000 @@ -97870,6 +101423,738 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16 (0x005DCE34) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_EN1_16___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_EN0_16___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_FB_16___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_IBIAS_MODE_16___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_EN1_16___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_EN1_16___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_EN0_16___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_EN0_16___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_FB_16___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_CELL_FB_16___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_IBIAS_MODE_16___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16__PA_IBIAS_MODE_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17 (0x005DCE38) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_EN1_17___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_EN0_17___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_FB_17___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_IBIAS_MODE_17___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_EN1_17___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_EN1_17___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_EN0_17___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_EN0_17___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_FB_17___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_CELL_FB_17___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_IBIAS_MODE_17___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17__PA_IBIAS_MODE_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18 (0x005DCE3C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_EN1_18___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_EN0_18___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_FB_18___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_IBIAS_MODE_18___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_EN1_18___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_EN1_18___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_EN0_18___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_EN0_18___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_FB_18___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_CELL_FB_18___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_IBIAS_MODE_18___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18__PA_IBIAS_MODE_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19 (0x005DCE40) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_EN1_19___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_EN0_19___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_FB_19___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_IBIAS_MODE_19___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_EN1_19___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_EN1_19___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_EN0_19___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_EN0_19___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_FB_19___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_CELL_FB_19___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_IBIAS_MODE_19___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19__PA_IBIAS_MODE_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20 (0x005DCE44) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_EN1_20___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_EN0_20___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_FB_20___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_IBIAS_MODE_20___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_EN1_20___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_EN1_20___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_EN0_20___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_EN0_20___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_FB_20___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_CELL_FB_20___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_IBIAS_MODE_20___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20__PA_IBIAS_MODE_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21 (0x005DCE48) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_EN1_21___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_EN0_21___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_FB_21___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_IBIAS_MODE_21___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_EN1_21___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_EN1_21___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_EN0_21___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_EN0_21___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_FB_21___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_CELL_FB_21___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_IBIAS_MODE_21___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21__PA_IBIAS_MODE_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22 (0x005DCE4C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22___POR 0xC0300C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_EN1_22___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_EN0_22___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_FB_22___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_IBIAS_MODE_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_EN1_22___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_EN1_22___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_EN0_22___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_EN0_22___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_FB_22___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_CELL_FB_22___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_IBIAS_MODE_22___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22__PA_IBIAS_MODE_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23 (0x005DCE50) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23___POR 0xC0300C01 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_EN1_23___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_EN0_23___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_FB_23___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_IBIAS_MODE_23___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_EN1_23___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_EN1_23___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_EN0_23___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_EN0_23___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_FB_23___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_CELL_FB_23___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_IBIAS_MODE_23___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23__PA_IBIAS_MODE_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24 (0x005DCE54) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24___POR 0xC0300C02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_EN1_24___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_EN0_24___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_FB_24___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_IBIAS_MODE_24___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_EN1_24___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_EN1_24___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_EN0_24___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_EN0_24___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_FB_24___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_CELL_FB_24___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_IBIAS_MODE_24___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24__PA_IBIAS_MODE_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25 (0x005DCE58) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_EN1_25___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_EN0_25___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_FB_25___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_IBIAS_MODE_25___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_EN1_25___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_EN1_25___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_EN0_25___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_EN0_25___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_FB_25___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_CELL_FB_25___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_IBIAS_MODE_25___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25__PA_IBIAS_MODE_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26 (0x005DCE5C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_EN1_26___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_EN0_26___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_FB_26___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_IBIAS_MODE_26___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_EN1_26___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_EN1_26___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_EN0_26___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_EN0_26___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_FB_26___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_CELL_FB_26___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_IBIAS_MODE_26___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26__PA_IBIAS_MODE_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27 (0x005DCE60) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_EN1_27___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_EN0_27___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_FB_27___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_IBIAS_MODE_27___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_EN1_27___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_EN1_27___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_EN0_27___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_EN0_27___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_FB_27___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_CELL_FB_27___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_IBIAS_MODE_27___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27__PA_IBIAS_MODE_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28 (0x005DCE64) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_EN1_28___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_EN0_28___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_FB_28___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_IBIAS_MODE_28___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_EN1_28___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_EN1_28___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_EN0_28___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_EN0_28___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_FB_28___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_CELL_FB_28___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_IBIAS_MODE_28___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28__PA_IBIAS_MODE_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29 (0x005DCE68) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_EN1_29___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_EN0_29___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_FB_29___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_IBIAS_MODE_29___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_EN1_29___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_EN1_29___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_EN0_29___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_EN0_29___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_FB_29___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_CELL_FB_29___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_IBIAS_MODE_29___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29__PA_IBIAS_MODE_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30 (0x005DCE6C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_EN1_30___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_EN0_30___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_FB_30___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_IBIAS_MODE_30___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_EN1_30___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_EN1_30___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_EN0_30___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_EN0_30___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_FB_30___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_CELL_FB_30___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_IBIAS_MODE_30___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30__PA_IBIAS_MODE_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31 (0x005DCE70) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_EN1_31___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_EN0_31___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_FB_31___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_IBIAS_MODE_31___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_EN1_31___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_EN1_31___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_EN0_31___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_EN0_31___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_FB_31___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_CELL_FB_31___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_IBIAS_MODE_31___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31__PA_IBIAS_MODE_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_31___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0 (0x005DCE74) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX1_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX0_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX1_CTRL_0___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX1_CTRL_0___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX0_CTRL_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX0_CTRL_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1 (0x005DCE78) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX1_CTRL_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX0_CTRL_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX1_CTRL_1___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX1_CTRL_1___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX0_CTRL_1___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX0_CTRL_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2 (0x005DCE7C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX1_CTRL_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX0_CTRL_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX1_CTRL_2___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX1_CTRL_2___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX0_CTRL_2___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX0_CTRL_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3 (0x005DCE80) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX1_CTRL_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX0_CTRL_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX1_CTRL_3___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX1_CTRL_3___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX0_CTRL_3___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX0_CTRL_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4 (0x005DCE84) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX1_CTRL_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX0_CTRL_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX1_CTRL_4___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX1_CTRL_4___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX0_CTRL_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX0_CTRL_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5 (0x005DCE88) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX1_CTRL_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX0_CTRL_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX1_CTRL_5___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX1_CTRL_5___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX0_CTRL_5___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX0_CTRL_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6 (0x005DCE8C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX1_CTRL_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX0_CTRL_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX1_CTRL_6___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX1_CTRL_6___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX0_CTRL_6___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX0_CTRL_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7 (0x005DCE90) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX1_CTRL_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX0_CTRL_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX1_CTRL_7___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX1_CTRL_7___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX0_CTRL_7___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX0_CTRL_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8 (0x005DCE94) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX1_CTRL_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX0_CTRL_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX1_CTRL_8___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX1_CTRL_8___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX0_CTRL_8___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX0_CTRL_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9 (0x005DCE98) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX1_CTRL_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX0_CTRL_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX1_CTRL_9___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX1_CTRL_9___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX0_CTRL_9___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX0_CTRL_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10 (0x005DCE9C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX1_CTRL_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX0_CTRL_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX1_CTRL_10___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX1_CTRL_10___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX0_CTRL_10___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX0_CTRL_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11 (0x005DCEA0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX1_CTRL_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX0_CTRL_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX1_CTRL_11___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX1_CTRL_11___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX0_CTRL_11___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX0_CTRL_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12 (0x005DCEA4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX1_CTRL_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX0_CTRL_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX1_CTRL_12___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX1_CTRL_12___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX0_CTRL_12___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX0_CTRL_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13 (0x005DCEA8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX1_CTRL_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX0_CTRL_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX1_CTRL_13___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX1_CTRL_13___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX0_CTRL_13___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX0_CTRL_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14 (0x005DCEAC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX1_CTRL_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX0_CTRL_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX1_CTRL_14___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX1_CTRL_14___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX0_CTRL_14___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX0_CTRL_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15 (0x005DCEB0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX1_CTRL_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX0_CTRL_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX1_CTRL_15___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX1_CTRL_15___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX0_CTRL_15___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX0_CTRL_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16 (0x005DCEB4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX1_CTRL_16___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX0_CTRL_16___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX1_CTRL_16___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX1_CTRL_16___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX0_CTRL_16___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX0_CTRL_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17 (0x005DCEB8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX1_CTRL_17___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX0_CTRL_17___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX1_CTRL_17___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX1_CTRL_17___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX0_CTRL_17___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX0_CTRL_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18 (0x005DCEBC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX1_CTRL_18___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX0_CTRL_18___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX1_CTRL_18___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX1_CTRL_18___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX0_CTRL_18___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX0_CTRL_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19 (0x005DCEC0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX1_CTRL_19___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX0_CTRL_19___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX1_CTRL_19___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX1_CTRL_19___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX0_CTRL_19___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX0_CTRL_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20 (0x005DCEC4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX1_CTRL_20___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX0_CTRL_20___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX1_CTRL_20___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX1_CTRL_20___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX0_CTRL_20___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX0_CTRL_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21 (0x005DCEC8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX1_CTRL_21___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX0_CTRL_21___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX1_CTRL_21___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX1_CTRL_21___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX0_CTRL_21___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX0_CTRL_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22 (0x005DCECC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX1_CTRL_22___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX0_CTRL_22___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX1_CTRL_22___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX1_CTRL_22___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX0_CTRL_22___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX0_CTRL_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23 (0x005DCED0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX1_CTRL_23___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX0_CTRL_23___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX1_CTRL_23___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX1_CTRL_23___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX0_CTRL_23___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX0_CTRL_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24 (0x005DCED4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX1_CTRL_24___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX0_CTRL_24___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX1_CTRL_24___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX1_CTRL_24___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX0_CTRL_24___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX0_CTRL_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25 (0x005DCED8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX1_CTRL_25___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX0_CTRL_25___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX1_CTRL_25___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX1_CTRL_25___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX0_CTRL_25___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX0_CTRL_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26 (0x005DCEDC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX1_CTRL_26___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX0_CTRL_26___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX1_CTRL_26___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX1_CTRL_26___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX0_CTRL_26___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX0_CTRL_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27 (0x005DCEE0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX1_CTRL_27___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX0_CTRL_27___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX1_CTRL_27___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX1_CTRL_27___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX0_CTRL_27___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX0_CTRL_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28 (0x005DCEE4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX1_CTRL_28___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX0_CTRL_28___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX1_CTRL_28___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX1_CTRL_28___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX0_CTRL_28___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX0_CTRL_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29 (0x005DCEE8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX1_CTRL_29___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX0_CTRL_29___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX1_CTRL_29___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX1_CTRL_29___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX0_CTRL_29___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX0_CTRL_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30 (0x005DCEEC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX1_CTRL_30___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX0_CTRL_30___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX1_CTRL_30___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX1_CTRL_30___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX0_CTRL_30___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX0_CTRL_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31 (0x005DCEF0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX1_CTRL_31___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX0_CTRL_31___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX1_CTRL_31___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX1_CTRL_31___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX0_CTRL_31___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX0_CTRL_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_2_31___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0 (0x005DCEF4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0___POR 0x00000005 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__PA_LP_CORE_XFRM_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__PA_LP_HS_CTRL_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__DA_HS_CTRL_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__PA_LP_CORE_XFRM_0___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__PA_LP_CORE_XFRM_0___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__PA_LP_HS_CTRL_0___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__PA_LP_HS_CTRL_0___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__DA_HS_CTRL_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0__DA_HS_CTRL_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1 (0x005DCEF8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1___POR 0x00000009 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__PA_LP_CORE_XFRM_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__PA_LP_HS_CTRL_1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__DA_HS_CTRL_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__PA_LP_CORE_XFRM_1___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__PA_LP_CORE_XFRM_1___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__PA_LP_HS_CTRL_1___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__PA_LP_HS_CTRL_1___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__DA_HS_CTRL_1___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1__DA_HS_CTRL_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2 (0x005DCEFC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2___POR 0x0000000A +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__PA_LP_CORE_XFRM_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__PA_LP_HS_CTRL_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__DA_HS_CTRL_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__PA_LP_CORE_XFRM_2___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__PA_LP_CORE_XFRM_2___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__PA_LP_HS_CTRL_2___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__PA_LP_HS_CTRL_2___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__DA_HS_CTRL_2___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2__DA_HS_CTRL_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3 (0x005DCF00) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3___POR 0x0000001A +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__PA_LP_CORE_XFRM_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__PA_LP_HS_CTRL_3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__DA_HS_CTRL_3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__PA_LP_CORE_XFRM_3___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__PA_LP_CORE_XFRM_3___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__PA_LP_HS_CTRL_3___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__PA_LP_HS_CTRL_3___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__DA_HS_CTRL_3___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3__DA_HS_CTRL_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_SUPPLY_0_3___S 0 + #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0 (0x005DD000) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___POR 0x70008884 @@ -97933,7 +102218,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET (0x005DD008) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2 (0x005DD008) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX1_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX1_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX1_EN___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX0_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_CAS_RDIV_AUX0_EN___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_EN___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_CTRL___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2__D_SHRD_PA_LP_GM_DS_RDIV_CTRL___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET (0x005DD00C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___POR 0x0 @@ -97975,7 +102278,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___M 0x0007FBFB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0 (0x005DD00C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0 (0x005DD010) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___POR 0x0 @@ -98011,7 +102314,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___M 0x0FFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1 (0x005DD010) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1 (0x005DD014) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___POR 0x0 @@ -98041,9 +102344,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___M 0x07FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2 (0x005DD014) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2 (0x005DD018) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_FE_RFIO_CAP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_BOOST_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___POR 0x0 @@ -98058,6 +102363,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_FE_RFIO_CAP_EN_OVS___M 0x60000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_FE_RFIO_CAP_EN_OVS___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_BOOST_OVS___M 0x18000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_BOOST_OVS___S 27 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___M 0x04000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___M 0x03800000 @@ -98086,12 +102395,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___S 5 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___M 0x0000001F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___M 0x7FFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3 (0x005DD018) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3 (0x005DD01C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___POR 0x0 @@ -98102,6 +102413,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OV___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OVD___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_LP_HS_CTRL_OVD___S 28 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___M 0x08000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___S 27 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___M 0x07000000 @@ -98122,24 +102437,21 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___M 0x000003FF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___M 0x7FFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4 (0x005DD01C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4 (0x005DD020) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___POR 0x000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___POR 0x000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___M 0x80000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___S 31 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___M 0x7C000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2___M 0x7C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___M 0x01000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___S 24 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___M 0x00FFC000 @@ -98152,17 +102464,20 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___S 2 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___M 0x00000003 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___M 0xFDFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___M 0x7DFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5 (0x005DD020) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5 (0x005DD024) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_LP_CORE_XFRM_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXMIX_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_LP_CORE_XFRM_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_LP_CORE_XFRM_OVS___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___M 0x00000300 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___S 8 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___M 0x000000C0 @@ -98173,18 +102488,42 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___S 2 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___M 0x00000003 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___M 0x00000FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL (0x005DD024) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6 (0x005DD028) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OV___S 11 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OVD___M 0x000007C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX1_CTRL_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6__PA_CAS_RDIV_AUX0_CTRL_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6___M 0x00000FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL (0x005DD02C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OV___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OVD___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__TX_CLASS_OVD___S 18 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x00020000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S 17 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x0001F000 @@ -98197,25 +102536,28 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S 5 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x0000001F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___M 0x0003FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___M 0x001FFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL (0x005DD02C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL (0x005DD030) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RO #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_TX_CLASS___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_TX_CLASS___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_TX_CLASS___S 24 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___M 0x0001F000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___S 12 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___M 0x000007C0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___S 6 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___M 0x0000001F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___M 0x0001F7DF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___M 0x0301F7DF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0 (0x005DD030) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0 (0x005DD034) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___POR 0x00 @@ -98227,7 +102569,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1 (0x005DD034) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1 (0x005DD038) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___POR 0x00 @@ -98239,7 +102581,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2 (0x005DD038) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2 (0x005DD03C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___POR 0x00 @@ -98251,7 +102593,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3 (0x005DD03C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3 (0x005DD040) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___POR 0x00 @@ -98263,7 +102605,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4 (0x005DD040) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4 (0x005DD044) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___POR 0x00 @@ -98275,7 +102617,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5 (0x005DD044) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5 (0x005DD048) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___POR 0x00 @@ -98287,7 +102629,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6 (0x005DD048) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6 (0x005DD04C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___POR 0x00 @@ -98299,7 +102641,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7 (0x005DD04C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7 (0x005DD050) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___POR 0x00 @@ -98311,7 +102653,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8 (0x005DD050) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8 (0x005DD054) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___POR 0x00 @@ -98323,7 +102665,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9 (0x005DD054) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9 (0x005DD058) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___POR 0x00 @@ -98335,7 +102677,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10 (0x005DD058) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10 (0x005DD05C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___POR 0x00 @@ -98347,7 +102689,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11 (0x005DD05C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11 (0x005DD060) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___POR 0x00 @@ -98359,7 +102701,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12 (0x005DD060) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12 (0x005DD064) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___POR 0x00 @@ -98371,7 +102713,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13 (0x005DD064) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13 (0x005DD068) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___POR 0x00 @@ -98383,7 +102725,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14 (0x005DD068) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14 (0x005DD06C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___POR 0x00 @@ -98395,7 +102737,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15 (0x005DD06C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15 (0x005DD070) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___POR 0x00 @@ -98407,15 +102749,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___M 0x00003F3F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0 (0x005DD070) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0 (0x005DD074) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___POR 0x02407007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CTUNE_0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CELL_EN_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CELL_EN_0___POR 0x007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___M 0x00700000 @@ -98431,15 +102773,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1 (0x005DD074) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1 (0x005DD078) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___POR 0x0240700C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CTUNE_1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CELL_EN_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CELL_EN_1___POR 0x00C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___M 0x00700000 @@ -98455,15 +102797,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2 (0x005DD078) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2 (0x005DD07C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___POR 0x0240700E +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CTUNE_2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CELL_EN_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CELL_EN_2___POR 0x00E #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___M 0x00700000 @@ -98479,15 +102821,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3 (0x005DD07C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3 (0x005DD080) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___POR 0x0240700F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CTUNE_3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CELL_EN_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CELL_EN_3___POR 0x00F #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___M 0x00700000 @@ -98503,15 +102845,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4 (0x005DD080) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4 (0x005DD084) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___POR 0x02407015 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CTUNE_4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CELL_EN_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CELL_EN_4___POR 0x015 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___M 0x00700000 @@ -98527,15 +102869,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5 (0x005DD084) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5 (0x005DD088) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___POR 0x02407017 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CTUNE_5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CELL_EN_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CELL_EN_5___POR 0x017 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___M 0x00700000 @@ -98551,15 +102893,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6 (0x005DD088) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6 (0x005DD08C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___POR 0x0240701A +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CTUNE_6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CELL_EN_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CELL_EN_6___POR 0x01A #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___M 0x00700000 @@ -98575,15 +102917,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7 (0x005DD08C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7 (0x005DD090) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___POR 0x02407024 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CTUNE_7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CELL_EN_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CELL_EN_7___POR 0x024 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___M 0x00700000 @@ -98599,15 +102941,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8 (0x005DD090) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8 (0x005DD094) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___POR 0x02407028 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CTUNE_8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CELL_EN_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CELL_EN_8___POR 0x028 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___M 0x00700000 @@ -98623,15 +102965,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9 (0x005DD094) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9 (0x005DD098) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___POR 0x0240702B +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CTUNE_9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CELL_EN_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CELL_EN_9___POR 0x02B #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___M 0x00700000 @@ -98647,15 +102989,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10 (0x005DD098) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10 (0x005DD09C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___POR 0x02407033 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CTUNE_10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CELL_EN_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CELL_EN_10___POR 0x033 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___M 0x00700000 @@ -98671,15 +103013,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11 (0x005DD09C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11 (0x005DD0A0) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___POR 0x02407037 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CTUNE_11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CELL_EN_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CELL_EN_11___POR 0x037 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___M 0x00700000 @@ -98695,15 +103037,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12 (0x005DD0A0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12 (0x005DD0A4) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___POR 0x0240703C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CTUNE_12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CELL_EN_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CELL_EN_12___POR 0x03C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___M 0x00700000 @@ -98719,15 +103061,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13 (0x005DD0A4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13 (0x005DD0A8) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___POR 0x0240704A +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CTUNE_13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CELL_EN_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CELL_EN_13___POR 0x04A #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___M 0x00700000 @@ -98743,15 +103085,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14 (0x005DD0A8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14 (0x005DD0AC) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___POR 0x02407054 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CTUNE_14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CELL_EN_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CELL_EN_14___POR 0x054 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___M 0x00700000 @@ -98767,15 +103109,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15 (0x005DD0AC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15 (0x005DD0B0) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___POR 0x0240705A +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CTUNE_15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___POR 0x7 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CELL_EN_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CELL_EN_15___POR 0x05A #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___M 0x00700000 @@ -98791,14 +103133,397 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___M 0x03FFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0 (0x005DD0B0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16 (0x005DD0B4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16___POR 0x0240706B +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_IBIAS_LOWER_LIM_16___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_ISLOPE_16___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CTUNE_16___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CAS_BIAS_16___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CASOFF_BIAS_16___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CELL_EN_16___POR 0x06B +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_IBIAS_LOWER_LIM_16___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_IBIAS_LOWER_LIM_16___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_ISLOPE_16___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_ISLOPE_16___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CTUNE_16___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CTUNE_16___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CAS_BIAS_16___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CAS_BIAS_16___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CASOFF_BIAS_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CASOFF_BIAS_16___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CELL_EN_16___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16__DA_CELL_EN_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17 (0x005DD0B8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17___POR 0x02407078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_IBIAS_LOWER_LIM_17___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_ISLOPE_17___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CTUNE_17___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CAS_BIAS_17___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CASOFF_BIAS_17___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CELL_EN_17___POR 0x078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_IBIAS_LOWER_LIM_17___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_IBIAS_LOWER_LIM_17___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_ISLOPE_17___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_ISLOPE_17___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CTUNE_17___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CTUNE_17___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CAS_BIAS_17___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CAS_BIAS_17___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CASOFF_BIAS_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CASOFF_BIAS_17___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CELL_EN_17___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17__DA_CELL_EN_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18 (0x005DD0BC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18___POR 0x02407089 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_IBIAS_LOWER_LIM_18___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_ISLOPE_18___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CTUNE_18___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CAS_BIAS_18___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CASOFF_BIAS_18___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CELL_EN_18___POR 0x089 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_IBIAS_LOWER_LIM_18___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_IBIAS_LOWER_LIM_18___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_ISLOPE_18___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_ISLOPE_18___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CTUNE_18___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CTUNE_18___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CAS_BIAS_18___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CAS_BIAS_18___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CASOFF_BIAS_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CASOFF_BIAS_18___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CELL_EN_18___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18__DA_CELL_EN_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19 (0x005DD0C0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19___POR 0x02407092 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_IBIAS_LOWER_LIM_19___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_ISLOPE_19___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CTUNE_19___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CAS_BIAS_19___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CASOFF_BIAS_19___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CELL_EN_19___POR 0x092 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_IBIAS_LOWER_LIM_19___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_IBIAS_LOWER_LIM_19___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_ISLOPE_19___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_ISLOPE_19___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CTUNE_19___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CTUNE_19___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CAS_BIAS_19___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CAS_BIAS_19___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CASOFF_BIAS_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CASOFF_BIAS_19___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CELL_EN_19___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19__DA_CELL_EN_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20 (0x005DD0C4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20___POR 0x024070A0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_IBIAS_LOWER_LIM_20___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_ISLOPE_20___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CTUNE_20___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CAS_BIAS_20___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CASOFF_BIAS_20___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CELL_EN_20___POR 0x0A0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_IBIAS_LOWER_LIM_20___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_IBIAS_LOWER_LIM_20___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_ISLOPE_20___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_ISLOPE_20___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CTUNE_20___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CTUNE_20___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CAS_BIAS_20___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CAS_BIAS_20___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CASOFF_BIAS_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CASOFF_BIAS_20___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CELL_EN_20___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20__DA_CELL_EN_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21 (0x005DD0C8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21___POR 0x02407096 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_IBIAS_LOWER_LIM_21___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_ISLOPE_21___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CTUNE_21___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CAS_BIAS_21___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CASOFF_BIAS_21___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CELL_EN_21___POR 0x096 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_IBIAS_LOWER_LIM_21___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_IBIAS_LOWER_LIM_21___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_ISLOPE_21___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_ISLOPE_21___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CTUNE_21___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CTUNE_21___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CAS_BIAS_21___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CAS_BIAS_21___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CASOFF_BIAS_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CASOFF_BIAS_21___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CELL_EN_21___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21__DA_CELL_EN_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22 (0x005DD0CC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22___POR 0x024070AD +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_IBIAS_LOWER_LIM_22___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_ISLOPE_22___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CTUNE_22___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CAS_BIAS_22___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CASOFF_BIAS_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CELL_EN_22___POR 0x0AD +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_IBIAS_LOWER_LIM_22___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_IBIAS_LOWER_LIM_22___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_ISLOPE_22___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_ISLOPE_22___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CTUNE_22___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CTUNE_22___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CAS_BIAS_22___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CAS_BIAS_22___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CASOFF_BIAS_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CASOFF_BIAS_22___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CELL_EN_22___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22__DA_CELL_EN_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23 (0x005DD0D0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23___POR 0x024070B4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_IBIAS_LOWER_LIM_23___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_ISLOPE_23___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CTUNE_23___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CAS_BIAS_23___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CASOFF_BIAS_23___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CELL_EN_23___POR 0x0B4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_IBIAS_LOWER_LIM_23___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_IBIAS_LOWER_LIM_23___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_ISLOPE_23___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_ISLOPE_23___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CTUNE_23___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CTUNE_23___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CAS_BIAS_23___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CAS_BIAS_23___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CASOFF_BIAS_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CASOFF_BIAS_23___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CELL_EN_23___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23__DA_CELL_EN_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24 (0x005DD0D4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24___POR 0x024070C8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_IBIAS_LOWER_LIM_24___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_ISLOPE_24___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CTUNE_24___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CAS_BIAS_24___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CASOFF_BIAS_24___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CELL_EN_24___POR 0x0C8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_IBIAS_LOWER_LIM_24___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_IBIAS_LOWER_LIM_24___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_ISLOPE_24___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_ISLOPE_24___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CTUNE_24___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CTUNE_24___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CAS_BIAS_24___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CAS_BIAS_24___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CASOFF_BIAS_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CASOFF_BIAS_24___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CELL_EN_24___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24__DA_CELL_EN_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25 (0x005DD0D8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25___POR 0x024070DC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_IBIAS_LOWER_LIM_25___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_ISLOPE_25___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CTUNE_25___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CAS_BIAS_25___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CASOFF_BIAS_25___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CELL_EN_25___POR 0x0DC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_IBIAS_LOWER_LIM_25___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_IBIAS_LOWER_LIM_25___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_ISLOPE_25___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_ISLOPE_25___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CTUNE_25___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CTUNE_25___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CAS_BIAS_25___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CAS_BIAS_25___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CASOFF_BIAS_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CASOFF_BIAS_25___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CELL_EN_25___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25__DA_CELL_EN_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26 (0x005DD0DC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26___POR 0x024070E6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_IBIAS_LOWER_LIM_26___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_ISLOPE_26___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CTUNE_26___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CAS_BIAS_26___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CASOFF_BIAS_26___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CELL_EN_26___POR 0x0E6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_IBIAS_LOWER_LIM_26___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_IBIAS_LOWER_LIM_26___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_ISLOPE_26___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_ISLOPE_26___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CTUNE_26___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CTUNE_26___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CAS_BIAS_26___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CAS_BIAS_26___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CASOFF_BIAS_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CASOFF_BIAS_26___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CELL_EN_26___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26__DA_CELL_EN_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27 (0x005DD0E0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27___POR 0x024070FB +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_IBIAS_LOWER_LIM_27___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_ISLOPE_27___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CTUNE_27___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CAS_BIAS_27___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CASOFF_BIAS_27___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CELL_EN_27___POR 0x0FB +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_IBIAS_LOWER_LIM_27___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_IBIAS_LOWER_LIM_27___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_ISLOPE_27___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_ISLOPE_27___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CTUNE_27___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CTUNE_27___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CAS_BIAS_27___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CAS_BIAS_27___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CASOFF_BIAS_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CASOFF_BIAS_27___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CELL_EN_27___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27__DA_CELL_EN_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28 (0x005DD0E4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28___POR 0x02407118 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_IBIAS_LOWER_LIM_28___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_ISLOPE_28___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CTUNE_28___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CAS_BIAS_28___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CASOFF_BIAS_28___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CELL_EN_28___POR 0x118 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_IBIAS_LOWER_LIM_28___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_IBIAS_LOWER_LIM_28___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_ISLOPE_28___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_ISLOPE_28___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CTUNE_28___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CTUNE_28___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CAS_BIAS_28___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CAS_BIAS_28___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CASOFF_BIAS_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CASOFF_BIAS_28___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CELL_EN_28___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28__DA_CELL_EN_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29 (0x005DD0E8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29___POR 0x02407140 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_IBIAS_LOWER_LIM_29___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_ISLOPE_29___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CTUNE_29___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CAS_BIAS_29___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CASOFF_BIAS_29___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CELL_EN_29___POR 0x140 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_IBIAS_LOWER_LIM_29___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_IBIAS_LOWER_LIM_29___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_ISLOPE_29___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_ISLOPE_29___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CTUNE_29___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CTUNE_29___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CAS_BIAS_29___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CAS_BIAS_29___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CASOFF_BIAS_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CASOFF_BIAS_29___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CELL_EN_29___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29__DA_CELL_EN_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30 (0x005DD0EC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30___POR 0x02407190 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_IBIAS_LOWER_LIM_30___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_ISLOPE_30___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CTUNE_30___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CAS_BIAS_30___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CASOFF_BIAS_30___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CELL_EN_30___POR 0x190 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_IBIAS_LOWER_LIM_30___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_IBIAS_LOWER_LIM_30___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_ISLOPE_30___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_ISLOPE_30___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CTUNE_30___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CTUNE_30___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CAS_BIAS_30___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CAS_BIAS_30___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CASOFF_BIAS_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CASOFF_BIAS_30___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CELL_EN_30___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30__DA_CELL_EN_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31 (0x005DD0F0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31___POR 0x024071FD +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_IBIAS_LOWER_LIM_31___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_ISLOPE_31___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CTUNE_31___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CAS_BIAS_31___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CASOFF_BIAS_31___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CELL_EN_31___POR 0x1FD +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_IBIAS_LOWER_LIM_31___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_IBIAS_LOWER_LIM_31___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_ISLOPE_31___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_ISLOPE_31___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CTUNE_31___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CTUNE_31___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CAS_BIAS_31___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CAS_BIAS_31___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CASOFF_BIAS_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CASOFF_BIAS_31___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CELL_EN_31___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31__DA_CELL_EN_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_31___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0 (0x005DD0F4) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___POR 0x000005E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___POR 0x02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___M 0x000001C0 @@ -98807,19 +103532,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1 (0x005DD0B4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1 (0x005DD0F8) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___POR 0x000005E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___POR 0x02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___M 0x000001C0 @@ -98828,19 +103550,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2 (0x005DD0B8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2 (0x005DD0FC) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___POR 0x000005E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___POR 0x02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___M 0x000001C0 @@ -98849,19 +103568,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3 (0x005DD0BC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3 (0x005DD100) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___POR 0x000005E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___POR 0x02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___M 0x000001C0 @@ -98870,19 +103586,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4 (0x005DD0C0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4 (0x005DD104) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___POR 0x000007E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___M 0x000001C0 @@ -98891,19 +103604,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5 (0x005DD0C4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5 (0x005DD108) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___POR 0x000007E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___M 0x000001C0 @@ -98912,19 +103622,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6 (0x005DD0C8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6 (0x005DD10C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___POR 0x000007E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___M 0x000001C0 @@ -98933,19 +103640,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7 (0x005DD0CC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7 (0x005DD110) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___POR 0x000007E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___M 0x000001C0 @@ -98954,19 +103658,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8 (0x005DD0D0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8 (0x005DD114) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___POR 0x000009E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___POR 0x04 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___M 0x000001C0 @@ -98975,19 +103676,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9 (0x005DD0D4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9 (0x005DD118) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___POR 0x00000DE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___POR 0x06 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___M 0x000001C0 @@ -98996,19 +103694,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10 (0x005DD0D8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10 (0x005DD11C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___POR 0x000015E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___POR 0x0A +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___M 0x000001C0 @@ -99017,19 +103712,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11 (0x005DD0DC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11 (0x005DD120) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___POR 0x000019E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___POR 0x0C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___M 0x000001C0 @@ -99038,19 +103730,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12 (0x005DD0E0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12 (0x005DD124) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___POR 0x000019E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___POR 0x0C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___M 0x000001C0 @@ -99059,19 +103748,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13 (0x005DD0E4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13 (0x005DD128) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___POR 0x00001DE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___POR 0x0E +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___M 0x000001C0 @@ -99080,19 +103766,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14 (0x005DD0E8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14 (0x005DD12C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___POR 0x00001FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___POR 0x0F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___M 0x000001C0 @@ -99101,19 +103784,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15 (0x005DD0EC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15 (0x005DD130) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___POR 0x000025E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___POR 0x12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___M 0x0001FE00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___S 9 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___M 0x000001C0 @@ -99122,30 +103802,319 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___S 4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___M 0x0000000C #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___M 0x00000003 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___M 0x0001FFFF -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___S 2 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0 (0x005DD0F0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16 (0x005DD134) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16___POR 0x000031E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_CELL_AUX_EN_16___POR 0x18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_CAS_BIAS_AUX_16___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_ILEVEL_16___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_ILEVEL_COARSE_16___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_CELL_AUX_EN_16___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_CELL_AUX_EN_16___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_CAS_BIAS_AUX_16___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_CAS_BIAS_AUX_16___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_ILEVEL_16___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_ILEVEL_16___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_ILEVEL_COARSE_16___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16__DA_ILEVEL_COARSE_16___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_16___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17 (0x005DD138) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17___POR 0x00003FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_CELL_AUX_EN_17___POR 0x1F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_CAS_BIAS_AUX_17___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_ILEVEL_17___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_ILEVEL_COARSE_17___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_CELL_AUX_EN_17___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_CELL_AUX_EN_17___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_CAS_BIAS_AUX_17___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_CAS_BIAS_AUX_17___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_ILEVEL_17___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_ILEVEL_17___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_ILEVEL_COARSE_17___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17__DA_ILEVEL_COARSE_17___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_17___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18 (0x005DD13C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18___POR 0x000055E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_CELL_AUX_EN_18___POR 0x2A +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_CAS_BIAS_AUX_18___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_ILEVEL_18___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_ILEVEL_COARSE_18___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_CELL_AUX_EN_18___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_CELL_AUX_EN_18___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_CAS_BIAS_AUX_18___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_CAS_BIAS_AUX_18___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_ILEVEL_18___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_ILEVEL_18___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_ILEVEL_COARSE_18___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18__DA_ILEVEL_COARSE_18___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_18___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19 (0x005DD140) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19___POR 0x000055E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_CELL_AUX_EN_19___POR 0x2A +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_CAS_BIAS_AUX_19___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_ILEVEL_19___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_ILEVEL_COARSE_19___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_CELL_AUX_EN_19___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_CELL_AUX_EN_19___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_CAS_BIAS_AUX_19___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_CAS_BIAS_AUX_19___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_ILEVEL_19___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_ILEVEL_19___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_ILEVEL_COARSE_19___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19__DA_ILEVEL_COARSE_19___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_19___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20 (0x005DD144) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20___POR 0x000067E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_CELL_AUX_EN_20___POR 0x33 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_CAS_BIAS_AUX_20___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_ILEVEL_20___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_ILEVEL_COARSE_20___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_CELL_AUX_EN_20___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_CELL_AUX_EN_20___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_CAS_BIAS_AUX_20___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_CAS_BIAS_AUX_20___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_ILEVEL_20___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_ILEVEL_20___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_ILEVEL_COARSE_20___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20__DA_ILEVEL_COARSE_20___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_20___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21 (0x005DD148) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21___POR 0x000079E4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_CELL_AUX_EN_21___POR 0x3C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_CAS_BIAS_AUX_21___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_ILEVEL_21___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_ILEVEL_COARSE_21___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_CELL_AUX_EN_21___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_CELL_AUX_EN_21___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_CAS_BIAS_AUX_21___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_CAS_BIAS_AUX_21___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_ILEVEL_21___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_ILEVEL_21___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_ILEVEL_COARSE_21___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21__DA_ILEVEL_COARSE_21___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_21___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22 (0x005DD14C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_CELL_AUX_EN_22___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_CAS_BIAS_AUX_22___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_ILEVEL_22___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_ILEVEL_COARSE_22___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_CELL_AUX_EN_22___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_CELL_AUX_EN_22___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_CAS_BIAS_AUX_22___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_CAS_BIAS_AUX_22___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_ILEVEL_22___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_ILEVEL_22___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_ILEVEL_COARSE_22___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22__DA_ILEVEL_COARSE_22___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_22___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23 (0x005DD150) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_CELL_AUX_EN_23___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_CAS_BIAS_AUX_23___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_ILEVEL_23___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_ILEVEL_COARSE_23___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_CELL_AUX_EN_23___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_CELL_AUX_EN_23___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_CAS_BIAS_AUX_23___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_CAS_BIAS_AUX_23___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_ILEVEL_23___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_ILEVEL_23___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_ILEVEL_COARSE_23___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23__DA_ILEVEL_COARSE_23___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_23___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24 (0x005DD154) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_CELL_AUX_EN_24___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_CAS_BIAS_AUX_24___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_ILEVEL_24___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_ILEVEL_COARSE_24___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_CELL_AUX_EN_24___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_CELL_AUX_EN_24___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_CAS_BIAS_AUX_24___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_CAS_BIAS_AUX_24___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_ILEVEL_24___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_ILEVEL_24___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_ILEVEL_COARSE_24___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24__DA_ILEVEL_COARSE_24___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_24___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25 (0x005DD158) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_CELL_AUX_EN_25___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_CAS_BIAS_AUX_25___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_ILEVEL_25___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_ILEVEL_COARSE_25___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_CELL_AUX_EN_25___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_CELL_AUX_EN_25___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_CAS_BIAS_AUX_25___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_CAS_BIAS_AUX_25___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_ILEVEL_25___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_ILEVEL_25___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_ILEVEL_COARSE_25___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25__DA_ILEVEL_COARSE_25___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_25___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26 (0x005DD15C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_CELL_AUX_EN_26___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_CAS_BIAS_AUX_26___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_ILEVEL_26___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_ILEVEL_COARSE_26___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_CELL_AUX_EN_26___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_CELL_AUX_EN_26___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_CAS_BIAS_AUX_26___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_CAS_BIAS_AUX_26___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_ILEVEL_26___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_ILEVEL_26___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_ILEVEL_COARSE_26___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26__DA_ILEVEL_COARSE_26___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_26___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27 (0x005DD160) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_CELL_AUX_EN_27___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_CAS_BIAS_AUX_27___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_ILEVEL_27___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_ILEVEL_COARSE_27___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_CELL_AUX_EN_27___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_CELL_AUX_EN_27___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_CAS_BIAS_AUX_27___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_CAS_BIAS_AUX_27___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_ILEVEL_27___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_ILEVEL_27___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_ILEVEL_COARSE_27___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27__DA_ILEVEL_COARSE_27___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_27___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28 (0x005DD164) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_CELL_AUX_EN_28___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_CAS_BIAS_AUX_28___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_ILEVEL_28___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_ILEVEL_COARSE_28___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_CELL_AUX_EN_28___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_CELL_AUX_EN_28___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_CAS_BIAS_AUX_28___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_CAS_BIAS_AUX_28___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_ILEVEL_28___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_ILEVEL_28___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_ILEVEL_COARSE_28___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28__DA_ILEVEL_COARSE_28___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_28___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29 (0x005DD168) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_CELL_AUX_EN_29___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_CAS_BIAS_AUX_29___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_ILEVEL_29___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_ILEVEL_COARSE_29___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_CELL_AUX_EN_29___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_CELL_AUX_EN_29___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_CAS_BIAS_AUX_29___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_CAS_BIAS_AUX_29___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_ILEVEL_29___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_ILEVEL_29___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_ILEVEL_COARSE_29___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29__DA_ILEVEL_COARSE_29___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_29___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30 (0x005DD16C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_CELL_AUX_EN_30___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_CAS_BIAS_AUX_30___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_ILEVEL_30___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_ILEVEL_COARSE_30___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_CELL_AUX_EN_30___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_CELL_AUX_EN_30___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_CAS_BIAS_AUX_30___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_CAS_BIAS_AUX_30___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_ILEVEL_30___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_ILEVEL_30___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_ILEVEL_COARSE_30___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30__DA_ILEVEL_COARSE_30___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_30___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31 (0x005DD170) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31___POR 0x00007FE4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_CELL_AUX_EN_31___POR 0x3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_CAS_BIAS_AUX_31___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_ILEVEL_31___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_ILEVEL_COARSE_31___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_CELL_AUX_EN_31___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_CELL_AUX_EN_31___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_CAS_BIAS_AUX_31___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_CAS_BIAS_AUX_31___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_ILEVEL_31___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_ILEVEL_31___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_ILEVEL_COARSE_31___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31__DA_ILEVEL_COARSE_31___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31___M 0x0001FFFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_31___S 2 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0 (0x005DD174) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_BOOST_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__FE_RFIO_CAP_EN_0___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_BOOST_0___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_BOOST_0___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__FE_RFIO_CAP_EN_0___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__FE_RFIO_CAP_EN_0___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___M 0x00000380 @@ -99154,28 +104123,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1 (0x005DD0F4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1 (0x005DD178) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_BOOST_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__FE_RFIO_CAP_EN_1___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_BOOST_1___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_BOOST_1___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__FE_RFIO_CAP_EN_1___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__FE_RFIO_CAP_EN_1___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___M 0x00000380 @@ -99184,28 +104156,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2 (0x005DD0F8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2 (0x005DD17C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_BOOST_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__FE_RFIO_CAP_EN_2___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_BOOST_2___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_BOOST_2___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__FE_RFIO_CAP_EN_2___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__FE_RFIO_CAP_EN_2___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___M 0x00000380 @@ -99214,28 +104189,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3 (0x005DD0FC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3 (0x005DD180) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_BOOST_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__FE_RFIO_CAP_EN_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_BOOST_3___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_BOOST_3___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__FE_RFIO_CAP_EN_3___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__FE_RFIO_CAP_EN_3___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___M 0x00000380 @@ -99244,28 +104222,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4 (0x005DD100) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4 (0x005DD184) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_BOOST_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__FE_RFIO_CAP_EN_4___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_BOOST_4___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_BOOST_4___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__FE_RFIO_CAP_EN_4___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__FE_RFIO_CAP_EN_4___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___M 0x00000380 @@ -99274,28 +104255,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5 (0x005DD104) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5 (0x005DD188) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_BOOST_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__FE_RFIO_CAP_EN_5___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_BOOST_5___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_BOOST_5___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__FE_RFIO_CAP_EN_5___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__FE_RFIO_CAP_EN_5___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___M 0x00000380 @@ -99304,28 +104288,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6 (0x005DD108) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6 (0x005DD18C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_BOOST_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__FE_RFIO_CAP_EN_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_BOOST_6___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_BOOST_6___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__FE_RFIO_CAP_EN_6___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__FE_RFIO_CAP_EN_6___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___M 0x00000380 @@ -99334,28 +104321,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7 (0x005DD10C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7 (0x005DD190) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___POR 0x1A8C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_BOOST_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__FE_RFIO_CAP_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_BOOST_7___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_BOOST_7___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__FE_RFIO_CAP_EN_7___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__FE_RFIO_CAP_EN_7___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___M 0x00000380 @@ -99364,28 +104354,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8 (0x005DD110) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8 (0x005DD194) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___POR 0x128C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_BOOST_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__FE_RFIO_CAP_EN_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_BOOST_8___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_BOOST_8___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__FE_RFIO_CAP_EN_8___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__FE_RFIO_CAP_EN_8___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___M 0x00000380 @@ -99394,28 +104387,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9 (0x005DD114) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9 (0x005DD198) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___POR 0x0A8C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_BOOST_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__FE_RFIO_CAP_EN_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_BOOST_9___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_BOOST_9___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__FE_RFIO_CAP_EN_9___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__FE_RFIO_CAP_EN_9___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___M 0x00000380 @@ -99424,28 +104420,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10 (0x005DD118) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10 (0x005DD19C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___POR 0x028C1758 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_BOOST_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__FE_RFIO_CAP_EN_10___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___POR 0xB #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_BOOST_10___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_BOOST_10___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__FE_RFIO_CAP_EN_10___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__FE_RFIO_CAP_EN_10___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___M 0x00000380 @@ -99454,28 +104453,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11 (0x005DD11C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11 (0x005DD1A0) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___POR 0x028C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_BOOST_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__FE_RFIO_CAP_EN_11___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_BOOST_11___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_BOOST_11___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__FE_RFIO_CAP_EN_11___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__FE_RFIO_CAP_EN_11___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___M 0x00000380 @@ -99484,28 +104486,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12 (0x005DD120) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12 (0x005DD1A4) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___POR 0x428C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_BOOST_12___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__FE_RFIO_CAP_EN_12___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_BOOST_12___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_BOOST_12___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__FE_RFIO_CAP_EN_12___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__FE_RFIO_CAP_EN_12___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___M 0x00000380 @@ -99514,28 +104519,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13 (0x005DD124) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13 (0x005DD1A8) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_BOOST_13___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__FE_RFIO_CAP_EN_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_BOOST_13___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_BOOST_13___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__FE_RFIO_CAP_EN_13___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__FE_RFIO_CAP_EN_13___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___M 0x00000380 @@ -99544,28 +104552,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14 (0x005DD128) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14 (0x005DD1AC) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_BOOST_14___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__FE_RFIO_CAP_EN_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_BOOST_14___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_BOOST_14___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__FE_RFIO_CAP_EN_14___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__FE_RFIO_CAP_EN_14___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___M 0x00000380 @@ -99574,28 +104585,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15 (0x005DD12C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15 (0x005DD1B0) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___POR 0x00 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___POR 0x0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___POR 0x5A8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_BOOST_15___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__FE_RFIO_CAP_EN_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___POR 0x4 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_BOOST_15___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_BOOST_15___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__FE_RFIO_CAP_EN_15___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__FE_RFIO_CAP_EN_15___S 29 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___M 0x1C000000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___S 26 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___M 0x03800000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___S 23 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___M 0x007C0000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___S 18 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___M 0x0003E000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___S 13 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___M 0x00001C00 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___S 10 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___M 0x00000380 @@ -99604,16 +104618,544 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___S 3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___M 0x00000007 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___M 0x7FFC1FFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0 (0x005DD130) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16 (0x005DD1B4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16___POR 0x568C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_IBIAS_BOOST_16___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__FE_RFIO_CAP_EN_16___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_IBIAS_LOWER_LIM_16___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_ISLOPE_16___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_ILEVEL_16___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX1_16___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX0_16___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_16___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CASOFF_BIAS_16___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_IBIAS_BOOST_16___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_IBIAS_BOOST_16___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__FE_RFIO_CAP_EN_16___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__FE_RFIO_CAP_EN_16___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_IBIAS_LOWER_LIM_16___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_IBIAS_LOWER_LIM_16___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_ISLOPE_16___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_ISLOPE_16___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_ILEVEL_16___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_ILEVEL_16___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX1_16___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX1_16___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX0_16___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_AUX0_16___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_16___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CAS_BIAS_16___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CASOFF_BIAS_16___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16__PA_CASOFF_BIAS_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17 (0x005DD1B8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_IBIAS_BOOST_17___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__FE_RFIO_CAP_EN_17___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_IBIAS_LOWER_LIM_17___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_ISLOPE_17___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_ILEVEL_17___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX1_17___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX0_17___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_17___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CASOFF_BIAS_17___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_IBIAS_BOOST_17___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_IBIAS_BOOST_17___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__FE_RFIO_CAP_EN_17___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__FE_RFIO_CAP_EN_17___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_IBIAS_LOWER_LIM_17___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_IBIAS_LOWER_LIM_17___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_ISLOPE_17___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_ISLOPE_17___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_ILEVEL_17___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_ILEVEL_17___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX1_17___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX1_17___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX0_17___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_AUX0_17___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_17___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CAS_BIAS_17___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CASOFF_BIAS_17___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17__PA_CASOFF_BIAS_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18 (0x005DD1BC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18___POR 0x4E8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_IBIAS_BOOST_18___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__FE_RFIO_CAP_EN_18___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_IBIAS_LOWER_LIM_18___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_ISLOPE_18___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_ILEVEL_18___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX1_18___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX0_18___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_18___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CASOFF_BIAS_18___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_IBIAS_BOOST_18___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_IBIAS_BOOST_18___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__FE_RFIO_CAP_EN_18___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__FE_RFIO_CAP_EN_18___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_IBIAS_LOWER_LIM_18___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_IBIAS_LOWER_LIM_18___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_ISLOPE_18___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_ISLOPE_18___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_ILEVEL_18___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_ILEVEL_18___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX1_18___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX1_18___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX0_18___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_AUX0_18___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_18___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CAS_BIAS_18___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CASOFF_BIAS_18___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18__PA_CASOFF_BIAS_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19 (0x005DD1C0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19___POR 0x4A8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_IBIAS_BOOST_19___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__FE_RFIO_CAP_EN_19___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_IBIAS_LOWER_LIM_19___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_ISLOPE_19___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_ILEVEL_19___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX1_19___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX0_19___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_19___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CASOFF_BIAS_19___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_IBIAS_BOOST_19___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_IBIAS_BOOST_19___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__FE_RFIO_CAP_EN_19___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__FE_RFIO_CAP_EN_19___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_IBIAS_LOWER_LIM_19___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_IBIAS_LOWER_LIM_19___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_ISLOPE_19___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_ISLOPE_19___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_ILEVEL_19___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_ILEVEL_19___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX1_19___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX1_19___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX0_19___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_AUX0_19___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_19___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CAS_BIAS_19___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CASOFF_BIAS_19___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19__PA_CASOFF_BIAS_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20 (0x005DD1C4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20___POR 0x468C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_IBIAS_BOOST_20___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__FE_RFIO_CAP_EN_20___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_IBIAS_LOWER_LIM_20___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_ISLOPE_20___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_ILEVEL_20___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX1_20___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX0_20___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_20___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CASOFF_BIAS_20___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_IBIAS_BOOST_20___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_IBIAS_BOOST_20___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__FE_RFIO_CAP_EN_20___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__FE_RFIO_CAP_EN_20___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_IBIAS_LOWER_LIM_20___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_IBIAS_LOWER_LIM_20___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_ISLOPE_20___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_ISLOPE_20___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_ILEVEL_20___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_ILEVEL_20___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX1_20___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX1_20___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX0_20___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_AUX0_20___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_20___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CAS_BIAS_20___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CASOFF_BIAS_20___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20__PA_CASOFF_BIAS_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21 (0x005DD1C8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21___POR 0x428C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_IBIAS_BOOST_21___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__FE_RFIO_CAP_EN_21___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_IBIAS_LOWER_LIM_21___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_ISLOPE_21___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_ILEVEL_21___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX1_21___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX0_21___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_21___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CASOFF_BIAS_21___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_IBIAS_BOOST_21___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_IBIAS_BOOST_21___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__FE_RFIO_CAP_EN_21___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__FE_RFIO_CAP_EN_21___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_IBIAS_LOWER_LIM_21___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_IBIAS_LOWER_LIM_21___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_ISLOPE_21___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_ISLOPE_21___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_ILEVEL_21___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_ILEVEL_21___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX1_21___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX1_21___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX0_21___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_AUX0_21___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_21___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CAS_BIAS_21___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CASOFF_BIAS_21___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21__PA_CASOFF_BIAS_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22 (0x005DD1CC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22___POR 0x428C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_IBIAS_BOOST_22___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__FE_RFIO_CAP_EN_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_IBIAS_LOWER_LIM_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_ISLOPE_22___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_ILEVEL_22___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX1_22___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX0_22___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_22___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CASOFF_BIAS_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_IBIAS_BOOST_22___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_IBIAS_BOOST_22___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__FE_RFIO_CAP_EN_22___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__FE_RFIO_CAP_EN_22___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_IBIAS_LOWER_LIM_22___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_IBIAS_LOWER_LIM_22___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_ISLOPE_22___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_ISLOPE_22___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_ILEVEL_22___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_ILEVEL_22___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX1_22___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX1_22___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX0_22___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_AUX0_22___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_22___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CAS_BIAS_22___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CASOFF_BIAS_22___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22__PA_CASOFF_BIAS_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23 (0x005DD1D0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_IBIAS_BOOST_23___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__FE_RFIO_CAP_EN_23___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_IBIAS_LOWER_LIM_23___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_ISLOPE_23___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_ILEVEL_23___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX1_23___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX0_23___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_23___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CASOFF_BIAS_23___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_IBIAS_BOOST_23___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_IBIAS_BOOST_23___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__FE_RFIO_CAP_EN_23___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__FE_RFIO_CAP_EN_23___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_IBIAS_LOWER_LIM_23___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_IBIAS_LOWER_LIM_23___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_ISLOPE_23___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_ISLOPE_23___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_ILEVEL_23___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_ILEVEL_23___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX1_23___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX1_23___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX0_23___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_AUX0_23___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_23___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CAS_BIAS_23___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CASOFF_BIAS_23___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23__PA_CASOFF_BIAS_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24 (0x005DD1D4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_IBIAS_BOOST_24___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__FE_RFIO_CAP_EN_24___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_IBIAS_LOWER_LIM_24___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_ISLOPE_24___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_ILEVEL_24___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX1_24___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX0_24___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_24___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CASOFF_BIAS_24___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_IBIAS_BOOST_24___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_IBIAS_BOOST_24___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__FE_RFIO_CAP_EN_24___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__FE_RFIO_CAP_EN_24___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_IBIAS_LOWER_LIM_24___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_IBIAS_LOWER_LIM_24___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_ISLOPE_24___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_ISLOPE_24___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_ILEVEL_24___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_ILEVEL_24___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX1_24___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX1_24___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX0_24___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_AUX0_24___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_24___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CAS_BIAS_24___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CASOFF_BIAS_24___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24__PA_CASOFF_BIAS_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25 (0x005DD1D8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25___POR 0x428C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_IBIAS_BOOST_25___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__FE_RFIO_CAP_EN_25___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_IBIAS_LOWER_LIM_25___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_ISLOPE_25___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_ILEVEL_25___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX1_25___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX0_25___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_25___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CASOFF_BIAS_25___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_IBIAS_BOOST_25___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_IBIAS_BOOST_25___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__FE_RFIO_CAP_EN_25___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__FE_RFIO_CAP_EN_25___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_IBIAS_LOWER_LIM_25___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_IBIAS_LOWER_LIM_25___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_ISLOPE_25___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_ISLOPE_25___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_ILEVEL_25___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_ILEVEL_25___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX1_25___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX1_25___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX0_25___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_AUX0_25___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_25___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CAS_BIAS_25___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CASOFF_BIAS_25___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25__PA_CASOFF_BIAS_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26 (0x005DD1DC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26___POR 0x468C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_IBIAS_BOOST_26___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__FE_RFIO_CAP_EN_26___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_IBIAS_LOWER_LIM_26___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_ISLOPE_26___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_ILEVEL_26___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX1_26___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX0_26___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_26___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CASOFF_BIAS_26___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_IBIAS_BOOST_26___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_IBIAS_BOOST_26___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__FE_RFIO_CAP_EN_26___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__FE_RFIO_CAP_EN_26___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_IBIAS_LOWER_LIM_26___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_IBIAS_LOWER_LIM_26___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_ISLOPE_26___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_ISLOPE_26___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_ILEVEL_26___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_ILEVEL_26___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX1_26___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX1_26___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX0_26___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_AUX0_26___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_26___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CAS_BIAS_26___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CASOFF_BIAS_26___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26__PA_CASOFF_BIAS_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27 (0x005DD1E0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27___POR 0x4A8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_IBIAS_BOOST_27___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__FE_RFIO_CAP_EN_27___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_IBIAS_LOWER_LIM_27___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_ISLOPE_27___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_ILEVEL_27___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX1_27___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX0_27___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_27___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CASOFF_BIAS_27___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_IBIAS_BOOST_27___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_IBIAS_BOOST_27___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__FE_RFIO_CAP_EN_27___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__FE_RFIO_CAP_EN_27___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_IBIAS_LOWER_LIM_27___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_IBIAS_LOWER_LIM_27___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_ISLOPE_27___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_ISLOPE_27___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_ILEVEL_27___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_ILEVEL_27___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX1_27___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX1_27___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX0_27___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_AUX0_27___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_27___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CAS_BIAS_27___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CASOFF_BIAS_27___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27__PA_CASOFF_BIAS_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28 (0x005DD1E4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28___POR 0x4E8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_IBIAS_BOOST_28___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__FE_RFIO_CAP_EN_28___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_IBIAS_LOWER_LIM_28___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_ISLOPE_28___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_ILEVEL_28___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX1_28___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX0_28___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_28___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CASOFF_BIAS_28___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_IBIAS_BOOST_28___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_IBIAS_BOOST_28___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__FE_RFIO_CAP_EN_28___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__FE_RFIO_CAP_EN_28___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_IBIAS_LOWER_LIM_28___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_IBIAS_LOWER_LIM_28___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_ISLOPE_28___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_ISLOPE_28___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_ILEVEL_28___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_ILEVEL_28___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX1_28___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX1_28___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX0_28___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_AUX0_28___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_28___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CAS_BIAS_28___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CASOFF_BIAS_28___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28__PA_CASOFF_BIAS_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29 (0x005DD1E8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29___POR 0x528C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_IBIAS_BOOST_29___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__FE_RFIO_CAP_EN_29___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_IBIAS_LOWER_LIM_29___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_ISLOPE_29___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_ILEVEL_29___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX1_29___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX0_29___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_29___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CASOFF_BIAS_29___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_IBIAS_BOOST_29___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_IBIAS_BOOST_29___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__FE_RFIO_CAP_EN_29___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__FE_RFIO_CAP_EN_29___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_IBIAS_LOWER_LIM_29___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_IBIAS_LOWER_LIM_29___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_ISLOPE_29___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_ISLOPE_29___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_ILEVEL_29___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_ILEVEL_29___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX1_29___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX1_29___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX0_29___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_AUX0_29___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_29___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CAS_BIAS_29___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CASOFF_BIAS_29___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29__PA_CASOFF_BIAS_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30 (0x005DD1EC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30___POR 0x568C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_IBIAS_BOOST_30___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__FE_RFIO_CAP_EN_30___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_IBIAS_LOWER_LIM_30___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_ISLOPE_30___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_ILEVEL_30___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX1_30___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX0_30___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_30___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CASOFF_BIAS_30___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_IBIAS_BOOST_30___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_IBIAS_BOOST_30___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__FE_RFIO_CAP_EN_30___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__FE_RFIO_CAP_EN_30___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_IBIAS_LOWER_LIM_30___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_IBIAS_LOWER_LIM_30___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_ISLOPE_30___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_ISLOPE_30___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_ILEVEL_30___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_ILEVEL_30___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX1_30___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX1_30___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX0_30___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_AUX0_30___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_30___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CAS_BIAS_30___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CASOFF_BIAS_30___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30__PA_CASOFF_BIAS_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31 (0x005DD1F0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31___POR 0x5A8C1720 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_IBIAS_BOOST_31___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__FE_RFIO_CAP_EN_31___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_IBIAS_LOWER_LIM_31___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_ISLOPE_31___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_ILEVEL_31___POR 0x03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX1_31___POR 0x5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX0_31___POR 0x6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_31___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CASOFF_BIAS_31___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_IBIAS_BOOST_31___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_IBIAS_BOOST_31___S 30 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__FE_RFIO_CAP_EN_31___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__FE_RFIO_CAP_EN_31___S 29 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_IBIAS_LOWER_LIM_31___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_IBIAS_LOWER_LIM_31___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_ISLOPE_31___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_ISLOPE_31___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_ILEVEL_31___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_ILEVEL_31___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX1_31___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX1_31___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX0_31___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_AUX0_31___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_31___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CAS_BIAS_31___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CASOFF_BIAS_31___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31__PA_CASOFF_BIAS_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31___M 0x7FFC1FFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_31___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0 (0x005DD1F4) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_FB_0___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___POR 0x00401007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___POR 0x001 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___POR 0x001 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_FB_0___POR 0x001 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___M 0x003FF000 @@ -99625,13 +105167,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1 (0x005DD134) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1 (0x005DD1F8) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_FB_1___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___POR 0x00C0300F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___POR 0x003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___POR 0x003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_FB_1___POR 0x003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___M 0x003FF000 @@ -99643,13 +105185,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2 (0x005DD138) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2 (0x005DD1FC) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_FB_2___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___POR 0x01C0701F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___POR 0x007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___POR 0x007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_FB_2___POR 0x007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___M 0x003FF000 @@ -99661,13 +105203,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3 (0x005DD13C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3 (0x005DD200) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_FB_3___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___POR 0x03C0F03F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___POR 0x00F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___POR 0x00F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_FB_3___POR 0x00F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___M 0x003FF000 @@ -99679,13 +105221,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4 (0x005DD140) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4 (0x005DD204) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_FB_4___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___POR 0x07C1F07F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___POR 0x01F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___POR 0x01F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_FB_4___POR 0x01F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___M 0x003FF000 @@ -99697,13 +105239,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5 (0x005DD144) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5 (0x005DD208) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_FB_5___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___POR 0x0FC3F0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___POR 0x03F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___POR 0x03F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_FB_5___POR 0x03F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___M 0x003FF000 @@ -99715,13 +105257,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6 (0x005DD148) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6 (0x005DD20C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_FB_6___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___POR 0x1FC7F1FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___POR 0x07F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___POR 0x07F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_FB_6___POR 0x07F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___M 0x003FF000 @@ -99733,13 +105275,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7 (0x005DD14C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7 (0x005DD210) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_FB_7___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___POR 0x3FCFF3FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_FB_7___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___M 0x003FF000 @@ -99751,13 +105293,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8 (0x005DD150) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8 (0x005DD214) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_FB_8___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___POR 0x3FCFF3FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_FB_8___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___M 0x003FF000 @@ -99769,13 +105311,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9 (0x005DD154) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9 (0x005DD218) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_FB_9___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___POR 0x3FCFF3FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_FB_9___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___M 0x003FF000 @@ -99787,13 +105329,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10 (0x005DD158) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10 (0x005DD21C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_FB_10___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___POR 0x3FCFF3FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_FB_10___POR 0x0FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___M 0x003FF000 @@ -99805,13 +105347,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11 (0x005DD15C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11 (0x005DD220) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_FB_11___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_FB_11___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___M 0x003FF000 @@ -99823,12 +105365,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12 (0x005DD160) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12 (0x005DD224) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN0_12___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_FB_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___POR 0x80200800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN0_12___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_FB_12___POR 0x200 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___POR 0x0 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___S 22 @@ -99841,13 +105383,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13 (0x005DD164) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13 (0x005DD228) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_FB_13___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___POR 0x80200801 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_FB_13___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___POR 0x1 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___M 0x003FF000 @@ -99859,13 +105401,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14 (0x005DD168) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14 (0x005DD22C) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_FB_14___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___POR 0x80200802 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_FB_14___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___POR 0x2 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___M 0x003FF000 @@ -99877,13 +105419,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___S 0 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15 (0x005DD16C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15 (0x005DD230) #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___POR 0x00000000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_FB_15___POR 0x000 -#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_FB_15___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___POR 0x3 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___M 0xFFC00000 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___S 22 #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___M 0x003FF000 @@ -99895,6 +105437,738 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___M 0xFFFFFFFF #define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16 (0x005DD234) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_EN1_16___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_EN0_16___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_FB_16___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_IBIAS_MODE_16___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_EN1_16___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_EN1_16___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_EN0_16___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_EN0_16___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_FB_16___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_CELL_FB_16___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_IBIAS_MODE_16___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16__PA_IBIAS_MODE_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17 (0x005DD238) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_EN1_17___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_EN0_17___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_FB_17___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_IBIAS_MODE_17___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_EN1_17___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_EN1_17___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_EN0_17___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_EN0_17___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_FB_17___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_CELL_FB_17___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_IBIAS_MODE_17___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17__PA_IBIAS_MODE_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18 (0x005DD23C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_EN1_18___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_EN0_18___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_FB_18___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_IBIAS_MODE_18___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_EN1_18___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_EN1_18___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_EN0_18___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_EN0_18___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_FB_18___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_CELL_FB_18___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_IBIAS_MODE_18___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18__PA_IBIAS_MODE_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19 (0x005DD240) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_EN1_19___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_EN0_19___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_FB_19___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_IBIAS_MODE_19___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_EN1_19___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_EN1_19___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_EN0_19___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_EN0_19___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_FB_19___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_CELL_FB_19___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_IBIAS_MODE_19___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19__PA_IBIAS_MODE_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20 (0x005DD244) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_EN1_20___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_EN0_20___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_FB_20___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_IBIAS_MODE_20___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_EN1_20___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_EN1_20___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_EN0_20___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_EN0_20___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_FB_20___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_CELL_FB_20___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_IBIAS_MODE_20___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20__PA_IBIAS_MODE_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21 (0x005DD248) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21___POR 0x80200803 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_EN1_21___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_EN0_21___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_FB_21___POR 0x200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_IBIAS_MODE_21___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_EN1_21___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_EN1_21___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_EN0_21___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_EN0_21___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_FB_21___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_CELL_FB_21___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_IBIAS_MODE_21___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21__PA_IBIAS_MODE_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22 (0x005DD24C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22___POR 0xC0300C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_EN1_22___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_EN0_22___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_FB_22___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_IBIAS_MODE_22___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_EN1_22___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_EN1_22___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_EN0_22___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_EN0_22___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_FB_22___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_CELL_FB_22___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_IBIAS_MODE_22___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22__PA_IBIAS_MODE_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23 (0x005DD250) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23___POR 0xC0300C01 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_EN1_23___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_EN0_23___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_FB_23___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_IBIAS_MODE_23___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_EN1_23___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_EN1_23___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_EN0_23___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_EN0_23___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_FB_23___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_CELL_FB_23___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_IBIAS_MODE_23___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23__PA_IBIAS_MODE_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24 (0x005DD254) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24___POR 0xC0300C02 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_EN1_24___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_EN0_24___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_FB_24___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_IBIAS_MODE_24___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_EN1_24___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_EN1_24___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_EN0_24___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_EN0_24___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_FB_24___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_CELL_FB_24___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_IBIAS_MODE_24___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24__PA_IBIAS_MODE_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25 (0x005DD258) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_EN1_25___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_EN0_25___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_FB_25___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_IBIAS_MODE_25___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_EN1_25___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_EN1_25___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_EN0_25___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_EN0_25___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_FB_25___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_CELL_FB_25___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_IBIAS_MODE_25___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25__PA_IBIAS_MODE_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26 (0x005DD25C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_EN1_26___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_EN0_26___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_FB_26___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_IBIAS_MODE_26___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_EN1_26___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_EN1_26___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_EN0_26___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_EN0_26___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_FB_26___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_CELL_FB_26___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_IBIAS_MODE_26___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26__PA_IBIAS_MODE_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27 (0x005DD260) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_EN1_27___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_EN0_27___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_FB_27___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_IBIAS_MODE_27___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_EN1_27___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_EN1_27___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_EN0_27___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_EN0_27___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_FB_27___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_CELL_FB_27___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_IBIAS_MODE_27___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27__PA_IBIAS_MODE_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28 (0x005DD264) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_EN1_28___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_EN0_28___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_FB_28___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_IBIAS_MODE_28___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_EN1_28___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_EN1_28___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_EN0_28___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_EN0_28___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_FB_28___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_CELL_FB_28___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_IBIAS_MODE_28___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28__PA_IBIAS_MODE_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29 (0x005DD268) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_EN1_29___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_EN0_29___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_FB_29___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_IBIAS_MODE_29___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_EN1_29___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_EN1_29___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_EN0_29___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_EN0_29___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_FB_29___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_CELL_FB_29___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_IBIAS_MODE_29___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29__PA_IBIAS_MODE_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30 (0x005DD26C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_EN1_30___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_EN0_30___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_FB_30___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_IBIAS_MODE_30___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_EN1_30___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_EN1_30___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_EN0_30___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_EN0_30___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_FB_30___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_CELL_FB_30___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_IBIAS_MODE_30___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30__PA_IBIAS_MODE_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31 (0x005DD270) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31___POR 0xC0300C03 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_EN1_31___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_EN0_31___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_FB_31___POR 0x300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_IBIAS_MODE_31___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_EN1_31___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_EN1_31___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_EN0_31___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_EN0_31___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_FB_31___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_CELL_FB_31___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_IBIAS_MODE_31___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31__PA_IBIAS_MODE_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_31___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0 (0x005DD274) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX1_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX0_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX1_CTRL_0___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX1_CTRL_0___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX0_CTRL_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0__PA_CAS_RDIV_AUX0_CTRL_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1 (0x005DD278) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX1_CTRL_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX0_CTRL_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX1_CTRL_1___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX1_CTRL_1___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX0_CTRL_1___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1__PA_CAS_RDIV_AUX0_CTRL_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2 (0x005DD27C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX1_CTRL_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX0_CTRL_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX1_CTRL_2___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX1_CTRL_2___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX0_CTRL_2___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2__PA_CAS_RDIV_AUX0_CTRL_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3 (0x005DD280) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX1_CTRL_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX0_CTRL_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX1_CTRL_3___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX1_CTRL_3___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX0_CTRL_3___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3__PA_CAS_RDIV_AUX0_CTRL_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4 (0x005DD284) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX1_CTRL_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX0_CTRL_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX1_CTRL_4___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX1_CTRL_4___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX0_CTRL_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4__PA_CAS_RDIV_AUX0_CTRL_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5 (0x005DD288) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX1_CTRL_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX0_CTRL_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX1_CTRL_5___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX1_CTRL_5___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX0_CTRL_5___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5__PA_CAS_RDIV_AUX0_CTRL_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6 (0x005DD28C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX1_CTRL_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX0_CTRL_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX1_CTRL_6___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX1_CTRL_6___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX0_CTRL_6___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6__PA_CAS_RDIV_AUX0_CTRL_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7 (0x005DD290) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX1_CTRL_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX0_CTRL_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX1_CTRL_7___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX1_CTRL_7___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX0_CTRL_7___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7__PA_CAS_RDIV_AUX0_CTRL_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8 (0x005DD294) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX1_CTRL_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX0_CTRL_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX1_CTRL_8___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX1_CTRL_8___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX0_CTRL_8___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8__PA_CAS_RDIV_AUX0_CTRL_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9 (0x005DD298) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX1_CTRL_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX0_CTRL_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX1_CTRL_9___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX1_CTRL_9___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX0_CTRL_9___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9__PA_CAS_RDIV_AUX0_CTRL_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10 (0x005DD29C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX1_CTRL_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX0_CTRL_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX1_CTRL_10___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX1_CTRL_10___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX0_CTRL_10___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10__PA_CAS_RDIV_AUX0_CTRL_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11 (0x005DD2A0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX1_CTRL_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX0_CTRL_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX1_CTRL_11___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX1_CTRL_11___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX0_CTRL_11___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11__PA_CAS_RDIV_AUX0_CTRL_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12 (0x005DD2A4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX1_CTRL_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX0_CTRL_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX1_CTRL_12___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX1_CTRL_12___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX0_CTRL_12___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12__PA_CAS_RDIV_AUX0_CTRL_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13 (0x005DD2A8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX1_CTRL_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX0_CTRL_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX1_CTRL_13___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX1_CTRL_13___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX0_CTRL_13___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13__PA_CAS_RDIV_AUX0_CTRL_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14 (0x005DD2AC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX1_CTRL_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX0_CTRL_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX1_CTRL_14___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX1_CTRL_14___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX0_CTRL_14___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14__PA_CAS_RDIV_AUX0_CTRL_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15 (0x005DD2B0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX1_CTRL_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX0_CTRL_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX1_CTRL_15___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX1_CTRL_15___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX0_CTRL_15___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15__PA_CAS_RDIV_AUX0_CTRL_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16 (0x005DD2B4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX1_CTRL_16___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX0_CTRL_16___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX1_CTRL_16___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX1_CTRL_16___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX0_CTRL_16___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16__PA_CAS_RDIV_AUX0_CTRL_16___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_16___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17 (0x005DD2B8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX1_CTRL_17___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX0_CTRL_17___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX1_CTRL_17___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX1_CTRL_17___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX0_CTRL_17___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17__PA_CAS_RDIV_AUX0_CTRL_17___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_17___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18 (0x005DD2BC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX1_CTRL_18___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX0_CTRL_18___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX1_CTRL_18___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX1_CTRL_18___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX0_CTRL_18___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18__PA_CAS_RDIV_AUX0_CTRL_18___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_18___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19 (0x005DD2C0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX1_CTRL_19___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX0_CTRL_19___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX1_CTRL_19___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX1_CTRL_19___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX0_CTRL_19___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19__PA_CAS_RDIV_AUX0_CTRL_19___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_19___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20 (0x005DD2C4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX1_CTRL_20___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX0_CTRL_20___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX1_CTRL_20___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX1_CTRL_20___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX0_CTRL_20___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20__PA_CAS_RDIV_AUX0_CTRL_20___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_20___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21 (0x005DD2C8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX1_CTRL_21___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX0_CTRL_21___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX1_CTRL_21___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX1_CTRL_21___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX0_CTRL_21___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21__PA_CAS_RDIV_AUX0_CTRL_21___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_21___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22 (0x005DD2CC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX1_CTRL_22___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX0_CTRL_22___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX1_CTRL_22___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX1_CTRL_22___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX0_CTRL_22___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22__PA_CAS_RDIV_AUX0_CTRL_22___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_22___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23 (0x005DD2D0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX1_CTRL_23___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX0_CTRL_23___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX1_CTRL_23___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX1_CTRL_23___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX0_CTRL_23___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23__PA_CAS_RDIV_AUX0_CTRL_23___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_23___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24 (0x005DD2D4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX1_CTRL_24___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX0_CTRL_24___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX1_CTRL_24___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX1_CTRL_24___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX0_CTRL_24___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24__PA_CAS_RDIV_AUX0_CTRL_24___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_24___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25 (0x005DD2D8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX1_CTRL_25___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX0_CTRL_25___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX1_CTRL_25___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX1_CTRL_25___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX0_CTRL_25___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25__PA_CAS_RDIV_AUX0_CTRL_25___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_25___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26 (0x005DD2DC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX1_CTRL_26___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX0_CTRL_26___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX1_CTRL_26___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX1_CTRL_26___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX0_CTRL_26___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26__PA_CAS_RDIV_AUX0_CTRL_26___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_26___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27 (0x005DD2E0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX1_CTRL_27___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX0_CTRL_27___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX1_CTRL_27___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX1_CTRL_27___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX0_CTRL_27___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27__PA_CAS_RDIV_AUX0_CTRL_27___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_27___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28 (0x005DD2E4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX1_CTRL_28___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX0_CTRL_28___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX1_CTRL_28___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX1_CTRL_28___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX0_CTRL_28___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28__PA_CAS_RDIV_AUX0_CTRL_28___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_28___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29 (0x005DD2E8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX1_CTRL_29___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX0_CTRL_29___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX1_CTRL_29___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX1_CTRL_29___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX0_CTRL_29___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29__PA_CAS_RDIV_AUX0_CTRL_29___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_29___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30 (0x005DD2EC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX1_CTRL_30___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX0_CTRL_30___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX1_CTRL_30___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX1_CTRL_30___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX0_CTRL_30___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30__PA_CAS_RDIV_AUX0_CTRL_30___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_30___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31 (0x005DD2F0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX1_CTRL_31___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX0_CTRL_31___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX1_CTRL_31___M 0x000003E0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX1_CTRL_31___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX0_CTRL_31___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31__PA_CAS_RDIV_AUX0_CTRL_31___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_2_31___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0 (0x005DD2F4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0___POR 0x00000005 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__PA_LP_CORE_XFRM_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__PA_LP_HS_CTRL_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__DA_HS_CTRL_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__PA_LP_CORE_XFRM_0___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__PA_LP_CORE_XFRM_0___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__PA_LP_HS_CTRL_0___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__PA_LP_HS_CTRL_0___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__DA_HS_CTRL_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0__DA_HS_CTRL_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1 (0x005DD2F8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1___POR 0x00000009 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__PA_LP_CORE_XFRM_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__PA_LP_HS_CTRL_1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__DA_HS_CTRL_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__PA_LP_CORE_XFRM_1___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__PA_LP_CORE_XFRM_1___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__PA_LP_HS_CTRL_1___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__PA_LP_HS_CTRL_1___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__DA_HS_CTRL_1___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1__DA_HS_CTRL_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2 (0x005DD2FC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2___POR 0x0000000A +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__PA_LP_CORE_XFRM_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__PA_LP_HS_CTRL_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__DA_HS_CTRL_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__PA_LP_CORE_XFRM_2___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__PA_LP_CORE_XFRM_2___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__PA_LP_HS_CTRL_2___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__PA_LP_HS_CTRL_2___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__DA_HS_CTRL_2___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2__DA_HS_CTRL_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3 (0x005DD300) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3___POR 0x0000001A +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__PA_LP_CORE_XFRM_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__PA_LP_HS_CTRL_3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__DA_HS_CTRL_3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__PA_LP_CORE_XFRM_3___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__PA_LP_CORE_XFRM_3___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__PA_LP_HS_CTRL_3___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__PA_LP_HS_CTRL_3___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__DA_HS_CTRL_3___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3__DA_HS_CTRL_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_SUPPLY_0_3___S 0 + #define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG (0x005DE800) #define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___RWC QCSR_REG_RO #define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___POR 0x10000000 @@ -102103,6 +108377,438 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___M 0x000000FF #define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0 (0x005DECA4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0___POR 0x181A1A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_3___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_2___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_1___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_0___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1 (0x005DECA8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1___POR 0x0808120A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_7___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_6___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_5___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_4___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2 (0x005DECAC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2___POR 0x0E061012 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_3___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_2___POR 0x06 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_1___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_0___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3 (0x005DECB0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3___POR 0x08080208 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_7___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_6___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_5___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_4___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4 (0x005DECB4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4___POR 0x060C0210 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_3___POR 0x06 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_2___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_1___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_0___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5 (0x005DECB8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5___POR 0x06060404 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_7___POR 0x06 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_6___POR 0x06 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_5___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_4___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6 (0x005DECBC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6___POR 0x04040402 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_3___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_2___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_1___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_0___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7 (0x005DECC0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7___POR 0x02020204 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_7___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_6___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_5___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_4___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_XLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0 (0x005DECC4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0___POR 0x0A080808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_3___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1 (0x005DECC8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1___POR 0x19190A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_7___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_6___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_5___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_4___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2 (0x005DECCC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2___POR 0x071E1005 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_3___POR 0x07 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_2___POR 0x1E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_1___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_0___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3 (0x005DECD0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3___POR 0x19191F19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_7___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_6___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_5___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_4___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4 (0x005DECD4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4___POR 0x1E0F1F10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_3___POR 0x1E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_2___POR 0x0F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_1___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_0___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5 (0x005DECD8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5___POR 0x1E1E1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_7___POR 0x1E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_6___POR 0x1E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_5___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_4___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6 (0x005DECDC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6___POR 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_3___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_2___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_1___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_0___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7 (0x005DECE0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7___POR 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_7___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_6___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_5___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_4___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_XLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0 (0x005DECE4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1 (0x005DECE8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1___POR 0x1111050C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_7___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_6___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_5___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_4___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2 (0x005DECEC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2___POR 0x03140805 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_3___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_2___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_0___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3 (0x005DECF0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3___POR 0x11111C11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_7___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_6___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_5___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_4___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4 (0x005DECF4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4___POR 0x14081C08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_3___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_1___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5 (0x005DECF8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5___POR 0x14141818 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_7___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_6___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_5___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_4___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6 (0x005DECFC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6___POR 0x1818181C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_3___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_2___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_1___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_0___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7 (0x005DED00) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7___POR 0x1C1C1C18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_7___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_6___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_5___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_4___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_XLNA_LUT_7___S 0 + #define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0 (0x005DEE00) #define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___POR 0x00000000 @@ -102877,6 +109583,438 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___M 0x000000FF #define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0 (0x005DEEA4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0___POR 0x181A1A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_3___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_2___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_1___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_0___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_XLNA_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1 (0x005DEEA8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1___POR 0x0808120A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_7___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_6___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_5___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_4___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_XLNA_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2 (0x005DEEAC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2___POR 0x0E061012 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_3___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_2___POR 0x06 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_1___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_0___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_XLNA_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3 (0x005DEEB0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3___POR 0x08080208 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_7___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_6___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_5___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_4___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_XLNA_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4 (0x005DEEB4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4___POR 0x060C0210 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_3___POR 0x06 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_2___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_1___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_0___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_XLNA_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5 (0x005DEEB8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5___POR 0x06060404 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_7___POR 0x06 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_6___POR 0x06 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_5___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_4___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_XLNA_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6 (0x005DEEBC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6___POR 0x04040402 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_3___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_2___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_1___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_0___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_XLNA_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7 (0x005DEEC0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7___POR 0x02020204 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_7___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_6___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_5___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_4___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_XLNA_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_XLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0 (0x005DEEC4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0___POR 0x0A080808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_3___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1 (0x005DEEC8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1___POR 0x19190A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_7___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_6___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_5___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_4___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2 (0x005DEECC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2___POR 0x071E1005 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_3___POR 0x07 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_2___POR 0x1E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_1___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_0___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3 (0x005DEED0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3___POR 0x19191F19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_7___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_6___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_5___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_4___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4 (0x005DEED4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4___POR 0x1E0F1F10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_3___POR 0x1E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_2___POR 0x0F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_1___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_0___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5 (0x005DEED8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5___POR 0x1E1E1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_7___POR 0x1E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_6___POR 0x1E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_5___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_4___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6 (0x005DEEDC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6___POR 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_3___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_2___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_1___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_0___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7 (0x005DEEE0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7___POR 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_7___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_6___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_5___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_4___POR 0x1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_XLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0 (0x005DEEE4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1 (0x005DEEE8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1___POR 0x1111050C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_7___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_6___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_5___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_4___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1__D_RXBB_TIA_CAP_FINE_XLNA_2M_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2 (0x005DEEEC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2___POR 0x03140805 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_3___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_2___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_0___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3 (0x005DEEF0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3___POR 0x11111C11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_7___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_6___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_5___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_4___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3__D_RXBB_TIA_CAP_FINE_XLNA_2M_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4 (0x005DEEF4) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4___POR 0x14081C08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_3___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_1___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5 (0x005DEEF8) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5___POR 0x14141818 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_7___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_6___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_5___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_4___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5__D_RXBB_TIA_CAP_FINE_XLNA_2M_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6 (0x005DEEFC) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6___POR 0x1818181C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_3___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_2___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_1___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_0___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7 (0x005DEF00) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7___POR 0x1C1C1C18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_7___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_6___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_5___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_4___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7__D_RXBB_TIA_CAP_FINE_XLNA_2M_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_XLNA_LUT_7___S 0 + #define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0 (0x005DF000) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___POR 0x04280E87 @@ -103101,8 +110239,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OV___POR 0x0 @@ -103111,10 +110249,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___S 26 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___M 0x03800000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___S 23 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___M 0x00400000 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___S 22 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___M 0x00300000 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OV___S 22 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OVD___S 20 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___M 0x00004000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___S 14 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___M 0x00003000 @@ -103305,18 +110443,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0 (0x005DF04C) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___POR 0x40666401 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x3 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___POR 0x20824080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__BYPS_HG_0___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x00 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000 @@ -103344,18 +110482,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1 (0x005DF050) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___POR 0x40A26401 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___POR 0x20A24080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x5 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__BYPS_HG_1___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x00 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000 @@ -103383,18 +110521,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2 (0x005DF054) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___POR 0x41628501 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___POR 0x21624080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_GAINA_2___POR 0xB #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__BYPS_HG_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__BYPS_HG_2___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x00 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000 @@ -103422,18 +110560,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3 (0x005DF058) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___POR 0x0002A380 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___POR 0x20022304 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x04 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000 @@ -103461,18 +110599,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4 (0x005DF05C) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___POR 0x001E4380 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___POR 0x20022309 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x09 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000 @@ -103500,18 +110638,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5 (0x005DF060) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___POR 0x001E0380 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___POR 0x40022313 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x13 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000 @@ -103539,18 +110677,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6 (0x005DF064) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___POR 0x00020380 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___POR 0x40022327 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x27 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000 @@ -103578,7 +110716,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7 (0x005DF068) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___POR 0x00026380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___POR 0x00026339 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0 @@ -103588,8 +110726,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x39 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000 @@ -103617,17 +110755,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0 (0x005DF06C) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___POR 0x00000001 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___POR 0x000000A9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARASE_GAIN0___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARASE_GAIN0___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARASE_GAIN0___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___M 0x000003FF @@ -103635,17 +110773,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1 (0x005DF070) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___POR 0x00000082 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___POR 0x00000149 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARASE_GAIN1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARASE_GAIN1___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARASE_GAIN1___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___M 0x000003FF @@ -103653,17 +110791,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2 (0x005DF074) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___POR 0x00000103 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___POR 0x000001D1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARASE_GAIN2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARASE_GAIN2___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARASE_GAIN2___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___M 0x000003FF @@ -103671,17 +110809,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3 (0x005DF078) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___POR 0x000000D3 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___POR 0x00000253 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___POR 0x4 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARASE_GAIN3___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___POR 0x3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARASE_GAIN3___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARASE_GAIN3___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___M 0x000003FF @@ -103689,17 +110827,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4 (0x005DF07C) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___POR 0x00000153 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___POR 0x000002D3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___POR 0x5 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARASE_GAIN4___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___POR 0x3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARASE_GAIN4___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARASE_GAIN4___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___M 0x000003FF @@ -103707,17 +110845,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5 (0x005DF080) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___POR 0x0000022B -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___POR 0x4 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___POR 0x0000037C +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___POR 0x6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARASE_GAIN5___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___POR 0x4 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARASE_GAIN5___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARASE_GAIN5___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___M 0x000003FF @@ -103725,17 +110863,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6 (0x005DF084) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___POR 0x0000027C -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___POR 0x4 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___POR 0x3 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___POR 0x3 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___POR 0x000003D5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARASE_GAIN6___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___POR 0x5 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARASE_GAIN6___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARASE_GAIN6___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___M 0x000003FF @@ -103743,17 +110881,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7 (0x005DF088) #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___POR 0x00000354 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___POR 0x6 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___POR 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARASE_GAIN7___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___POR 0x7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARASE_GAIN7___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARASE_GAIN7___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___M 0x000003FF @@ -103983,8 +111121,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___POR 0x00000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OV___POR 0x0 @@ -103993,10 +111131,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___S 26 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___M 0x03800000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___S 23 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___M 0x00400000 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___S 22 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___M 0x00300000 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OV___S 22 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARASE_GAIN_OVD___S 20 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___M 0x00004000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___S 14 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___M 0x00003000 @@ -104187,18 +111325,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0 (0x005DF24C) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___POR 0x40666401 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x3 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___POR 0x20824080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__BYPS_HG_0___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x00 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000 @@ -104226,18 +111364,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1 (0x005DF250) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___POR 0x40A26401 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___POR 0x20A24080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x5 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__BYPS_HG_1___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x00 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000 @@ -104265,18 +111403,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2 (0x005DF254) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___POR 0x41628501 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___POR 0x21624080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_GAINA_2___POR 0xB #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__BYPS_HG_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__BYPS_HG_2___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x00 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000 @@ -104304,18 +111442,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3 (0x005DF258) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___POR 0x0002A380 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___POR 0x20022304 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x04 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000 @@ -104343,18 +111481,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4 (0x005DF25C) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___POR 0x001E4380 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___POR 0x20022309 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x09 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000 @@ -104382,18 +111520,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5 (0x005DF260) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___POR 0x001E0380 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___POR 0x40022313 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x13 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000 @@ -104421,18 +111559,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6 (0x005DF264) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___POR 0x00020380 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___POR 0x40022327 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x27 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000 @@ -104460,7 +111598,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7 (0x005DF268) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___POR 0x00026380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___POR 0x00026339 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0 @@ -104470,8 +111608,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x39 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000 @@ -104499,17 +111637,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0 (0x005DF26C) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___POR 0x00000001 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___POR 0x000000A9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARASE_GAIN0___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARASE_GAIN0___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARASE_GAIN0___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___M 0x000003FF @@ -104517,17 +111655,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1 (0x005DF270) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___POR 0x00000082 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___POR 0x00000149 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARASE_GAIN1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARASE_GAIN1___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARASE_GAIN1___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___M 0x000003FF @@ -104535,17 +111673,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2 (0x005DF274) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___POR 0x00000103 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___POR 0x0 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___POR 0x000001D1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARASE_GAIN2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___POR 0x1 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARASE_GAIN2___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARASE_GAIN2___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___M 0x000003FF @@ -104553,17 +111691,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3 (0x005DF278) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___POR 0x000000D3 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___POR 0x00000253 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___POR 0x4 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARASE_GAIN3___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___POR 0x3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARASE_GAIN3___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARASE_GAIN3___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___M 0x000003FF @@ -104571,17 +111709,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4 (0x005DF27C) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___POR 0x00000153 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___POR 0x000002D3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___POR 0x5 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARASE_GAIN4___POR 0x2 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___POR 0x3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARASE_GAIN4___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARASE_GAIN4___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___M 0x000003FF @@ -104589,17 +111727,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5 (0x005DF280) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___POR 0x0000022B -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___POR 0x4 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___POR 0x1 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___POR 0x0000037C +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___POR 0x6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARASE_GAIN5___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___POR 0x4 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARASE_GAIN5___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARASE_GAIN5___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___M 0x000003FF @@ -104607,17 +111745,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6 (0x005DF284) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___POR 0x0000027C -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___POR 0x4 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___POR 0x3 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___POR 0x3 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___POR 0x000003D5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARASE_GAIN6___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___POR 0x5 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARASE_GAIN6___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARASE_GAIN6___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___M 0x000003FF @@ -104625,17 +111763,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7 (0x005DF288) #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___POR 0x00000354 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___POR 0x6 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___POR 0x2 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___POR 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARASE_GAIN7___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___POR 0x7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___M 0x00000380 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___S 7 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___M 0x00000060 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___S 5 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___M 0x00000018 -#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARASE_GAIN7___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARASE_GAIN7___S 3 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___M 0x00000007 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___S 0 #define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___M 0x000003FF @@ -106173,7 +113311,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x07800000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___S 23 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___S 20 @@ -106189,7 +113327,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___S 4 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___S 0 -#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___M 0x07FFFFFF #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___S 0 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0 (0x005E00A0) @@ -106293,7 +113431,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x07800000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___S 23 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___S 20 @@ -106309,7 +113447,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___S 4 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___S 0 -#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___M 0x07FFFFFF #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___S 0 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1 (0x005E00B8) @@ -106903,6 +114041,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___M 0xFC000000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0 (0x005E01C0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0__QFEM_EXT_PRODUCT_ID___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0__QFEM_SLAVE_ID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0__QFEM_EXT_PRODUCT_ID___M 0x00000FF0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0__QFEM_EXT_PRODUCT_ID___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0__QFEM_SLAVE_ID___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0__QFEM_SLAVE_ID___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_QFEM_0___S 0 + #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG (0x005E1000) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___POR 0x44FE2111 @@ -106955,6 +114105,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___POR 0x60A25480 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_CASCODE_BIAS_CTRL_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x5 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 @@ -106967,6 +114118,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x00 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_CASCODE_BIAS_CTRL_0___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_CASCODE_BIAS_CTRL_0___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000 @@ -106987,13 +114140,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1 (0x005E1014) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___POR 0x60E24480 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_CASCODE_BIAS_CTRL_1___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 @@ -107006,6 +114160,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x00 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_CASCODE_BIAS_CTRL_1___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_CASCODE_BIAS_CTRL_1___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000 @@ -107026,13 +114182,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2 (0x005E1018) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___POR 0x601E030A #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_CASCODE_BIAS_CTRL_2___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 @@ -107045,6 +114202,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x0A #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_CASCODE_BIAS_CTRL_2___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_CASCODE_BIAS_CTRL_2___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000 @@ -107065,13 +114224,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3 (0x005E101C) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___POR 0x60022304 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_CASCODE_BIAS_CTRL_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 @@ -107084,6 +114244,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x04 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_CASCODE_BIAS_CTRL_3___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_CASCODE_BIAS_CTRL_3___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000 @@ -107104,13 +114266,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4 (0x005E1020) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___POR 0x60022309 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_CASCODE_BIAS_CTRL_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 @@ -107123,6 +114286,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x09 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_CASCODE_BIAS_CTRL_4___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_CASCODE_BIAS_CTRL_4___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000 @@ -107143,13 +114308,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5 (0x005E1024) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___POR 0x60022312 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_CASCODE_BIAS_CTRL_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 @@ -107162,6 +114328,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x12 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_CASCODE_BIAS_CTRL_5___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_CASCODE_BIAS_CTRL_5___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000 @@ -107182,13 +114350,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6 (0x005E1028) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___POR 0x4002231C #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_CASCODE_BIAS_CTRL_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 @@ -107201,6 +114370,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x1C #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_CASCODE_BIAS_CTRL_6___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_CASCODE_BIAS_CTRL_6___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000 @@ -107221,13 +114392,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7 (0x005E102C) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___POR 0x00026339 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_CASCODE_BIAS_CTRL_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1 @@ -107240,6 +114412,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x39 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_CASCODE_BIAS_CTRL_7___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_CASCODE_BIAS_CTRL_7___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000 @@ -107260,7 +114434,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0 (0x005E1030) @@ -107459,6 +114633,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OVD___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S 30 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000 @@ -107467,8 +114643,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OV___S 27 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___M 0x07E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___S 21 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OV___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OVD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___S 16 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1 (0x005E1088) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___RWC QCSR_REG_RW @@ -107558,6 +114738,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__DPD_XPA_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S 30 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___M 0x30000000 @@ -107566,8 +114747,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S 27 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S 20 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___M 0xFFF00000 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__DPD_XPA_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__DPD_XPA_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___S 18 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL (0x005E1098) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO @@ -107630,6 +114813,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_LNA_CASCODE_BIAS_CTRL___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___M 0x80000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___S 31 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___M 0x7E000000 @@ -107638,8 +114822,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___S 19 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___M 0x00070000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___S 16 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_LNA_CASCODE_BIAS_CTRL___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_LNA_CASCODE_BIAS_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___S 12 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2 (0x005E10A4) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO @@ -109233,192 +116419,528 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_IBIAS_BOOST_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_OPAMP_BOOST_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX0_PD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX1_PD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX1_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX0_CTRL_0___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_CTRL_0___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_CTRL_0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_IBIAS_BOOST_0___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_IBIAS_BOOST_0___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_OPAMP_BOOST_0___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_OPAMP_BOOST_0___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX0_PD_0___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX0_PD_0___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX1_PD_0___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX1_PD_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX1_CTRL_0___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX1_CTRL_0___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX0_CTRL_0___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX0_CTRL_0___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1 (0x005E1434) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_CTRL_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_IBIAS_BOOST_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_OPAMP_BOOST_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX0_PD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX1_PD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX1_CTRL_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX0_CTRL_1___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_CTRL_1___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_CTRL_1___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_IBIAS_BOOST_1___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_IBIAS_BOOST_1___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_OPAMP_BOOST_1___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_OPAMP_BOOST_1___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX0_PD_1___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX0_PD_1___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX1_PD_1___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX1_PD_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX1_CTRL_1___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX1_CTRL_1___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX0_CTRL_1___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX0_CTRL_1___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2 (0x005E1438) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_CTRL_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_IBIAS_BOOST_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_OPAMP_BOOST_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX0_PD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX1_PD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX1_CTRL_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX0_CTRL_2___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_CTRL_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_CTRL_2___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_IBIAS_BOOST_2___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_IBIAS_BOOST_2___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_OPAMP_BOOST_2___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_OPAMP_BOOST_2___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX0_PD_2___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX0_PD_2___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX1_PD_2___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX1_PD_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX1_CTRL_2___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX1_CTRL_2___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX0_CTRL_2___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX0_CTRL_2___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3 (0x005E143C) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_CTRL_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_IBIAS_BOOST_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_OPAMP_BOOST_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX0_PD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX1_PD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX1_CTRL_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX0_CTRL_3___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_CTRL_3___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_CTRL_3___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_IBIAS_BOOST_3___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_IBIAS_BOOST_3___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_OPAMP_BOOST_3___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_OPAMP_BOOST_3___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX0_PD_3___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX0_PD_3___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX1_PD_3___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX1_PD_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX1_CTRL_3___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX1_CTRL_3___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX0_CTRL_3___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX0_CTRL_3___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4 (0x005E1440) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_CTRL_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_IBIAS_BOOST_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_OPAMP_BOOST_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX0_PD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX1_PD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX1_CTRL_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX0_CTRL_4___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_CTRL_4___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_CTRL_4___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_IBIAS_BOOST_4___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_IBIAS_BOOST_4___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_OPAMP_BOOST_4___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_OPAMP_BOOST_4___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX0_PD_4___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX0_PD_4___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX1_PD_4___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX1_PD_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX1_CTRL_4___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX1_CTRL_4___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX0_CTRL_4___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX0_CTRL_4___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5 (0x005E1444) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_CTRL_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_IBIAS_BOOST_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_OPAMP_BOOST_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX0_PD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX1_PD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX1_CTRL_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX0_CTRL_5___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_CTRL_5___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_CTRL_5___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_IBIAS_BOOST_5___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_IBIAS_BOOST_5___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_OPAMP_BOOST_5___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_OPAMP_BOOST_5___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX0_PD_5___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX0_PD_5___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX1_PD_5___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX1_PD_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX1_CTRL_5___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX1_CTRL_5___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX0_CTRL_5___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX0_CTRL_5___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6 (0x005E1448) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_CTRL_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_IBIAS_BOOST_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_OPAMP_BOOST_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX0_PD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX1_PD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX1_CTRL_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX0_CTRL_6___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_CTRL_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_CTRL_6___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_IBIAS_BOOST_6___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_IBIAS_BOOST_6___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_OPAMP_BOOST_6___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_OPAMP_BOOST_6___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX0_PD_6___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX0_PD_6___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX1_PD_6___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX1_PD_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX1_CTRL_6___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX1_CTRL_6___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX0_CTRL_6___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX0_CTRL_6___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7 (0x005E144C) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_CTRL_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_IBIAS_BOOST_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_OPAMP_BOOST_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX0_PD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX1_PD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX1_CTRL_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX0_CTRL_7___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_CTRL_7___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_CTRL_7___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_IBIAS_BOOST_7___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_IBIAS_BOOST_7___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_OPAMP_BOOST_7___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_OPAMP_BOOST_7___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX0_PD_7___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX0_PD_7___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX1_PD_7___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX1_PD_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX1_CTRL_7___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX1_CTRL_7___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX0_CTRL_7___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX0_CTRL_7___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8 (0x005E1450) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_CTRL_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_IBIAS_BOOST_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_OPAMP_BOOST_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX0_PD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX1_PD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX1_CTRL_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX0_CTRL_8___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_CTRL_8___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_CTRL_8___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_IBIAS_BOOST_8___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_IBIAS_BOOST_8___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_OPAMP_BOOST_8___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_OPAMP_BOOST_8___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX0_PD_8___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX0_PD_8___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX1_PD_8___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX1_PD_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX1_CTRL_8___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX1_CTRL_8___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX0_CTRL_8___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX0_CTRL_8___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9 (0x005E1454) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_CTRL_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_IBIAS_BOOST_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_OPAMP_BOOST_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX0_PD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX1_PD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX1_CTRL_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX0_CTRL_9___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_CTRL_9___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_CTRL_9___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_IBIAS_BOOST_9___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_IBIAS_BOOST_9___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_OPAMP_BOOST_9___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_OPAMP_BOOST_9___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX0_PD_9___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX0_PD_9___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX1_PD_9___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX1_PD_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX1_CTRL_9___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX1_CTRL_9___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX0_CTRL_9___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX0_CTRL_9___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10 (0x005E1458) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_CTRL_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_IBIAS_BOOST_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_OPAMP_BOOST_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX0_PD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX1_PD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX1_CTRL_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX0_CTRL_10___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_CTRL_10___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_CTRL_10___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_IBIAS_BOOST_10___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_IBIAS_BOOST_10___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_OPAMP_BOOST_10___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_OPAMP_BOOST_10___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX0_PD_10___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX0_PD_10___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX1_PD_10___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX1_PD_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX1_CTRL_10___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX1_CTRL_10___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX0_CTRL_10___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX0_CTRL_10___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11 (0x005E145C) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_CTRL_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_IBIAS_BOOST_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_OPAMP_BOOST_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX0_PD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX1_PD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX1_CTRL_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX0_CTRL_11___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_CTRL_11___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_CTRL_11___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_IBIAS_BOOST_11___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_IBIAS_BOOST_11___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_OPAMP_BOOST_11___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_OPAMP_BOOST_11___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX0_PD_11___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX0_PD_11___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX1_PD_11___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX1_PD_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX1_CTRL_11___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX1_CTRL_11___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX0_CTRL_11___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX0_CTRL_11___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12 (0x005E1460) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_CTRL_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_IBIAS_BOOST_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_OPAMP_BOOST_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX0_PD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX1_PD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX1_CTRL_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX0_CTRL_12___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_CTRL_12___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_CTRL_12___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_IBIAS_BOOST_12___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_IBIAS_BOOST_12___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_OPAMP_BOOST_12___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_OPAMP_BOOST_12___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX0_PD_12___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX0_PD_12___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX1_PD_12___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX1_PD_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX1_CTRL_12___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX1_CTRL_12___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX0_CTRL_12___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX0_CTRL_12___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13 (0x005E1464) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_CTRL_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_IBIAS_BOOST_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_OPAMP_BOOST_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX0_PD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX1_PD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX1_CTRL_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX0_CTRL_13___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_CTRL_13___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_CTRL_13___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_IBIAS_BOOST_13___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_IBIAS_BOOST_13___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_OPAMP_BOOST_13___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_OPAMP_BOOST_13___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX0_PD_13___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX0_PD_13___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX1_PD_13___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX1_PD_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX1_CTRL_13___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX1_CTRL_13___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX0_CTRL_13___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX0_CTRL_13___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14 (0x005E1468) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_CTRL_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_IBIAS_BOOST_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_OPAMP_BOOST_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX0_PD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX1_PD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX1_CTRL_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX0_CTRL_14___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_CTRL_14___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_CTRL_14___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_IBIAS_BOOST_14___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_IBIAS_BOOST_14___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_OPAMP_BOOST_14___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_OPAMP_BOOST_14___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX0_PD_14___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX0_PD_14___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX1_PD_14___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX1_PD_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX1_CTRL_14___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX1_CTRL_14___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX0_CTRL_14___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX0_CTRL_14___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15 (0x005E146C) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_CTRL_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_IBIAS_BOOST_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_OPAMP_BOOST_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX0_PD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX1_PD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX1_CTRL_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX0_CTRL_15___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_CTRL_15___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_CTRL_15___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_IBIAS_BOOST_15___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_IBIAS_BOOST_15___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_OPAMP_BOOST_15___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_OPAMP_BOOST_15___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX0_PD_15___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX0_PD_15___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX1_PD_15___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX1_PD_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX1_CTRL_15___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX1_CTRL_15___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX0_CTRL_15___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX0_CTRL_15___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0 (0x005E1470) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___RWC QCSR_REG_RW @@ -109431,6 +116953,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000 @@ -109447,8 +116971,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OV___S 11 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___S 8 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___M 0xFFFFFF00 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OVD___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OVD___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1 (0x005E1474) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___RWC QCSR_REG_RW @@ -109461,6 +116989,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OV___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OV___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000 @@ -109477,8 +117007,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OV___S 8 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___M 0x000000C0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___S 6 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OV___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___S 0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4 (0x005E1478) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___RWC QCSR_REG_RW @@ -109561,14 +117095,32 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_RDIV_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_RDIV_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_IBIAS_BOOST_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_OPAMP_BOOST_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_BIAS_AUX0_PD_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_BIAS_AUX1_PD_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___S 30 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___M 0x20000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___S 29 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___M 0x1FF80000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___S 19 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___M 0xFFF80000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_RDIV_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_RDIV_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_RDIV_CTRL_OVD___M 0x0003E000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_RDIV_CTRL_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_IBIAS_BOOST_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_IBIAS_BOOST_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_OPAMP_BOOST_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_OPAMP_BOOST_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_BIAS_AUX0_PD_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_BIAS_AUX0_PD_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_BIAS_AUX1_PD_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CAS_BIAS_AUX1_PD_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___S 5 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0 (0x005E1484) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___RWC QCSR_REG_RW @@ -109643,6 +117195,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_SW_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_FC_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S 30 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000 @@ -109669,8 +117222,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___S 6 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___M 0x00000030 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___S 4 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___M 0xFFF3FFF0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_FC_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_FC_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___M 0xFFF3FFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0 (0x005E1490) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO @@ -109726,13 +117281,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3 (0x005E1498) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_CAS_RDIV_AUX0_CTRL___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_CAS_RDIV_AUX0_CTRL___M 0x0000F800 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_CAS_RDIV_AUX0_CTRL___S 11 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000007C0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S 6 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000003E #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S 1 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___M 0x000007FE +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___M 0x0000FFFE #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___S 1 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4 (0x005E149C) @@ -109743,6 +117301,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_IBIAS_BOOST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_OPAMP_BOOST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0_PD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1_PD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_RDIV_AUX1_CTRL___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S 29 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000 @@ -109753,8 +117316,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S 19 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S 9 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___M 0xFFFFFE00 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_IBIAS_BOOST___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_IBIAS_BOOST___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_OPAMP_BOOST___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_OPAMP_BOOST___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0_PD___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0_PD___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1_PD___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1_PD___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_RDIV_AUX1_CTRL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_RDIV_AUX1_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___S 0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5 (0x005E14A0) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO @@ -109765,6 +117338,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CAS_RDIV_CTRL___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S 22 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___M 0x00300000 @@ -109777,8 +117351,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___S 16 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___M 0x0000FFC0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___S 6 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CAS_RDIV_CTRL___M 0x0000003E +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CAS_RDIV_CTRL___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___S 1 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0 (0x005E14A4) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO @@ -109790,6 +117366,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_FC_EN___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___S 30 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___M 0x20000000 @@ -109804,8 +117381,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___S 25 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___M 0x01000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___S 24 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___M 0x7F000000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_FC_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_FC_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___M 0x7F800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___S 23 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0 (0x005E14C0) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___RWC QCSR_REG_RW @@ -109964,9 +117543,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___POR 0x2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ISLOPE___POR 0x5 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX1_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_EN___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___M 0x70000000 @@ -109975,14 +117556,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ISLOPE___S 25 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___M 0x01C00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___S 22 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___M 0x00200000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___M 0x00100000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___S 20 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___M 0x00080000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___S 19 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___M 0xFFF80000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_EN___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_EN___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX1_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX1_EN___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX0_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX0_EN___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_CTRL___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_EN___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___S 14 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY (0x005E14E0) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW @@ -110187,13 +117772,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1 (0x005E2084) #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___POR 0x00F80204 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___POR 0x3FF8FE04 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___S 24 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___S 22 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000 @@ -110202,11 +117799,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S 18 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___S 10 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S 5 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S 0 -#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___M 0x00FF03FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___M 0x3FFFFFFF #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___S 0 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2 (0x005E2088) @@ -139503,9 +147106,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__UPC_GAIN_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DA_GAIN_0___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__XPA_GAIN_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___S 19 @@ -139533,9 +147136,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__UPC_GAIN_1___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DA_GAIN_1___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__XPA_GAIN_1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___S 19 @@ -139563,9 +147166,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__UPC_GAIN_2___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DA_GAIN_2___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__XPA_GAIN_2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___S 19 @@ -139593,9 +147196,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__UPC_GAIN_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DA_GAIN_3___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__XPA_GAIN_3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___S 19 @@ -139623,9 +147226,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__UPC_GAIN_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DA_GAIN_4___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__XPA_GAIN_4___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___S 19 @@ -139653,9 +147256,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__UPC_GAIN_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DA_GAIN_5___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__XPA_GAIN_5___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___S 19 @@ -139683,9 +147286,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__UPC_GAIN_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DA_GAIN_6___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__XPA_GAIN_6___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___S 19 @@ -139713,9 +147316,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__UPC_GAIN_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DA_GAIN_7___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__XPA_GAIN_7___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___S 19 @@ -139743,9 +147346,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__UPC_GAIN_8___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DA_GAIN_8___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__XPA_GAIN_8___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___S 19 @@ -139773,9 +147376,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__UPC_GAIN_9___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DA_GAIN_9___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__XPA_GAIN_9___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___S 19 @@ -139803,9 +147406,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__UPC_GAIN_10___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DA_GAIN_10___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__XPA_GAIN_10___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___S 19 @@ -139833,9 +147436,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__UPC_GAIN_11___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DA_GAIN_11___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__XPA_GAIN_11___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___S 19 @@ -139863,9 +147466,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__UPC_GAIN_12___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DA_GAIN_12___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__XPA_GAIN_12___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___S 19 @@ -139893,9 +147496,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__UPC_GAIN_13___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DA_GAIN_13___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__XPA_GAIN_13___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___S 19 @@ -139923,9 +147526,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__UPC_GAIN_14___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DA_GAIN_14___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__XPA_GAIN_14___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___S 19 @@ -139953,9 +147556,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__UPC_GAIN_15___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DA_GAIN_15___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__XPA_GAIN_15___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___S 19 @@ -139983,9 +147586,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__UPC_GAIN_16___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DA_GAIN_16___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__XPA_GAIN_16___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___S 19 @@ -140013,9 +147616,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__UPC_GAIN_17___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DA_GAIN_17___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__XPA_GAIN_17___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___S 19 @@ -140043,9 +147646,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__UPC_GAIN_18___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DA_GAIN_18___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__XPA_GAIN_18___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___S 19 @@ -140073,9 +147676,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__UPC_GAIN_19___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DA_GAIN_19___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__XPA_GAIN_19___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___S 19 @@ -140103,9 +147706,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__UPC_GAIN_20___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DA_GAIN_20___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__XPA_GAIN_20___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___S 19 @@ -140133,9 +147736,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__UPC_GAIN_21___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DA_GAIN_21___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__XPA_GAIN_21___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___S 19 @@ -140163,9 +147766,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__UPC_GAIN_22___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DA_GAIN_22___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__XPA_GAIN_22___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___S 19 @@ -140193,9 +147796,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__UPC_GAIN_23___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DA_GAIN_23___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__XPA_GAIN_23___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___S 19 @@ -140223,9 +147826,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__UPC_GAIN_24___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DA_GAIN_24___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__XPA_GAIN_24___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___S 19 @@ -140253,9 +147856,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__UPC_GAIN_25___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DA_GAIN_25___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__XPA_GAIN_25___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___S 19 @@ -140283,9 +147886,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__UPC_GAIN_26___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DA_GAIN_26___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__XPA_GAIN_26___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___S 19 @@ -140313,9 +147916,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__UPC_GAIN_27___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DA_GAIN_27___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__XPA_GAIN_27___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___S 19 @@ -140343,9 +147946,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__UPC_GAIN_28___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DA_GAIN_28___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__XPA_GAIN_28___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___S 19 @@ -140373,9 +147976,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__UPC_GAIN_29___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DA_GAIN_29___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__XPA_GAIN_29___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___S 19 @@ -140403,9 +148006,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__UPC_GAIN_30___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DA_GAIN_30___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__XPA_GAIN_30___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___S 19 @@ -140433,9 +148036,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__UPC_GAIN_31___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DA_GAIN_31___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__XPA_GAIN_31___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___S 19 @@ -140463,9 +148066,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__UPC_GAIN_32___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DA_GAIN_32___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__XPA_GAIN_32___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___S 19 @@ -140493,9 +148096,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__UPC_GAIN_33___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DA_GAIN_33___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__XPA_GAIN_33___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___S 19 @@ -140523,9 +148126,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__UPC_GAIN_34___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DA_GAIN_34___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__XPA_GAIN_34___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___S 19 @@ -140553,9 +148156,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__UPC_GAIN_35___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DA_GAIN_35___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__XPA_GAIN_35___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___S 19 @@ -140583,9 +148186,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__UPC_GAIN_36___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DA_GAIN_36___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__XPA_GAIN_36___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___S 19 @@ -140613,9 +148216,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__UPC_GAIN_37___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DA_GAIN_37___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__XPA_GAIN_37___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___S 19 @@ -140643,9 +148246,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__UPC_GAIN_38___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DA_GAIN_38___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__XPA_GAIN_38___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___S 19 @@ -140673,9 +148276,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__UPC_GAIN_39___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DA_GAIN_39___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__XPA_GAIN_39___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___S 19 @@ -140703,9 +148306,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__UPC_GAIN_40___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DA_GAIN_40___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__XPA_GAIN_40___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___S 19 @@ -140733,9 +148336,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__UPC_GAIN_41___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DA_GAIN_41___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__XPA_GAIN_41___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___S 19 @@ -140763,9 +148366,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__UPC_GAIN_42___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DA_GAIN_42___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__XPA_GAIN_42___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___S 19 @@ -140793,9 +148396,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__UPC_GAIN_43___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DA_GAIN_43___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__XPA_GAIN_43___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___S 19 @@ -140823,9 +148426,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__UPC_GAIN_44___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DA_GAIN_44___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__XPA_GAIN_44___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___S 19 @@ -140853,9 +148456,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__UPC_GAIN_45___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DA_GAIN_45___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__XPA_GAIN_45___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___S 19 @@ -140883,9 +148486,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__UPC_GAIN_46___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DA_GAIN_46___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__XPA_GAIN_46___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___S 19 @@ -140913,9 +148516,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__UPC_GAIN_47___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DA_GAIN_47___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__XPA_GAIN_47___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___S 19 @@ -140943,9 +148546,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__UPC_GAIN_48___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DA_GAIN_48___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__XPA_GAIN_48___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___S 19 @@ -140973,9 +148576,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__UPC_GAIN_49___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DA_GAIN_49___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__XPA_GAIN_49___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___S 19 @@ -141003,9 +148606,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__UPC_GAIN_50___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DA_GAIN_50___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__XPA_GAIN_50___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___S 19 @@ -141033,9 +148636,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__UPC_GAIN_51___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DA_GAIN_51___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__XPA_GAIN_51___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___S 19 @@ -141063,9 +148666,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__UPC_GAIN_52___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DA_GAIN_52___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__XPA_GAIN_52___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___S 19 @@ -141093,9 +148696,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__UPC_GAIN_53___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DA_GAIN_53___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__XPA_GAIN_53___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___S 19 @@ -141123,9 +148726,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__UPC_GAIN_54___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DA_GAIN_54___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__XPA_GAIN_54___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___S 19 @@ -141153,9 +148756,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__UPC_GAIN_55___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DA_GAIN_55___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__XPA_GAIN_55___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___S 19 @@ -141183,9 +148786,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__UPC_GAIN_56___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DA_GAIN_56___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__XPA_GAIN_56___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___S 19 @@ -141213,9 +148816,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__UPC_GAIN_57___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DA_GAIN_57___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__XPA_GAIN_57___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___S 19 @@ -141243,9 +148846,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__UPC_GAIN_58___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DA_GAIN_58___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__XPA_GAIN_58___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___S 19 @@ -141273,9 +148876,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__UPC_GAIN_59___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DA_GAIN_59___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__XPA_GAIN_59___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___S 19 @@ -141303,9 +148906,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__UPC_GAIN_60___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DA_GAIN_60___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__XPA_GAIN_60___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___S 19 @@ -141333,9 +148936,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__UPC_GAIN_61___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DA_GAIN_61___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__XPA_GAIN_61___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___S 19 @@ -141363,9 +148966,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__UPC_GAIN_62___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DA_GAIN_62___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__XPA_GAIN_62___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___S 19 @@ -141393,9 +148996,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__UPC_GAIN_63___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DA_GAIN_63___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__XPA_GAIN_63___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___S 19 @@ -141423,9 +149026,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__UPC_GAIN_64___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DA_GAIN_64___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__XPA_GAIN_64___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___S 19 @@ -141453,9 +149056,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__UPC_GAIN_65___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DA_GAIN_65___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__XPA_GAIN_65___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___S 19 @@ -141483,9 +149086,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__UPC_GAIN_66___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DA_GAIN_66___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__XPA_GAIN_66___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___S 19 @@ -141513,9 +149116,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__UPC_GAIN_67___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DA_GAIN_67___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__XPA_GAIN_67___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___S 19 @@ -141543,9 +149146,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__UPC_GAIN_68___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DA_GAIN_68___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__XPA_GAIN_68___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___S 19 @@ -141573,9 +149176,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__UPC_GAIN_69___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DA_GAIN_69___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__XPA_GAIN_69___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___S 19 @@ -141603,9 +149206,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__UPC_GAIN_70___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DA_GAIN_70___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__XPA_GAIN_70___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___S 19 @@ -141633,9 +149236,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__UPC_GAIN_71___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DA_GAIN_71___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__XPA_GAIN_71___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___S 19 @@ -141663,9 +149266,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__UPC_GAIN_72___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DA_GAIN_72___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__XPA_GAIN_72___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___S 19 @@ -141693,9 +149296,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__UPC_GAIN_73___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DA_GAIN_73___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__XPA_GAIN_73___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___S 19 @@ -141723,9 +149326,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__UPC_GAIN_74___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DA_GAIN_74___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__XPA_GAIN_74___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___S 19 @@ -141753,9 +149356,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__UPC_GAIN_75___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DA_GAIN_75___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__XPA_GAIN_75___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___S 19 @@ -141783,9 +149386,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__UPC_GAIN_76___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DA_GAIN_76___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__XPA_GAIN_76___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___S 19 @@ -141813,9 +149416,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__UPC_GAIN_77___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DA_GAIN_77___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__XPA_GAIN_77___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___S 19 @@ -141843,9 +149446,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__UPC_GAIN_78___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DA_GAIN_78___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__XPA_GAIN_78___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___S 19 @@ -141873,9 +149476,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__UPC_GAIN_79___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DA_GAIN_79___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__XPA_GAIN_79___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___S 19 @@ -141903,9 +149506,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__UPC_GAIN_80___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DA_GAIN_80___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__XPA_GAIN_80___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___S 19 @@ -141933,9 +149536,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__UPC_GAIN_81___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DA_GAIN_81___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__XPA_GAIN_81___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___S 19 @@ -141963,9 +149566,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__UPC_GAIN_82___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DA_GAIN_82___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__XPA_GAIN_82___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___S 19 @@ -141993,9 +149596,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__UPC_GAIN_83___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DA_GAIN_83___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__XPA_GAIN_83___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___S 19 @@ -142023,9 +149626,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__UPC_GAIN_84___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DA_GAIN_84___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__XPA_GAIN_84___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___S 19 @@ -142053,9 +149656,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__UPC_GAIN_85___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DA_GAIN_85___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__XPA_GAIN_85___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___S 19 @@ -142083,9 +149686,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__UPC_GAIN_86___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DA_GAIN_86___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__XPA_GAIN_86___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___S 19 @@ -142113,9 +149716,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__UPC_GAIN_87___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DA_GAIN_87___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__XPA_GAIN_87___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___S 19 @@ -142143,9 +149746,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__UPC_GAIN_88___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DA_GAIN_88___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__XPA_GAIN_88___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___S 19 @@ -142173,9 +149776,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__UPC_GAIN_89___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DA_GAIN_89___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__XPA_GAIN_89___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___S 19 @@ -142203,9 +149806,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__UPC_GAIN_90___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DA_GAIN_90___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__XPA_GAIN_90___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___S 19 @@ -142233,9 +149836,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__UPC_GAIN_91___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DA_GAIN_91___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__XPA_GAIN_91___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___S 19 @@ -142263,9 +149866,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__UPC_GAIN_92___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DA_GAIN_92___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__XPA_GAIN_92___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___S 19 @@ -142293,9 +149896,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__UPC_GAIN_93___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DA_GAIN_93___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__XPA_GAIN_93___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___S 19 @@ -142323,9 +149926,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__UPC_GAIN_94___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DA_GAIN_94___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__XPA_GAIN_94___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___S 19 @@ -142353,9 +149956,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__UPC_GAIN_95___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DA_GAIN_95___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__XPA_GAIN_95___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___S 19 @@ -142383,9 +149986,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__UPC_GAIN_96___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DA_GAIN_96___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__XPA_GAIN_96___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___S 19 @@ -142413,9 +150016,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__UPC_GAIN_97___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DA_GAIN_97___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__XPA_GAIN_97___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___S 19 @@ -142443,9 +150046,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__UPC_GAIN_98___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DA_GAIN_98___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__XPA_GAIN_98___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___S 19 @@ -142473,9 +150076,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__UPC_GAIN_99___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DA_GAIN_99___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__XPA_GAIN_99___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___S 19 @@ -142503,9 +150106,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__UPC_GAIN_100___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DA_GAIN_100___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__XPA_GAIN_100___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___S 19 @@ -142533,9 +150136,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__UPC_GAIN_101___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DA_GAIN_101___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__XPA_GAIN_101___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___S 19 @@ -142563,9 +150166,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__UPC_GAIN_102___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DA_GAIN_102___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__XPA_GAIN_102___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___S 19 @@ -142593,9 +150196,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__UPC_GAIN_103___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DA_GAIN_103___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__XPA_GAIN_103___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___S 19 @@ -142623,9 +150226,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__UPC_GAIN_104___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DA_GAIN_104___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__XPA_GAIN_104___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___S 19 @@ -142653,9 +150256,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__UPC_GAIN_105___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DA_GAIN_105___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__XPA_GAIN_105___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___S 19 @@ -142683,9 +150286,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__UPC_GAIN_106___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DA_GAIN_106___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__XPA_GAIN_106___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___S 19 @@ -142713,9 +150316,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__UPC_GAIN_107___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DA_GAIN_107___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__XPA_GAIN_107___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___S 19 @@ -142743,9 +150346,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__UPC_GAIN_108___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DA_GAIN_108___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__XPA_GAIN_108___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___S 19 @@ -142773,9 +150376,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__UPC_GAIN_109___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DA_GAIN_109___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__XPA_GAIN_109___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___S 19 @@ -142803,9 +150406,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__UPC_GAIN_110___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DA_GAIN_110___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__XPA_GAIN_110___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___S 19 @@ -142833,9 +150436,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__UPC_GAIN_111___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DA_GAIN_111___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__XPA_GAIN_111___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___S 19 @@ -142863,9 +150466,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__UPC_GAIN_112___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DA_GAIN_112___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__XPA_GAIN_112___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___S 19 @@ -142893,9 +150496,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__UPC_GAIN_113___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DA_GAIN_113___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__XPA_GAIN_113___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___S 19 @@ -142923,9 +150526,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__UPC_GAIN_114___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DA_GAIN_114___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__XPA_GAIN_114___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___S 19 @@ -142953,9 +150556,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__UPC_GAIN_115___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DA_GAIN_115___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__XPA_GAIN_115___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___S 19 @@ -142983,9 +150586,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__UPC_GAIN_116___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DA_GAIN_116___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__XPA_GAIN_116___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___S 19 @@ -143013,9 +150616,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__UPC_GAIN_117___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DA_GAIN_117___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__XPA_GAIN_117___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___S 19 @@ -143043,9 +150646,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__UPC_GAIN_118___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DA_GAIN_118___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__XPA_GAIN_118___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___S 19 @@ -143073,9 +150676,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__UPC_GAIN_119___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DA_GAIN_119___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__XPA_GAIN_119___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___S 19 @@ -143103,9 +150706,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__UPC_GAIN_120___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DA_GAIN_120___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__XPA_GAIN_120___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___S 19 @@ -143133,9 +150736,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__UPC_GAIN_121___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DA_GAIN_121___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__XPA_GAIN_121___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___S 19 @@ -143163,9 +150766,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__UPC_GAIN_122___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DA_GAIN_122___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__XPA_GAIN_122___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___S 19 @@ -143193,9 +150796,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__UPC_GAIN_123___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DA_GAIN_123___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__XPA_GAIN_123___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___S 19 @@ -143223,9 +150826,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__UPC_GAIN_124___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DA_GAIN_124___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__XPA_GAIN_124___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___S 19 @@ -143253,9 +150856,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__UPC_GAIN_125___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DA_GAIN_125___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__XPA_GAIN_125___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___S 19 @@ -143283,9 +150886,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__UPC_GAIN_126___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DA_GAIN_126___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__XPA_GAIN_126___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___S 19 @@ -143313,9 +150916,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__UPC_GAIN_127___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DA_GAIN_127___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__XPA_GAIN_127___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___S 19 @@ -143826,7 +151429,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x07800000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___S 23 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___S 20 @@ -143842,7 +151445,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___S 4 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___S 0 -#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___M 0x07FFFFFF #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___S 0 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0 (0x005E80A0) @@ -143946,7 +151549,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x07800000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___S 23 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___S 20 @@ -143962,7 +151565,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___S 4 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___S 0 -#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___M 0x07FFFFFF #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___S 0 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1 (0x005E80B8) @@ -144556,6 +152159,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___M 0xFC000000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0 (0x005E81C0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0__QFEM_EXT_PRODUCT_ID___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0__QFEM_SLAVE_ID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0__QFEM_EXT_PRODUCT_ID___M 0x00000FF0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0__QFEM_EXT_PRODUCT_ID___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0__QFEM_SLAVE_ID___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0__QFEM_SLAVE_ID___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_QFEM_0___S 0 + #define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL (0x005E8400) #define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___POR 0x00000000 @@ -146275,59 +153890,59 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___M 0xFFFFFC00 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___S 10 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT (0x005E8558) -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___POR 0x00BFF234 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___POR 0x0 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___POR 0x005 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___POR 0xF -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___POR 0xF -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___POR 0x4 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___POR 0x4 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___POR 0x3 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___POR 0x2 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___S 30 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___M 0x3FE00000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___S 21 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___M 0x001E0000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___S 17 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___M 0x0001E000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___S 13 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___M 0x00001C00 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___S 10 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___M 0x00000380 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___S 7 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___M 0x00000070 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___S 4 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___M 0x0000000E -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___S 1 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___M 0xFFFFFFFE -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0 (0x005E8558) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0___POR 0x00BFF234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_CCADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_CFBCAL___POR 0x005 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ICQADJ___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_VCMINTADJ___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IR25_IP___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IC25_OP___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_OP_OS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IPTAT25_OP___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_CCADJ___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_CCADJ___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_CFBCAL___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_CFBCAL___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ICQADJ___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ICQADJ___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_VCMINTADJ___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_VCMINTADJ___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IR25_IP___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IR25_IP___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IC25_OP___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IC25_OP___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_OP_OS___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_OP_OS___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0__DPD_TIA_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA0___S 1 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT (0x005E855C) -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___POR 0x2AC01776 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___POR 0x15 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___POR 0x3 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___POR 0x000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___POR 0x17 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___POR 0x7 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___POR 0x3 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___M 0xFE000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___S 25 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___M 0x01C00000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___S 22 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___M 0x003FE000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___S 13 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___M 0x00001F00 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___S 8 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___M 0x000000F0 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___S 4 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___M 0x0000000E -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___S 1 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___M 0xFFFFFFFE -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ (0x005E855C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___POR 0x2AC01776 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_CFBCAL___POR 0x15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_OP_OS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_CIN_CT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IC25_IP___POR 0x17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IC25_OP___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IPTAT25_OP___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_CFBCAL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_CFBCAL___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_OP_OS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_OP_OS___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_CIN_CT___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_CIN_CT___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IC25_IP___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IC25_IP___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IC25_OP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IC25_OP___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___S 1 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA (0x005E8560) #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___RWC QCSR_REG_RW @@ -146336,6 +153951,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_I___POR 0x3 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_Q___POR 0x3 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_FULL_BW_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RMCAP___M 0x80000000 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RMCAP___S 31 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_I___M 0x70000000 @@ -146344,20 +153961,108 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_Q___S 25 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___M 0x01C00000 #define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___S 22 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___M 0xFFC00000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_FULL_BW_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_FULL_BW_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___S 18 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ (0x005E8564) -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___POR 0x8 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___S 31 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___M 0x78000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___S 27 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___M 0xF8000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV (0x005E8564) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV__DPD_BQ_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV__DPD_BQ_VCM_SEL___POR 0x8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV__DPD_BQ_BYPASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV__DPD_BQ_BYPASS___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV__DPD_BQ_VCM_SEL___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV__DPD_BQ_VCM_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_OV___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC (0x005E8580) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_TIA_BW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_BW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC1ADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC2ADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_SELQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BOOST_BQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_TIA_BW___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_TIA_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_BW___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_BW___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC1ADJ___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC1ADJ___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC2ADJ___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC2ADJ___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR1___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR1___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR2___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR2___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_SELQ___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_SELQ___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BOOST_BQ___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BOOST_BQ___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_CH_BW_AC___S 10 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0 (0x005E8584) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CCADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CFBCAL___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ICQADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_VCMINTADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IR25_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IC25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_OP_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IPTAT25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CCADJ___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CCADJ___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CFBCAL___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CFBCAL___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ICQADJ___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ICQADJ___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_VCMINTADJ___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_VCMINTADJ___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IR25_IP___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IR25_IP___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IC25_OP___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IC25_OP___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_OP_OS___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_OP_OS___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_TIA0___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ (0x005E8588) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CFBCAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_OP_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CIN_CT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_IP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IPTAT25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CFBCAL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CFBCAL___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_OP_OS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_OP_OS___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CIN_CT___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CIN_CT___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_IP___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_IP___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_OP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_OP___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_MIDBW_BQ___S 1 #define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG (0x005E8800) #define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___RWC QCSR_REG_RW @@ -151206,13 +158911,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1 (0x005EA084) #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___POR 0x00F80204 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___POR 0x3FF8FE04 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___S 24 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___S 22 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000 @@ -151221,11 +158938,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S 18 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___S 10 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S 5 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S 0 -#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___M 0x00FF03FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___M 0x3FFFFFFF #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___S 0 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2 (0x005EA088) @@ -187752,7 +195475,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x07800000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___S 23 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___S 20 @@ -187768,7 +195491,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___S 4 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___S 0 -#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___M 0x07FFFFFF #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___S 0 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0 (0x005F00A0) @@ -187872,7 +195595,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x07800000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___S 23 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___S 20 @@ -187888,7 +195611,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___S 4 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___S 0 -#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___M 0x07FFFFFF #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___S 0 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1 (0x005F00B8) @@ -188482,6 +196205,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___M 0xFC000000 #define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0 (0x005F01C0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0__QFEM_EXT_PRODUCT_ID___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0__QFEM_SLAVE_ID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0__QFEM_EXT_PRODUCT_ID___M 0x00000FF0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0__QFEM_EXT_PRODUCT_ID___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0__QFEM_SLAVE_ID___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0__QFEM_SLAVE_ID___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_QFEM_0___S 0 + #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG (0x005F1000) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___POR 0x44FE2111 @@ -188534,6 +196269,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___POR 0x60A25480 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_CASCODE_BIAS_CTRL_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x5 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 @@ -188546,6 +196282,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x00 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_CASCODE_BIAS_CTRL_0___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_CASCODE_BIAS_CTRL_0___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000 @@ -188566,13 +196304,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1 (0x005F1014) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___POR 0x60E24480 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_CASCODE_BIAS_CTRL_1___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 @@ -188585,6 +196324,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x00 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_CASCODE_BIAS_CTRL_1___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_CASCODE_BIAS_CTRL_1___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000 @@ -188605,13 +196346,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2 (0x005F1018) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___POR 0x601E030A #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_CASCODE_BIAS_CTRL_2___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 @@ -188624,6 +196366,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x0A #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_CASCODE_BIAS_CTRL_2___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_CASCODE_BIAS_CTRL_2___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000 @@ -188644,13 +196388,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3 (0x005F101C) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___POR 0x60022304 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_CASCODE_BIAS_CTRL_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 @@ -188663,6 +196408,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x04 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_CASCODE_BIAS_CTRL_3___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_CASCODE_BIAS_CTRL_3___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000 @@ -188683,13 +196430,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4 (0x005F1020) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___POR 0x60022309 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_CASCODE_BIAS_CTRL_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 @@ -188702,6 +196450,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x09 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_CASCODE_BIAS_CTRL_4___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_CASCODE_BIAS_CTRL_4___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000 @@ -188722,13 +196472,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5 (0x005F1024) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___POR 0x60022312 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_CASCODE_BIAS_CTRL_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 @@ -188741,6 +196492,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x12 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_CASCODE_BIAS_CTRL_5___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_CASCODE_BIAS_CTRL_5___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000 @@ -188761,13 +196514,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6 (0x005F1028) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___POR 0x4002231C #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_CASCODE_BIAS_CTRL_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 @@ -188780,6 +196534,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x1C #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_CASCODE_BIAS_CTRL_6___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_CASCODE_BIAS_CTRL_6___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000 @@ -188800,13 +196556,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7 (0x005F102C) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___POR 0x00026339 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_CASCODE_BIAS_CTRL_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1 @@ -188819,6 +196576,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x39 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_CASCODE_BIAS_CTRL_7___M 0x1E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_CASCODE_BIAS_CTRL_7___S 25 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___S 21 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000 @@ -188839,7 +196598,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S 7 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___S 0 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___M 0xFFFFFFBF #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___S 0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0 (0x005F1030) @@ -189038,6 +196797,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OVD___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S 30 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000 @@ -189046,8 +196807,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OV___S 27 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___M 0x07E00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___S 21 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OV___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OVD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_CASCODE_BIAS_CTRL_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___S 16 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1 (0x005F1088) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___RWC QCSR_REG_RW @@ -189137,6 +196902,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__DPD_XPA_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S 30 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___M 0x30000000 @@ -189145,8 +196911,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S 27 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S 20 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___M 0xFFF00000 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__DPD_XPA_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__DPD_XPA_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___S 18 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL (0x005F1098) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO @@ -189209,6 +196977,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_LNA_CASCODE_BIAS_CTRL___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___M 0x80000000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___S 31 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___M 0x7E000000 @@ -189217,8 +196986,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___S 19 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___M 0x00070000 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___S 16 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___M 0xFFFF0000 -#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_LNA_CASCODE_BIAS_CTRL___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_LNA_CASCODE_BIAS_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___S 12 #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2 (0x005F10A4) #define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO @@ -190812,192 +198583,528 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_IBIAS_BOOST_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_OPAMP_BOOST_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX0_PD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX1_PD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX1_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX0_CTRL_0___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_CTRL_0___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_CTRL_0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_IBIAS_BOOST_0___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_IBIAS_BOOST_0___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_OPAMP_BOOST_0___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_OPAMP_BOOST_0___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX0_PD_0___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX0_PD_0___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX1_PD_0___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_BIAS_AUX1_PD_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX1_CTRL_0___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX1_CTRL_0___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX0_CTRL_0___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CAS_RDIV_AUX0_CTRL_0___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1 (0x005F1434) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_CTRL_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_IBIAS_BOOST_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_OPAMP_BOOST_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX0_PD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX1_PD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX1_CTRL_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX0_CTRL_1___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_CTRL_1___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_CTRL_1___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_IBIAS_BOOST_1___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_IBIAS_BOOST_1___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_OPAMP_BOOST_1___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_OPAMP_BOOST_1___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX0_PD_1___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX0_PD_1___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX1_PD_1___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_BIAS_AUX1_PD_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX1_CTRL_1___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX1_CTRL_1___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX0_CTRL_1___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CAS_RDIV_AUX0_CTRL_1___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2 (0x005F1438) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_CTRL_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_IBIAS_BOOST_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_OPAMP_BOOST_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX0_PD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX1_PD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX1_CTRL_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX0_CTRL_2___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_CTRL_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_CTRL_2___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_IBIAS_BOOST_2___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_IBIAS_BOOST_2___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_OPAMP_BOOST_2___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_OPAMP_BOOST_2___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX0_PD_2___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX0_PD_2___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX1_PD_2___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_BIAS_AUX1_PD_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX1_CTRL_2___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX1_CTRL_2___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX0_CTRL_2___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CAS_RDIV_AUX0_CTRL_2___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3 (0x005F143C) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_CTRL_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_IBIAS_BOOST_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_OPAMP_BOOST_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX0_PD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX1_PD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX1_CTRL_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX0_CTRL_3___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_CTRL_3___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_CTRL_3___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_IBIAS_BOOST_3___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_IBIAS_BOOST_3___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_OPAMP_BOOST_3___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_OPAMP_BOOST_3___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX0_PD_3___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX0_PD_3___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX1_PD_3___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_BIAS_AUX1_PD_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX1_CTRL_3___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX1_CTRL_3___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX0_CTRL_3___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CAS_RDIV_AUX0_CTRL_3___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4 (0x005F1440) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_CTRL_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_IBIAS_BOOST_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_OPAMP_BOOST_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX0_PD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX1_PD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX1_CTRL_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX0_CTRL_4___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_CTRL_4___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_CTRL_4___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_IBIAS_BOOST_4___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_IBIAS_BOOST_4___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_OPAMP_BOOST_4___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_OPAMP_BOOST_4___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX0_PD_4___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX0_PD_4___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX1_PD_4___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_BIAS_AUX1_PD_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX1_CTRL_4___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX1_CTRL_4___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX0_CTRL_4___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CAS_RDIV_AUX0_CTRL_4___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5 (0x005F1444) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_CTRL_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_IBIAS_BOOST_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_OPAMP_BOOST_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX0_PD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX1_PD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX1_CTRL_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX0_CTRL_5___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_CTRL_5___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_CTRL_5___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_IBIAS_BOOST_5___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_IBIAS_BOOST_5___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_OPAMP_BOOST_5___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_OPAMP_BOOST_5___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX0_PD_5___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX0_PD_5___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX1_PD_5___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_BIAS_AUX1_PD_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX1_CTRL_5___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX1_CTRL_5___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX0_CTRL_5___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CAS_RDIV_AUX0_CTRL_5___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6 (0x005F1448) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_CTRL_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_IBIAS_BOOST_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_OPAMP_BOOST_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX0_PD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX1_PD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX1_CTRL_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX0_CTRL_6___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_CTRL_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_CTRL_6___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_IBIAS_BOOST_6___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_IBIAS_BOOST_6___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_OPAMP_BOOST_6___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_OPAMP_BOOST_6___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX0_PD_6___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX0_PD_6___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX1_PD_6___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_BIAS_AUX1_PD_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX1_CTRL_6___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX1_CTRL_6___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX0_CTRL_6___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CAS_RDIV_AUX0_CTRL_6___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7 (0x005F144C) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___POR 0x60000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_CTRL_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_IBIAS_BOOST_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_OPAMP_BOOST_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX0_PD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX1_PD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX1_CTRL_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX0_CTRL_7___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_CTRL_7___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_CTRL_7___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_IBIAS_BOOST_7___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_IBIAS_BOOST_7___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_OPAMP_BOOST_7___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_OPAMP_BOOST_7___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX0_PD_7___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX0_PD_7___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX1_PD_7___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_BIAS_AUX1_PD_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX1_CTRL_7___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX1_CTRL_7___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX0_CTRL_7___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CAS_RDIV_AUX0_CTRL_7___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8 (0x005F1450) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_CTRL_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_IBIAS_BOOST_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_OPAMP_BOOST_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX0_PD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX1_PD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX1_CTRL_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX0_CTRL_8___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_CTRL_8___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_CTRL_8___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_IBIAS_BOOST_8___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_IBIAS_BOOST_8___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_OPAMP_BOOST_8___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_OPAMP_BOOST_8___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX0_PD_8___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX0_PD_8___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX1_PD_8___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_BIAS_AUX1_PD_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX1_CTRL_8___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX1_CTRL_8___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX0_CTRL_8___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CAS_RDIV_AUX0_CTRL_8___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9 (0x005F1454) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_CTRL_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_IBIAS_BOOST_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_OPAMP_BOOST_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX0_PD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX1_PD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX1_CTRL_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX0_CTRL_9___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_CTRL_9___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_CTRL_9___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_IBIAS_BOOST_9___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_IBIAS_BOOST_9___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_OPAMP_BOOST_9___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_OPAMP_BOOST_9___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX0_PD_9___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX0_PD_9___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX1_PD_9___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_BIAS_AUX1_PD_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX1_CTRL_9___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX1_CTRL_9___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX0_CTRL_9___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CAS_RDIV_AUX0_CTRL_9___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10 (0x005F1458) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_CTRL_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_IBIAS_BOOST_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_OPAMP_BOOST_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX0_PD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX1_PD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX1_CTRL_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX0_CTRL_10___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_CTRL_10___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_CTRL_10___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_IBIAS_BOOST_10___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_IBIAS_BOOST_10___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_OPAMP_BOOST_10___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_OPAMP_BOOST_10___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX0_PD_10___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX0_PD_10___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX1_PD_10___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_BIAS_AUX1_PD_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX1_CTRL_10___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX1_CTRL_10___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX0_CTRL_10___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CAS_RDIV_AUX0_CTRL_10___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11 (0x005F145C) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_CTRL_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_IBIAS_BOOST_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_OPAMP_BOOST_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX0_PD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX1_PD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX1_CTRL_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX0_CTRL_11___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_CTRL_11___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_CTRL_11___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_IBIAS_BOOST_11___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_IBIAS_BOOST_11___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_OPAMP_BOOST_11___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_OPAMP_BOOST_11___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX0_PD_11___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX0_PD_11___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX1_PD_11___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_BIAS_AUX1_PD_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX1_CTRL_11___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX1_CTRL_11___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX0_CTRL_11___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CAS_RDIV_AUX0_CTRL_11___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12 (0x005F1460) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_CTRL_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_IBIAS_BOOST_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_OPAMP_BOOST_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX0_PD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX1_PD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX1_CTRL_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX0_CTRL_12___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_CTRL_12___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_CTRL_12___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_IBIAS_BOOST_12___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_IBIAS_BOOST_12___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_OPAMP_BOOST_12___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_OPAMP_BOOST_12___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX0_PD_12___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX0_PD_12___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX1_PD_12___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_BIAS_AUX1_PD_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX1_CTRL_12___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX1_CTRL_12___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX0_CTRL_12___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CAS_RDIV_AUX0_CTRL_12___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13 (0x005F1464) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_CTRL_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_IBIAS_BOOST_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_OPAMP_BOOST_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX0_PD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX1_PD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX1_CTRL_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX0_CTRL_13___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_CTRL_13___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_CTRL_13___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_IBIAS_BOOST_13___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_IBIAS_BOOST_13___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_OPAMP_BOOST_13___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_OPAMP_BOOST_13___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX0_PD_13___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX0_PD_13___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX1_PD_13___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_BIAS_AUX1_PD_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX1_CTRL_13___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX1_CTRL_13___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX0_CTRL_13___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CAS_RDIV_AUX0_CTRL_13___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14 (0x005F1468) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_CTRL_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_IBIAS_BOOST_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_OPAMP_BOOST_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX0_PD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX1_PD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX1_CTRL_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX0_CTRL_14___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_CTRL_14___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_CTRL_14___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_IBIAS_BOOST_14___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_IBIAS_BOOST_14___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_OPAMP_BOOST_14___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_OPAMP_BOOST_14___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX0_PD_14___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX0_PD_14___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX1_PD_14___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_BIAS_AUX1_PD_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX1_CTRL_14___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX1_CTRL_14___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX0_CTRL_14___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CAS_RDIV_AUX0_CTRL_14___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15 (0x005F146C) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___POR 0x1FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_CTRL_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_IBIAS_BOOST_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_OPAMP_BOOST_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX0_PD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX1_PD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX1_CTRL_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX0_CTRL_15___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___M 0x7FE00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___M 0xFFE00000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_CTRL_15___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_CTRL_15___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_IBIAS_BOOST_15___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_IBIAS_BOOST_15___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_OPAMP_BOOST_15___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_OPAMP_BOOST_15___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX0_PD_15___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX0_PD_15___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX1_PD_15___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_BIAS_AUX1_PD_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX1_CTRL_15___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX1_CTRL_15___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX0_CTRL_15___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CAS_RDIV_AUX0_CTRL_15___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0 (0x005F1470) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___RWC QCSR_REG_RW @@ -191010,6 +199117,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000 @@ -191026,8 +199135,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OV___S 11 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___S 8 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___M 0xFFFFFF00 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OVD___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__PA_CAS_RDIV_AUX0_CTRL_OVD___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1 (0x005F1474) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___RWC QCSR_REG_RW @@ -191040,6 +199153,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OV___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OV___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000 @@ -191056,8 +199171,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OV___S 8 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___M 0x000000C0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___S 6 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OV___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__PA_CAS_RDIV_AUX1_CTRL_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___S 0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4 (0x005F1478) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___RWC QCSR_REG_RW @@ -191140,14 +199259,32 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_RDIV_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_RDIV_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_IBIAS_BOOST_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_OPAMP_BOOST_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_BIAS_AUX0_PD_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_BIAS_AUX1_PD_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___S 30 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___M 0x20000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___S 29 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___M 0x1FF80000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___S 19 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___M 0xFFF80000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_RDIV_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_RDIV_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_RDIV_CTRL_OVD___M 0x0003E000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_RDIV_CTRL_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_IBIAS_BOOST_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_IBIAS_BOOST_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_OPAMP_BOOST_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_OPAMP_BOOST_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_BIAS_AUX0_PD_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_BIAS_AUX0_PD_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_BIAS_AUX1_PD_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CAS_BIAS_AUX1_PD_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___S 5 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0 (0x005F1484) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___RWC QCSR_REG_RW @@ -191222,6 +199359,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_SW_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_FC_EN_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S 30 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000 @@ -191248,8 +199386,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___S 6 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___M 0x00000030 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___S 4 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___M 0xFFF3FFF0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_FC_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_FC_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___M 0xFFF3FFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___S 2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0 (0x005F1490) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO @@ -191305,13 +199445,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3 (0x005F1498) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_CAS_RDIV_AUX0_CTRL___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_CAS_RDIV_AUX0_CTRL___M 0x0000F800 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_CAS_RDIV_AUX0_CTRL___S 11 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000007C0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S 6 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000003E #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S 1 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___M 0x000007FE +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___M 0x0000FFFE #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___S 1 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4 (0x005F149C) @@ -191322,6 +199465,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_IBIAS_BOOST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_OPAMP_BOOST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0_PD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1_PD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_RDIV_AUX1_CTRL___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S 29 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000 @@ -191332,8 +199480,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S 19 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S 9 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___M 0xFFFFFE00 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_IBIAS_BOOST___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_IBIAS_BOOST___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_OPAMP_BOOST___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_OPAMP_BOOST___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0_PD___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0_PD___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1_PD___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1_PD___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_RDIV_AUX1_CTRL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_RDIV_AUX1_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___S 0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5 (0x005F14A0) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO @@ -191344,6 +199502,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CAS_RDIV_CTRL___POR 0x00 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S 22 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___M 0x00300000 @@ -191356,8 +199515,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___S 16 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___M 0x0000FFC0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___S 6 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___M 0xFFFFFFC0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CAS_RDIV_CTRL___M 0x0000003E +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CAS_RDIV_CTRL___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___S 1 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0 (0x005F14A4) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO @@ -191369,6 +199530,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_FC_EN___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___S 30 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___M 0x20000000 @@ -191383,8 +199545,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___S 25 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___M 0x01000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___S 24 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___M 0x7F000000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_FC_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_FC_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___M 0x7F800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___S 23 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0 (0x005F14C0) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___RWC QCSR_REG_RW @@ -191543,9 +199707,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___POR 0x2 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ISLOPE___POR 0x5 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___POR 0x0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX1_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_EN___POR 0x0 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___M 0x80000000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___S 31 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___M 0x70000000 @@ -191554,14 +199720,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ISLOPE___S 25 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___M 0x01C00000 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___S 22 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___M 0x00200000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___S 21 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___M 0x00100000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___S 20 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___M 0x00080000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___S 19 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___M 0xFFF80000 -#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_EN___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_EN___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX1_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX1_EN___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX0_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_RDIV_AUX0_EN___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_CTRL___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_LP_GM_DS_RDIV_EN___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___S 14 #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY (0x005F14E0) #define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW @@ -191766,13 +199936,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1 (0x005F2084) #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___POR 0x00F80204 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___POR 0x3FF8FE04 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___S 24 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___S 22 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000 @@ -191781,11 +199963,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S 18 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___S 10 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S 5 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S 0 -#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___M 0x00FF03FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___M 0x3FFFFFFF #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___S 0 #define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2 (0x005F2088) @@ -221082,9 +229270,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__UPC_GAIN_0___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DA_GAIN_0___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__XPA_GAIN_0___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___S 19 @@ -221112,9 +229300,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__UPC_GAIN_1___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DA_GAIN_1___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__XPA_GAIN_1___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___S 19 @@ -221142,9 +229330,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__UPC_GAIN_2___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DA_GAIN_2___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__XPA_GAIN_2___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___S 19 @@ -221172,9 +229360,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__UPC_GAIN_3___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DA_GAIN_3___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__XPA_GAIN_3___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___S 19 @@ -221202,9 +229390,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__UPC_GAIN_4___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DA_GAIN_4___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__XPA_GAIN_4___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___S 19 @@ -221232,9 +229420,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__UPC_GAIN_5___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DA_GAIN_5___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__XPA_GAIN_5___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___S 19 @@ -221262,9 +229450,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__UPC_GAIN_6___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DA_GAIN_6___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__XPA_GAIN_6___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___S 19 @@ -221292,9 +229480,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__UPC_GAIN_7___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DA_GAIN_7___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__XPA_GAIN_7___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___S 19 @@ -221322,9 +229510,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__UPC_GAIN_8___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DA_GAIN_8___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__XPA_GAIN_8___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___S 19 @@ -221352,9 +229540,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__UPC_GAIN_9___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DA_GAIN_9___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__XPA_GAIN_9___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___S 19 @@ -221382,9 +229570,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__UPC_GAIN_10___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DA_GAIN_10___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__XPA_GAIN_10___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___S 19 @@ -221412,9 +229600,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__UPC_GAIN_11___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DA_GAIN_11___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__XPA_GAIN_11___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___S 19 @@ -221442,9 +229630,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__UPC_GAIN_12___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DA_GAIN_12___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__XPA_GAIN_12___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___S 19 @@ -221472,9 +229660,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__UPC_GAIN_13___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DA_GAIN_13___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__XPA_GAIN_13___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___S 19 @@ -221502,9 +229690,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__UPC_GAIN_14___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DA_GAIN_14___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__XPA_GAIN_14___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___S 19 @@ -221532,9 +229720,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__UPC_GAIN_15___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DA_GAIN_15___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__XPA_GAIN_15___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___S 19 @@ -221562,9 +229750,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__UPC_GAIN_16___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DA_GAIN_16___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__XPA_GAIN_16___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___S 19 @@ -221592,9 +229780,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__UPC_GAIN_17___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DA_GAIN_17___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__XPA_GAIN_17___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___S 19 @@ -221622,9 +229810,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__UPC_GAIN_18___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DA_GAIN_18___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__XPA_GAIN_18___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___S 19 @@ -221652,9 +229840,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__UPC_GAIN_19___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DA_GAIN_19___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__XPA_GAIN_19___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___S 19 @@ -221682,9 +229870,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__UPC_GAIN_20___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DA_GAIN_20___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__XPA_GAIN_20___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___S 19 @@ -221712,9 +229900,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__UPC_GAIN_21___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DA_GAIN_21___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__XPA_GAIN_21___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___S 19 @@ -221742,9 +229930,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__UPC_GAIN_22___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DA_GAIN_22___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__XPA_GAIN_22___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___S 19 @@ -221772,9 +229960,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__UPC_GAIN_23___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DA_GAIN_23___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__XPA_GAIN_23___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___S 19 @@ -221802,9 +229990,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__UPC_GAIN_24___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DA_GAIN_24___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__XPA_GAIN_24___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___S 19 @@ -221832,9 +230020,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__UPC_GAIN_25___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DA_GAIN_25___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__XPA_GAIN_25___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___S 19 @@ -221862,9 +230050,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__UPC_GAIN_26___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DA_GAIN_26___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__XPA_GAIN_26___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___S 19 @@ -221892,9 +230080,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__UPC_GAIN_27___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DA_GAIN_27___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__XPA_GAIN_27___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___S 19 @@ -221922,9 +230110,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__UPC_GAIN_28___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DA_GAIN_28___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__XPA_GAIN_28___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___S 19 @@ -221952,9 +230140,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__UPC_GAIN_29___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DA_GAIN_29___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__XPA_GAIN_29___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___S 19 @@ -221982,9 +230170,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__UPC_GAIN_30___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DA_GAIN_30___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__XPA_GAIN_30___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___S 19 @@ -222012,9 +230200,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__UPC_GAIN_31___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DA_GAIN_31___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__XPA_GAIN_31___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___S 19 @@ -222042,9 +230230,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__UPC_GAIN_32___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DA_GAIN_32___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__XPA_GAIN_32___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___S 19 @@ -222072,9 +230260,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__UPC_GAIN_33___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DA_GAIN_33___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__XPA_GAIN_33___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___S 19 @@ -222102,9 +230290,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__UPC_GAIN_34___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DA_GAIN_34___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__XPA_GAIN_34___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___S 19 @@ -222132,9 +230320,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__UPC_GAIN_35___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DA_GAIN_35___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__XPA_GAIN_35___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___S 19 @@ -222162,9 +230350,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__UPC_GAIN_36___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DA_GAIN_36___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__XPA_GAIN_36___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___S 19 @@ -222192,9 +230380,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__UPC_GAIN_37___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DA_GAIN_37___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__XPA_GAIN_37___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___S 19 @@ -222222,9 +230410,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__UPC_GAIN_38___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DA_GAIN_38___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__XPA_GAIN_38___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___S 19 @@ -222252,9 +230440,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__UPC_GAIN_39___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DA_GAIN_39___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__XPA_GAIN_39___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___S 19 @@ -222282,9 +230470,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__UPC_GAIN_40___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DA_GAIN_40___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__XPA_GAIN_40___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___S 19 @@ -222312,9 +230500,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__UPC_GAIN_41___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DA_GAIN_41___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__XPA_GAIN_41___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___S 19 @@ -222342,9 +230530,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__UPC_GAIN_42___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DA_GAIN_42___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__XPA_GAIN_42___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___S 19 @@ -222372,9 +230560,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__UPC_GAIN_43___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DA_GAIN_43___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__XPA_GAIN_43___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___S 19 @@ -222402,9 +230590,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__UPC_GAIN_44___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DA_GAIN_44___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__XPA_GAIN_44___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___S 19 @@ -222432,9 +230620,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__UPC_GAIN_45___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DA_GAIN_45___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__XPA_GAIN_45___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___S 19 @@ -222462,9 +230650,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__UPC_GAIN_46___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DA_GAIN_46___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__XPA_GAIN_46___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___S 19 @@ -222492,9 +230680,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__UPC_GAIN_47___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DA_GAIN_47___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__XPA_GAIN_47___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___S 19 @@ -222522,9 +230710,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__UPC_GAIN_48___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DA_GAIN_48___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__XPA_GAIN_48___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___S 19 @@ -222552,9 +230740,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__UPC_GAIN_49___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DA_GAIN_49___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__XPA_GAIN_49___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___S 19 @@ -222582,9 +230770,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__UPC_GAIN_50___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DA_GAIN_50___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__XPA_GAIN_50___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___S 19 @@ -222612,9 +230800,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__UPC_GAIN_51___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DA_GAIN_51___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__XPA_GAIN_51___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___S 19 @@ -222642,9 +230830,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__UPC_GAIN_52___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DA_GAIN_52___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__XPA_GAIN_52___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___S 19 @@ -222672,9 +230860,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__UPC_GAIN_53___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DA_GAIN_53___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__XPA_GAIN_53___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___S 19 @@ -222702,9 +230890,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__UPC_GAIN_54___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DA_GAIN_54___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__XPA_GAIN_54___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___S 19 @@ -222732,9 +230920,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__UPC_GAIN_55___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DA_GAIN_55___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__XPA_GAIN_55___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___S 19 @@ -222762,9 +230950,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__UPC_GAIN_56___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DA_GAIN_56___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__XPA_GAIN_56___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___S 19 @@ -222792,9 +230980,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__UPC_GAIN_57___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DA_GAIN_57___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__XPA_GAIN_57___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___S 19 @@ -222822,9 +231010,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__UPC_GAIN_58___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DA_GAIN_58___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__XPA_GAIN_58___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___S 19 @@ -222852,9 +231040,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__UPC_GAIN_59___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DA_GAIN_59___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__XPA_GAIN_59___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___S 19 @@ -222882,9 +231070,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__UPC_GAIN_60___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DA_GAIN_60___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__XPA_GAIN_60___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___S 19 @@ -222912,9 +231100,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__UPC_GAIN_61___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DA_GAIN_61___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__XPA_GAIN_61___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___S 19 @@ -222942,9 +231130,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__UPC_GAIN_62___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DA_GAIN_62___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__XPA_GAIN_62___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___S 19 @@ -222972,9 +231160,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__UPC_GAIN_63___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DA_GAIN_63___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__XPA_GAIN_63___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___S 19 @@ -223002,9 +231190,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__UPC_GAIN_64___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DA_GAIN_64___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__XPA_GAIN_64___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___S 19 @@ -223032,9 +231220,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__UPC_GAIN_65___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DA_GAIN_65___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__XPA_GAIN_65___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___S 19 @@ -223062,9 +231250,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__UPC_GAIN_66___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DA_GAIN_66___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__XPA_GAIN_66___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___S 19 @@ -223092,9 +231280,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__UPC_GAIN_67___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DA_GAIN_67___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__XPA_GAIN_67___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___S 19 @@ -223122,9 +231310,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__UPC_GAIN_68___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DA_GAIN_68___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__XPA_GAIN_68___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___S 19 @@ -223152,9 +231340,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__UPC_GAIN_69___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DA_GAIN_69___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__XPA_GAIN_69___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___S 19 @@ -223182,9 +231370,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__UPC_GAIN_70___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DA_GAIN_70___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__XPA_GAIN_70___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___S 19 @@ -223212,9 +231400,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__UPC_GAIN_71___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DA_GAIN_71___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__XPA_GAIN_71___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___S 19 @@ -223242,9 +231430,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__UPC_GAIN_72___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DA_GAIN_72___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__XPA_GAIN_72___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___S 19 @@ -223272,9 +231460,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__UPC_GAIN_73___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DA_GAIN_73___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__XPA_GAIN_73___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___S 19 @@ -223302,9 +231490,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__UPC_GAIN_74___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DA_GAIN_74___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__XPA_GAIN_74___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___S 19 @@ -223332,9 +231520,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__UPC_GAIN_75___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DA_GAIN_75___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__XPA_GAIN_75___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___S 19 @@ -223362,9 +231550,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__UPC_GAIN_76___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DA_GAIN_76___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__XPA_GAIN_76___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___S 19 @@ -223392,9 +231580,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__UPC_GAIN_77___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DA_GAIN_77___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__XPA_GAIN_77___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___S 19 @@ -223422,9 +231610,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__UPC_GAIN_78___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DA_GAIN_78___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__XPA_GAIN_78___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___S 19 @@ -223452,9 +231640,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__UPC_GAIN_79___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DA_GAIN_79___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__XPA_GAIN_79___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___S 19 @@ -223482,9 +231670,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__UPC_GAIN_80___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DA_GAIN_80___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__XPA_GAIN_80___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___S 19 @@ -223512,9 +231700,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__UPC_GAIN_81___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DA_GAIN_81___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__XPA_GAIN_81___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___S 19 @@ -223542,9 +231730,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__UPC_GAIN_82___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DA_GAIN_82___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__XPA_GAIN_82___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___S 19 @@ -223572,9 +231760,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__UPC_GAIN_83___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DA_GAIN_83___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__XPA_GAIN_83___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___S 19 @@ -223602,9 +231790,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__UPC_GAIN_84___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DA_GAIN_84___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__XPA_GAIN_84___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___S 19 @@ -223632,9 +231820,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__UPC_GAIN_85___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DA_GAIN_85___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__XPA_GAIN_85___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___S 19 @@ -223662,9 +231850,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__UPC_GAIN_86___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DA_GAIN_86___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__XPA_GAIN_86___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___S 19 @@ -223692,9 +231880,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__UPC_GAIN_87___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DA_GAIN_87___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__XPA_GAIN_87___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___S 19 @@ -223722,9 +231910,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__UPC_GAIN_88___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DA_GAIN_88___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__XPA_GAIN_88___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___S 19 @@ -223752,9 +231940,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__UPC_GAIN_89___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DA_GAIN_89___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__XPA_GAIN_89___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___S 19 @@ -223782,9 +231970,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__UPC_GAIN_90___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DA_GAIN_90___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__XPA_GAIN_90___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___S 19 @@ -223812,9 +232000,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__UPC_GAIN_91___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DA_GAIN_91___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__XPA_GAIN_91___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___S 19 @@ -223842,9 +232030,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__UPC_GAIN_92___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DA_GAIN_92___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__XPA_GAIN_92___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___S 19 @@ -223872,9 +232060,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__UPC_GAIN_93___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DA_GAIN_93___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__XPA_GAIN_93___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___S 19 @@ -223902,9 +232090,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__UPC_GAIN_94___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DA_GAIN_94___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__XPA_GAIN_94___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___S 19 @@ -223932,9 +232120,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__UPC_GAIN_95___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DA_GAIN_95___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__XPA_GAIN_95___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___S 19 @@ -223962,9 +232150,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__UPC_GAIN_96___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DA_GAIN_96___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__XPA_GAIN_96___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___S 19 @@ -223992,9 +232180,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__UPC_GAIN_97___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DA_GAIN_97___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__XPA_GAIN_97___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___S 19 @@ -224022,9 +232210,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__UPC_GAIN_98___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DA_GAIN_98___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__XPA_GAIN_98___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___S 19 @@ -224052,9 +232240,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__UPC_GAIN_99___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DA_GAIN_99___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__XPA_GAIN_99___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___S 19 @@ -224082,9 +232270,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__UPC_GAIN_100___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DA_GAIN_100___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__XPA_GAIN_100___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___S 19 @@ -224112,9 +232300,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__UPC_GAIN_101___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DA_GAIN_101___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__XPA_GAIN_101___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___S 19 @@ -224142,9 +232330,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__UPC_GAIN_102___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DA_GAIN_102___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__XPA_GAIN_102___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___S 19 @@ -224172,9 +232360,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__UPC_GAIN_103___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DA_GAIN_103___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__XPA_GAIN_103___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___S 19 @@ -224202,9 +232390,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__UPC_GAIN_104___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DA_GAIN_104___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__XPA_GAIN_104___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___S 19 @@ -224232,9 +232420,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__UPC_GAIN_105___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DA_GAIN_105___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__XPA_GAIN_105___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___S 19 @@ -224262,9 +232450,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__UPC_GAIN_106___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DA_GAIN_106___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__XPA_GAIN_106___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___S 19 @@ -224292,9 +232480,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__UPC_GAIN_107___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DA_GAIN_107___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__XPA_GAIN_107___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___S 19 @@ -224322,9 +232510,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__UPC_GAIN_108___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DA_GAIN_108___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__XPA_GAIN_108___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___S 19 @@ -224352,9 +232540,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__UPC_GAIN_109___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DA_GAIN_109___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__XPA_GAIN_109___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___S 19 @@ -224382,9 +232570,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__UPC_GAIN_110___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DA_GAIN_110___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__XPA_GAIN_110___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___S 19 @@ -224412,9 +232600,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__UPC_GAIN_111___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DA_GAIN_111___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__XPA_GAIN_111___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___S 19 @@ -224442,9 +232630,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__UPC_GAIN_112___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DA_GAIN_112___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__XPA_GAIN_112___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___S 19 @@ -224472,9 +232660,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__UPC_GAIN_113___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DA_GAIN_113___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__XPA_GAIN_113___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___S 19 @@ -224502,9 +232690,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__UPC_GAIN_114___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DA_GAIN_114___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__XPA_GAIN_114___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___S 19 @@ -224532,9 +232720,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__UPC_GAIN_115___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DA_GAIN_115___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__XPA_GAIN_115___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___S 19 @@ -224562,9 +232750,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__UPC_GAIN_116___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DA_GAIN_116___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__XPA_GAIN_116___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___S 19 @@ -224592,9 +232780,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__UPC_GAIN_117___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DA_GAIN_117___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__XPA_GAIN_117___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___S 19 @@ -224622,9 +232810,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__UPC_GAIN_118___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DA_GAIN_118___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__XPA_GAIN_118___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___S 19 @@ -224652,9 +232840,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__UPC_GAIN_119___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DA_GAIN_119___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__XPA_GAIN_119___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___S 19 @@ -224682,9 +232870,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__UPC_GAIN_120___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DA_GAIN_120___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__XPA_GAIN_120___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___S 19 @@ -224712,9 +232900,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__UPC_GAIN_121___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DA_GAIN_121___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__XPA_GAIN_121___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___S 19 @@ -224742,9 +232930,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__UPC_GAIN_122___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DA_GAIN_122___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__XPA_GAIN_122___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___S 19 @@ -224772,9 +232960,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__UPC_GAIN_123___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DA_GAIN_123___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__XPA_GAIN_123___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___S 19 @@ -224802,9 +232990,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__UPC_GAIN_124___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DA_GAIN_124___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__XPA_GAIN_124___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___S 19 @@ -224832,9 +233020,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__UPC_GAIN_125___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DA_GAIN_125___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__XPA_GAIN_125___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___S 19 @@ -224862,9 +233050,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__UPC_GAIN_126___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DA_GAIN_126___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__XPA_GAIN_126___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___S 19 @@ -224892,9 +233080,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__UPC_GAIN_127___POR 0x0 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DA_GAIN_127___POR 0x00 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__XPA_GAIN_127___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___M 0x03800000 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___S 23 -#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___S 22 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___M 0x00300000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___S 20 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000 #define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___S 19 @@ -225405,7 +233593,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x07800000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___S 23 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___S 20 @@ -225421,7 +233609,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___S 4 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___S 0 -#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___M 0x07FFFFFF #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___S 0 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0 (0x005F80A0) @@ -225525,7 +233713,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0 -#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x07800000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___S 23 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___S 20 @@ -225541,7 +233729,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___S 4 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___S 0 -#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___M 0x07FFFFFF #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___S 0 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1 (0x005F80B8) @@ -226135,6 +234323,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___M 0xFC000000 #define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0 (0x005F81C0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0__QFEM_EXT_PRODUCT_ID___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0__QFEM_SLAVE_ID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0__QFEM_EXT_PRODUCT_ID___M 0x00000FF0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0__QFEM_EXT_PRODUCT_ID___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0__QFEM_SLAVE_ID___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0__QFEM_SLAVE_ID___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_QFEM_0___S 0 + #define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL (0x005F8400) #define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___RWC QCSR_REG_RW #define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___POR 0x00000000 @@ -227854,59 +236054,59 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___M 0xFFFFFC00 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___S 10 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT (0x005F8558) -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___POR 0x00BFF234 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___POR 0x0 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___POR 0x005 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___POR 0xF -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___POR 0xF -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___POR 0x4 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___POR 0x4 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___POR 0x3 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___POR 0x2 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___M 0xC0000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___S 30 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___M 0x3FE00000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___S 21 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___M 0x001E0000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___S 17 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___M 0x0001E000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___S 13 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___M 0x00001C00 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___S 10 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___M 0x00000380 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___S 7 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___M 0x00000070 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___S 4 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___M 0x0000000E -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___S 1 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___M 0xFFFFFFFE -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0 (0x005F8558) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0___POR 0x00BFF234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_CCADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_CFBCAL___POR 0x005 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ICQADJ___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_VCMINTADJ___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IR25_IP___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IC25_OP___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_OP_OS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IPTAT25_OP___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_CCADJ___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_CCADJ___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_CFBCAL___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_CFBCAL___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ICQADJ___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ICQADJ___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_VCMINTADJ___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_VCMINTADJ___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IR25_IP___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IR25_IP___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IC25_OP___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IC25_OP___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_OP_OS___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_OP_OS___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0__DPD_TIA_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA0___S 1 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT (0x005F855C) -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___POR 0x2AC01776 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___POR 0x15 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___POR 0x3 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___POR 0x000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___POR 0x17 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___POR 0x7 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___POR 0x3 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___M 0xFE000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___S 25 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___M 0x01C00000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___S 22 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___M 0x003FE000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___S 13 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___M 0x00001F00 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___S 8 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___M 0x000000F0 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___S 4 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___M 0x0000000E -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___S 1 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___M 0xFFFFFFFE -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ (0x005F855C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___POR 0x2AC01776 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_CFBCAL___POR 0x15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_OP_OS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_CIN_CT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IC25_IP___POR 0x17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IC25_OP___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IPTAT25_OP___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_CFBCAL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_CFBCAL___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_OP_OS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_OP_OS___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_CIN_CT___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_CIN_CT___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IC25_IP___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IC25_IP___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IC25_OP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IC25_OP___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___S 1 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA (0x005F8560) #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___RWC QCSR_REG_RW @@ -227915,6 +236115,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_I___POR 0x3 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_Q___POR 0x3 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_FULL_BW_OVS___POR 0x0 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RMCAP___M 0x80000000 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RMCAP___S 31 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_I___M 0x70000000 @@ -227923,20 +236125,108 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_Q___S 25 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___M 0x01C00000 #define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___S 22 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___M 0xFFC00000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_FULL_BW_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_FULL_BW_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___S 18 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ (0x005F8564) -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___POR 0x40000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___POR 0x0 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___POR 0x8 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___M 0x80000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___S 31 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___M 0x78000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___S 27 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___M 0xF8000000 -#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV (0x005F8564) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV__DPD_BQ_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV__DPD_BQ_VCM_SEL___POR 0x8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV__DPD_BQ_BYPASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV__DPD_BQ_BYPASS___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV__DPD_BQ_VCM_SEL___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV__DPD_BQ_VCM_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_OV___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC (0x005F8580) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_TIA_BW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_BW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC1ADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC2ADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_SELQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BOOST_BQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_TIA_BW___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_TIA_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_BW___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_BW___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC1ADJ___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC1ADJ___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC2ADJ___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_CC2ADJ___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR1___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR1___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR2___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_ZR2___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_SELQ___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BQ_SELQ___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BOOST_BQ___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC__DPD_MIDBW_BOOST_BQ___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_CH_BW_AC___S 10 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0 (0x005F8584) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CCADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CFBCAL___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ICQADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_VCMINTADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IR25_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IC25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_OP_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IPTAT25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CCADJ___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CCADJ___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CFBCAL___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_CFBCAL___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ICQADJ___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ICQADJ___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_VCMINTADJ___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_VCMINTADJ___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IR25_IP___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IR25_IP___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IC25_OP___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IC25_OP___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_OP_OS___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_OP_OS___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0__DPD_MIDBW_TIA_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_TIA0___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ (0x005F8588) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CFBCAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_OP_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CIN_CT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_IP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IPTAT25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CFBCAL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CFBCAL___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_OP_OS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_OP_OS___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CIN_CT___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_CIN_CT___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_IP___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_IP___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_OP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IC25_OP___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ__DPD_MIDBW_BQ_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_MIDBW_BQ___S 1 #define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG (0x005F8800) #define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___RWC QCSR_REG_RW @@ -232785,13 +241075,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1 (0x005FA084) #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___RWC QCSR_REG_RW -#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___POR 0x00F80204 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___POR 0x3FF8FE04 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___POR 0x3 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_XPA___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_IS___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG_IPA_PO___S 24 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___S 22 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000 @@ -232800,11 +241102,17 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S 18 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_XPA___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_IS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG_IPA_PO___S 10 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S 5 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S 0 -#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___M 0x00FF03FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___M 0x3FFFFFFF #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___S 0 #define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2 (0x005FA088) @@ -277780,10 +286088,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR (0x00A30094) #define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO #define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___POR 0x00000000 -#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___POR 0x000 -#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___M 0x00000FFF +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___POR 0x00000 +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___M 0x0001FFFF #define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___S 0 -#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___M 0x00000FFF +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___M 0x0001FFFF #define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___S 0 #define UMAC_TRACER_R0_INT_CTRL (0x00A30098) @@ -278502,8 +286810,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_WBM_R0_MISC_CONTROL (0x00A34038) #define UMAC_WBM_R0_MISC_CONTROL___RWC QCSR_REG_RW -#define UMAC_WBM_R0_MISC_CONTROL___POR 0x000000C0 -#define UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___POR 0x00000030 +#define UMAC_WBM_R0_MISC_CONTROL___POR 0x000001C0 +#define UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___POR 0x00000070 #define UMAC_WBM_R0_MISC_CONTROL__GXI_WRITE_STRUCT_SWAP___POR 0x0 #define UMAC_WBM_R0_MISC_CONTROL__GXI_READ_STRUCT_SWAP___POR 0x0 #define UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___M 0xFFFFFFFC @@ -288426,16 +296734,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R0_CACHE_CTL_CONFIG_SET (0x00A386AC) #define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___RWC QCSR_REG_RW -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___POR 0x01F808FF -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___POR 0xFC -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___POR 0x04 -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___POR 0x0FF -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___M 0x01FE0000 -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___S 17 -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___M 0x0001FE00 -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___S 9 -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___M 0x000001FF -#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___S 0 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___POR 0x00000000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___POR 0x0000000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___M 0x01FFFFFF +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___S 0 #define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___M 0x01FFFFFF #define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___S 0 @@ -288703,7 +297005,73 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___M 0x00000001 #define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___S 0 -#define UMAC_REO_R1_END_OF_TEST_CHECK (0x00A3A040) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1 (0x00A3A040) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__BACKUP___POR 0x00 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_WITHOUT_INVALIDATE___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_ENTIRE_CACHE___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_REQ___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__BACKUP___M 0x000007F8 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__BACKUP___S 3 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_WITHOUT_INVALIDATE___M 0x00000004 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_WITHOUT_INVALIDATE___S 2 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_ENTIRE_CACHE___M 0x00000002 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_ENTIRE_CACHE___S 1 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_REQ___M 0x00000001 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_REQ___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1___M 0x000007FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2 (0x00A3A044) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2__FLUSH_ADDR_31_0___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2__FLUSH_ADDR_31_0___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2__FLUSH_ADDR_31_0___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3 (0x00A3A048) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3__FLUSH_ADDR_39_32___POR 0x00 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3__FLUSH_ADDR_39_32___M 0x000000FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3__FLUSH_ADDR_39_32___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3___M 0x000000FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS (0x00A3A04C) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS___POR 0x00000001 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__BACKUP___POR 0x00 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_COUNT___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HW_IF_BUSY___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_ERROR___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_CLIENT_ID___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_DESC_TYPE___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HIT___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_DONE___POR 0x1 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__BACKUP___M 0x3FC00000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__BACKUP___S 22 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_COUNT___M 0x003FF000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_COUNT___S 12 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HW_IF_BUSY___M 0x00000800 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HW_IF_BUSY___S 11 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_ERROR___M 0x00000600 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_ERROR___S 9 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_CLIENT_ID___M 0x000001E0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_CLIENT_ID___S 5 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_DESC_TYPE___M 0x0000001C +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_DESC_TYPE___S 2 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HIT___M 0x00000002 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HIT___S 1 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_DONE___M 0x00000001 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_DONE___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS___M 0x3FFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS___S 0 + +#define UMAC_REO_R1_END_OF_TEST_CHECK (0x00A3A050) #define UMAC_REO_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW #define UMAC_REO_R1_END_OF_TEST_CHECK___POR 0x00000000 #define UMAC_REO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 @@ -288712,7 +297080,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_END_OF_TEST_CHECK___M 0x00000001 #define UMAC_REO_R1_END_OF_TEST_CHECK___S 0 -#define UMAC_REO_R1_SM_ALL_IDLE (0x00A3A044) +#define UMAC_REO_R1_SM_ALL_IDLE (0x00A3A054) #define UMAC_REO_R1_SM_ALL_IDLE___RWC QCSR_REG_RO #define UMAC_REO_R1_SM_ALL_IDLE___POR 0x00000001 #define UMAC_REO_R1_SM_ALL_IDLE__REO_ENTRANCE_RINGS_NOT_EMPTY___POR 0x0 @@ -288727,7 +297095,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_SM_ALL_IDLE___M 0x00000007 #define UMAC_REO_R1_SM_ALL_IDLE___S 0 -#define UMAC_REO_R1_TESTBUS_CTRL (0x00A3A048) +#define UMAC_REO_R1_TESTBUS_CTRL (0x00A3A058) #define UMAC_REO_R1_TESTBUS_CTRL___RWC QCSR_REG_RW #define UMAC_REO_R1_TESTBUS_CTRL___POR 0x00000000 #define UMAC_REO_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00 @@ -288736,7 +297104,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_TESTBUS_CTRL___M 0x0000007F #define UMAC_REO_R1_TESTBUS_CTRL___S 0 -#define UMAC_REO_R1_TESTBUS_LOWER (0x00A3A04C) +#define UMAC_REO_R1_TESTBUS_LOWER (0x00A3A05C) #define UMAC_REO_R1_TESTBUS_LOWER___RWC QCSR_REG_RO #define UMAC_REO_R1_TESTBUS_LOWER___POR 0x00000000 #define UMAC_REO_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 @@ -288745,7 +297113,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_TESTBUS_LOWER___M 0xFFFFFFFF #define UMAC_REO_R1_TESTBUS_LOWER___S 0 -#define UMAC_REO_R1_TESTBUS_HIGHER (0x00A3A050) +#define UMAC_REO_R1_TESTBUS_HIGHER (0x00A3A060) #define UMAC_REO_R1_TESTBUS_HIGHER___RWC QCSR_REG_RO #define UMAC_REO_R1_TESTBUS_HIGHER___POR 0x00000000 #define UMAC_REO_R1_TESTBUS_HIGHER__VALUE___POR 0x00 @@ -288754,7 +297122,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_TESTBUS_HIGHER___M 0x000000FF #define UMAC_REO_R1_TESTBUS_HIGHER___S 0 -#define UMAC_REO_R1_SM_STATES_IX_0 (0x00A3A054) +#define UMAC_REO_R1_SM_STATES_IX_0 (0x00A3A064) #define UMAC_REO_R1_SM_STATES_IX_0___RWC QCSR_REG_RO #define UMAC_REO_R1_SM_STATES_IX_0___POR 0x00000000 #define UMAC_REO_R1_SM_STATES_IX_0__SM_STATE___POR 0x00000000 @@ -288763,7 +297131,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_SM_STATES_IX_0___M 0xFFFFFFFF #define UMAC_REO_R1_SM_STATES_IX_0___S 0 -#define UMAC_REO_R1_SM_STATES_IX_1 (0x00A3A058) +#define UMAC_REO_R1_SM_STATES_IX_1 (0x00A3A068) #define UMAC_REO_R1_SM_STATES_IX_1___RWC QCSR_REG_RO #define UMAC_REO_R1_SM_STATES_IX_1___POR 0x00000000 #define UMAC_REO_R1_SM_STATES_IX_1__SM_STATE___POR 0x00000000 @@ -288772,7 +297140,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_SM_STATES_IX_1___M 0xFFFFFFFF #define UMAC_REO_R1_SM_STATES_IX_1___S 0 -#define UMAC_REO_R1_SM_STATES_IX_2 (0x00A3A05C) +#define UMAC_REO_R1_SM_STATES_IX_2 (0x00A3A06C) #define UMAC_REO_R1_SM_STATES_IX_2___RWC QCSR_REG_RO #define UMAC_REO_R1_SM_STATES_IX_2___POR 0x00000000 #define UMAC_REO_R1_SM_STATES_IX_2__SM_STATE___POR 0x00000000 @@ -288781,7 +297149,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_SM_STATES_IX_2___M 0xFFFFFFFF #define UMAC_REO_R1_SM_STATES_IX_2___S 0 -#define UMAC_REO_R1_SM_STATES_IX_3 (0x00A3A060) +#define UMAC_REO_R1_SM_STATES_IX_3 (0x00A3A070) #define UMAC_REO_R1_SM_STATES_IX_3___RWC QCSR_REG_RO #define UMAC_REO_R1_SM_STATES_IX_3___POR 0x00000000 #define UMAC_REO_R1_SM_STATES_IX_3__SM_STATE___POR 0x00000000 @@ -288790,7 +297158,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_SM_STATES_IX_3___M 0xFFFFFFFF #define UMAC_REO_R1_SM_STATES_IX_3___S 0 -#define UMAC_REO_R1_SM_STATES_IX_4 (0x00A3A064) +#define UMAC_REO_R1_SM_STATES_IX_4 (0x00A3A074) #define UMAC_REO_R1_SM_STATES_IX_4___RWC QCSR_REG_RO #define UMAC_REO_R1_SM_STATES_IX_4___POR 0x00000000 #define UMAC_REO_R1_SM_STATES_IX_4__SM_STATE___POR 0x00000000 @@ -288799,7 +297167,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_SM_STATES_IX_4___M 0xFFFFFFFF #define UMAC_REO_R1_SM_STATES_IX_4___S 0 -#define UMAC_REO_R1_SM_STATES_IX_5 (0x00A3A068) +#define UMAC_REO_R1_SM_STATES_IX_5 (0x00A3A078) #define UMAC_REO_R1_SM_STATES_IX_5___RWC QCSR_REG_RO #define UMAC_REO_R1_SM_STATES_IX_5___POR 0x00000000 #define UMAC_REO_R1_SM_STATES_IX_5__SM_STATE___POR 0x00000000 @@ -288808,7 +297176,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_SM_STATES_IX_5___M 0xFFFFFFFF #define UMAC_REO_R1_SM_STATES_IX_5___S 0 -#define UMAC_REO_R1_SM_STATES_IX_6 (0x00A3A06C) +#define UMAC_REO_R1_SM_STATES_IX_6 (0x00A3A07C) #define UMAC_REO_R1_SM_STATES_IX_6___RWC QCSR_REG_RO #define UMAC_REO_R1_SM_STATES_IX_6___POR 0x00000000 #define UMAC_REO_R1_SM_STATES_IX_6__SM_STATE___POR 0x00000000 @@ -288817,7 +297185,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_SM_STATES_IX_6___M 0xFFFFFFFF #define UMAC_REO_R1_SM_STATES_IX_6___S 0 -#define UMAC_REO_R1_IDLE_STATES_IX_0 (0x00A3A070) +#define UMAC_REO_R1_IDLE_STATES_IX_0 (0x00A3A080) #define UMAC_REO_R1_IDLE_STATES_IX_0___RWC QCSR_REG_RO #define UMAC_REO_R1_IDLE_STATES_IX_0___POR 0x00000000 #define UMAC_REO_R1_IDLE_STATES_IX_0__IDLE_STATE___POR 0x00000000 @@ -288826,7 +297194,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_REO_R1_IDLE_STATES_IX_0___M 0xFFFFFFFF #define UMAC_REO_R1_IDLE_STATES_IX_0___S 0 -#define UMAC_REO_R1_INVALID_APB_ACCESS (0x00A3A074) +#define UMAC_REO_R1_INVALID_APB_ACCESS (0x00A3A084) #define UMAC_REO_R1_INVALID_APB_ACCESS___RWC QCSR_REG_RW #define UMAC_REO_R1_INVALID_APB_ACCESS___POR 0x00000000 #define UMAC_REO_R1_INVALID_APB_ACCESS__ERR_TYPE___POR 0x0 @@ -292606,7 +300974,73 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___M 0x00000001 #define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___S 0 -#define UMAC_TQM_R1_PREFETCH_BUF (0x00A3E038) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1 (0x00A3E038) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__BACKUP___POR 0x00 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_WITHOUT_INVALIDATE___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_ENTIRE_CACHE___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_REQ___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__BACKUP___M 0x000007F8 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__BACKUP___S 3 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_WITHOUT_INVALIDATE___M 0x00000004 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_WITHOUT_INVALIDATE___S 2 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_ENTIRE_CACHE___M 0x00000002 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_ENTIRE_CACHE___S 1 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_REQ___M 0x00000001 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1__FLUSH_REQ___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1___M 0x000007FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2 (0x00A3E03C) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2__FLUSH_ADDR_31_0___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2__FLUSH_ADDR_31_0___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2__FLUSH_ADDR_31_0___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3 (0x00A3E040) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3__FLUSH_ADDR_39_32___POR 0x00 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3__FLUSH_ADDR_39_32___M 0x000000FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3__FLUSH_ADDR_39_32___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3___M 0x000000FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS (0x00A3E044) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS___POR 0x00000001 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__BACKUP___POR 0x00 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_COUNT___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HW_IF_BUSY___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_ERROR___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_CLIENT_ID___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_DESC_TYPE___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HIT___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_DONE___POR 0x1 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__BACKUP___M 0x3FC00000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__BACKUP___S 22 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_COUNT___M 0x003FF000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_COUNT___S 12 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HW_IF_BUSY___M 0x00000800 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HW_IF_BUSY___S 11 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_ERROR___M 0x00000600 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_ERROR___S 9 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_CLIENT_ID___M 0x000001E0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_CLIENT_ID___S 5 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_DESC_TYPE___M 0x0000001C +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_DESC_TYPE___S 2 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HIT___M 0x00000002 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_STATUS_HIT___S 1 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_DONE___M 0x00000001 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS__FLUSH_DONE___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS___M 0x3FFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS___S 0 + +#define UMAC_TQM_R1_PREFETCH_BUF (0x00A3E048) #define UMAC_TQM_R1_PREFETCH_BUF___RWC QCSR_REG_RW #define UMAC_TQM_R1_PREFETCH_BUF___POR 0x00000000 #define UMAC_TQM_R1_PREFETCH_BUF__ADDR___POR 0x000 @@ -292615,7 +301049,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_PREFETCH_BUF___M 0x00000FFC #define UMAC_TQM_R1_PREFETCH_BUF___S 2 -#define UMAC_TQM_R1_PREFETCH_BUF_DATA (0x00A3E03C) +#define UMAC_TQM_R1_PREFETCH_BUF_DATA (0x00A3E04C) #define UMAC_TQM_R1_PREFETCH_BUF_DATA___RWC QCSR_REG_RO #define UMAC_TQM_R1_PREFETCH_BUF_DATA___POR 0x00000000 #define UMAC_TQM_R1_PREFETCH_BUF_DATA__VALUE___POR 0x00000000 @@ -292624,7 +301058,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_PREFETCH_BUF_DATA___M 0xFFFFFFFF #define UMAC_TQM_R1_PREFETCH_BUF_DATA___S 0 -#define UMAC_TQM_R1_CACHE_BUF (0x00A3E040) +#define UMAC_TQM_R1_CACHE_BUF (0x00A3E050) #define UMAC_TQM_R1_CACHE_BUF___RWC QCSR_REG_RW #define UMAC_TQM_R1_CACHE_BUF___POR 0x00000000 #define UMAC_TQM_R1_CACHE_BUF__ADDR___POR 0x0000 @@ -292633,7 +301067,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_CACHE_BUF___M 0x0000FFFC #define UMAC_TQM_R1_CACHE_BUF___S 2 -#define UMAC_TQM_R1_CACHE_BUF_DATA (0x00A3E044) +#define UMAC_TQM_R1_CACHE_BUF_DATA (0x00A3E054) #define UMAC_TQM_R1_CACHE_BUF_DATA___RWC QCSR_REG_RO #define UMAC_TQM_R1_CACHE_BUF_DATA___POR 0x00000000 #define UMAC_TQM_R1_CACHE_BUF_DATA__VALUE___POR 0x00000000 @@ -292642,7 +301076,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_CACHE_BUF_DATA___M 0xFFFFFFFF #define UMAC_TQM_R1_CACHE_BUF_DATA___S 0 -#define UMAC_TQM_R1_MISC_DEBUG_CTRL (0x00A3E048) +#define UMAC_TQM_R1_MISC_DEBUG_CTRL (0x00A3E058) #define UMAC_TQM_R1_MISC_DEBUG_CTRL___RWC QCSR_REG_RW #define UMAC_TQM_R1_MISC_DEBUG_CTRL___POR 0x00000000 #define UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ___POR 0x0 @@ -292654,7 +301088,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_MISC_DEBUG_CTRL___M 0x00000003 #define UMAC_TQM_R1_MISC_DEBUG_CTRL___S 0 -#define UMAC_TQM_R1_LOG (0x00A3E04C) +#define UMAC_TQM_R1_LOG (0x00A3E05C) #define UMAC_TQM_R1_LOG___RWC QCSR_REG_RO #define UMAC_TQM_R1_LOG___POR 0x0FFFFFFF #define UMAC_TQM_R1_LOG__CURR_CMD_IDX___POR 0xF @@ -292666,7 +301100,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_LOG___M 0x0FFFFFFF #define UMAC_TQM_R1_LOG___S 0 -#define UMAC_TQM_R1_BANK_SM_STATES_IX0 (0x00A3E050) +#define UMAC_TQM_R1_BANK_SM_STATES_IX0 (0x00A3E060) #define UMAC_TQM_R1_BANK_SM_STATES_IX0___RWC QCSR_REG_RO #define UMAC_TQM_R1_BANK_SM_STATES_IX0___POR 0x00000000 #define UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_QUEUE_STATS_SM___POR 0x0 @@ -292693,7 +301127,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_BANK_SM_STATES_IX0___M 0x1FFFFFFF #define UMAC_TQM_R1_BANK_SM_STATES_IX0___S 0 -#define UMAC_TQM_R1_BANK_SM_STATES_IX1 (0x00A3E054) +#define UMAC_TQM_R1_BANK_SM_STATES_IX1 (0x00A3E064) #define UMAC_TQM_R1_BANK_SM_STATES_IX1___RWC QCSR_REG_RO #define UMAC_TQM_R1_BANK_SM_STATES_IX1___POR 0x00000000 #define UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK1_SM___POR 0x0 @@ -292723,7 +301157,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_BANK_SM_STATES_IX1___M 0xFFFFFFFF #define UMAC_TQM_R1_BANK_SM_STATES_IX1___S 0 -#define UMAC_TQM_R1_BANK_SM_STATES_IX2 (0x00A3E058) +#define UMAC_TQM_R1_BANK_SM_STATES_IX2 (0x00A3E068) #define UMAC_TQM_R1_BANK_SM_STATES_IX2___RWC QCSR_REG_RO #define UMAC_TQM_R1_BANK_SM_STATES_IX2___POR 0x00000000 #define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_ASYNC_SM___POR 0x0 @@ -292747,7 +301181,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_BANK_SM_STATES_IX2___M 0xFFFFFFFF #define UMAC_TQM_R1_BANK_SM_STATES_IX2___S 0 -#define UMAC_TQM_R1_BANK_SM_STATES_IX3 (0x00A3E05C) +#define UMAC_TQM_R1_BANK_SM_STATES_IX3 (0x00A3E06C) #define UMAC_TQM_R1_BANK_SM_STATES_IX3___RWC QCSR_REG_RO #define UMAC_TQM_R1_BANK_SM_STATES_IX3___POR 0x00000000 #define UMAC_TQM_R1_BANK_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___POR 0x00 @@ -292765,7 +301199,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_BANK_SM_STATES_IX3___M 0x00000FFF #define UMAC_TQM_R1_BANK_SM_STATES_IX3___S 0 -#define UMAC_TQM_R1_CCMN_IDLE (0x00A3E060) +#define UMAC_TQM_R1_CCMN_IDLE (0x00A3E070) #define UMAC_TQM_R1_CCMN_IDLE___RWC QCSR_REG_RO #define UMAC_TQM_R1_CCMN_IDLE___POR 0x00000000 #define UMAC_TQM_R1_CCMN_IDLE__SOURCES___POR 0x00000000 @@ -292774,7 +301208,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_CCMN_IDLE___M 0xFFFFFFFF #define UMAC_TQM_R1_CCMN_IDLE___S 0 -#define UMAC_TQM_R1_CURRENT_COMMAND (0x00A3E064) +#define UMAC_TQM_R1_CURRENT_COMMAND (0x00A3E074) #define UMAC_TQM_R1_CURRENT_COMMAND___RWC QCSR_REG_RO #define UMAC_TQM_R1_CURRENT_COMMAND___POR 0x00000000 #define UMAC_TQM_R1_CURRENT_COMMAND__POINTER___POR 0x0 @@ -292804,7 +301238,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_CURRENT_COMMAND___M 0xFFFFFFFF #define UMAC_TQM_R1_CURRENT_COMMAND___S 0 -#define UMAC_TQM_R1_LOG_ADD_MSDU (0x00A3E068) +#define UMAC_TQM_R1_LOG_ADD_MSDU (0x00A3E078) #define UMAC_TQM_R1_LOG_ADD_MSDU___RWC QCSR_REG_RO #define UMAC_TQM_R1_LOG_ADD_MSDU___POR 0x00FFFFFF #define UMAC_TQM_R1_LOG_ADD_MSDU__CURR_CMD_NUM___POR 0xFFFFFF @@ -292813,7 +301247,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_LOG_ADD_MSDU___M 0x00FFFFFF #define UMAC_TQM_R1_LOG_ADD_MSDU___S 0 -#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0 (0x00A3E06C) +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0 (0x00A3E07C) #define UMAC_TQM_R1_LOG_TIMESTAMP_IX0___RWC QCSR_REG_RO #define UMAC_TQM_R1_LOG_TIMESTAMP_IX0___POR 0x00000000 #define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_2___POR 0x000 @@ -292828,7 +301262,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_LOG_TIMESTAMP_IX0___M 0x3FFFFFFF #define UMAC_TQM_R1_LOG_TIMESTAMP_IX0___S 0 -#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1 (0x00A3E070) +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1 (0x00A3E080) #define UMAC_TQM_R1_LOG_TIMESTAMP_IX1___RWC QCSR_REG_RO #define UMAC_TQM_R1_LOG_TIMESTAMP_IX1___POR 0x00000000 #define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_5___POR 0x000 @@ -292843,7 +301277,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_LOG_TIMESTAMP_IX1___M 0x3FFFFFFF #define UMAC_TQM_R1_LOG_TIMESTAMP_IX1___S 0 -#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2 (0x00A3E074) +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2 (0x00A3E084) #define UMAC_TQM_R1_LOG_TIMESTAMP_IX2___RWC QCSR_REG_RO #define UMAC_TQM_R1_LOG_TIMESTAMP_IX2___POR 0x00000000 #define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__POINTER___POR 0x0 @@ -292858,7 +301292,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_LOG_TIMESTAMP_IX2___M 0x007FFFFF #define UMAC_TQM_R1_LOG_TIMESTAMP_IX2___S 0 -#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3 (0x00A3E078) +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3 (0x00A3E088) #define UMAC_TQM_R1_LOG_TIMESTAMP_IX3___RWC QCSR_REG_RO #define UMAC_TQM_R1_LOG_TIMESTAMP_IX3___POR 0x00000000 #define UMAC_TQM_R1_LOG_TIMESTAMP_IX3__WATCHDOG_SNAPSHOT___POR 0x000000 @@ -292870,7 +301304,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_LOG_TIMESTAMP_IX3___M 0xFFFFFFFF #define UMAC_TQM_R1_LOG_TIMESTAMP_IX3___S 0 -#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0 (0x00A3E07C) +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0 (0x00A3E08C) #define UMAC_TQM_R1_WATCHDOG_STATUS_IX0___RWC QCSR_REG_RO #define UMAC_TQM_R1_WATCHDOG_STATUS_IX0___POR 0x00000000 #define UMAC_TQM_R1_WATCHDOG_STATUS_IX0__SW_SM_WATCHDOG___POR 0x0000 @@ -292882,16 +301316,19 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_WATCHDOG_STATUS_IX0___M 0xFFFFFFFF #define UMAC_TQM_R1_WATCHDOG_STATUS_IX0___S 0 -#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1 (0x00A3E080) +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1 (0x00A3E090) #define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___RWC QCSR_REG_RO #define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___POR 0x00000000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__IDLE_SEQUENCE_SM___POR 0x00 #define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___POR 0x0000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__IDLE_SEQUENCE_SM___M 0x001F0000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__IDLE_SEQUENCE_SM___S 16 #define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___M 0x0000FFFF #define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___S 0 -#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___M 0x0000FFFF +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___M 0x001FFFFF #define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___S 0 -#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH (0x00A3E084) +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH (0x00A3E094) #define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___RWC QCSR_REG_RO #define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___POR 0x00000000 #define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH__ADDRESS___POR 0x00000000 @@ -292900,7 +301337,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___M 0xFFFFFFFF #define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___S 0 -#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH (0x00A3E088) +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH (0x00A3E098) #define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___RWC QCSR_REG_RO #define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___POR 0x00000000 #define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH__ADDRESS___POR 0x00000000 @@ -293091,7 +301528,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN (0x00A40000) #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___RWC QCSR_REG_RW -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___POR 0x002FFFE2 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___POR 0x002FFE62 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__UMAC_DBG___POR 0x1 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC_APB___POR 0x1 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC___POR 0x1 @@ -293104,8 +301541,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO_APB___POR 0x1 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO___POR 0x1 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___POR 0x1 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___POR 0x1 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___POR 0x1 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___POR 0x1 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___POR 0x1 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___POR 0x1 @@ -293133,17 +301568,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO___S 10 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___M 0x00000200 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___S 9 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___M 0x00000100 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___S 8 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___M 0x00000080 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___S 7 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___M 0x00000040 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___S 6 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___M 0x00000020 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___S 5 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___M 0x00000002 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___S 1 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___M 0x002FFFE2 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___M 0x002FFE62 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___S 1 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE (0x00A40004) @@ -293160,8 +301591,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO_APB___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___POR 0x0 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___POR 0x0 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___POR 0x1 @@ -293187,17 +301616,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO_APB___S 11 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___M 0x00000400 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___S 10 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___M 0x00000100 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___S 8 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___M 0x00000080 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___S 7 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___M 0x00000040 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___S 6 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___M 0x00000020 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___S 5 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___M 0x00000002 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___S 1 -#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___M 0x002FFDE2 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___M 0x002FFC62 #define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___S 1 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET (0x00A40008) @@ -293209,7 +301634,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TQM___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TCL___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___POR 0x0 -#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___POR 0x0 @@ -293225,15 +301649,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TCL___S 5 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___M 0x00000010 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___S 4 -#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___M 0x00000008 -#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___S 3 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___M 0x00000004 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___S 2 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___M 0x00000002 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___S 1 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___M 0x00000001 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___S 0 -#define UMAC_UMCMN_R0_UMRCM_SOFTRESET___M 0x000005FF +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET___M 0x000005F7 #define UMAC_UMCMN_R0_UMRCM_SOFTRESET___S 0 #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET (0x00A4000C) @@ -293244,7 +301666,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TQM___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TCL___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___POR 0x0 -#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TRC___M 0x00000020 #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TRC___S 5 #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__WBM___M 0x00000010 @@ -293255,10 +301676,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TCL___S 2 #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___M 0x00000002 #define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___S 1 -#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___M 0x00000001 -#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___S 0 -#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET___M 0x0000003F -#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET___S 0 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET___M 0x0000003E +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET___S 1 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE (0x00A40010) #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___RWC QCSR_REG_RW @@ -293274,8 +301693,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO_APB___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___POR 0x0 -#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___POR 0x0 -#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___POR 0x0 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___POR 0x0 @@ -293301,17 +301718,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO_APB___S 11 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___M 0x00000400 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___S 10 -#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___M 0x00000100 -#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___S 8 -#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___M 0x00000080 -#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___S 7 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___M 0x00000040 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___S 6 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___M 0x00000020 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___S 5 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___M 0x00000002 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___S 1 -#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___M 0x004FFDE2 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___M 0x004FFC62 #define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___S 1 #define UMAC_UMCMN_R0_UMAC_RTL_VERSION (0x00A40014) @@ -293349,8 +301762,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_CLK_GATE_DISABLE___POR 0x00000000 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x0 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___POR 0x0 -#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___POR 0x0000000 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___POR 0x000000 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___POR 0x0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__INTR_EXTEND___POR 0x0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__IND_INTR___POR 0x0 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___POR 0x0 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMAC_IDLE_GENERATE___POR 0x0 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMCMN_TOP___POR 0x0 @@ -293358,10 +301773,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S 31 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___M 0x40000000 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___S 30 -#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___M 0x3FFFFFF0 -#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___S 4 -#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___M 0x00000008 -#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___S 3 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___M 0x3FFFFFC0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___S 6 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___M 0x00000020 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___S 5 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__INTR_EXTEND___M 0x00000010 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__INTR_EXTEND___S 4 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__IND_INTR___M 0x00000008 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__IND_INTR___S 3 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___M 0x00000004 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___S 2 #define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMAC_IDLE_GENERATE___M 0x00000002 @@ -293533,9 +301952,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S0 (0x00A4003C) #define UMAC_UMCMN_R0_ISR_S0___RWC QCSR_REG_RW #define UMAC_UMCMN_R0_ISR_S0___POR 0x00000000 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___POR 0x0 #define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___POR 0x0 #define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_INVALID___POR 0x0 #define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_TO_RD_INVALID___POR 0x0 @@ -293557,12 +301973,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S0__REO_APB_RD_INVALID___POR 0x0 #define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_INVALID___POR 0x0 #define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___M 0x00800000 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___S 23 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___M 0x00400000 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___S 22 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___M 0x00200000 -#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___S 21 #define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___M 0x00100000 #define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___S 20 #define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_INVALID___M 0x00080000 @@ -293605,14 +302015,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_INVALID___S 1 #define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___M 0x00000001 #define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___S 0 -#define UMAC_UMCMN_R0_ISR_S0___M 0x00FFFFFF +#define UMAC_UMCMN_R0_ISR_S0___M 0x001FFFFF #define UMAC_UMCMN_R0_ISR_S0___S 0 #define UMAC_UMCMN_R0_ISR_S1 (0x00A40040) #define UMAC_UMCMN_R0_ISR_S1___RWC QCSR_REG_RW #define UMAC_UMCMN_R0_ISR_S1___POR 0x00000000 -#define UMAC_UMCMN_R0_ISR_S1__CE_WDG___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S1__CE_ERR___POR 0x0 #define UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___POR 0x0 #define UMAC_UMCMN_R0_ISR_S1__LCMH_STROBE___POR 0x0 #define UMAC_UMCMN_R0_ISR_S1__MCIM___POR 0x0 @@ -293620,10 +302028,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S1__PMH___POR 0x0 #define UMAC_UMCMN_R0_ISR_S1__LMH___POR 0x0 #define UMAC_UMCMN_R0_ISR_S1__BMH___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S1__CE_WDG___M 0x00020000 -#define UMAC_UMCMN_R0_ISR_S1__CE_WDG___S 17 -#define UMAC_UMCMN_R0_ISR_S1__CE_ERR___M 0x00010000 -#define UMAC_UMCMN_R0_ISR_S1__CE_ERR___S 16 #define UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___M 0x00000040 #define UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___S 6 #define UMAC_UMCMN_R0_ISR_S1__LCMH_STROBE___M 0x00000020 @@ -293638,7 +302042,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S1__LMH___S 1 #define UMAC_UMCMN_R0_ISR_S1__BMH___M 0x00000001 #define UMAC_UMCMN_R0_ISR_S1__BMH___S 0 -#define UMAC_UMCMN_R0_ISR_S1___M 0x0003007F +#define UMAC_UMCMN_R0_ISR_S1___M 0x0000007F #define UMAC_UMCMN_R0_ISR_S1___S 0 #define UMAC_UMCMN_R0_ISR_S2 (0x00A40044) @@ -293930,7 +302334,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S6__SW2REO_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_ISR_S6__REO_CMD_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__SW2REO1_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO0_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_ISR_S6__REO_STATUS_RING_WDG___M 0x00008000 @@ -293959,8 +302363,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S6__REO_CMD_RING_WDG___S 4 #define UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___M 0x00000008 #define UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___S 3 -#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___M 0x00000004 -#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___S 2 +#define UMAC_UMCMN_R0_ISR_S6__SW2REO1_RING_WDG___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S6__SW2REO1_RING_WDG___S 2 #define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___M 0x00000002 #define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___S 1 #define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO0_RING_WDG___M 0x00000001 @@ -294413,10 +302817,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S16___RWC QCSR_REG_RW #define UMAC_UMCMN_R0_ISR_S16___POR 0x00000000 #define UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___POR 0x0000 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___POR 0x0 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___POR 0x0 #define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___POR 0x0 #define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_RD_ERR___POR 0x0 #define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_LAST_WR_ERR___POR 0x0 @@ -294431,14 +302831,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___POR 0x0 #define UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___M 0xFFFF0000 #define UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___S 16 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___M 0x00008000 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___S 15 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___M 0x00004000 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___S 14 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___M 0x00002000 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___S 13 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___M 0x00001000 -#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___S 12 #define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___M 0x00000800 #define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___S 11 #define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_RD_ERR___M 0x00000400 @@ -294463,7 +302855,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_LAST_WR_ERR___S 1 #define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___M 0x00000001 #define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___S 0 -#define UMAC_UMCMN_R0_ISR_S16___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_ISR_S16___M 0xFFFF0FFF #define UMAC_UMCMN_R0_ISR_S16___S 0 #define UMAC_UMCMN_R0_IMR_P (0x00A40080) @@ -294526,9 +302918,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S0 (0x00A40084) #define UMAC_UMCMN_R0_IMR_S0___RWC QCSR_REG_RW #define UMAC_UMCMN_R0_IMR_S0___POR 0x00000000 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___POR 0x0 #define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___POR 0x0 #define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_INVALID___POR 0x0 #define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_TO_RD_INVALID___POR 0x0 @@ -294550,12 +302939,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S0__REO_APB_RD_INVALID___POR 0x0 #define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_INVALID___POR 0x0 #define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___M 0x00800000 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___S 23 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___M 0x00400000 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___S 22 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___M 0x00200000 -#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___S 21 #define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___M 0x00100000 #define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___S 20 #define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_INVALID___M 0x00080000 @@ -294598,14 +302981,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_INVALID___S 1 #define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___M 0x00000001 #define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___S 0 -#define UMAC_UMCMN_R0_IMR_S0___M 0x00FFFFFF +#define UMAC_UMCMN_R0_IMR_S0___M 0x001FFFFF #define UMAC_UMCMN_R0_IMR_S0___S 0 #define UMAC_UMCMN_R0_IMR_S1 (0x00A40088) #define UMAC_UMCMN_R0_IMR_S1___RWC QCSR_REG_RW #define UMAC_UMCMN_R0_IMR_S1___POR 0x00000000 -#define UMAC_UMCMN_R0_IMR_S1__CE_WDG___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S1__CE_ERR___POR 0x0 #define UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___POR 0x0 #define UMAC_UMCMN_R0_IMR_S1__LCMH_STROBE___POR 0x0 #define UMAC_UMCMN_R0_IMR_S1__MCIM___POR 0x0 @@ -294613,10 +302994,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S1__PMH___POR 0x0 #define UMAC_UMCMN_R0_IMR_S1__LMH___POR 0x0 #define UMAC_UMCMN_R0_IMR_S1__BMH___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S1__CE_WDG___M 0x00020000 -#define UMAC_UMCMN_R0_IMR_S1__CE_WDG___S 17 -#define UMAC_UMCMN_R0_IMR_S1__CE_ERR___M 0x00010000 -#define UMAC_UMCMN_R0_IMR_S1__CE_ERR___S 16 #define UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___M 0x00000040 #define UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___S 6 #define UMAC_UMCMN_R0_IMR_S1__LCMH_STROBE___M 0x00000020 @@ -294631,7 +303008,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S1__LMH___S 1 #define UMAC_UMCMN_R0_IMR_S1__BMH___M 0x00000001 #define UMAC_UMCMN_R0_IMR_S1__BMH___S 0 -#define UMAC_UMCMN_R0_IMR_S1___M 0x0003007F +#define UMAC_UMCMN_R0_IMR_S1___M 0x0000007F #define UMAC_UMCMN_R0_IMR_S1___S 0 #define UMAC_UMCMN_R0_IMR_S2 (0x00A4008C) @@ -294923,7 +303300,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S6__SW2REO_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_IMR_S6__REO_CMD_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__SW2REO1_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO0_RING_WDG___POR 0x0 #define UMAC_UMCMN_R0_IMR_S6__REO_STATUS_RING_WDG___M 0x00008000 @@ -294952,8 +303329,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S6__REO_CMD_RING_WDG___S 4 #define UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___M 0x00000008 #define UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___S 3 -#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___M 0x00000004 -#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___S 2 +#define UMAC_UMCMN_R0_IMR_S6__SW2REO1_RING_WDG___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S6__SW2REO1_RING_WDG___S 2 #define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___M 0x00000002 #define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___S 1 #define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO0_RING_WDG___M 0x00000001 @@ -295406,10 +303783,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S16___RWC QCSR_REG_RW #define UMAC_UMCMN_R0_IMR_S16___POR 0x00000000 #define UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___POR 0x0000 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___POR 0x0 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___POR 0x0 #define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___POR 0x0 #define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_RD_ERR___POR 0x0 #define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_LAST_WR_ERR___POR 0x0 @@ -295424,14 +303797,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___POR 0x0 #define UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___M 0xFFFF0000 #define UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___S 16 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___M 0x00008000 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___S 15 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___M 0x00004000 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___S 14 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___M 0x00002000 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___S 13 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___M 0x00001000 -#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___S 12 #define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___M 0x00000800 #define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___S 11 #define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_RD_ERR___M 0x00000400 @@ -295456,7 +303821,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_LAST_WR_ERR___S 1 #define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___M 0x00000001 #define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___S 0 -#define UMAC_UMCMN_R0_IMR_S16___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_IMR_S16___M 0xFFFF0FFF #define UMAC_UMCMN_R0_IMR_S16___S 0 #define UMAC_UMCMN_R0_WOCLR_ISR_P_EN (0x00A400C8) @@ -295489,7 +303854,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_NOC_IDLE_REQ___POR 0x0 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_WBM_IDLE_REQ___POR 0x0 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___POR 0x0 -#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___POR 0x0 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___POR 0x0 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TCL_IDLE_REQ___POR 0x0 #define UMAC_UMCMN_R0_IDLE_CTRL0__INTER_STATE_DLY___POR 0x01F @@ -295501,8 +303865,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_WBM_IDLE_REQ___S 20 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___M 0x00080000 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___S 19 -#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___M 0x00040000 -#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___S 18 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___M 0x00020000 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___S 17 #define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TCL_IDLE_REQ___M 0x00010000 @@ -295513,7 +303875,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___S 1 #define UMAC_UMCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___M 0x00000001 #define UMAC_UMCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___S 0 -#define UMAC_UMCMN_R0_IDLE_CTRL0___M 0x003FFFFF +#define UMAC_UMCMN_R0_IDLE_CTRL0___M 0x003BFFFF #define UMAC_UMCMN_R0_IDLE_CTRL0___S 0 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR (0x00A400D4) @@ -295525,8 +303887,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_OVR___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_DATA___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___POR 0x0 -#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___POR 0x0 -#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_OVR___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_DATA___POR 0x0 @@ -295544,10 +303904,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_DATA___S 8 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___M 0x00000080 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___S 7 -#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___M 0x00000040 -#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___S 6 -#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___M 0x00000020 -#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___S 5 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___M 0x00000010 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___S 4 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_OVR___M 0x00000008 @@ -295558,7 +303914,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_OVR___S 1 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__GLOBAL_SW_OVR___M 0x00000001 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__GLOBAL_SW_OVR___S 0 -#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___M 0x00001FFF +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___M 0x00001F9F #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___S 0 #define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL (0x00A400D8) @@ -295578,13 +303934,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IDLE_SIGNAL (0x00A400DC) #define UMAC_UMCMN_R0_IDLE_SIGNAL___RWC QCSR_REG_RO -#define UMAC_UMCMN_R0_IDLE_SIGNAL___POR 0x0000007D +#define UMAC_UMCMN_R0_IDLE_SIGNAL___POR 0x0000007C #define UMAC_UMCMN_R0_IDLE_SIGNAL__REO___POR 0x1 #define UMAC_UMCMN_R0_IDLE_SIGNAL__TCL___POR 0x1 #define UMAC_UMCMN_R0_IDLE_SIGNAL__WBM___POR 0x1 #define UMAC_UMCMN_R0_IDLE_SIGNAL__TQM___POR 0x1 #define UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___POR 0x1 -#define UMAC_UMCMN_R0_IDLE_SIGNAL__CE___POR 0x1 #define UMAC_UMCMN_R0_IDLE_SIGNAL__REO___M 0x00000040 #define UMAC_UMCMN_R0_IDLE_SIGNAL__REO___S 6 #define UMAC_UMCMN_R0_IDLE_SIGNAL__TCL___M 0x00000020 @@ -295595,10 +303950,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_IDLE_SIGNAL__TQM___S 3 #define UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___M 0x00000004 #define UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___S 2 -#define UMAC_UMCMN_R0_IDLE_SIGNAL__CE___M 0x00000001 -#define UMAC_UMCMN_R0_IDLE_SIGNAL__CE___S 0 -#define UMAC_UMCMN_R0_IDLE_SIGNAL___M 0x0000007D -#define UMAC_UMCMN_R0_IDLE_SIGNAL___S 0 +#define UMAC_UMCMN_R0_IDLE_SIGNAL___M 0x0000007C +#define UMAC_UMCMN_R0_IDLE_SIGNAL___S 2 #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS (0x00A400E0) #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___RWC QCSR_REG_RO @@ -295607,7 +303960,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TQM_CMD_RING___POR 0x0 #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__REO_CMD_RING___POR 0x0 #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___POR 0x0 -#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___POR 0x0 #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__WBM_REL_RING___M 0x00000010 #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__WBM_REL_RING___S 4 #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TQM_CMD_RING___M 0x00000008 @@ -295616,10 +303968,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__REO_CMD_RING___S 2 #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___M 0x00000002 #define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___S 1 -#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___M 0x00000001 -#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___S 0 -#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___M 0x0000001F -#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___S 0 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___M 0x0000001E +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___S 1 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR (0x00A400E4) #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___RWC QCSR_REG_RW @@ -295630,8 +303980,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR_DATA___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___POR 0x0 -#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___POR 0x0 -#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR___POR 0x0 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR_DATA___POR 0x0 @@ -295648,10 +303996,6 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR_DATA___S 7 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___M 0x00000040 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___S 6 -#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___M 0x00000020 -#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___S 5 -#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___M 0x00000010 -#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___S 4 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___M 0x00000008 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___S 3 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR___M 0x00000004 @@ -295660,7 +304004,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR_DATA___S 1 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR___M 0x00000001 #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR___S 0 -#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___M 0x00000FFF +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___M 0x00000FCF #define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___S 0 #define UMAC_UMCMN_R0_S_PARE_0 (0x00A400E8) @@ -295729,6 +304073,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___M 0x0000000F #define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___S 0 +#define UMAC_UMCMN_R0_CXC_SMH_TRIGGER (0x00A40104) +#define UMAC_UMCMN_R0_CXC_SMH_TRIGGER___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_CXC_SMH_TRIGGER___POR 0x00000000 +#define UMAC_UMCMN_R0_CXC_SMH_TRIGGER__VALUE___POR 0x0 +#define UMAC_UMCMN_R0_CXC_SMH_TRIGGER__VALUE___M 0x00000001 +#define UMAC_UMCMN_R0_CXC_SMH_TRIGGER__VALUE___S 0 +#define UMAC_UMCMN_R0_CXC_SMH_TRIGGER___M 0x00000001 +#define UMAC_UMCMN_R0_CXC_SMH_TRIGGER___S 0 + #define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR (0x00A41000) #define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO #define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___POR 0x00000000 @@ -295740,14 +304093,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R1_UMAC_IDLE (0x00A41004) #define UMAC_UMCMN_R1_UMAC_IDLE___RWC QCSR_REG_RO -#define UMAC_UMCMN_R1_UMAC_IDLE___POR 0x00000001 +#define UMAC_UMCMN_R1_UMAC_IDLE___POR 0x00000000 #define UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___POR 0x0 -#define UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___POR 0x0001 -#define UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___M 0x00010000 -#define UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___S 16 -#define UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___M 0x0000FFFF +#define UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___POR 0x0 +#define UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___M 0x00000010 +#define UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___S 4 +#define UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___M 0x0000000F #define UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___S 0 -#define UMAC_UMCMN_R1_UMAC_IDLE___M 0x0001FFFF +#define UMAC_UMCMN_R1_UMAC_IDLE___M 0x0000001F #define UMAC_UMCMN_R1_UMAC_IDLE___S 0 #define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS (0x00A41008) @@ -295764,11 +304117,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___POR 0x00000000 #define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___POR 0x00 #define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___POR 0x00 -#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___M 0x00000FC0 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___M 0x000007C0 #define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___S 6 -#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___M 0x0000003F +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___M 0x0000001F #define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___S 0 -#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___M 0x00000FFF +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___M 0x000007DF #define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___S 0 #define UMAC_TCL_R0_SW2TCL1_RING_CTRL (0x00A44000) @@ -298526,7 +306879,19 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_S_PARE_REGISTER___M 0xFFFFFFFF #define UMAC_TCL_R0_S_PARE_REGISTER___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB (0x00A44690) +#define UMAC_TCL_R0_MISC_CTRL (0x00A44690) +#define UMAC_TCL_R0_MISC_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_MISC_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_MISC_CTRL__DATA_CORRUPT_FIX_DISABLE_CHK_BIT___POR 0x0 +#define UMAC_TCL_R0_MISC_CTRL__MSI_DISABLE_CHK_BIT___POR 0x0 +#define UMAC_TCL_R0_MISC_CTRL__DATA_CORRUPT_FIX_DISABLE_CHK_BIT___M 0x00000002 +#define UMAC_TCL_R0_MISC_CTRL__DATA_CORRUPT_FIX_DISABLE_CHK_BIT___S 1 +#define UMAC_TCL_R0_MISC_CTRL__MSI_DISABLE_CHK_BIT___M 0x00000001 +#define UMAC_TCL_R0_MISC_CTRL__MSI_DISABLE_CHK_BIT___S 0 +#define UMAC_TCL_R0_MISC_CTRL___M 0x00000003 +#define UMAC_TCL_R0_MISC_CTRL___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB (0x00A44694) #define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -298535,7 +306900,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB (0x00A44694) +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB (0x00A44698) #define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_SIZE___POR 0x00000 @@ -298547,7 +306912,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___M 0x0FFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_ID (0x00A44698) +#define UMAC_TCL_R0_SW2TCL1_RING_ID (0x00A4469C) #define UMAC_TCL_R0_SW2TCL1_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_ID__ENTRY_SIZE___POR 0x00 @@ -298556,7 +306921,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_ID___M 0x000000FF #define UMAC_TCL_R0_SW2TCL1_RING_ID___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_STATUS (0x00A4469C) +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS (0x00A446A0) #define UMAC_TCL_R0_SW2TCL1_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL1_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -298568,7 +306933,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_MISC (0x00A446A0) +#define UMAC_TCL_R0_SW2TCL1_RING_MISC (0x00A446A4) #define UMAC_TCL_R0_SW2TCL1_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_SW2TCL1_RING_MISC__SPARE_CONTROL___POR 0x00 @@ -298607,7 +306972,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_MISC___M 0x003FFFFF #define UMAC_TCL_R0_SW2TCL1_RING_MISC___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB (0x00A446AC) +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB (0x00A446B0) #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 @@ -298616,7 +306981,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB (0x00A446B0) +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB (0x00A446B4) #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 @@ -298625,7 +306990,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 (0x00A446C0) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 (0x00A446C4) #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -298640,7 +307005,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 (0x00A446C4) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 (0x00A446C8) #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 @@ -298649,7 +307014,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS (0x00A446C8) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS (0x00A446CC) #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -298664,7 +307029,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER (0x00A446CC) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER (0x00A446D0) #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 @@ -298673,7 +307038,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER (0x00A446D0) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER (0x00A446D4) #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 @@ -298682,7 +307047,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS (0x00A446D4) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS (0x00A446D8) #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 @@ -298694,7 +307059,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB (0x00A446D8) +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB (0x00A446DC) #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -298703,7 +307068,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB (0x00A446DC) +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB (0x00A446E0) #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -298715,7 +307080,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA (0x00A446E0) +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA (0x00A446E4) #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -298724,7 +307089,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET (0x00A446E4) +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET (0x00A446E8) #define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -298733,7 +307098,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB (0x00A446E8) +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB (0x00A446EC) #define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -298742,7 +307107,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB (0x00A446EC) +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB (0x00A446F0) #define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_SIZE___POR 0x00000 @@ -298754,7 +307119,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___M 0x0FFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_ID (0x00A446F0) +#define UMAC_TCL_R0_SW2TCL2_RING_ID (0x00A446F4) #define UMAC_TCL_R0_SW2TCL2_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_ID__ENTRY_SIZE___POR 0x00 @@ -298763,7 +307128,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_ID___M 0x000000FF #define UMAC_TCL_R0_SW2TCL2_RING_ID___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_STATUS (0x00A446F4) +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS (0x00A446F8) #define UMAC_TCL_R0_SW2TCL2_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL2_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -298775,7 +307140,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_MISC (0x00A446F8) +#define UMAC_TCL_R0_SW2TCL2_RING_MISC (0x00A446FC) #define UMAC_TCL_R0_SW2TCL2_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_SW2TCL2_RING_MISC__SPARE_CONTROL___POR 0x00 @@ -298814,7 +307179,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_MISC___M 0x003FFFFF #define UMAC_TCL_R0_SW2TCL2_RING_MISC___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB (0x00A44704) +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB (0x00A44708) #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 @@ -298823,7 +307188,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB (0x00A44708) +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB (0x00A4470C) #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 @@ -298832,7 +307197,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 (0x00A44718) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 (0x00A4471C) #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -298847,7 +307212,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 (0x00A4471C) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 (0x00A44720) #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 @@ -298856,7 +307221,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS (0x00A44720) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS (0x00A44724) #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -298871,7 +307236,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER (0x00A44724) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER (0x00A44728) #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 @@ -298880,7 +307245,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER (0x00A44728) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER (0x00A4472C) #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 @@ -298889,7 +307254,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS (0x00A4472C) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS (0x00A44730) #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 @@ -298901,7 +307266,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB (0x00A44730) +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB (0x00A44734) #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -298910,7 +307275,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB (0x00A44734) +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB (0x00A44738) #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -298922,7 +307287,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA (0x00A44738) +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA (0x00A4473C) #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -298931,7 +307296,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET (0x00A4473C) +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET (0x00A44740) #define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -298940,7 +307305,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB (0x00A44740) +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB (0x00A44744) #define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -298949,7 +307314,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB (0x00A44744) +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB (0x00A44748) #define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_SIZE___POR 0x00000 @@ -298961,7 +307326,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___M 0x0FFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_ID (0x00A44748) +#define UMAC_TCL_R0_SW2TCL3_RING_ID (0x00A4474C) #define UMAC_TCL_R0_SW2TCL3_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_ID__ENTRY_SIZE___POR 0x00 @@ -298970,7 +307335,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_ID___M 0x000000FF #define UMAC_TCL_R0_SW2TCL3_RING_ID___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_STATUS (0x00A4474C) +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS (0x00A44750) #define UMAC_TCL_R0_SW2TCL3_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL3_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -298982,7 +307347,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_MISC (0x00A44750) +#define UMAC_TCL_R0_SW2TCL3_RING_MISC (0x00A44754) #define UMAC_TCL_R0_SW2TCL3_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_SW2TCL3_RING_MISC__SPARE_CONTROL___POR 0x00 @@ -299021,7 +307386,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_MISC___M 0x003FFFFF #define UMAC_TCL_R0_SW2TCL3_RING_MISC___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB (0x00A4475C) +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB (0x00A44760) #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 @@ -299030,7 +307395,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB (0x00A44760) +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB (0x00A44764) #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 @@ -299039,7 +307404,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 (0x00A44770) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 (0x00A44774) #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -299054,7 +307419,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 (0x00A44774) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 (0x00A44778) #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 @@ -299063,7 +307428,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS (0x00A44778) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS (0x00A4477C) #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -299078,7 +307443,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER (0x00A4477C) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER (0x00A44780) #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 @@ -299087,7 +307452,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER (0x00A44780) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER (0x00A44784) #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 @@ -299096,7 +307461,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS (0x00A44784) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS (0x00A44788) #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 @@ -299108,7 +307473,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB (0x00A44788) +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB (0x00A4478C) #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -299117,7 +307482,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB (0x00A4478C) +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB (0x00A44790) #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -299129,7 +307494,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA (0x00A44790) +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA (0x00A44794) #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -299138,7 +307503,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET (0x00A44794) +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET (0x00A44798) #define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -299147,7 +307512,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB (0x00A44798) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB (0x00A4479C) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -299156,7 +307521,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB (0x00A4479C) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB (0x00A447A0) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_SIZE___POR 0x00000 @@ -299168,7 +307533,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___M 0x0FFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID (0x00A447A0) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID (0x00A447A4) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID__ENTRY_SIZE___POR 0x00 @@ -299177,7 +307542,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___M 0x000000FF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS (0x00A447A4) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS (0x00A447A8) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -299189,7 +307554,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC (0x00A447A8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC (0x00A447AC) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SPARE_CONTROL___POR 0x00 @@ -299228,7 +307593,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___M 0x003FFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB (0x00A447B4) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB (0x00A447B8) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 @@ -299237,7 +307602,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB (0x00A447B8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB (0x00A447BC) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 @@ -299246,7 +307611,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 (0x00A447C8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 (0x00A447CC) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -299261,7 +307626,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 (0x00A447CC) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 (0x00A447D0) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 @@ -299270,7 +307635,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS (0x00A447D0) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS (0x00A447D4) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -299285,7 +307650,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER (0x00A447D4) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER (0x00A447D8) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 @@ -299294,7 +307659,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER (0x00A447D8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER (0x00A447DC) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 @@ -299303,7 +307668,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS (0x00A447DC) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS (0x00A447E0) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 @@ -299315,7 +307680,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB (0x00A447E0) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB (0x00A447E4) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -299324,7 +307689,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB (0x00A447E4) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB (0x00A447E8) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -299336,7 +307701,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA (0x00A447E8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA (0x00A447EC) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -299345,7 +307710,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET (0x00A447EC) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET (0x00A447F0) #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -299354,7 +307719,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB (0x00A447F0) +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB (0x00A447F4) #define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -299363,7 +307728,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB (0x00A447F4) +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB (0x00A447F8) #define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_SIZE___POR 0x0000 @@ -299375,7 +307740,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___M 0x00FFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_ID (0x00A447F8) +#define UMAC_TCL_R0_FW2TCL1_RING_ID (0x00A447FC) #define UMAC_TCL_R0_FW2TCL1_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_ID__ENTRY_SIZE___POR 0x00 @@ -299384,7 +307749,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_ID___M 0x000000FF #define UMAC_TCL_R0_FW2TCL1_RING_ID___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_STATUS (0x00A447FC) +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS (0x00A44800) #define UMAC_TCL_R0_FW2TCL1_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_FW2TCL1_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -299396,7 +307761,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_STATUS___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_MISC (0x00A44800) +#define UMAC_TCL_R0_FW2TCL1_RING_MISC (0x00A44804) #define UMAC_TCL_R0_FW2TCL1_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_FW2TCL1_RING_MISC__SPARE_CONTROL___POR 0x00 @@ -299435,7 +307800,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_MISC___M 0x003FFFFF #define UMAC_TCL_R0_FW2TCL1_RING_MISC___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB (0x00A4480C) +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB (0x00A44810) #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 @@ -299444,7 +307809,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB (0x00A44810) +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB (0x00A44814) #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 @@ -299453,7 +307818,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 (0x00A44820) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 (0x00A44824) #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -299468,7 +307833,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 (0x00A44824) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 (0x00A44828) #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 @@ -299477,7 +307842,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS (0x00A44828) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS (0x00A4482C) #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -299492,7 +307857,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER (0x00A4482C) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER (0x00A44830) #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 @@ -299501,7 +307866,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER (0x00A44830) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER (0x00A44834) #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 @@ -299510,7 +307875,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS (0x00A44834) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS (0x00A44838) #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 @@ -299522,7 +307887,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB (0x00A44838) +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB (0x00A4483C) #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -299531,7 +307896,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB (0x00A4483C) +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB (0x00A44840) #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -299543,7 +307908,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA (0x00A44840) +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA (0x00A44844) #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -299552,7 +307917,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET (0x00A44844) +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET (0x00A44848) #define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -299561,7 +307926,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB (0x00A44848) +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB (0x00A4484C) #define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -299570,7 +307935,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB (0x00A4484C) +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB (0x00A44850) #define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000 @@ -299582,7 +307947,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___M 0x00FFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_ID (0x00A44850) +#define UMAC_TCL_R0_TCL2TQM_RING_ID (0x00A44854) #define UMAC_TCL_R0_TCL2TQM_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_ID__RING_ID___POR 0x00 @@ -299594,7 +307959,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_ID___M 0x0000FFFF #define UMAC_TCL_R0_TCL2TQM_RING_ID___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_STATUS (0x00A44854) +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS (0x00A44858) #define UMAC_TCL_R0_TCL2TQM_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_TCL2TQM_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -299606,7 +307971,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_STATUS___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_MISC (0x00A44858) +#define UMAC_TCL_R0_TCL2TQM_RING_MISC (0x00A4485C) #define UMAC_TCL_R0_TCL2TQM_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOP_CNT___POR 0x0 @@ -299648,7 +308013,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_MISC___M 0x03FFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_MISC___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB (0x00A4485C) +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB (0x00A44860) #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 @@ -299657,7 +308022,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB (0x00A44860) +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB (0x00A44864) #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 @@ -299666,7 +308031,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP (0x00A4486C) +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP (0x00A44870) #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -299681,7 +308046,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS (0x00A44870) +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS (0x00A44874) #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -299696,7 +308061,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER (0x00A44874) +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER (0x00A44878) #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 @@ -299705,7 +308070,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___M 0x000003FF #define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB (0x00A44890) +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB (0x00A44894) #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -299714,7 +308079,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB (0x00A44894) +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB (0x00A44898) #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -299726,7 +308091,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA (0x00A44898) +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA (0x00A4489C) #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -299735,7 +308100,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET (0x00A4489C) +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET (0x00A448A0) #define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -299744,7 +308109,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB (0x00A448A0) +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB (0x00A448A4) #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -299753,7 +308118,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB (0x00A448A4) +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB (0x00A448A8) #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_SIZE___POR 0x0000 @@ -299765,7 +308130,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___M 0x00FFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_ID (0x00A448A8) +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID (0x00A448AC) #define UMAC_TCL_R0_TCL_STATUS1_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_ID__RING_ID___POR 0x00 @@ -299777,7 +308142,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_ID___M 0x0000FFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_ID___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS (0x00A448AC) +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS (0x00A448B0) #define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -299789,7 +308154,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC (0x00A448B0) +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC (0x00A448B4) #define UMAC_TCL_R0_TCL_STATUS1_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOP_CNT___POR 0x0 @@ -299831,7 +308196,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_MISC___M 0x03FFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_MISC___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB (0x00A448B4) +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB (0x00A448B8) #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 @@ -299840,7 +308205,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB (0x00A448B8) +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB (0x00A448BC) #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 @@ -299849,7 +308214,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP (0x00A448C4) +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP (0x00A448C8) #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -299864,7 +308229,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS (0x00A448C8) +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS (0x00A448CC) #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -299879,7 +308244,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER (0x00A448CC) +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER (0x00A448D0) #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 @@ -299888,7 +308253,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___M 0x000003FF #define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB (0x00A448E8) +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB (0x00A448EC) #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -299897,7 +308262,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB (0x00A448EC) +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB (0x00A448F0) #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -299909,7 +308274,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA (0x00A448F0) +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA (0x00A448F4) #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -299918,7 +308283,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET (0x00A448F4) +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET (0x00A448F8) #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -299927,7 +308292,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB (0x00A448F8) +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB (0x00A448FC) #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -299936,7 +308301,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB (0x00A448FC) +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB (0x00A44900) #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_SIZE___POR 0x0000 @@ -299948,7 +308313,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___M 0x00FFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_ID (0x00A44900) +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID (0x00A44904) #define UMAC_TCL_R0_TCL_STATUS2_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_ID__RING_ID___POR 0x00 @@ -299960,7 +308325,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_ID___M 0x0000FFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_ID___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS (0x00A44904) +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS (0x00A44908) #define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -299972,7 +308337,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC (0x00A44908) +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC (0x00A4490C) #define UMAC_TCL_R0_TCL_STATUS2_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOP_CNT___POR 0x0 @@ -300014,7 +308379,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_MISC___M 0x03FFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_MISC___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB (0x00A4490C) +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB (0x00A44910) #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 @@ -300023,7 +308388,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB (0x00A44910) +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB (0x00A44914) #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 @@ -300032,7 +308397,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP (0x00A4491C) +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP (0x00A44920) #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -300047,7 +308412,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS (0x00A44920) +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS (0x00A44924) #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -300062,7 +308427,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER (0x00A44924) +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER (0x00A44928) #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 @@ -300071,7 +308436,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___M 0x000003FF #define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB (0x00A44940) +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB (0x00A44944) #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -300080,7 +308445,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB (0x00A44944) +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB (0x00A44948) #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -300092,7 +308457,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA (0x00A44948) +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA (0x00A4494C) #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -300101,7 +308466,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET (0x00A4494C) +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET (0x00A44950) #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -300110,7 +308475,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB (0x00A44950) +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB (0x00A44954) #define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 @@ -300119,7 +308484,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB (0x00A44954) +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB (0x00A44958) #define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_SIZE___POR 0x0000 @@ -300131,7 +308496,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___M 0x00FFFFFF #define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_ID (0x00A44958) +#define UMAC_TCL_R0_TCL2FW_RING_ID (0x00A4495C) #define UMAC_TCL_R0_TCL2FW_RING_ID___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_ID___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_ID__RING_ID___POR 0x00 @@ -300143,7 +308508,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_ID___M 0x0000FFFF #define UMAC_TCL_R0_TCL2FW_RING_ID___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_STATUS (0x00A4495C) +#define UMAC_TCL_R0_TCL2FW_RING_STATUS (0x00A44960) #define UMAC_TCL_R0_TCL2FW_RING_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_TCL2FW_RING_STATUS___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 @@ -300155,7 +308520,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2FW_RING_STATUS___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_MISC (0x00A44960) +#define UMAC_TCL_R0_TCL2FW_RING_MISC (0x00A44964) #define UMAC_TCL_R0_TCL2FW_RING_MISC___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_MISC___POR 0x00000080 #define UMAC_TCL_R0_TCL2FW_RING_MISC__LOOP_CNT___POR 0x0 @@ -300197,7 +308562,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_MISC___M 0x03FFFFFF #define UMAC_TCL_R0_TCL2FW_RING_MISC___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB (0x00A44964) +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB (0x00A44968) #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 @@ -300206,7 +308571,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB (0x00A44968) +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB (0x00A4496C) #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 @@ -300215,7 +308580,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___M 0x000000FF #define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP (0x00A44974) +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP (0x00A44978) #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 @@ -300230,7 +308595,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS (0x00A44978) +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS (0x00A4497C) #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 @@ -300245,7 +308610,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER (0x00A4497C) +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER (0x00A44980) #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 @@ -300254,7 +308619,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF #define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB (0x00A44998) +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB (0x00A4499C) #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 @@ -300263,7 +308628,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB (0x00A4499C) +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB (0x00A449A0) #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 @@ -300275,7 +308640,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___M 0x000001FF #define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA (0x00A449A0) +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA (0x00A449A4) #define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA__VALUE___POR 0x00000000 @@ -300284,7 +308649,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___M 0xFFFFFFFF #define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___S 0 -#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET (0x00A449A4) +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET (0x00A449A8) #define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW #define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___POR 0x00000000 #define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 @@ -300293,7 +308658,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF #define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___S 0 -#define UMAC_TCL_R0_GXI_TESTBUS_LOWER (0x00A449A8) +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER (0x00A449AC) #define UMAC_TCL_R0_GXI_TESTBUS_LOWER___RWC QCSR_REG_RO #define UMAC_TCL_R0_GXI_TESTBUS_LOWER___POR 0x00000000 #define UMAC_TCL_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000 @@ -300302,7 +308667,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_TESTBUS_LOWER___M 0xFFFFFFFF #define UMAC_TCL_R0_GXI_TESTBUS_LOWER___S 0 -#define UMAC_TCL_R0_GXI_TESTBUS_UPPER (0x00A449AC) +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER (0x00A449B0) #define UMAC_TCL_R0_GXI_TESTBUS_UPPER___RWC QCSR_REG_RO #define UMAC_TCL_R0_GXI_TESTBUS_UPPER___POR 0x00000000 #define UMAC_TCL_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00 @@ -300311,7 +308676,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_TESTBUS_UPPER___M 0x000000FF #define UMAC_TCL_R0_GXI_TESTBUS_UPPER___S 0 -#define UMAC_TCL_R0_GXI_SM_STATES_IX_0 (0x00A449B0) +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0 (0x00A449B4) #define UMAC_TCL_R0_GXI_SM_STATES_IX_0___RWC QCSR_REG_RO #define UMAC_TCL_R0_GXI_SM_STATES_IX_0___POR 0x00000211 #define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1 @@ -300326,7 +308691,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_SM_STATES_IX_0___M 0x00000FFF #define UMAC_TCL_R0_GXI_SM_STATES_IX_0___S 0 -#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK (0x00A449B4) +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK (0x00A449B8) #define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000 #define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 @@ -300335,7 +308700,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___M 0x00000001 #define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___S 0 -#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE (0x00A449B8) +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE (0x00A449BC) #define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000 #define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0 @@ -300380,7 +308745,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF #define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___S 0 -#define UMAC_TCL_R0_GXI_GXI_ERR_INTS (0x00A449BC) +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS (0x00A449C0) #define UMAC_TCL_R0_GXI_GXI_ERR_INTS___RWC QCSR_REG_RO #define UMAC_TCL_R0_GXI_GXI_ERR_INTS___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0 @@ -300398,7 +308763,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_ERR_INTS___M 0x01010101 #define UMAC_TCL_R0_GXI_GXI_ERR_INTS___S 0 -#define UMAC_TCL_R0_GXI_GXI_ERR_STATS (0x00A449C0) +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS (0x00A449C4) #define UMAC_TCL_R0_GXI_GXI_ERR_STATS___RWC QCSR_REG_RO #define UMAC_TCL_R0_GXI_GXI_ERR_STATS___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00 @@ -300413,7 +308778,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_ERR_STATS___M 0x003F3F3F #define UMAC_TCL_R0_GXI_GXI_ERR_STATS___S 0 -#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL (0x00A449C4) +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL (0x00A449C8) #define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00 @@ -300431,7 +308796,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F #define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___S 0 -#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL (0x00A449C8) +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL (0x00A449CC) #define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00 @@ -300449,7 +308814,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F #define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___S 0 -#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL (0x00A449CC) +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL (0x00A449D0) #define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000 #define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0 @@ -300485,7 +308850,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___M 0x0FFFFFFF #define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___S 0 -#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL (0x00A449D0) +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL (0x00A449D4) #define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000 #define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF @@ -300497,7 +308862,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___M 0xFFFF0001 #define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___S 0 -#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS (0x00A449D4) +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS (0x00A449D8) #define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___RWC QCSR_REG_RO #define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000 @@ -300506,7 +308871,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___M 0x0000FFFF #define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___S 0 -#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS (0x00A449D8) +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS (0x00A449DC) #define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___RWC QCSR_REG_RO #define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000 @@ -300518,7 +308883,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___M 0xFFFFFFFF #define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___S 0 -#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL (0x00A449DC) +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL (0x00A449E0) #define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 @@ -300533,7 +308898,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF #define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___S 0 -#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL (0x00A449E0) +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL (0x00A449E4) #define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 @@ -300548,7 +308913,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF #define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___S 0 -#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A449E4) +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A449E8) #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 @@ -300557,7 +308922,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S 0 -#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A449E8) +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A449EC) #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 @@ -300566,7 +308931,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF #define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S 0 -#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A449EC) +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A449F0) #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 @@ -300575,7 +308940,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S 0 -#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A449F0) +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A449F4) #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 @@ -300584,7 +308949,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF #define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S 0 -#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL (0x00A449F4) +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL (0x00A449F8) #define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW #define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000 #define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0 @@ -300602,7 +308967,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F #define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___S 0 -#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW (0x00A449F8) +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW (0x00A449FC) #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___RWC QCSR_REG_RW #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___POR 0x00000000 #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000 @@ -300611,7 +308976,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___M 0xFFFFFFFF #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___S 0 -#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH (0x00A449FC) +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH (0x00A44A00) #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___RWC QCSR_REG_RW #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___POR 0x00000000 #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH__VAL___POR 0x00 @@ -300620,7 +308985,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___M 0x000000FF #define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___S 0 -#define UMAC_TCL_R0_ASE_GST_SIZE (0x00A44A00) +#define UMAC_TCL_R0_ASE_GST_SIZE (0x00A44A04) #define UMAC_TCL_R0_ASE_GST_SIZE___RWC QCSR_REG_RW #define UMAC_TCL_R0_ASE_GST_SIZE___POR 0x00000000 #define UMAC_TCL_R0_ASE_GST_SIZE__VAL___POR 0x00000 @@ -300629,7 +308994,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_ASE_GST_SIZE___M 0x000FFFFF #define UMAC_TCL_R0_ASE_GST_SIZE___S 0 -#define UMAC_TCL_R0_ASE_SEARCH_CTRL (0x00A44A04) +#define UMAC_TCL_R0_ASE_SEARCH_CTRL (0x00A44A08) #define UMAC_TCL_R0_ASE_SEARCH_CTRL___RWC QCSR_REG_RW #define UMAC_TCL_R0_ASE_SEARCH_CTRL___POR 0x00003806 #define UMAC_TCL_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000 @@ -300659,7 +309024,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_ASE_SEARCH_CTRL___M 0xFFFF3FFF #define UMAC_TCL_R0_ASE_SEARCH_CTRL___S 0 -#define UMAC_TCL_R0_ASE_WATCHDOG (0x00A44A08) +#define UMAC_TCL_R0_ASE_WATCHDOG (0x00A44A0C) #define UMAC_TCL_R0_ASE_WATCHDOG___RWC QCSR_REG_RW #define UMAC_TCL_R0_ASE_WATCHDOG___POR 0x0000FFFF #define UMAC_TCL_R0_ASE_WATCHDOG__STATUS___POR 0x0000 @@ -300671,7 +309036,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_ASE_WATCHDOG___M 0xFFFFFFFF #define UMAC_TCL_R0_ASE_WATCHDOG___S 0 -#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE (0x00A44A0C) +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE (0x00A44A10) #define UMAC_TCL_R0_ASE_CLKGATE_DISABLE___RWC QCSR_REG_RW #define UMAC_TCL_R0_ASE_CLKGATE_DISABLE___POR 0x00000000 #define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 @@ -300713,7 +309078,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R0_ASE_CLKGATE_DISABLE___M 0xFFFFFFFF #define UMAC_TCL_R0_ASE_CLKGATE_DISABLE___S 0 -#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING (0x00A44A10) +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING (0x00A44A14) #define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___RWC QCSR_REG_RO #define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___POR 0x00000000 #define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING__STATUS___POR 0x0 @@ -300737,6 +309102,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_SM_STATES_IX_0 (0x00A45004) #define UMAC_TCL_R1_SM_STATES_IX_0___RWC QCSR_REG_RO #define UMAC_TCL_R1_SM_STATES_IX_0___POR 0x00000000 +#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL_RES_WR___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___POR 0x0 @@ -300746,9 +309112,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL3_RING___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL2_RING___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___POR 0x0 -#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___M 0x07000000 -#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___S 24 -#define UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___M 0x00E00000 +#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL_RES_WR___M 0x30000000 +#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL_RES_WR___S 28 +#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___M 0x0E000000 +#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___S 25 +#define UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___M 0x01E00000 #define UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___S 21 #define UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___M 0x001C0000 #define UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___S 18 @@ -300764,18 +309132,21 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL2_RING___S 3 #define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___M 0x00000007 #define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___S 0 -#define UMAC_TCL_R1_SM_STATES_IX_0___M 0x07FFFFFF +#define UMAC_TCL_R1_SM_STATES_IX_0___M 0x3FFFFFFF #define UMAC_TCL_R1_SM_STATES_IX_0___S 0 #define UMAC_TCL_R1_SM_STATES_IX_1 (0x00A45008) #define UMAC_TCL_R1_SM_STATES_IX_1___RWC QCSR_REG_RO #define UMAC_TCL_R1_SM_STATES_IX_1___POR 0x00000000 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_IDLE_SEQUENCE___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_1__PROD_CTRL___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS2___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS1___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_1__TCL2FW___POR 0x0 #define UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_IDLE_SEQUENCE___M 0x001C0000 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_IDLE_SEQUENCE___S 18 #define UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___M 0x00038000 #define UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___S 15 #define UMAC_TCL_R1_SM_STATES_IX_1__PROD_CTRL___M 0x00007000 @@ -300788,10 +309159,97 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_SM_STATES_IX_1__TCL2FW___S 3 #define UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___M 0x00000007 #define UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___S 0 -#define UMAC_TCL_R1_SM_STATES_IX_1___M 0x0003FFFF +#define UMAC_TCL_R1_SM_STATES_IX_1___M 0x001FFFFF #define UMAC_TCL_R1_SM_STATES_IX_1___S 0 -#define UMAC_TCL_R1_TESTBUS_CTRL_0 (0x00A4500C) +#define UMAC_TCL_R1_STATUS (0x00A4500C) +#define UMAC_TCL_R1_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R1_STATUS___POR 0x00000000 +#define UMAC_TCL_R1_STATUS__HDR_BUF_EMPTY___POR 0x0 +#define UMAC_TCL_R1_STATUS__DESC_BUF_EMPTY___POR 0x0 +#define UMAC_TCL_R1_STATUS__GSE_CCE_RES_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__PROD_RING_BUNC_FIFO_CTRL_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__PROD_RING_CTRL_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__TLV_DECODER_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__TLV_GEN_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__GSE_CTRL_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__CLFY_WRAP_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__CCE_OR_LCE_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__ASE_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__PARSER_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__TCL_STATUS2_PROD_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__TCL_STATUS1_PROD_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__TCL2FW_PROD_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__TCL2TQM_PROD_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__SW2TCL_CREDIT_CONS_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__FW2TCL1_CONS_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__SW2TCL3_CONS_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__SW2TCL2_CONS_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__SW2TCL1_CONS_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__GXI_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__DESC_RD_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__SDU_HDR_FETCH_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__LINK_DESC_FETCH_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__DATA_FETCH_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__TCL_INT_IDLE___POR 0x0 +#define UMAC_TCL_R1_STATUS__HDR_BUF_EMPTY___M 0x04000000 +#define UMAC_TCL_R1_STATUS__HDR_BUF_EMPTY___S 26 +#define UMAC_TCL_R1_STATUS__DESC_BUF_EMPTY___M 0x02000000 +#define UMAC_TCL_R1_STATUS__DESC_BUF_EMPTY___S 25 +#define UMAC_TCL_R1_STATUS__GSE_CCE_RES_IDLE___M 0x01000000 +#define UMAC_TCL_R1_STATUS__GSE_CCE_RES_IDLE___S 24 +#define UMAC_TCL_R1_STATUS__PROD_RING_BUNC_FIFO_CTRL_IDLE___M 0x00800000 +#define UMAC_TCL_R1_STATUS__PROD_RING_BUNC_FIFO_CTRL_IDLE___S 23 +#define UMAC_TCL_R1_STATUS__PROD_RING_CTRL_IDLE___M 0x00400000 +#define UMAC_TCL_R1_STATUS__PROD_RING_CTRL_IDLE___S 22 +#define UMAC_TCL_R1_STATUS__TLV_DECODER_IDLE___M 0x00200000 +#define UMAC_TCL_R1_STATUS__TLV_DECODER_IDLE___S 21 +#define UMAC_TCL_R1_STATUS__TLV_GEN_IDLE___M 0x00100000 +#define UMAC_TCL_R1_STATUS__TLV_GEN_IDLE___S 20 +#define UMAC_TCL_R1_STATUS__GSE_CTRL_IDLE___M 0x00080000 +#define UMAC_TCL_R1_STATUS__GSE_CTRL_IDLE___S 19 +#define UMAC_TCL_R1_STATUS__CLFY_WRAP_IDLE___M 0x00040000 +#define UMAC_TCL_R1_STATUS__CLFY_WRAP_IDLE___S 18 +#define UMAC_TCL_R1_STATUS__CCE_OR_LCE_IDLE___M 0x00020000 +#define UMAC_TCL_R1_STATUS__CCE_OR_LCE_IDLE___S 17 +#define UMAC_TCL_R1_STATUS__ASE_IDLE___M 0x00010000 +#define UMAC_TCL_R1_STATUS__ASE_IDLE___S 16 +#define UMAC_TCL_R1_STATUS__PARSER_IDLE___M 0x00008000 +#define UMAC_TCL_R1_STATUS__PARSER_IDLE___S 15 +#define UMAC_TCL_R1_STATUS__TCL_STATUS2_PROD_IDLE___M 0x00004000 +#define UMAC_TCL_R1_STATUS__TCL_STATUS2_PROD_IDLE___S 14 +#define UMAC_TCL_R1_STATUS__TCL_STATUS1_PROD_IDLE___M 0x00002000 +#define UMAC_TCL_R1_STATUS__TCL_STATUS1_PROD_IDLE___S 13 +#define UMAC_TCL_R1_STATUS__TCL2FW_PROD_IDLE___M 0x00001000 +#define UMAC_TCL_R1_STATUS__TCL2FW_PROD_IDLE___S 12 +#define UMAC_TCL_R1_STATUS__TCL2TQM_PROD_IDLE___M 0x00000800 +#define UMAC_TCL_R1_STATUS__TCL2TQM_PROD_IDLE___S 11 +#define UMAC_TCL_R1_STATUS__SW2TCL_CREDIT_CONS_IDLE___M 0x00000400 +#define UMAC_TCL_R1_STATUS__SW2TCL_CREDIT_CONS_IDLE___S 10 +#define UMAC_TCL_R1_STATUS__FW2TCL1_CONS_IDLE___M 0x00000200 +#define UMAC_TCL_R1_STATUS__FW2TCL1_CONS_IDLE___S 9 +#define UMAC_TCL_R1_STATUS__SW2TCL3_CONS_IDLE___M 0x00000100 +#define UMAC_TCL_R1_STATUS__SW2TCL3_CONS_IDLE___S 8 +#define UMAC_TCL_R1_STATUS__SW2TCL2_CONS_IDLE___M 0x00000080 +#define UMAC_TCL_R1_STATUS__SW2TCL2_CONS_IDLE___S 7 +#define UMAC_TCL_R1_STATUS__SW2TCL1_CONS_IDLE___M 0x00000040 +#define UMAC_TCL_R1_STATUS__SW2TCL1_CONS_IDLE___S 6 +#define UMAC_TCL_R1_STATUS__GXI_IDLE___M 0x00000020 +#define UMAC_TCL_R1_STATUS__GXI_IDLE___S 5 +#define UMAC_TCL_R1_STATUS__DESC_RD_IDLE___M 0x00000010 +#define UMAC_TCL_R1_STATUS__DESC_RD_IDLE___S 4 +#define UMAC_TCL_R1_STATUS__SDU_HDR_FETCH_IDLE___M 0x00000008 +#define UMAC_TCL_R1_STATUS__SDU_HDR_FETCH_IDLE___S 3 +#define UMAC_TCL_R1_STATUS__LINK_DESC_FETCH_IDLE___M 0x00000004 +#define UMAC_TCL_R1_STATUS__LINK_DESC_FETCH_IDLE___S 2 +#define UMAC_TCL_R1_STATUS__DATA_FETCH_IDLE___M 0x00000002 +#define UMAC_TCL_R1_STATUS__DATA_FETCH_IDLE___S 1 +#define UMAC_TCL_R1_STATUS__TCL_INT_IDLE___M 0x00000001 +#define UMAC_TCL_R1_STATUS__TCL_INT_IDLE___S 0 +#define UMAC_TCL_R1_STATUS___M 0x07FFFFFF +#define UMAC_TCL_R1_STATUS___S 0 + +#define UMAC_TCL_R1_TESTBUS_CTRL_0 (0x00A45010) #define UMAC_TCL_R1_TESTBUS_CTRL_0___RWC QCSR_REG_RW #define UMAC_TCL_R1_TESTBUS_CTRL_0___POR 0x00000000 #define UMAC_TCL_R1_TESTBUS_CTRL_0__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0 @@ -300818,7 +309276,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_TESTBUS_CTRL_0___M 0x3FFFFFFF #define UMAC_TCL_R1_TESTBUS_CTRL_0___S 0 -#define UMAC_TCL_R1_TESTBUS_LOW (0x00A45010) +#define UMAC_TCL_R1_TESTBUS_LOW (0x00A45014) #define UMAC_TCL_R1_TESTBUS_LOW___RWC QCSR_REG_RO #define UMAC_TCL_R1_TESTBUS_LOW___POR 0x00000000 #define UMAC_TCL_R1_TESTBUS_LOW__VAL___POR 0x00000000 @@ -300827,7 +309285,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_TESTBUS_LOW___M 0xFFFFFFFF #define UMAC_TCL_R1_TESTBUS_LOW___S 0 -#define UMAC_TCL_R1_TESTBUS_HIGH (0x00A45014) +#define UMAC_TCL_R1_TESTBUS_HIGH (0x00A45018) #define UMAC_TCL_R1_TESTBUS_HIGH___RWC QCSR_REG_RO #define UMAC_TCL_R1_TESTBUS_HIGH___POR 0x00000000 #define UMAC_TCL_R1_TESTBUS_HIGH__VAL___POR 0x00 @@ -300836,7 +309294,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_TESTBUS_HIGH___M 0x000000FF #define UMAC_TCL_R1_TESTBUS_HIGH___S 0 -#define UMAC_TCL_R1_EVENTMASK_IX_0 (0x00A45018) +#define UMAC_TCL_R1_EVENTMASK_IX_0 (0x00A4501C) #define UMAC_TCL_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW #define UMAC_TCL_R1_EVENTMASK_IX_0___POR 0x0000FFFF #define UMAC_TCL_R1_EVENTMASK_IX_0__VAL___POR 0x0000FFFF @@ -300845,7 +309303,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_EVENTMASK_IX_0___M 0xFFFFFFFF #define UMAC_TCL_R1_EVENTMASK_IX_0___S 0 -#define UMAC_TCL_R1_EVENTMASK_IX_1 (0x00A4501C) +#define UMAC_TCL_R1_EVENTMASK_IX_1 (0x00A45020) #define UMAC_TCL_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW #define UMAC_TCL_R1_EVENTMASK_IX_1___POR 0x0000FFFF #define UMAC_TCL_R1_EVENTMASK_IX_1__VAL___POR 0x0000FFFF @@ -300854,7 +309312,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_EVENTMASK_IX_1___M 0xFFFFFFFF #define UMAC_TCL_R1_EVENTMASK_IX_1___S 0 -#define UMAC_TCL_R1_EVENTMASK_IX_2 (0x00A45020) +#define UMAC_TCL_R1_EVENTMASK_IX_2 (0x00A45024) #define UMAC_TCL_R1_EVENTMASK_IX_2___RWC QCSR_REG_RW #define UMAC_TCL_R1_EVENTMASK_IX_2___POR 0x0000FFFF #define UMAC_TCL_R1_EVENTMASK_IX_2__VAL___POR 0x0000FFFF @@ -300863,7 +309321,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_EVENTMASK_IX_2___M 0xFFFFFFFF #define UMAC_TCL_R1_EVENTMASK_IX_2___S 0 -#define UMAC_TCL_R1_EVENTMASK_IX_3 (0x00A45024) +#define UMAC_TCL_R1_EVENTMASK_IX_3 (0x00A45028) #define UMAC_TCL_R1_EVENTMASK_IX_3___RWC QCSR_REG_RW #define UMAC_TCL_R1_EVENTMASK_IX_3___POR 0x0000FFFF #define UMAC_TCL_R1_EVENTMASK_IX_3__VAL___POR 0x0000FFFF @@ -300872,7 +309330,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_EVENTMASK_IX_3___M 0xFFFFFFFF #define UMAC_TCL_R1_EVENTMASK_IX_3___S 0 -#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A45028) +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A4502C) #define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW #define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 #define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF @@ -300890,7 +309348,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF #define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 -#define UMAC_TCL_R1_SPARE_REGISTER (0x00A4502C) +#define UMAC_TCL_R1_SPARE_REGISTER (0x00A45030) #define UMAC_TCL_R1_SPARE_REGISTER___RWC QCSR_REG_RW #define UMAC_TCL_R1_SPARE_REGISTER___POR 0x00000000 #define UMAC_TCL_R1_SPARE_REGISTER__TCL_SPARE_FIELD_32___POR 0x00000000 @@ -300899,7 +309357,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_SPARE_REGISTER___M 0xFFFFFFFF #define UMAC_TCL_R1_SPARE_REGISTER___S 0 -#define UMAC_TCL_R1_END_OF_TEST_CHECK (0x00A45030) +#define UMAC_TCL_R1_END_OF_TEST_CHECK (0x00A45034) #define UMAC_TCL_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW #define UMAC_TCL_R1_END_OF_TEST_CHECK___POR 0x00000000 #define UMAC_TCL_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 @@ -300908,7 +309366,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_END_OF_TEST_CHECK___M 0x00000001 #define UMAC_TCL_R1_END_OF_TEST_CHECK___S 0 -#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK (0x00A45034) +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK (0x00A45038) #define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___RWC QCSR_REG_RW #define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___POR 0x00000000 #define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 @@ -300917,7 +309375,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___M 0x00000001 #define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___S 0 -#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS (0x00A45038) +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS (0x00A4503C) #define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW #define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___POR 0x00000000 #define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0 @@ -300926,7 +309384,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___M 0x00000001 #define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___S 0 -#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A4503C) +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A45040) #define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000 #define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000 @@ -300935,7 +309393,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___S 0 -#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER (0x00A45040) +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER (0x00A45044) #define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000 #define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000 @@ -300944,7 +309402,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___S 0 -#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A45044) +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A45048) #define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000 #define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000 @@ -300956,7 +309414,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF #define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___S 0 -#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER (0x00A45048) +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER (0x00A4504C) #define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000 #define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000 @@ -300971,7 +309429,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF #define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___S 0 -#define UMAC_TCL_R1_ASE_SM_STATES (0x00A4504C) +#define UMAC_TCL_R1_ASE_SM_STATES (0x00A45050) #define UMAC_TCL_R1_ASE_SM_STATES___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_SM_STATES___POR 0x00000000 #define UMAC_TCL_R1_ASE_SM_STATES__GSE_CTRL_STATE___POR 0x0 @@ -300998,7 +309456,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_SM_STATES___M 0x003FFF0F #define UMAC_TCL_R1_ASE_SM_STATES___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG (0x00A45050) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG (0x00A45054) #define UMAC_TCL_R1_ASE_CACHE_DEBUG___RWC QCSR_REG_RW #define UMAC_TCL_R1_ASE_CACHE_DEBUG___POR 0x00000000 #define UMAC_TCL_R1_ASE_CACHE_DEBUG__READ_IDX___POR 0x000 @@ -301007,7 +309465,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_CACHE_DEBUG___M 0x000003FF #define UMAC_TCL_R1_ASE_CACHE_DEBUG___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS (0x00A45054) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS (0x00A45058) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000 #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000 @@ -301025,7 +309483,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n(n) (0x00A45058+0x4*(n)) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n(n) (0x00A4505C+0x4*(n)) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_nMIN 0 #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_nMAX 31 #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ELEM 32 @@ -301036,131 +309494,131 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___S 0 #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0 (0x00A45058) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0 (0x00A4505C) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1 (0x00A4505C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1 (0x00A45060) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2 (0x00A45060) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2 (0x00A45064) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3 (0x00A45064) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3 (0x00A45068) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4 (0x00A45068) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4 (0x00A4506C) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5 (0x00A4506C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5 (0x00A45070) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6 (0x00A45070) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6 (0x00A45074) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7 (0x00A45074) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7 (0x00A45078) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8 (0x00A45078) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8 (0x00A4507C) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9 (0x00A4507C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9 (0x00A45080) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10 (0x00A45080) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10 (0x00A45084) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11 (0x00A45084) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11 (0x00A45088) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12 (0x00A45088) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12 (0x00A4508C) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13 (0x00A4508C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13 (0x00A45090) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14 (0x00A45090) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14 (0x00A45094) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15 (0x00A45094) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15 (0x00A45098) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16 (0x00A45098) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16 (0x00A4509C) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17 (0x00A4509C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17 (0x00A450A0) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18 (0x00A450A0) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18 (0x00A450A4) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19 (0x00A450A4) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19 (0x00A450A8) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20 (0x00A450A8) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20 (0x00A450AC) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21 (0x00A450AC) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21 (0x00A450B0) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22 (0x00A450B0) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22 (0x00A450B4) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23 (0x00A450B4) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23 (0x00A450B8) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24 (0x00A450B8) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24 (0x00A450BC) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25 (0x00A450BC) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25 (0x00A450C0) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26 (0x00A450C0) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26 (0x00A450C4) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27 (0x00A450C4) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27 (0x00A450C8) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28 (0x00A450C8) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28 (0x00A450CC) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29 (0x00A450CC) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29 (0x00A450D0) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30 (0x00A450D0) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30 (0x00A450D4) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___S 0 -#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31 (0x00A450D4) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31 (0x00A450D8) #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF #define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___S 0 @@ -302007,11 +310465,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_FEATURE_ENABLE_II (0x00A80014) #define WMAC0_PDG_R0_FEATURE_ENABLE_II___RWC QCSR_REG_RW -#define WMAC0_PDG_R0_FEATURE_ENABLE_II___POR 0x00005973 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II___POR 0x0020D171 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_OBSS_SR_POWER_FIX___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_FIX_SIMUL_TX_FLUSH_PDG_RESP_TLV___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_EXCEED_SKIP_ZERO_LEN_TID___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TID_LIMIT_LENGTH_CHECK___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_FIT_AVAILABLE_USERS___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__SEPARATE_MIN_DUR_EN___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__WAIT_FOR_ALL_TIDS___POR 0x1 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___POR 0x1 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SU_MU_OFDMA_UPDATES___POR 0x0 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_MMSB___POR 0x1 -#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_FDPB___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_FDPB___POR 0x0 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__MD_THRESHOLD_CHK___POR 0x0 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER_MD___POR 0x0 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER___POR 0x1 @@ -302021,8 +310486,22 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_FEATURE_ENABLE_II__PREVENT_UL_RESP_NO_MPDU_INFO_SFM_ACCESS___POR 0x1 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_PROTECT_EXT_DUR_ADDITION___POR 0x0 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__CALC_ACCURATE_MIN_MPDU_DURATION_BITS___POR 0x0 -#define WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___POR 0x0 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_OBSS_SR_POWER_FIX___M 0x00200000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_OBSS_SR_POWER_FIX___S 21 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_FIX_SIMUL_TX_FLUSH_PDG_RESP_TLV___M 0x00100000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_FIX_SIMUL_TX_FLUSH_PDG_RESP_TLV___S 20 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_EXCEED_SKIP_ZERO_LEN_TID___M 0x00080000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_EXCEED_SKIP_ZERO_LEN_TID___S 19 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TID_LIMIT_LENGTH_CHECK___M 0x00040000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TID_LIMIT_LENGTH_CHECK___S 18 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_FIT_AVAILABLE_USERS___M 0x00020000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_FIT_AVAILABLE_USERS___S 17 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__SEPARATE_MIN_DUR_EN___M 0x00010000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__SEPARATE_MIN_DUR_EN___S 16 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__WAIT_FOR_ALL_TIDS___M 0x00008000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__WAIT_FOR_ALL_TIDS___S 15 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___M 0x00004000 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___S 14 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SU_MU_OFDMA_UPDATES___M 0x00002000 @@ -302053,7 +310532,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___S 1 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___M 0x00000001 #define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___S 0 -#define WMAC0_PDG_R0_FEATURE_ENABLE_II___M 0x00007FFF +#define WMAC0_PDG_R0_FEATURE_ENABLE_II___M 0x003FFFFF #define WMAC0_PDG_R0_FEATURE_ENABLE_II___S 0 #define WMAC0_PDG_R0_SPARE_REG (0x00A80018) @@ -303640,20 +312119,35 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_ILP_REGS (0x00A80220) #define WMAC0_PDG_R0_ILP_REGS___RWC QCSR_REG_RW -#define WMAC0_PDG_R0_ILP_REGS___POR 0x000044A3 -#define WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___POR 0x22 +#define WMAC0_PDG_R0_ILP_REGS___POR 0x000052A2 +#define WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___POR 0x029 #define WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___POR 0x51 -#define WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___POR 0x1 -#define WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___M 0x00007E00 +#define WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___POR 0x0 +#define WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___M 0x001FFE00 #define WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___S 9 #define WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___M 0x000001FE #define WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___S 1 #define WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___M 0x00000001 #define WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___S 0 -#define WMAC0_PDG_R0_ILP_REGS___M 0x00007FFF +#define WMAC0_PDG_R0_ILP_REGS___M 0x001FFFFF #define WMAC0_PDG_R0_ILP_REGS___S 0 -#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE (0x00A80224) +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS (0x00A80224) +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS___POR 0x00005EA2 +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__UNASSOC_UORA_BFRP_MIN_MPDU_BYTES___POR 0x02F +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__UNASSOC_UORA_BFRP_PHY_MAC_PCIE_LATENCY___POR 0x51 +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__ENABLE_UNASSOC_UORA_BFRP_FIT_CHECK___POR 0x0 +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__UNASSOC_UORA_BFRP_MIN_MPDU_BYTES___M 0x001FFE00 +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__UNASSOC_UORA_BFRP_MIN_MPDU_BYTES___S 9 +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__UNASSOC_UORA_BFRP_PHY_MAC_PCIE_LATENCY___M 0x000001FE +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__UNASSOC_UORA_BFRP_PHY_MAC_PCIE_LATENCY___S 1 +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__ENABLE_UNASSOC_UORA_BFRP_FIT_CHECK___M 0x00000001 +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS__ENABLE_UNASSOC_UORA_BFRP_FIT_CHECK___S 0 +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS___M 0x001FFFFF +#define WMAC0_PDG_R0_UNASSOC_UORA_BFRP_REGS___S 0 + +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE (0x00A80228) #define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___RWC QCSR_REG_RW #define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___POR 0x00000000 #define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0 @@ -303680,7 +312174,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___M 0x0000007F #define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___S 0 -#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE (0x00A80228) +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE (0x00A8022C) #define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___RWC QCSR_REG_RW #define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___POR 0x00000000 #define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0 @@ -303707,7 +312201,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___M 0x0000007F #define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___S 0 -#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE (0x00A8022C) +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE (0x00A80230) #define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___RWC QCSR_REG_RW #define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___POR 0x00000000 #define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0 @@ -303734,7 +312228,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___M 0x0000007F #define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___S 0 -#define WMAC0_PDG_R0_COEX_CTS_OFFSET (0x00A80230) +#define WMAC0_PDG_R0_COEX_CTS_OFFSET (0x00A80234) #define WMAC0_PDG_R0_COEX_CTS_OFFSET___RWC QCSR_REG_RW #define WMAC0_PDG_R0_COEX_CTS_OFFSET___POR 0x00000000 #define WMAC0_PDG_R0_COEX_CTS_OFFSET__COEX_CTS_OFFSET___POR 0x0000 @@ -303743,7 +312237,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_COEX_CTS_OFFSET___M 0x0000FFFF #define WMAC0_PDG_R0_COEX_CTS_OFFSET___S 0 -#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION (0x00A80234) +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION (0x00A80238) #define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___RWC QCSR_REG_RW #define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___POR 0x00000000 #define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION__COEX_CTS_MIN_DURATION___POR 0x0000 @@ -303752,7 +312246,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___M 0x0000FFFF #define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___S 0 -#define WMAC0_PDG_R0_COEX_CTS_MODE (0x00A80238) +#define WMAC0_PDG_R0_COEX_CTS_MODE (0x00A8023C) #define WMAC0_PDG_R0_COEX_CTS_MODE___RWC QCSR_REG_RW #define WMAC0_PDG_R0_COEX_CTS_MODE___POR 0x00000000 #define WMAC0_PDG_R0_COEX_CTS_MODE__COEX_CTS_MODE___POR 0x0 @@ -303761,7 +312255,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_PDG_R0_COEX_CTS_MODE___M 0x00000003 #define WMAC0_PDG_R0_COEX_CTS_MODE___S 0 -#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY (0x00A8023C) +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY (0x00A80240) #define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___RWC QCSR_REG_RW #define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___POR 0x00000000 #define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY__VALUE___POR 0x0 @@ -307774,7 +316268,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2 (0x00A86444) #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___RWC QCSR_REG_RW -#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___POR 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___POR 0x00000220 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__CLKGATE_REGISTER_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__MSI_DISABLE_ON_IDLE_REQ_CTL___POR 0x1 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___POR 0x0 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_FIFO_PENDING_EN___POR 0x0 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_WRITE_AT_USER_STATS_TRIG_EN___POR 0x1 @@ -307783,6 +316279,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_MSDU_END_EN___POR 0x0 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__IDLE_FLAG___POR 0x0 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__CLKGATE_REGISTER_DISABLE___M 0x00000400 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__CLKGATE_REGISTER_DISABLE___S 10 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__MSI_DISABLE_ON_IDLE_REQ_CTL___M 0x00000200 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__MSI_DISABLE_ON_IDLE_REQ_CTL___S 9 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___M 0x00000180 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___S 7 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_FIFO_PENDING_EN___M 0x00000040 @@ -307799,7 +316299,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__IDLE_FLAG___S 1 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___M 0x00000001 #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___S 0 -#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___M 0x000007FF #define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___S 0 #define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER (0x00A86448) @@ -307940,7 +316440,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___M 0x003FFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG (0x00A86470) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG (0x00A86470) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG___POR 0x00000A3F +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__COHERENCY_FIX_EN___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_DESC_FIFO_TIMER_SEL___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_WRITE_INACTIVITY_TIMER___POR 0x0A +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_WRITE_THRESHOLD_TIMER___POR 0x3F +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__COHERENCY_FIX_EN___M 0x00020000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__COHERENCY_FIX_EN___S 17 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_DESC_FIFO_TIMER_SEL___M 0x00010000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_DESC_FIFO_TIMER_SEL___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_WRITE_INACTIVITY_TIMER___M 0x0000FF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_WRITE_INACTIVITY_TIMER___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_WRITE_THRESHOLD_TIMER___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG__DEST_WRITE_THRESHOLD_TIMER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG___M 0x0003FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DEST_DESC_FIFO_CFG___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG (0x00A86474) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___POR 0x00000001 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__STATUS___POR 0x0 @@ -307952,7 +316470,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___M 0x00000003 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST (0x00A86474) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST (0x00A86478) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__STATUS___POR 0x0 @@ -307964,7 +316482,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___M 0x00000003 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___S 0 -#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE (0x00A86478) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE (0x00A8647C) #define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RING_THRESHOLD_FILTER_MPDU_DROP___POR 0x0 @@ -307991,7 +316509,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___M 0x0000007F #define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT (0x00A8647C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT (0x00A86480) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT__USER___POR 0x00 @@ -308000,7 +316518,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___M 0x0000003F #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB (0x00A86480) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB (0x00A86484) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000 @@ -308009,7 +316527,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB (0x00A86484) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB (0x00A86488) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000 @@ -308018,7 +316536,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB (0x00A86488) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB (0x00A8648C) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000 @@ -308027,7 +316545,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB (0x00A8648C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB (0x00A86490) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000 @@ -308036,7 +316554,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB (0x00A86490) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB (0x00A86494) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000 @@ -308045,7 +316563,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB (0x00A86494) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB (0x00A86498) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000 @@ -308054,7 +316572,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS (0x00A86498) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS (0x00A8649C) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2REO_DEST_DESC_FIFO_POPCOUNT___POR 0x00 @@ -308084,7 +316602,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___M 0x07FFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH (0x00A8649C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH (0x00A864A0) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2REO_DEST_DESC_FIFO_READ___POR 0x0 @@ -308108,7 +316626,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___M 0x0000003F #define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB (0x00A864A0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB (0x00A864A4) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000 @@ -308117,7 +316635,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB (0x00A864A4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB (0x00A864A8) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000 @@ -308126,7 +316644,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB (0x00A864A8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB (0x00A864AC) #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000 @@ -308135,7 +316653,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB (0x00A864AC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB (0x00A864B0) #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000 @@ -308144,7 +316662,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB (0x00A864B0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB (0x00A864B4) #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000 @@ -308153,7 +316671,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB (0x00A864B4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB (0x00A864B8) #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000 @@ -308162,7 +316680,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB (0x00A864B8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB (0x00A864BC) #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000 @@ -308171,7 +316689,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB (0x00A864BC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB (0x00A864C0) #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000 @@ -308180,7 +316698,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___S 0 -#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT (0x00A864C0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT (0x00A864C4) #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT__TLV_SEQ_USER_STATS___POR 0x00 @@ -308189,7 +316707,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___M 0x0000003F #define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___S 0 -#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR (0x00A864C4) +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR (0x00A864C8) #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR__VALUE___POR 0x000 @@ -308198,7 +316716,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___M 0x000007FF #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___S 0 -#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA (0x00A864C8) +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA (0x00A864CC) #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA__VALUE___POR 0x00000000 @@ -308207,7 +316725,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___S 0 -#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD (0x00A864CC) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD (0x00A864D0) #define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD__COUNT___POR 0x00000000 @@ -308216,7 +316734,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___S 0 -#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD (0x00A864D0) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD (0x00A864D4) #define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD__COUNT___POR 0x00000000 @@ -308225,7 +316743,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___S 0 -#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1 (0x00A864D4) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1 (0x00A864D8) #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__FW_COUNT___POR 0x0000 @@ -308237,7 +316755,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___S 0 -#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2 (0x00A864D8) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2 (0x00A864DC) #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__REO_COUNT___POR 0x0000 @@ -308249,7 +316767,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___S 0 -#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP (0x00A864DC) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP (0x00A864E0) #define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP__COUNT___POR 0x00000000 @@ -308258,7 +316776,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___S 0 -#define WMAC0_RXDMA_RXDMA_R0_WDOG (0x00A864E0) +#define WMAC0_RXDMA_RXDMA_R0_WDOG (0x00A864E4) #define WMAC0_RXDMA_RXDMA_R0_WDOG___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_WDOG___POR 0x0000FFFF #define WMAC0_RXDMA_RXDMA_R0_WDOG__LIMIT___POR 0xFFFF @@ -308267,7 +316785,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_WDOG___M 0x0000FFFF #define WMAC0_RXDMA_RXDMA_R0_WDOG___S 0 -#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL (0x00A864E4) +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL (0x00A864E8) #define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL__SELECT___POR 0x00 @@ -308276,7 +316794,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___M 0x0000003F #define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___S 0 -#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE (0x00A864E8) +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE (0x00A864EC) #define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___RWC QCSR_REG_RW #define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE__DISABLE___POR 0x00000000 @@ -308285,7 +316803,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___M 0xFFFFFFFF #define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___S 0 -#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR (0x00A864EC) +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR (0x00A864F0) #define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO #define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___POR 0x00000000 #define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 @@ -311110,21 +319628,21 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS (0x00A8926C) #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___RWC QCSR_REG_RW -#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___POR 0x000088C8 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___POR 0x00000000 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__LPEC___POR 0x0 -#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__SFM___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__SFM___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__APB_IF___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MAPB_MAC___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_PHY___POR 0x0 -#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXOLE___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXOLE___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXOLE___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RRI___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__CRYPTO___POR 0x0 -#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__HWSCH___POR 0x1 -#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MXI___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__HWSCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MXI___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__PDG___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXDMA___POR 0x0 -#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXPCU___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXPCU___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXDMA___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXPCU___POR 0x0 #define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_MAC___POR 0x0 @@ -311285,6 +319803,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE (0x00A89278) #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___RWC QCSR_REG_RW #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MCMN___POR 0x0 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___POR 0x0 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__SFM___POR 0x0 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXOLE___POR 0x0 @@ -311299,6 +319818,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXDMA___POR 0x0 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXPCU___POR 0x0 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MCMN___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MCMN___S 15 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___M 0x00004000 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___S 14 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__SFM___M 0x00001000 @@ -311327,7 +319848,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXPCU___S 1 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___M 0x00000001 #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___S 0 -#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___M 0x00005FFF +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___M 0x0000DFFF #define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___S 0 #define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE (0x00A8927C) @@ -312078,7 +320599,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ENABLE___S 0 #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ (0x00A8A064) -#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ__COUNT___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ__COUNT___M 0xFFFFFFFF @@ -312087,7 +320608,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___S 0 #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME (0x00A8A068) -#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME__DURATION___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME__DURATION___M 0xFFFFFFFF @@ -312096,7 +320617,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___S 0 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ (0x00A8A06C) -#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ__COUNT___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ__COUNT___M 0xFFFFFFFF @@ -312105,7 +320626,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___S 0 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME (0x00A8A070) -#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME__DURATION___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME__DURATION___M 0xFFFFFFFF @@ -312114,7 +320635,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___S 0 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ (0x00A8A074) -#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ__COUNT___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ__COUNT___M 0xFFFFFFFF @@ -312123,7 +320644,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___S 0 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME (0x00A8A078) -#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME__DURATION___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME__DURATION___M 0xFFFFFFFF @@ -312132,7 +320653,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___S 0 #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ (0x00A8A07C) -#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ__COUNT___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ__COUNT___M 0xFFFFFFFF @@ -312141,7 +320662,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___S 0 #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME (0x00A8A080) -#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME__DURATION___POR 0x00000000 #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME__DURATION___M 0xFFFFFFFF @@ -312149,6 +320670,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___M 0xFFFFFFFF #define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___S 0 +#define WMAC0_MCMN_R1_TLV_CAP_TIMESTAMP_TAG (0x00A8A084) +#define WMAC0_MCMN_R1_TLV_CAP_TIMESTAMP_TAG___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TLV_CAP_TIMESTAMP_TAG___POR 0x00000000 +#define WMAC0_MCMN_R1_TLV_CAP_TIMESTAMP_TAG__VAL___POR 0x000 +#define WMAC0_MCMN_R1_TLV_CAP_TIMESTAMP_TAG__VAL___M 0x000001FF +#define WMAC0_MCMN_R1_TLV_CAP_TIMESTAMP_TAG__VAL___S 0 +#define WMAC0_MCMN_R1_TLV_CAP_TIMESTAMP_TAG___M 0x000001FF +#define WMAC0_MCMN_R1_TLV_CAP_TIMESTAMP_TAG___S 0 + #define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW (0x00A8A220) #define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___RWC QCSR_REG_RW #define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___POR 0x00000000 @@ -312959,6 +321489,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_NAV_CFG (0x00A8C0B4) #define WMAC0_RXPCU_R0_NAV_CFG___RWC QCSR_REG_RW #define WMAC0_RXPCU_R0_NAV_CFG___POR 0x2803C13A +#define WMAC0_RXPCU_R0_NAV_CFG__NO_INBSS_NAV_CHECK_FOR_CTS___POR 0x0 #define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___POR 0x0 #define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_FOR_ABORTED_PPDU___POR 0x1 #define WMAC0_RXPCU_R0_NAV_CFG__REVERSE_TXOP_DURATION___POR 0x0 @@ -312968,6 +321499,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_NAV_CFG__NAV_UPDATE_FOR_MU_EN___POR 0x0 #define WMAC0_RXPCU_R0_NAV_CFG__OFDM___POR 0x03C #define WMAC0_RXPCU_R0_NAV_CFG__CCK___POR 0x13A +#define WMAC0_RXPCU_R0_NAV_CFG__NO_INBSS_NAV_CHECK_FOR_CTS___M 0x80000000 +#define WMAC0_RXPCU_R0_NAV_CFG__NO_INBSS_NAV_CHECK_FOR_CTS___S 31 #define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___M 0x40000000 #define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___S 30 #define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_FOR_ABORTED_PPDU___M 0x20000000 @@ -312986,7 +321519,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_NAV_CFG__OFDM___S 12 #define WMAC0_RXPCU_R0_NAV_CFG__CCK___M 0x00000FFF #define WMAC0_RXPCU_R0_NAV_CFG__CCK___S 0 -#define WMAC0_RXPCU_R0_NAV_CFG___M 0x7FFFFFFF +#define WMAC0_RXPCU_R0_NAV_CFG___M 0xFFFFFFFF #define WMAC0_RXPCU_R0_NAV_CFG___S 0 #define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1 (0x00A8C0B8) @@ -315377,7 +323910,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_CLKGATE_CTRL (0x00A8C380) #define WMAC0_RXPCU_R0_CLKGATE_CTRL___RWC QCSR_REG_RW #define WMAC0_RXPCU_R0_CLKGATE_CTRL___POR 0x00000000 -#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CPU_IF_UPDATE___POR 0x0 #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___POR 0x0 #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PHU_MSG___POR 0x0 #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BPU___POR 0x0 @@ -315409,8 +323942,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_MPI___POR 0x0 #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PMI___POR 0x0 #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_GSE___POR 0x0 -#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___M 0x80000000 -#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___S 31 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CPU_IF_UPDATE___M 0x80000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CPU_IF_UPDATE___S 31 #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___M 0x40000000 #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___S 30 #define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PHU_MSG___M 0x20000000 @@ -319048,9 +327581,9 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_CLKGATE_CTRL2 (0x00A8C96C) #define WMAC0_RXPCU_R0_CLKGATE_CTRL2___RWC QCSR_REG_RW -#define WMAC0_RXPCU_R0_CLKGATE_CTRL2___POR 0x00000004 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2___POR 0x00000000 #define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_AXI_TIMEOUT___POR 0x0 -#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_UDU_TOP_LEGACY___POR 0x1 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_UDU_TOP_LEGACY___POR 0x0 #define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_PUS___POR 0x0 #define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_TESTBUS___POR 0x0 #define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_AXI_TIMEOUT___M 0x00000008 @@ -319066,17 +327599,35 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_MISC_MODE5 (0x00A8C970) #define WMAC0_RXPCU_R0_MISC_MODE5___RWC QCSR_REG_RW -#define WMAC0_RXPCU_R0_MISC_MODE5___POR 0x00002008 +#define WMAC0_RXPCU_R0_MISC_MODE5___POR 0x00002000 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_NON_AGG_LEN_FIX___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE5__BCN_TIMEOUT_ON_EBT_IN_DTIM___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_CTS_SIG_BW_EN___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_DYNAMIC_EN___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_PIFS_CHECK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_SIG_BW_FOR_CTS_EN___POR 0x0 #define WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___POR 0x0 #define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___POR 0x010 -#define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___POR 0x008 +#define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___POR 0x000 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_NON_AGG_LEN_FIX___M 0x80000000 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_NON_AGG_LEN_FIX___S 31 +#define WMAC0_RXPCU_R0_MISC_MODE5__BCN_TIMEOUT_ON_EBT_IN_DTIM___M 0x00800000 +#define WMAC0_RXPCU_R0_MISC_MODE5__BCN_TIMEOUT_ON_EBT_IN_DTIM___S 23 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_CTS_SIG_BW_EN___M 0x00400000 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_CTS_SIG_BW_EN___S 22 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_DYNAMIC_EN___M 0x00200000 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_DYNAMIC_EN___S 21 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_PIFS_CHECK_EN___M 0x00100000 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_PIFS_CHECK_EN___S 20 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_SIG_BW_FOR_CTS_EN___M 0x00080000 +#define WMAC0_RXPCU_R0_MISC_MODE5__HT_VHT_HE_RTS_SIG_BW_FOR_CTS_EN___S 19 #define WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___M 0x00040000 #define WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___S 18 #define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___M 0x0003FE00 #define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___S 9 #define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___M 0x000001FF #define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___S 0 -#define WMAC0_RXPCU_R0_MISC_MODE5___M 0x0007FFFF +#define WMAC0_RXPCU_R0_MISC_MODE5___M 0x80FFFFFF #define WMAC0_RXPCU_R0_MISC_MODE5___S 0 #define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY (0x00A8C974) @@ -319425,8 +327976,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_ILP_CFG_1 (0x00A8C9E8) #define WMAC0_RXPCU_R0_ILP_CFG_1___RWC QCSR_REG_RW -#define WMAC0_RXPCU_R0_ILP_CFG_1___POR 0x1D000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1___POR 0x8D000000 #define WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___POR 0x1 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DELAY_L0_MASK_TILL_COMMON_INFO___POR 0x0 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_MASK_DISABLE___POR 0x0 +#define WMAC0_RXPCU_R0_ILP_CFG_1__IMMEDIATE_L0_REQ_FOR_ZERO_HIGH_THRESH___POR 0x0 #define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___POR 0x1 #define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_ONLY_FOR_FILTERED_IN_FRAME___POR 0x1 #define WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_IF_FCS_FAILS___POR 0x0 @@ -319434,8 +327988,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_AFTER_PPDU_END_DURATION___POR 0x00 #define WMAC0_RXPCU_R0_ILP_CFG_1__ASSERT_L0_REQ_B4_PPDU_END_DURATION___POR 0x00 #define WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___POR 0x00 -#define WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___M 0x10000000 -#define WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___S 28 +#define WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___M 0x80000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___S 31 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DELAY_L0_MASK_TILL_COMMON_INFO___M 0x40000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DELAY_L0_MASK_TILL_COMMON_INFO___S 30 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_MASK_DISABLE___M 0x20000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_MASK_DISABLE___S 29 +#define WMAC0_RXPCU_R0_ILP_CFG_1__IMMEDIATE_L0_REQ_FOR_ZERO_HIGH_THRESH___M 0x10000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__IMMEDIATE_L0_REQ_FOR_ZERO_HIGH_THRESH___S 28 #define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___M 0x08000000 #define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___S 27 #define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_ONLY_FOR_FILTERED_IN_FRAME___M 0x04000000 @@ -319450,15 +328010,15 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_ILP_CFG_1__ASSERT_L0_REQ_B4_PPDU_END_DURATION___S 8 #define WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___M 0x000000FF #define WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___S 0 -#define WMAC0_RXPCU_R0_ILP_CFG_1___M 0x1FFFFFFF +#define WMAC0_RXPCU_R0_ILP_CFG_1___M 0xFFFFFFFF #define WMAC0_RXPCU_R0_ILP_CFG_1___S 0 #define WMAC0_RXPCU_R0_ILP_CFG_2 (0x00A8C9EC) #define WMAC0_RXPCU_R0_ILP_CFG_2___RWC QCSR_REG_RW -#define WMAC0_RXPCU_R0_ILP_CFG_2___POR 0x00000000 -#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_0_TO_LESS_THAN_200___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_2___POR 0x029168C4 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___POR 0x0A4 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___POR 0x0B4 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_0_TO_LESS_THAN_200___POR 0x0C4 #define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___M 0x07FC0000 #define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___S 18 #define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___M 0x0003FE00 @@ -319470,10 +328030,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_ILP_CFG_3 (0x00A8C9F0) #define WMAC0_RXPCU_R0_ILP_CFG_3___RWC QCSR_REG_RW -#define WMAC0_RXPCU_R0_ILP_CFG_3___POR 0x00000000 -#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_600_TO_LESS_THAN_800___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_3___POR 0x01D10894 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___POR 0x074 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___POR 0x084 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_600_TO_LESS_THAN_800___POR 0x094 #define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___M 0x07FC0000 #define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___S 18 #define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___M 0x0003FE00 @@ -319485,10 +328045,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_ILP_CFG_4 (0x00A8C9F4) #define WMAC0_RXPCU_R0_ILP_CFG_4___RWC QCSR_REG_RW -#define WMAC0_RXPCU_R0_ILP_CFG_4___POR 0x00000000 -#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1200_TO_LESS_THAN_1400___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_4___POR 0x0150A864 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___POR 0x054 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___POR 0x054 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1200_TO_LESS_THAN_1400___POR 0x064 #define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___M 0x07FC0000 #define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___S 18 #define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___M 0x0003FE00 @@ -319500,10 +328060,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_ILP_CFG_5 (0x00A8C9F8) #define WMAC0_RXPCU_R0_ILP_CFG_5___RWC QCSR_REG_RW -#define WMAC0_RXPCU_R0_ILP_CFG_5___POR 0x00000000 -#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_1800_TO_LESS_THAN_2000___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_5___POR 0x00906844 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___POR 0x024 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___POR 0x034 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_1800_TO_LESS_THAN_2000___POR 0x044 #define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___M 0x07FC0000 #define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___S 18 #define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___M 0x0003FE00 @@ -319515,10 +328075,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_ILP_CFG_6 (0x00A8C9FC) #define WMAC0_RXPCU_R0_ILP_CFG_6___RWC QCSR_REG_RW -#define WMAC0_RXPCU_R0_ILP_CFG_6___POR 0x00000000 +#define WMAC0_RXPCU_R0_ILP_CFG_6___POR 0x00000814 #define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___POR 0x000 -#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2400_TO_LESS_THAN_2600___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___POR 0x004 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2400_TO_LESS_THAN_2600___POR 0x014 #define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___M 0x07FC0000 #define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___S 18 #define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___M 0x0003FE00 @@ -319531,15 +328091,54 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R0_ILP_CFG_7 (0x00A8CA00) #define WMAC0_RXPCU_R0_ILP_CFG_7___RWC QCSR_REG_RW #define WMAC0_RXPCU_R0_ILP_CFG_7___POR 0x00008000 +#define WMAC0_RXPCU_R0_ILP_CFG_7__STATS_CLEAR___POR 0x0 #define WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___POR 0x40 #define WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_7__STATS_CLEAR___M 0x00010000 +#define WMAC0_RXPCU_R0_ILP_CFG_7__STATS_CLEAR___S 16 #define WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___M 0x0000FE00 #define WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___S 9 #define WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___M 0x000001FF #define WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___S 0 -#define WMAC0_RXPCU_R0_ILP_CFG_7___M 0x0000FFFF +#define WMAC0_RXPCU_R0_ILP_CFG_7___M 0x0001FFFF #define WMAC0_RXPCU_R0_ILP_CFG_7___S 0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING (0x00A8CA04) +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING___POR 0x00000000 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__AP_STA_LATCH_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__UL_HE_STA___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_INBSS_HE_TXOP_HOLDER___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_OBSS_HE_TXOP_HOLDER___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_INBSS_NAV_P_DLY_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_OBSS_NAV_P_DLY_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__FIX_LAST_BSS_FLAG_ON_HWSCH_INBSS_NAV___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__FIX_LAST_BSS_FLAG_ON_HWSCH_NAV___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__IGNORE_UORA_TXOP_INBSS_NAV_CHK___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__IGNORE_UORA_TXOP_OBSS_NAV_CHK___POR 0x0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__AP_STA_LATCH_SEL___M 0x00000800 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__AP_STA_LATCH_SEL___S 11 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__UL_HE_STA___M 0x00000400 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__UL_HE_STA___S 10 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_INBSS_HE_TXOP_HOLDER___M 0x00000200 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_INBSS_HE_TXOP_HOLDER___S 9 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_OBSS_HE_TXOP_HOLDER___M 0x00000100 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_OBSS_HE_TXOP_HOLDER___S 8 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_INBSS_NAV_P_DLY_SEL___M 0x000000C0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_INBSS_NAV_P_DLY_SEL___S 6 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_OBSS_NAV_P_DLY_SEL___M 0x00000030 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__SET_OBSS_NAV_P_DLY_SEL___S 4 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__FIX_LAST_BSS_FLAG_ON_HWSCH_INBSS_NAV___M 0x00000008 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__FIX_LAST_BSS_FLAG_ON_HWSCH_INBSS_NAV___S 3 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__FIX_LAST_BSS_FLAG_ON_HWSCH_NAV___M 0x00000004 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__FIX_LAST_BSS_FLAG_ON_HWSCH_NAV___S 2 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__IGNORE_UORA_TXOP_INBSS_NAV_CHK___M 0x00000002 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__IGNORE_UORA_TXOP_INBSS_NAV_CHK___S 1 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__IGNORE_UORA_TXOP_OBSS_NAV_CHK___M 0x00000001 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING__IGNORE_UORA_TXOP_OBSS_NAV_CHK___S 0 +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING___M 0x00000FFF +#define WMAC0_RXPCU_R0_TXOP_OWNER_TRACKING___S 0 + #define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK (0x00A8D000) #define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___RWC QCSR_REG_RW #define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___POR 0x00000000 @@ -320400,6 +328999,60 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXPCU_R1_PMI_ERROR_STATUS___M 0x7FFFFFFF #define WMAC0_RXPCU_R1_PMI_ERROR_STATUS___S 0 +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_CLOSE (0x00A8D198) +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_CLOSE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_CLOSE___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_CLOSE__VALUE___POR 0x000 +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_CLOSE__VALUE___M 0x000007FF +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_CLOSE__VALUE___S 0 +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_CLOSE___M 0x000007FF +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_CLOSE___S 0 + +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_OPEN (0x00A8D19C) +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_OPEN___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_OPEN___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_OPEN__VALUE___POR 0x000 +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_OPEN__VALUE___M 0x000007FF +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_OPEN__VALUE___S 0 +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_OPEN___M 0x000007FF +#define WMAC0_RXPCU_R1_ILP_STATS_MAX_SFM_OCCUPANCY_AT_GATE_OPEN___S 0 + +#define WMAC0_RXPCU_R1_ILP_STATS_2_TIME_SPENT_IN_BUFFERING (0x00A8D1A0) +#define WMAC0_RXPCU_R1_ILP_STATS_2_TIME_SPENT_IN_BUFFERING___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_ILP_STATS_2_TIME_SPENT_IN_BUFFERING___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_2_TIME_SPENT_IN_BUFFERING__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_2_TIME_SPENT_IN_BUFFERING__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_ILP_STATS_2_TIME_SPENT_IN_BUFFERING__VALUE___S 0 +#define WMAC0_RXPCU_R1_ILP_STATS_2_TIME_SPENT_IN_BUFFERING___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_ILP_STATS_2_TIME_SPENT_IN_BUFFERING___S 0 + +#define WMAC0_RXPCU_R1_ILP_STATS_3_TIME_SPENT_IN_DRAINING (0x00A8D1A4) +#define WMAC0_RXPCU_R1_ILP_STATS_3_TIME_SPENT_IN_DRAINING___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_ILP_STATS_3_TIME_SPENT_IN_DRAINING___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_3_TIME_SPENT_IN_DRAINING__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_3_TIME_SPENT_IN_DRAINING__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_ILP_STATS_3_TIME_SPENT_IN_DRAINING__VALUE___S 0 +#define WMAC0_RXPCU_R1_ILP_STATS_3_TIME_SPENT_IN_DRAINING___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_ILP_STATS_3_TIME_SPENT_IN_DRAINING___S 0 + +#define WMAC0_RXPCU_R1_ILP_STATS_4_AGGR_PPDU_DURATION_63_32 (0x00A8D1A8) +#define WMAC0_RXPCU_R1_ILP_STATS_4_AGGR_PPDU_DURATION_63_32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_ILP_STATS_4_AGGR_PPDU_DURATION_63_32___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_4_AGGR_PPDU_DURATION_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_4_AGGR_PPDU_DURATION_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_ILP_STATS_4_AGGR_PPDU_DURATION_63_32__VALUE___S 0 +#define WMAC0_RXPCU_R1_ILP_STATS_4_AGGR_PPDU_DURATION_63_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_ILP_STATS_4_AGGR_PPDU_DURATION_63_32___S 0 + +#define WMAC0_RXPCU_R1_ILP_STATS_5_AGGR_PPDU_DURATION_31_0 (0x00A8D1AC) +#define WMAC0_RXPCU_R1_ILP_STATS_5_AGGR_PPDU_DURATION_31_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_ILP_STATS_5_AGGR_PPDU_DURATION_31_0___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_5_AGGR_PPDU_DURATION_31_0__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_ILP_STATS_5_AGGR_PPDU_DURATION_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_ILP_STATS_5_AGGR_PPDU_DURATION_31_0__VALUE___S 0 +#define WMAC0_RXPCU_R1_ILP_STATS_5_AGGR_PPDU_DURATION_31_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_ILP_STATS_5_AGGR_PPDU_DURATION_31_0___S 0 + #define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS (0x00A8F000) #define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___POR 0x30301919 @@ -320742,6 +329395,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_MISC_MODE_EXT (0x00A8F048) #define WMAC0_TXPCU_R0_MISC_MODE_EXT___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_MISC_MODE_EXT___POR 0x0A000840 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_SYNTH_PHY_ON_OFF_COUNTERS___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_PPDU_AFTER_CTS2SELF_TIMER_UPDATE___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_NON_LEGACYRTS_EXPANSION___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_DONT_WAIT_FOR_ACK_ON_SOFT_ABORT___POR 0x0 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___POR 0x280 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_FLUSH_FOR_LATE_PRE_PHY___POR 0x0 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_RESP___POR 0x0 @@ -320761,6 +329418,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_MISC_MODE_EXT__RELAYED_FRAME___POR 0x0 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__DURATION_INDICATION___POR 0x0 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_SYNTH_PHY_ON_OFF_COUNTERS___M 0x80000000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_SYNTH_PHY_ON_OFF_COUNTERS___S 31 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_PPDU_AFTER_CTS2SELF_TIMER_UPDATE___M 0x40000000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_PPDU_AFTER_CTS2SELF_TIMER_UPDATE___S 30 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_NON_LEGACYRTS_EXPANSION___M 0x20000000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_NON_LEGACYRTS_EXPANSION___S 29 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_DONT_WAIT_FOR_ACK_ON_SOFT_ABORT___M 0x10000000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_DONT_WAIT_FOR_ACK_ON_SOFT_ABORT___S 28 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___M 0x0FFC0000 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___S 18 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_FLUSH_FOR_LATE_PRE_PHY___M 0x00020000 @@ -320799,10 +329464,31 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_MISC_MODE_EXT__DURATION_INDICATION___S 1 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___M 0x00000001 #define WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___S 0 -#define WMAC0_TXPCU_R0_MISC_MODE_EXT___M 0x0FFFFFFF +#define WMAC0_TXPCU_R0_MISC_MODE_EXT___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_MISC_MODE_EXT___S 0 -#define WMAC0_TXPCU_R0_TQM_UPDATE (0x00A8F04C) +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1 (0x00A8F04C) +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1___POR 0x00000240 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__ENABLE_PREVENT_BA_RESP_IF_RCVD_RTS___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__ENABLE_PREVENT_ACK_RESP_IF_RCVD_RTS___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__DISABLE_NO_GENFLUSH_FOR_NOMPDU_CASE___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__DISABLE_EARLY_QNULL_USR_SWITCH___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__QOSNULL_SWITCH_THRESHOLD___POR 0x40 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__ENABLE_PREVENT_BA_RESP_IF_RCVD_RTS___M 0x00000800 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__ENABLE_PREVENT_BA_RESP_IF_RCVD_RTS___S 11 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__ENABLE_PREVENT_ACK_RESP_IF_RCVD_RTS___M 0x00000400 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__ENABLE_PREVENT_ACK_RESP_IF_RCVD_RTS___S 10 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__DISABLE_NO_GENFLUSH_FOR_NOMPDU_CASE___M 0x00000200 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__DISABLE_NO_GENFLUSH_FOR_NOMPDU_CASE___S 9 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__DISABLE_EARLY_QNULL_USR_SWITCH___M 0x00000100 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__DISABLE_EARLY_QNULL_USR_SWITCH___S 8 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__QOSNULL_SWITCH_THRESHOLD___M 0x000000FF +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1__QOSNULL_SWITCH_THRESHOLD___S 0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1___M 0x00000FFF +#define WMAC0_TXPCU_R0_MISC_MODE_EXT1___S 0 + +#define WMAC0_TXPCU_R0_TQM_UPDATE (0x00A8F050) #define WMAC0_TXPCU_R0_TQM_UPDATE___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_TQM_UPDATE___POR 0x00000000 #define WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_RING___POR 0x0 @@ -320817,7 +329503,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_TQM_UPDATE___M 0x03FFFFFF #define WMAC0_TXPCU_R0_TQM_UPDATE___S 0 -#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY (0x00A8F050) +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY (0x00A8F054) #define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___POR 0x01400001 #define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__R2R_WAIT_VALUE___POR 0x0140 @@ -320829,7 +329515,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___M 0xFFFF00FF #define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___S 0 -#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE (0x00A8F054) +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE (0x00A8F058) #define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___POR 0x00000C00 #define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE__VALUE___POR 0x0C00 @@ -320838,7 +329524,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___M 0x0000FFFF #define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___S 0 -#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE (0x00A8F058) +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE (0x00A8F05C) #define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___POR 0x00000080 #define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE__VALUE___POR 0x0080 @@ -320847,7 +329533,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___M 0x0000FFFF #define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___S 0 -#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME (0x00A8F05C) +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME (0x00A8F060) #define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___POR 0x00000009 #define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME__VALUE___POR 0x09 @@ -320856,7 +329542,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___M 0x000000FF #define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___S 0 -#define WMAC0_TXPCU_R0_CBF_PADDING (0x00A8F060) +#define WMAC0_TXPCU_R0_CBF_PADDING (0x00A8F064) #define WMAC0_TXPCU_R0_CBF_PADDING___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CBF_PADDING___POR 0x00040001 #define WMAC0_TXPCU_R0_CBF_PADDING__RESPONSE_DENSITY___POR 0x04 @@ -320868,7 +329554,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CBF_PADDING___M 0x001FFFFF #define WMAC0_TXPCU_R0_CBF_PADDING___S 0 -#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC (0x00A8F064) +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC (0x00A8F068) #define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___POR 0x00A00780 #define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__MAC_CLK___POR 0x00A0 @@ -320880,7 +329566,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___S 0 -#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER (0x00A8F068) +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER (0x00A8F06C) #define WMAC0_TXPCU_R0_RESP_PIFS_TIMER___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_PIFS_TIMER___POR 0x0E600D20 #define WMAC0_TXPCU_R0_RESP_PIFS_TIMER__TIMEOUT_PIFS___POR 0x0E60 @@ -320892,7 +329578,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_PIFS_TIMER___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_PIFS_TIMER___S 0 -#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL (0x00A8F06C) +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL (0x00A8F070) #define WMAC0_TXPCU_R0_TRIG_RESP_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_TRIG_RESP_CTRL___POR 0x001F0780 #define WMAC0_TXPCU_R0_TRIG_RESP_CTRL__STATUS_TLV_UPD_ENA___POR 0x001F @@ -321009,7 +329695,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___M 0x0001FFFF #define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___S 0 -#define WMAC0_TXPCU_R0_SELF_GEN_ERROR (0x00A8F0E0) +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR (0x00A8F090) #define WMAC0_TXPCU_R0_SELF_GEN_ERROR___RWC QCSR_REG_RO #define WMAC0_TXPCU_R0_SELF_GEN_ERROR___POR 0x00000000 #define WMAC0_TXPCU_R0_SELF_GEN_ERROR__STATUS___POR 0x00 @@ -321018,7 +329704,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_SELF_GEN_ERROR___M 0x000000FF #define WMAC0_TXPCU_R0_SELF_GEN_ERROR___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n(n) (0x00A8F104+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n(n) (0x00A8F094+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_nMAX 6 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_ELEM 7 @@ -321029,36 +329715,36 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0 (0x00A8F104) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0 (0x00A8F094) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1 (0x00A8F108) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1 (0x00A8F098) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2 (0x00A8F10C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2 (0x00A8F09C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3 (0x00A8F110) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3 (0x00A8F0A0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4 (0x00A8F114) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4 (0x00A8F0A4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5 (0x00A8F118) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5 (0x00A8F0A8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6 (0x00A8F11C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6 (0x00A8F0AC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n(n) (0x00A8F120+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n(n) (0x00A8F0B0+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_ELEM 8 @@ -321069,40 +329755,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0 (0x00A8F120) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0 (0x00A8F0B0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1 (0x00A8F124) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1 (0x00A8F0B4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2 (0x00A8F128) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2 (0x00A8F0B8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3 (0x00A8F12C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3 (0x00A8F0BC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4 (0x00A8F130) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4 (0x00A8F0C0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5 (0x00A8F134) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5 (0x00A8F0C4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6 (0x00A8F138) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6 (0x00A8F0C8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7 (0x00A8F13C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7 (0x00A8F0CC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n(n) (0x00A8F140+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n(n) (0x00A8F0D0+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_ELEM 8 @@ -321113,40 +329799,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0 (0x00A8F140) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0 (0x00A8F0D0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1 (0x00A8F144) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1 (0x00A8F0D4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2 (0x00A8F148) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2 (0x00A8F0D8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3 (0x00A8F14C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3 (0x00A8F0DC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4 (0x00A8F150) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4 (0x00A8F0E0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5 (0x00A8F154) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5 (0x00A8F0E4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6 (0x00A8F158) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6 (0x00A8F0E8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7 (0x00A8F15C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7 (0x00A8F0EC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n(n) (0x00A8F160+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n(n) (0x00A8F0F0+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_nMAX 11 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_ELEM 12 @@ -321157,56 +329843,56 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0 (0x00A8F160) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0 (0x00A8F0F0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1 (0x00A8F164) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1 (0x00A8F0F4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2 (0x00A8F168) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2 (0x00A8F0F8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3 (0x00A8F16C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3 (0x00A8F0FC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4 (0x00A8F170) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4 (0x00A8F100) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5 (0x00A8F174) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5 (0x00A8F104) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6 (0x00A8F178) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6 (0x00A8F108) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7 (0x00A8F17C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7 (0x00A8F10C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8 (0x00A8F180) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8 (0x00A8F110) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9 (0x00A8F184) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9 (0x00A8F114) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10 (0x00A8F188) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10 (0x00A8F118) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11 (0x00A8F18C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11 (0x00A8F11C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n(n) (0x00A8F190+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n(n) (0x00A8F120+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_nMAX 13 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_ELEM 14 @@ -321217,64 +329903,64 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0 (0x00A8F190) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0 (0x00A8F120) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1 (0x00A8F194) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1 (0x00A8F124) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2 (0x00A8F198) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2 (0x00A8F128) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3 (0x00A8F19C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3 (0x00A8F12C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4 (0x00A8F1A0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4 (0x00A8F130) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5 (0x00A8F1A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5 (0x00A8F134) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6 (0x00A8F1A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6 (0x00A8F138) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7 (0x00A8F1AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7 (0x00A8F13C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8 (0x00A8F1B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8 (0x00A8F140) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9 (0x00A8F1B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9 (0x00A8F144) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10 (0x00A8F1B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10 (0x00A8F148) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11 (0x00A8F1BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11 (0x00A8F14C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12 (0x00A8F1C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12 (0x00A8F150) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13 (0x00A8F1C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13 (0x00A8F154) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n(n) (0x00A8F1C8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n(n) (0x00A8F158+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_ELEM 8 @@ -321285,40 +329971,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0 (0x00A8F1C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0 (0x00A8F158) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1 (0x00A8F1CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1 (0x00A8F15C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2 (0x00A8F1D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2 (0x00A8F160) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3 (0x00A8F1D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3 (0x00A8F164) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4 (0x00A8F1D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4 (0x00A8F168) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5 (0x00A8F1DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5 (0x00A8F16C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6 (0x00A8F1E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6 (0x00A8F170) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7 (0x00A8F1E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7 (0x00A8F174) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n(n) (0x00A8F1E8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n(n) (0x00A8F178+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_ELEM 8 @@ -321329,40 +330015,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0 (0x00A8F1E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0 (0x00A8F178) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1 (0x00A8F1EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1 (0x00A8F17C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2 (0x00A8F1F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2 (0x00A8F180) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3 (0x00A8F1F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3 (0x00A8F184) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4 (0x00A8F1F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4 (0x00A8F188) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5 (0x00A8F1FC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5 (0x00A8F18C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6 (0x00A8F200) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6 (0x00A8F190) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7 (0x00A8F204) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7 (0x00A8F194) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n(n) (0x00A8F208+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n(n) (0x00A8F198+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_ELEM 8 @@ -321373,40 +330059,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0 (0x00A8F208) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0 (0x00A8F198) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1 (0x00A8F20C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1 (0x00A8F19C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2 (0x00A8F210) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2 (0x00A8F1A0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3 (0x00A8F214) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3 (0x00A8F1A4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4 (0x00A8F218) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4 (0x00A8F1A8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5 (0x00A8F21C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5 (0x00A8F1AC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6 (0x00A8F220) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6 (0x00A8F1B0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7 (0x00A8F224) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7 (0x00A8F1B4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n(n) (0x00A8F228+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n(n) (0x00A8F1B8+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_nMAX 11 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_ELEM 12 @@ -321417,56 +330103,56 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0 (0x00A8F228) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0 (0x00A8F1B8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1 (0x00A8F22C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1 (0x00A8F1BC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2 (0x00A8F230) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2 (0x00A8F1C0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3 (0x00A8F234) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3 (0x00A8F1C4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4 (0x00A8F238) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4 (0x00A8F1C8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5 (0x00A8F23C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5 (0x00A8F1CC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6 (0x00A8F240) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6 (0x00A8F1D0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7 (0x00A8F244) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7 (0x00A8F1D4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8 (0x00A8F248) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8 (0x00A8F1D8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9 (0x00A8F24C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9 (0x00A8F1DC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10 (0x00A8F250) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10 (0x00A8F1E0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11 (0x00A8F254) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11 (0x00A8F1E4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n(n) (0x00A8F258+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n(n) (0x00A8F1E8+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_nMAX 13 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_ELEM 14 @@ -321477,64 +330163,64 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0 (0x00A8F258) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0 (0x00A8F1E8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1 (0x00A8F25C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1 (0x00A8F1EC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2 (0x00A8F260) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2 (0x00A8F1F0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3 (0x00A8F264) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3 (0x00A8F1F4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4 (0x00A8F268) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4 (0x00A8F1F8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5 (0x00A8F26C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5 (0x00A8F1FC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6 (0x00A8F270) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6 (0x00A8F200) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7 (0x00A8F274) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7 (0x00A8F204) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8 (0x00A8F278) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8 (0x00A8F208) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9 (0x00A8F27C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9 (0x00A8F20C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10 (0x00A8F280) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10 (0x00A8F210) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11 (0x00A8F284) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11 (0x00A8F214) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12 (0x00A8F288) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12 (0x00A8F218) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13 (0x00A8F28C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13 (0x00A8F21C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n(n) (0x00A8F290+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n(n) (0x00A8F220+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_nMAX 13 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_ELEM 14 @@ -321545,64 +330231,64 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0 (0x00A8F290) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0 (0x00A8F220) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1 (0x00A8F294) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1 (0x00A8F224) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2 (0x00A8F298) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2 (0x00A8F228) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3 (0x00A8F29C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3 (0x00A8F22C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4 (0x00A8F2A0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4 (0x00A8F230) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5 (0x00A8F2A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5 (0x00A8F234) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6 (0x00A8F2A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6 (0x00A8F238) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7 (0x00A8F2AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7 (0x00A8F23C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8 (0x00A8F2B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8 (0x00A8F240) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9 (0x00A8F2B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9 (0x00A8F244) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10 (0x00A8F2B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10 (0x00A8F248) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11 (0x00A8F2BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11 (0x00A8F24C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12 (0x00A8F2C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12 (0x00A8F250) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13 (0x00A8F2C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13 (0x00A8F254) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n(n) (0x00A8F2C8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n(n) (0x00A8F258+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_ELEM 8 @@ -321613,40 +330299,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0 (0x00A8F2C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0 (0x00A8F258) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1 (0x00A8F2CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1 (0x00A8F25C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2 (0x00A8F2D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2 (0x00A8F260) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3 (0x00A8F2D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3 (0x00A8F264) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4 (0x00A8F2D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4 (0x00A8F268) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5 (0x00A8F2DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5 (0x00A8F26C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6 (0x00A8F2E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6 (0x00A8F270) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7 (0x00A8F2E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7 (0x00A8F274) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n(n) (0x00A8F2E8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n(n) (0x00A8F278+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_nMAX 11 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_ELEM 12 @@ -321657,56 +330343,56 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0 (0x00A8F2E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0 (0x00A8F278) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1 (0x00A8F2EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1 (0x00A8F27C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2 (0x00A8F2F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2 (0x00A8F280) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3 (0x00A8F2F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3 (0x00A8F284) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4 (0x00A8F2F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4 (0x00A8F288) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5 (0x00A8F2FC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5 (0x00A8F28C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6 (0x00A8F300) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6 (0x00A8F290) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7 (0x00A8F304) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7 (0x00A8F294) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8 (0x00A8F308) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8 (0x00A8F298) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9 (0x00A8F30C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9 (0x00A8F29C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10 (0x00A8F310) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10 (0x00A8F2A0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11 (0x00A8F314) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11 (0x00A8F2A4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n(n) (0x00A8F318+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n(n) (0x00A8F2A8+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_nMAX 13 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_ELEM 14 @@ -321717,64 +330403,64 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0 (0x00A8F318) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0 (0x00A8F2A8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1 (0x00A8F31C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1 (0x00A8F2AC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2 (0x00A8F320) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2 (0x00A8F2B0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3 (0x00A8F324) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3 (0x00A8F2B4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4 (0x00A8F328) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4 (0x00A8F2B8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5 (0x00A8F32C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5 (0x00A8F2BC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6 (0x00A8F330) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6 (0x00A8F2C0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7 (0x00A8F334) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7 (0x00A8F2C4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8 (0x00A8F338) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8 (0x00A8F2C8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9 (0x00A8F33C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9 (0x00A8F2CC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10 (0x00A8F340) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10 (0x00A8F2D0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11 (0x00A8F344) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11 (0x00A8F2D4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12 (0x00A8F348) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12 (0x00A8F2D8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13 (0x00A8F34C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13 (0x00A8F2DC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n(n) (0x00A8F350+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n(n) (0x00A8F2E0+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_nMAX 13 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_ELEM 14 @@ -321785,64 +330471,64 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0 (0x00A8F350) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0 (0x00A8F2E0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1 (0x00A8F354) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1 (0x00A8F2E4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2 (0x00A8F358) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2 (0x00A8F2E8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3 (0x00A8F35C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3 (0x00A8F2EC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4 (0x00A8F360) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4 (0x00A8F2F0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5 (0x00A8F364) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5 (0x00A8F2F4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6 (0x00A8F368) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6 (0x00A8F2F8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7 (0x00A8F36C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7 (0x00A8F2FC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8 (0x00A8F370) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8 (0x00A8F300) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9 (0x00A8F374) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9 (0x00A8F304) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10 (0x00A8F378) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10 (0x00A8F308) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11 (0x00A8F37C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11 (0x00A8F30C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12 (0x00A8F380) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12 (0x00A8F310) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13 (0x00A8F384) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13 (0x00A8F314) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n(n) (0x00A8F388+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n(n) (0x00A8F318+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_ELEM 8 @@ -321853,40 +330539,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0 (0x00A8F388) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0 (0x00A8F318) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1 (0x00A8F38C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1 (0x00A8F31C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2 (0x00A8F390) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2 (0x00A8F320) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3 (0x00A8F394) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3 (0x00A8F324) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4 (0x00A8F398) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4 (0x00A8F328) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5 (0x00A8F39C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5 (0x00A8F32C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6 (0x00A8F3A0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6 (0x00A8F330) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7 (0x00A8F3A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7 (0x00A8F334) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n(n) (0x00A8F3A8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n(n) (0x00A8F338+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_ELEM 8 @@ -321897,40 +330583,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0 (0x00A8F3A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0 (0x00A8F338) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1 (0x00A8F3AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1 (0x00A8F33C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2 (0x00A8F3B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2 (0x00A8F340) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3 (0x00A8F3B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3 (0x00A8F344) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4 (0x00A8F3B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4 (0x00A8F348) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5 (0x00A8F3BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5 (0x00A8F34C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6 (0x00A8F3C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6 (0x00A8F350) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7 (0x00A8F3C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7 (0x00A8F354) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n(n) (0x00A8F3C8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n(n) (0x00A8F358+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_ELEM 8 @@ -321941,40 +330627,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0 (0x00A8F3C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0 (0x00A8F358) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1 (0x00A8F3CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1 (0x00A8F35C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2 (0x00A8F3D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2 (0x00A8F360) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3 (0x00A8F3D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3 (0x00A8F364) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4 (0x00A8F3D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4 (0x00A8F368) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5 (0x00A8F3DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5 (0x00A8F36C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6 (0x00A8F3E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6 (0x00A8F370) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7 (0x00A8F3E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7 (0x00A8F374) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n(n) (0x00A8F3E8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n(n) (0x00A8F378+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_ELEM 8 @@ -321985,40 +330671,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0 (0x00A8F3E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0 (0x00A8F378) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1 (0x00A8F3EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1 (0x00A8F37C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2 (0x00A8F3F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2 (0x00A8F380) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3 (0x00A8F3F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3 (0x00A8F384) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4 (0x00A8F3F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4 (0x00A8F388) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5 (0x00A8F3FC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5 (0x00A8F38C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6 (0x00A8F400) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6 (0x00A8F390) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7 (0x00A8F404) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7 (0x00A8F394) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n(n) (0x00A8F408+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n(n) (0x00A8F398+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_ELEM 8 @@ -322029,40 +330715,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0 (0x00A8F408) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0 (0x00A8F398) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1 (0x00A8F40C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1 (0x00A8F39C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2 (0x00A8F410) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2 (0x00A8F3A0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3 (0x00A8F414) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3 (0x00A8F3A4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4 (0x00A8F418) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4 (0x00A8F3A8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5 (0x00A8F41C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5 (0x00A8F3AC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6 (0x00A8F420) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6 (0x00A8F3B0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7 (0x00A8F424) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7 (0x00A8F3B4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n(n) (0x00A8F428+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n(n) (0x00A8F3B8+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_ELEM 8 @@ -322073,40 +330759,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0 (0x00A8F428) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0 (0x00A8F3B8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1 (0x00A8F42C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1 (0x00A8F3BC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2 (0x00A8F430) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2 (0x00A8F3C0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3 (0x00A8F434) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3 (0x00A8F3C4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4 (0x00A8F438) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4 (0x00A8F3C8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5 (0x00A8F43C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5 (0x00A8F3CC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6 (0x00A8F440) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6 (0x00A8F3D0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7 (0x00A8F444) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7 (0x00A8F3D4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n(n) (0x00A8F448+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n(n) (0x00A8F3D8+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_ELEM 8 @@ -322117,40 +330803,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0 (0x00A8F448) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0 (0x00A8F3D8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1 (0x00A8F44C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1 (0x00A8F3DC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2 (0x00A8F450) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2 (0x00A8F3E0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3 (0x00A8F454) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3 (0x00A8F3E4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4 (0x00A8F458) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4 (0x00A8F3E8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5 (0x00A8F45C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5 (0x00A8F3EC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6 (0x00A8F460) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6 (0x00A8F3F0) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7 (0x00A8F464) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7 (0x00A8F3F4) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n(n) (0x00A8F468+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n(n) (0x00A8F3F8+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_nMAX 7 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_ELEM 8 @@ -322161,40 +330847,40 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0 (0x00A8F468) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0 (0x00A8F3F8) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1 (0x00A8F46C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1 (0x00A8F3FC) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2 (0x00A8F470) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2 (0x00A8F400) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3 (0x00A8F474) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3 (0x00A8F404) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4 (0x00A8F478) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4 (0x00A8F408) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5 (0x00A8F47C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5 (0x00A8F40C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6 (0x00A8F480) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6 (0x00A8F410) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7 (0x00A8F484) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7 (0x00A8F414) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n(n) (0x00A8F488+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n(n) (0x00A8F418+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_nMAX 3 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_ELEM 4 @@ -322205,24 +330891,24 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0 (0x00A8F488) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0 (0x00A8F418) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1 (0x00A8F48C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1 (0x00A8F41C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2 (0x00A8F490) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2 (0x00A8F420) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3 (0x00A8F494) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3 (0x00A8F424) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n(n) (0x00A8F498+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n(n) (0x00A8F428+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_nMAX 3 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_ELEM 4 @@ -322233,24 +330919,24 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0 (0x00A8F498) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0 (0x00A8F428) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1 (0x00A8F49C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1 (0x00A8F42C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2 (0x00A8F4A0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2 (0x00A8F430) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3 (0x00A8F4A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3 (0x00A8F434) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n(n) (0x00A8F4A8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n(n) (0x00A8F438+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_nMAX 3 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_ELEM 4 @@ -322261,24 +330947,24 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0 (0x00A8F4A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0 (0x00A8F438) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1 (0x00A8F4AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1 (0x00A8F43C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2 (0x00A8F4B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2 (0x00A8F440) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3 (0x00A8F4B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3 (0x00A8F444) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n(n) (0x00A8F4B8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n(n) (0x00A8F448+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_nMAX 3 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_ELEM 4 @@ -322289,24 +330975,24 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0 (0x00A8F4B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0 (0x00A8F448) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1 (0x00A8F4BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1 (0x00A8F44C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2 (0x00A8F4C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2 (0x00A8F450) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3 (0x00A8F4C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3 (0x00A8F454) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n(n) (0x00A8F4C8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n(n) (0x00A8F458+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_nMAX 13 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_ELEM 14 @@ -322317,64 +331003,64 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0 (0x00A8F4C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0 (0x00A8F458) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1 (0x00A8F4CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1 (0x00A8F45C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2 (0x00A8F4D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2 (0x00A8F460) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3 (0x00A8F4D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3 (0x00A8F464) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4 (0x00A8F4D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4 (0x00A8F468) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5 (0x00A8F4DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5 (0x00A8F46C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6 (0x00A8F4E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6 (0x00A8F470) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7 (0x00A8F4E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7 (0x00A8F474) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8 (0x00A8F4E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8 (0x00A8F478) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9 (0x00A8F4EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9 (0x00A8F47C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10 (0x00A8F4F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10 (0x00A8F480) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11 (0x00A8F4F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11 (0x00A8F484) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12 (0x00A8F4F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12 (0x00A8F488) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13 (0x00A8F4FC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13 (0x00A8F48C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13__VALUE___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n(n) (0x00A8F500+0x4*(n)) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n(n) (0x00A8F490+0x4*(n)) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_nMIN 0 #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_nMAX 1023 #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_ELEM 1024 @@ -322385,4104 +331071,4104 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n__DATA___S 0 #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0 (0x00A8F500) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0 (0x00A8F490) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1 (0x00A8F504) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1 (0x00A8F494) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2 (0x00A8F508) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2 (0x00A8F498) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3 (0x00A8F50C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3 (0x00A8F49C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4 (0x00A8F510) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4 (0x00A8F4A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5 (0x00A8F514) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5 (0x00A8F4A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6 (0x00A8F518) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6 (0x00A8F4A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7 (0x00A8F51C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7 (0x00A8F4AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8 (0x00A8F520) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8 (0x00A8F4B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9 (0x00A8F524) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9 (0x00A8F4B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10 (0x00A8F528) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10 (0x00A8F4B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11 (0x00A8F52C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11 (0x00A8F4BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12 (0x00A8F530) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12 (0x00A8F4C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13 (0x00A8F534) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13 (0x00A8F4C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14 (0x00A8F538) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14 (0x00A8F4C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15 (0x00A8F53C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15 (0x00A8F4CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16 (0x00A8F540) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16 (0x00A8F4D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17 (0x00A8F544) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17 (0x00A8F4D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18 (0x00A8F548) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18 (0x00A8F4D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19 (0x00A8F54C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19 (0x00A8F4DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20 (0x00A8F550) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20 (0x00A8F4E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21 (0x00A8F554) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21 (0x00A8F4E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22 (0x00A8F558) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22 (0x00A8F4E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23 (0x00A8F55C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23 (0x00A8F4EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24 (0x00A8F560) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24 (0x00A8F4F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25 (0x00A8F564) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25 (0x00A8F4F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26 (0x00A8F568) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26 (0x00A8F4F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27 (0x00A8F56C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27 (0x00A8F4FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28 (0x00A8F570) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28 (0x00A8F500) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29 (0x00A8F574) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29 (0x00A8F504) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30 (0x00A8F578) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30 (0x00A8F508) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31 (0x00A8F57C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31 (0x00A8F50C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32 (0x00A8F580) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32 (0x00A8F510) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33 (0x00A8F584) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33 (0x00A8F514) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34 (0x00A8F588) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34 (0x00A8F518) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35 (0x00A8F58C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35 (0x00A8F51C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36 (0x00A8F590) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36 (0x00A8F520) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37 (0x00A8F594) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37 (0x00A8F524) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38 (0x00A8F598) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38 (0x00A8F528) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39 (0x00A8F59C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39 (0x00A8F52C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40 (0x00A8F5A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40 (0x00A8F530) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41 (0x00A8F5A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41 (0x00A8F534) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42 (0x00A8F5A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42 (0x00A8F538) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43 (0x00A8F5AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43 (0x00A8F53C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44 (0x00A8F5B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44 (0x00A8F540) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45 (0x00A8F5B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45 (0x00A8F544) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46 (0x00A8F5B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46 (0x00A8F548) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47 (0x00A8F5BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47 (0x00A8F54C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48 (0x00A8F5C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48 (0x00A8F550) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49 (0x00A8F5C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49 (0x00A8F554) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50 (0x00A8F5C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50 (0x00A8F558) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51 (0x00A8F5CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51 (0x00A8F55C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52 (0x00A8F5D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52 (0x00A8F560) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53 (0x00A8F5D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53 (0x00A8F564) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54 (0x00A8F5D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54 (0x00A8F568) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55 (0x00A8F5DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55 (0x00A8F56C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56 (0x00A8F5E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56 (0x00A8F570) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57 (0x00A8F5E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57 (0x00A8F574) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58 (0x00A8F5E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58 (0x00A8F578) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59 (0x00A8F5EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59 (0x00A8F57C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60 (0x00A8F5F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60 (0x00A8F580) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61 (0x00A8F5F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61 (0x00A8F584) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62 (0x00A8F5F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62 (0x00A8F588) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63 (0x00A8F5FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63 (0x00A8F58C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64 (0x00A8F600) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64 (0x00A8F590) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65 (0x00A8F604) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65 (0x00A8F594) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66 (0x00A8F608) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66 (0x00A8F598) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67 (0x00A8F60C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67 (0x00A8F59C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68 (0x00A8F610) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68 (0x00A8F5A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69 (0x00A8F614) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69 (0x00A8F5A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70 (0x00A8F618) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70 (0x00A8F5A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71 (0x00A8F61C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71 (0x00A8F5AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72 (0x00A8F620) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72 (0x00A8F5B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73 (0x00A8F624) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73 (0x00A8F5B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74 (0x00A8F628) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74 (0x00A8F5B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75 (0x00A8F62C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75 (0x00A8F5BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76 (0x00A8F630) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76 (0x00A8F5C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77 (0x00A8F634) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77 (0x00A8F5C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78 (0x00A8F638) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78 (0x00A8F5C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79 (0x00A8F63C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79 (0x00A8F5CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80 (0x00A8F640) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80 (0x00A8F5D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81 (0x00A8F644) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81 (0x00A8F5D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82 (0x00A8F648) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82 (0x00A8F5D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83 (0x00A8F64C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83 (0x00A8F5DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84 (0x00A8F650) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84 (0x00A8F5E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85 (0x00A8F654) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85 (0x00A8F5E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86 (0x00A8F658) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86 (0x00A8F5E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87 (0x00A8F65C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87 (0x00A8F5EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88 (0x00A8F660) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88 (0x00A8F5F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89 (0x00A8F664) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89 (0x00A8F5F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90 (0x00A8F668) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90 (0x00A8F5F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91 (0x00A8F66C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91 (0x00A8F5FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92 (0x00A8F670) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92 (0x00A8F600) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93 (0x00A8F674) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93 (0x00A8F604) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94 (0x00A8F678) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94 (0x00A8F608) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95 (0x00A8F67C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95 (0x00A8F60C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96 (0x00A8F680) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96 (0x00A8F610) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97 (0x00A8F684) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97 (0x00A8F614) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98 (0x00A8F688) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98 (0x00A8F618) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99 (0x00A8F68C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99 (0x00A8F61C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100 (0x00A8F690) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100 (0x00A8F620) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101 (0x00A8F694) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101 (0x00A8F624) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102 (0x00A8F698) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102 (0x00A8F628) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103 (0x00A8F69C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103 (0x00A8F62C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104 (0x00A8F6A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104 (0x00A8F630) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105 (0x00A8F6A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105 (0x00A8F634) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106 (0x00A8F6A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106 (0x00A8F638) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107 (0x00A8F6AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107 (0x00A8F63C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108 (0x00A8F6B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108 (0x00A8F640) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109 (0x00A8F6B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109 (0x00A8F644) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110 (0x00A8F6B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110 (0x00A8F648) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111 (0x00A8F6BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111 (0x00A8F64C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112 (0x00A8F6C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112 (0x00A8F650) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113 (0x00A8F6C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113 (0x00A8F654) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114 (0x00A8F6C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114 (0x00A8F658) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115 (0x00A8F6CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115 (0x00A8F65C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116 (0x00A8F6D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116 (0x00A8F660) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117 (0x00A8F6D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117 (0x00A8F664) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118 (0x00A8F6D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118 (0x00A8F668) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119 (0x00A8F6DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119 (0x00A8F66C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120 (0x00A8F6E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120 (0x00A8F670) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121 (0x00A8F6E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121 (0x00A8F674) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122 (0x00A8F6E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122 (0x00A8F678) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123 (0x00A8F6EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123 (0x00A8F67C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124 (0x00A8F6F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124 (0x00A8F680) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125 (0x00A8F6F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125 (0x00A8F684) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126 (0x00A8F6F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126 (0x00A8F688) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127 (0x00A8F6FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127 (0x00A8F68C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128 (0x00A8F700) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128 (0x00A8F690) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129 (0x00A8F704) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129 (0x00A8F694) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130 (0x00A8F708) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130 (0x00A8F698) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131 (0x00A8F70C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131 (0x00A8F69C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132 (0x00A8F710) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132 (0x00A8F6A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133 (0x00A8F714) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133 (0x00A8F6A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134 (0x00A8F718) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134 (0x00A8F6A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135 (0x00A8F71C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135 (0x00A8F6AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136 (0x00A8F720) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136 (0x00A8F6B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137 (0x00A8F724) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137 (0x00A8F6B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138 (0x00A8F728) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138 (0x00A8F6B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139 (0x00A8F72C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139 (0x00A8F6BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140 (0x00A8F730) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140 (0x00A8F6C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141 (0x00A8F734) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141 (0x00A8F6C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142 (0x00A8F738) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142 (0x00A8F6C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143 (0x00A8F73C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143 (0x00A8F6CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144 (0x00A8F740) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144 (0x00A8F6D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145 (0x00A8F744) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145 (0x00A8F6D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146 (0x00A8F748) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146 (0x00A8F6D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147 (0x00A8F74C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147 (0x00A8F6DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148 (0x00A8F750) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148 (0x00A8F6E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149 (0x00A8F754) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149 (0x00A8F6E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150 (0x00A8F758) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150 (0x00A8F6E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151 (0x00A8F75C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151 (0x00A8F6EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152 (0x00A8F760) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152 (0x00A8F6F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153 (0x00A8F764) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153 (0x00A8F6F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154 (0x00A8F768) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154 (0x00A8F6F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155 (0x00A8F76C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155 (0x00A8F6FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156 (0x00A8F770) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156 (0x00A8F700) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157 (0x00A8F774) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157 (0x00A8F704) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158 (0x00A8F778) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158 (0x00A8F708) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159 (0x00A8F77C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159 (0x00A8F70C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160 (0x00A8F780) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160 (0x00A8F710) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161 (0x00A8F784) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161 (0x00A8F714) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162 (0x00A8F788) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162 (0x00A8F718) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163 (0x00A8F78C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163 (0x00A8F71C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164 (0x00A8F790) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164 (0x00A8F720) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165 (0x00A8F794) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165 (0x00A8F724) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166 (0x00A8F798) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166 (0x00A8F728) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167 (0x00A8F79C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167 (0x00A8F72C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168 (0x00A8F7A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168 (0x00A8F730) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169 (0x00A8F7A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169 (0x00A8F734) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170 (0x00A8F7A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170 (0x00A8F738) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171 (0x00A8F7AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171 (0x00A8F73C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172 (0x00A8F7B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172 (0x00A8F740) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173 (0x00A8F7B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173 (0x00A8F744) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174 (0x00A8F7B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174 (0x00A8F748) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175 (0x00A8F7BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175 (0x00A8F74C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176 (0x00A8F7C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176 (0x00A8F750) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177 (0x00A8F7C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177 (0x00A8F754) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178 (0x00A8F7C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178 (0x00A8F758) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179 (0x00A8F7CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179 (0x00A8F75C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180 (0x00A8F7D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180 (0x00A8F760) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181 (0x00A8F7D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181 (0x00A8F764) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182 (0x00A8F7D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182 (0x00A8F768) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183 (0x00A8F7DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183 (0x00A8F76C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184 (0x00A8F7E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184 (0x00A8F770) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185 (0x00A8F7E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185 (0x00A8F774) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186 (0x00A8F7E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186 (0x00A8F778) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187 (0x00A8F7EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187 (0x00A8F77C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188 (0x00A8F7F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188 (0x00A8F780) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189 (0x00A8F7F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189 (0x00A8F784) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190 (0x00A8F7F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190 (0x00A8F788) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191 (0x00A8F7FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191 (0x00A8F78C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192 (0x00A8F800) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192 (0x00A8F790) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193 (0x00A8F804) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193 (0x00A8F794) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194 (0x00A8F808) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194 (0x00A8F798) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195 (0x00A8F80C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195 (0x00A8F79C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196 (0x00A8F810) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196 (0x00A8F7A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197 (0x00A8F814) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197 (0x00A8F7A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198 (0x00A8F818) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198 (0x00A8F7A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199 (0x00A8F81C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199 (0x00A8F7AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200 (0x00A8F820) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200 (0x00A8F7B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201 (0x00A8F824) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201 (0x00A8F7B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202 (0x00A8F828) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202 (0x00A8F7B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203 (0x00A8F82C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203 (0x00A8F7BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204 (0x00A8F830) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204 (0x00A8F7C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205 (0x00A8F834) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205 (0x00A8F7C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206 (0x00A8F838) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206 (0x00A8F7C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207 (0x00A8F83C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207 (0x00A8F7CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208 (0x00A8F840) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208 (0x00A8F7D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209 (0x00A8F844) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209 (0x00A8F7D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210 (0x00A8F848) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210 (0x00A8F7D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211 (0x00A8F84C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211 (0x00A8F7DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212 (0x00A8F850) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212 (0x00A8F7E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213 (0x00A8F854) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213 (0x00A8F7E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214 (0x00A8F858) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214 (0x00A8F7E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215 (0x00A8F85C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215 (0x00A8F7EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216 (0x00A8F860) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216 (0x00A8F7F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217 (0x00A8F864) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217 (0x00A8F7F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218 (0x00A8F868) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218 (0x00A8F7F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219 (0x00A8F86C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219 (0x00A8F7FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220 (0x00A8F870) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220 (0x00A8F800) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221 (0x00A8F874) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221 (0x00A8F804) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222 (0x00A8F878) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222 (0x00A8F808) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223 (0x00A8F87C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223 (0x00A8F80C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224 (0x00A8F880) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224 (0x00A8F810) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225 (0x00A8F884) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225 (0x00A8F814) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226 (0x00A8F888) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226 (0x00A8F818) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227 (0x00A8F88C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227 (0x00A8F81C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228 (0x00A8F890) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228 (0x00A8F820) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229 (0x00A8F894) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229 (0x00A8F824) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230 (0x00A8F898) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230 (0x00A8F828) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231 (0x00A8F89C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231 (0x00A8F82C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232 (0x00A8F8A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232 (0x00A8F830) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233 (0x00A8F8A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233 (0x00A8F834) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234 (0x00A8F8A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234 (0x00A8F838) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235 (0x00A8F8AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235 (0x00A8F83C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236 (0x00A8F8B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236 (0x00A8F840) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237 (0x00A8F8B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237 (0x00A8F844) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238 (0x00A8F8B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238 (0x00A8F848) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239 (0x00A8F8BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239 (0x00A8F84C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240 (0x00A8F8C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240 (0x00A8F850) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241 (0x00A8F8C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241 (0x00A8F854) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242 (0x00A8F8C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242 (0x00A8F858) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243 (0x00A8F8CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243 (0x00A8F85C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244 (0x00A8F8D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244 (0x00A8F860) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245 (0x00A8F8D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245 (0x00A8F864) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246 (0x00A8F8D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246 (0x00A8F868) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247 (0x00A8F8DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247 (0x00A8F86C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248 (0x00A8F8E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248 (0x00A8F870) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249 (0x00A8F8E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249 (0x00A8F874) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250 (0x00A8F8E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250 (0x00A8F878) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251 (0x00A8F8EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251 (0x00A8F87C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252 (0x00A8F8F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252 (0x00A8F880) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253 (0x00A8F8F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253 (0x00A8F884) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254 (0x00A8F8F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254 (0x00A8F888) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255 (0x00A8F8FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255 (0x00A8F88C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256 (0x00A8F900) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256 (0x00A8F890) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257 (0x00A8F904) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257 (0x00A8F894) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258 (0x00A8F908) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258 (0x00A8F898) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259 (0x00A8F90C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259 (0x00A8F89C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260 (0x00A8F910) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260 (0x00A8F8A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261 (0x00A8F914) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261 (0x00A8F8A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262 (0x00A8F918) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262 (0x00A8F8A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263 (0x00A8F91C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263 (0x00A8F8AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264 (0x00A8F920) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264 (0x00A8F8B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265 (0x00A8F924) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265 (0x00A8F8B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266 (0x00A8F928) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266 (0x00A8F8B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267 (0x00A8F92C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267 (0x00A8F8BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268 (0x00A8F930) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268 (0x00A8F8C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269 (0x00A8F934) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269 (0x00A8F8C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270 (0x00A8F938) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270 (0x00A8F8C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271 (0x00A8F93C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271 (0x00A8F8CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272 (0x00A8F940) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272 (0x00A8F8D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273 (0x00A8F944) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273 (0x00A8F8D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274 (0x00A8F948) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274 (0x00A8F8D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275 (0x00A8F94C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275 (0x00A8F8DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276 (0x00A8F950) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276 (0x00A8F8E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277 (0x00A8F954) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277 (0x00A8F8E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278 (0x00A8F958) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278 (0x00A8F8E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279 (0x00A8F95C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279 (0x00A8F8EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280 (0x00A8F960) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280 (0x00A8F8F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281 (0x00A8F964) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281 (0x00A8F8F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282 (0x00A8F968) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282 (0x00A8F8F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283 (0x00A8F96C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283 (0x00A8F8FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284 (0x00A8F970) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284 (0x00A8F900) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285 (0x00A8F974) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285 (0x00A8F904) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286 (0x00A8F978) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286 (0x00A8F908) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287 (0x00A8F97C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287 (0x00A8F90C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288 (0x00A8F980) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288 (0x00A8F910) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289 (0x00A8F984) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289 (0x00A8F914) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290 (0x00A8F988) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290 (0x00A8F918) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291 (0x00A8F98C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291 (0x00A8F91C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292 (0x00A8F990) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292 (0x00A8F920) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293 (0x00A8F994) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293 (0x00A8F924) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294 (0x00A8F998) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294 (0x00A8F928) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295 (0x00A8F99C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295 (0x00A8F92C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296 (0x00A8F9A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296 (0x00A8F930) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297 (0x00A8F9A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297 (0x00A8F934) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298 (0x00A8F9A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298 (0x00A8F938) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299 (0x00A8F9AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299 (0x00A8F93C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300 (0x00A8F9B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300 (0x00A8F940) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301 (0x00A8F9B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301 (0x00A8F944) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302 (0x00A8F9B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302 (0x00A8F948) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303 (0x00A8F9BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303 (0x00A8F94C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304 (0x00A8F9C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304 (0x00A8F950) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305 (0x00A8F9C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305 (0x00A8F954) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306 (0x00A8F9C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306 (0x00A8F958) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307 (0x00A8F9CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307 (0x00A8F95C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308 (0x00A8F9D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308 (0x00A8F960) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309 (0x00A8F9D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309 (0x00A8F964) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310 (0x00A8F9D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310 (0x00A8F968) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311 (0x00A8F9DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311 (0x00A8F96C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312 (0x00A8F9E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312 (0x00A8F970) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313 (0x00A8F9E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313 (0x00A8F974) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314 (0x00A8F9E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314 (0x00A8F978) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315 (0x00A8F9EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315 (0x00A8F97C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316 (0x00A8F9F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316 (0x00A8F980) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317 (0x00A8F9F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317 (0x00A8F984) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318 (0x00A8F9F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318 (0x00A8F988) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319 (0x00A8F9FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319 (0x00A8F98C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320 (0x00A8FA00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320 (0x00A8F990) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321 (0x00A8FA04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321 (0x00A8F994) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322 (0x00A8FA08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322 (0x00A8F998) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323 (0x00A8FA0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323 (0x00A8F99C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324 (0x00A8FA10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324 (0x00A8F9A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325 (0x00A8FA14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325 (0x00A8F9A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326 (0x00A8FA18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326 (0x00A8F9A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327 (0x00A8FA1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327 (0x00A8F9AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328 (0x00A8FA20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328 (0x00A8F9B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329 (0x00A8FA24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329 (0x00A8F9B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330 (0x00A8FA28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330 (0x00A8F9B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331 (0x00A8FA2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331 (0x00A8F9BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332 (0x00A8FA30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332 (0x00A8F9C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333 (0x00A8FA34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333 (0x00A8F9C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334 (0x00A8FA38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334 (0x00A8F9C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335 (0x00A8FA3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335 (0x00A8F9CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336 (0x00A8FA40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336 (0x00A8F9D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337 (0x00A8FA44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337 (0x00A8F9D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338 (0x00A8FA48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338 (0x00A8F9D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339 (0x00A8FA4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339 (0x00A8F9DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340 (0x00A8FA50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340 (0x00A8F9E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341 (0x00A8FA54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341 (0x00A8F9E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342 (0x00A8FA58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342 (0x00A8F9E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343 (0x00A8FA5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343 (0x00A8F9EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344 (0x00A8FA60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344 (0x00A8F9F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345 (0x00A8FA64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345 (0x00A8F9F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346 (0x00A8FA68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346 (0x00A8F9F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347 (0x00A8FA6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347 (0x00A8F9FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348 (0x00A8FA70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348 (0x00A8FA00) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349 (0x00A8FA74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349 (0x00A8FA04) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350 (0x00A8FA78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350 (0x00A8FA08) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351 (0x00A8FA7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351 (0x00A8FA0C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352 (0x00A8FA80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352 (0x00A8FA10) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353 (0x00A8FA84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353 (0x00A8FA14) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354 (0x00A8FA88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354 (0x00A8FA18) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355 (0x00A8FA8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355 (0x00A8FA1C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356 (0x00A8FA90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356 (0x00A8FA20) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357 (0x00A8FA94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357 (0x00A8FA24) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358 (0x00A8FA98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358 (0x00A8FA28) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359 (0x00A8FA9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359 (0x00A8FA2C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360 (0x00A8FAA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360 (0x00A8FA30) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361 (0x00A8FAA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361 (0x00A8FA34) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362 (0x00A8FAA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362 (0x00A8FA38) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363 (0x00A8FAAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363 (0x00A8FA3C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364 (0x00A8FAB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364 (0x00A8FA40) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365 (0x00A8FAB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365 (0x00A8FA44) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366 (0x00A8FAB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366 (0x00A8FA48) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367 (0x00A8FABC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367 (0x00A8FA4C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368 (0x00A8FAC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368 (0x00A8FA50) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369 (0x00A8FAC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369 (0x00A8FA54) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370 (0x00A8FAC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370 (0x00A8FA58) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371 (0x00A8FACC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371 (0x00A8FA5C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372 (0x00A8FAD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372 (0x00A8FA60) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373 (0x00A8FAD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373 (0x00A8FA64) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374 (0x00A8FAD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374 (0x00A8FA68) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375 (0x00A8FADC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375 (0x00A8FA6C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376 (0x00A8FAE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376 (0x00A8FA70) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377 (0x00A8FAE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377 (0x00A8FA74) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378 (0x00A8FAE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378 (0x00A8FA78) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379 (0x00A8FAEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379 (0x00A8FA7C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380 (0x00A8FAF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380 (0x00A8FA80) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381 (0x00A8FAF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381 (0x00A8FA84) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382 (0x00A8FAF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382 (0x00A8FA88) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383 (0x00A8FAFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383 (0x00A8FA8C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384 (0x00A8FB00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384 (0x00A8FA90) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385 (0x00A8FB04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385 (0x00A8FA94) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386 (0x00A8FB08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386 (0x00A8FA98) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387 (0x00A8FB0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387 (0x00A8FA9C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388 (0x00A8FB10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388 (0x00A8FAA0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389 (0x00A8FB14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389 (0x00A8FAA4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390 (0x00A8FB18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390 (0x00A8FAA8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391 (0x00A8FB1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391 (0x00A8FAAC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392 (0x00A8FB20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392 (0x00A8FAB0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393 (0x00A8FB24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393 (0x00A8FAB4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394 (0x00A8FB28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394 (0x00A8FAB8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395 (0x00A8FB2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395 (0x00A8FABC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396 (0x00A8FB30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396 (0x00A8FAC0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397 (0x00A8FB34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397 (0x00A8FAC4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398 (0x00A8FB38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398 (0x00A8FAC8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399 (0x00A8FB3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399 (0x00A8FACC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400 (0x00A8FB40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400 (0x00A8FAD0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401 (0x00A8FB44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401 (0x00A8FAD4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402 (0x00A8FB48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402 (0x00A8FAD8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403 (0x00A8FB4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403 (0x00A8FADC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404 (0x00A8FB50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404 (0x00A8FAE0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405 (0x00A8FB54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405 (0x00A8FAE4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406 (0x00A8FB58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406 (0x00A8FAE8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407 (0x00A8FB5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407 (0x00A8FAEC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408 (0x00A8FB60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408 (0x00A8FAF0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409 (0x00A8FB64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409 (0x00A8FAF4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410 (0x00A8FB68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410 (0x00A8FAF8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411 (0x00A8FB6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411 (0x00A8FAFC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412 (0x00A8FB70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412 (0x00A8FB00) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413 (0x00A8FB74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413 (0x00A8FB04) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414 (0x00A8FB78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414 (0x00A8FB08) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415 (0x00A8FB7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415 (0x00A8FB0C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416 (0x00A8FB80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416 (0x00A8FB10) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417 (0x00A8FB84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417 (0x00A8FB14) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418 (0x00A8FB88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418 (0x00A8FB18) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419 (0x00A8FB8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419 (0x00A8FB1C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420 (0x00A8FB90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420 (0x00A8FB20) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421 (0x00A8FB94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421 (0x00A8FB24) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422 (0x00A8FB98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422 (0x00A8FB28) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423 (0x00A8FB9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423 (0x00A8FB2C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424 (0x00A8FBA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424 (0x00A8FB30) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425 (0x00A8FBA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425 (0x00A8FB34) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426 (0x00A8FBA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426 (0x00A8FB38) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427 (0x00A8FBAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427 (0x00A8FB3C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428 (0x00A8FBB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428 (0x00A8FB40) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429 (0x00A8FBB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429 (0x00A8FB44) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430 (0x00A8FBB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430 (0x00A8FB48) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431 (0x00A8FBBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431 (0x00A8FB4C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432 (0x00A8FBC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432 (0x00A8FB50) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433 (0x00A8FBC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433 (0x00A8FB54) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434 (0x00A8FBC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434 (0x00A8FB58) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435 (0x00A8FBCC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435 (0x00A8FB5C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436 (0x00A8FBD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436 (0x00A8FB60) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437 (0x00A8FBD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437 (0x00A8FB64) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438 (0x00A8FBD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438 (0x00A8FB68) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439 (0x00A8FBDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439 (0x00A8FB6C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440 (0x00A8FBE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440 (0x00A8FB70) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441 (0x00A8FBE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441 (0x00A8FB74) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442 (0x00A8FBE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442 (0x00A8FB78) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443 (0x00A8FBEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443 (0x00A8FB7C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444 (0x00A8FBF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444 (0x00A8FB80) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445 (0x00A8FBF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445 (0x00A8FB84) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446 (0x00A8FBF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446 (0x00A8FB88) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447 (0x00A8FBFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447 (0x00A8FB8C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448 (0x00A8FC00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448 (0x00A8FB90) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449 (0x00A8FC04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449 (0x00A8FB94) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450 (0x00A8FC08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450 (0x00A8FB98) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451 (0x00A8FC0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451 (0x00A8FB9C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452 (0x00A8FC10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452 (0x00A8FBA0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453 (0x00A8FC14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453 (0x00A8FBA4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454 (0x00A8FC18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454 (0x00A8FBA8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455 (0x00A8FC1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455 (0x00A8FBAC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456 (0x00A8FC20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456 (0x00A8FBB0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457 (0x00A8FC24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457 (0x00A8FBB4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458 (0x00A8FC28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458 (0x00A8FBB8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459 (0x00A8FC2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459 (0x00A8FBBC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460 (0x00A8FC30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460 (0x00A8FBC0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461 (0x00A8FC34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461 (0x00A8FBC4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462 (0x00A8FC38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462 (0x00A8FBC8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463 (0x00A8FC3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463 (0x00A8FBCC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464 (0x00A8FC40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464 (0x00A8FBD0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465 (0x00A8FC44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465 (0x00A8FBD4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466 (0x00A8FC48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466 (0x00A8FBD8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467 (0x00A8FC4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467 (0x00A8FBDC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468 (0x00A8FC50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468 (0x00A8FBE0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469 (0x00A8FC54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469 (0x00A8FBE4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470 (0x00A8FC58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470 (0x00A8FBE8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471 (0x00A8FC5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471 (0x00A8FBEC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472 (0x00A8FC60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472 (0x00A8FBF0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473 (0x00A8FC64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473 (0x00A8FBF4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474 (0x00A8FC68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474 (0x00A8FBF8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475 (0x00A8FC6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475 (0x00A8FBFC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476 (0x00A8FC70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476 (0x00A8FC00) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477 (0x00A8FC74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477 (0x00A8FC04) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478 (0x00A8FC78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478 (0x00A8FC08) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479 (0x00A8FC7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479 (0x00A8FC0C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480 (0x00A8FC80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480 (0x00A8FC10) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481 (0x00A8FC84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481 (0x00A8FC14) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482 (0x00A8FC88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482 (0x00A8FC18) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483 (0x00A8FC8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483 (0x00A8FC1C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484 (0x00A8FC90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484 (0x00A8FC20) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485 (0x00A8FC94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485 (0x00A8FC24) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486 (0x00A8FC98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486 (0x00A8FC28) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487 (0x00A8FC9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487 (0x00A8FC2C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488 (0x00A8FCA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488 (0x00A8FC30) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489 (0x00A8FCA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489 (0x00A8FC34) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490 (0x00A8FCA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490 (0x00A8FC38) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491 (0x00A8FCAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491 (0x00A8FC3C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492 (0x00A8FCB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492 (0x00A8FC40) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493 (0x00A8FCB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493 (0x00A8FC44) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494 (0x00A8FCB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494 (0x00A8FC48) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495 (0x00A8FCBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495 (0x00A8FC4C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496 (0x00A8FCC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496 (0x00A8FC50) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497 (0x00A8FCC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497 (0x00A8FC54) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498 (0x00A8FCC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498 (0x00A8FC58) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499 (0x00A8FCCC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499 (0x00A8FC5C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500 (0x00A8FCD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500 (0x00A8FC60) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501 (0x00A8FCD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501 (0x00A8FC64) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502 (0x00A8FCD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502 (0x00A8FC68) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503 (0x00A8FCDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503 (0x00A8FC6C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504 (0x00A8FCE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504 (0x00A8FC70) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505 (0x00A8FCE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505 (0x00A8FC74) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506 (0x00A8FCE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506 (0x00A8FC78) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507 (0x00A8FCEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507 (0x00A8FC7C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508 (0x00A8FCF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508 (0x00A8FC80) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509 (0x00A8FCF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509 (0x00A8FC84) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510 (0x00A8FCF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510 (0x00A8FC88) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511 (0x00A8FCFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511 (0x00A8FC8C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512 (0x00A8FD00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512 (0x00A8FC90) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513 (0x00A8FD04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513 (0x00A8FC94) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514 (0x00A8FD08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514 (0x00A8FC98) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515 (0x00A8FD0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515 (0x00A8FC9C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516 (0x00A8FD10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516 (0x00A8FCA0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517 (0x00A8FD14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517 (0x00A8FCA4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518 (0x00A8FD18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518 (0x00A8FCA8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519 (0x00A8FD1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519 (0x00A8FCAC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520 (0x00A8FD20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520 (0x00A8FCB0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521 (0x00A8FD24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521 (0x00A8FCB4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522 (0x00A8FD28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522 (0x00A8FCB8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523 (0x00A8FD2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523 (0x00A8FCBC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524 (0x00A8FD30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524 (0x00A8FCC0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525 (0x00A8FD34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525 (0x00A8FCC4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526 (0x00A8FD38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526 (0x00A8FCC8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527 (0x00A8FD3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527 (0x00A8FCCC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528 (0x00A8FD40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528 (0x00A8FCD0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529 (0x00A8FD44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529 (0x00A8FCD4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530 (0x00A8FD48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530 (0x00A8FCD8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531 (0x00A8FD4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531 (0x00A8FCDC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532 (0x00A8FD50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532 (0x00A8FCE0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533 (0x00A8FD54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533 (0x00A8FCE4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534 (0x00A8FD58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534 (0x00A8FCE8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535 (0x00A8FD5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535 (0x00A8FCEC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536 (0x00A8FD60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536 (0x00A8FCF0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537 (0x00A8FD64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537 (0x00A8FCF4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538 (0x00A8FD68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538 (0x00A8FCF8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539 (0x00A8FD6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539 (0x00A8FCFC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540 (0x00A8FD70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540 (0x00A8FD00) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541 (0x00A8FD74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541 (0x00A8FD04) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542 (0x00A8FD78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542 (0x00A8FD08) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543 (0x00A8FD7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543 (0x00A8FD0C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544 (0x00A8FD80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544 (0x00A8FD10) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545 (0x00A8FD84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545 (0x00A8FD14) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546 (0x00A8FD88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546 (0x00A8FD18) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547 (0x00A8FD8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547 (0x00A8FD1C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548 (0x00A8FD90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548 (0x00A8FD20) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549 (0x00A8FD94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549 (0x00A8FD24) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550 (0x00A8FD98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550 (0x00A8FD28) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551 (0x00A8FD9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551 (0x00A8FD2C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552 (0x00A8FDA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552 (0x00A8FD30) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553 (0x00A8FDA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553 (0x00A8FD34) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554 (0x00A8FDA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554 (0x00A8FD38) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555 (0x00A8FDAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555 (0x00A8FD3C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556 (0x00A8FDB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556 (0x00A8FD40) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557 (0x00A8FDB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557 (0x00A8FD44) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558 (0x00A8FDB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558 (0x00A8FD48) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559 (0x00A8FDBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559 (0x00A8FD4C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560 (0x00A8FDC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560 (0x00A8FD50) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561 (0x00A8FDC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561 (0x00A8FD54) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562 (0x00A8FDC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562 (0x00A8FD58) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563 (0x00A8FDCC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563 (0x00A8FD5C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564 (0x00A8FDD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564 (0x00A8FD60) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565 (0x00A8FDD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565 (0x00A8FD64) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566 (0x00A8FDD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566 (0x00A8FD68) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567 (0x00A8FDDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567 (0x00A8FD6C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568 (0x00A8FDE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568 (0x00A8FD70) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569 (0x00A8FDE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569 (0x00A8FD74) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570 (0x00A8FDE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570 (0x00A8FD78) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571 (0x00A8FDEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571 (0x00A8FD7C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572 (0x00A8FDF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572 (0x00A8FD80) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573 (0x00A8FDF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573 (0x00A8FD84) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574 (0x00A8FDF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574 (0x00A8FD88) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575 (0x00A8FDFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575 (0x00A8FD8C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576 (0x00A8FE00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576 (0x00A8FD90) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577 (0x00A8FE04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577 (0x00A8FD94) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578 (0x00A8FE08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578 (0x00A8FD98) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579 (0x00A8FE0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579 (0x00A8FD9C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580 (0x00A8FE10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580 (0x00A8FDA0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581 (0x00A8FE14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581 (0x00A8FDA4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582 (0x00A8FE18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582 (0x00A8FDA8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583 (0x00A8FE1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583 (0x00A8FDAC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584 (0x00A8FE20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584 (0x00A8FDB0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585 (0x00A8FE24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585 (0x00A8FDB4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586 (0x00A8FE28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586 (0x00A8FDB8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587 (0x00A8FE2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587 (0x00A8FDBC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588 (0x00A8FE30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588 (0x00A8FDC0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589 (0x00A8FE34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589 (0x00A8FDC4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590 (0x00A8FE38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590 (0x00A8FDC8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591 (0x00A8FE3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591 (0x00A8FDCC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592 (0x00A8FE40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592 (0x00A8FDD0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593 (0x00A8FE44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593 (0x00A8FDD4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594 (0x00A8FE48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594 (0x00A8FDD8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595 (0x00A8FE4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595 (0x00A8FDDC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596 (0x00A8FE50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596 (0x00A8FDE0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597 (0x00A8FE54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597 (0x00A8FDE4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598 (0x00A8FE58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598 (0x00A8FDE8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599 (0x00A8FE5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599 (0x00A8FDEC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600 (0x00A8FE60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600 (0x00A8FDF0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601 (0x00A8FE64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601 (0x00A8FDF4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602 (0x00A8FE68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602 (0x00A8FDF8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603 (0x00A8FE6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603 (0x00A8FDFC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604 (0x00A8FE70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604 (0x00A8FE00) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605 (0x00A8FE74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605 (0x00A8FE04) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606 (0x00A8FE78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606 (0x00A8FE08) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607 (0x00A8FE7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607 (0x00A8FE0C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608 (0x00A8FE80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608 (0x00A8FE10) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609 (0x00A8FE84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609 (0x00A8FE14) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610 (0x00A8FE88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610 (0x00A8FE18) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611 (0x00A8FE8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611 (0x00A8FE1C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612 (0x00A8FE90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612 (0x00A8FE20) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613 (0x00A8FE94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613 (0x00A8FE24) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614 (0x00A8FE98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614 (0x00A8FE28) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615 (0x00A8FE9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615 (0x00A8FE2C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616 (0x00A8FEA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616 (0x00A8FE30) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617 (0x00A8FEA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617 (0x00A8FE34) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618 (0x00A8FEA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618 (0x00A8FE38) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619 (0x00A8FEAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619 (0x00A8FE3C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620 (0x00A8FEB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620 (0x00A8FE40) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621 (0x00A8FEB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621 (0x00A8FE44) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622 (0x00A8FEB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622 (0x00A8FE48) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623 (0x00A8FEBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623 (0x00A8FE4C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624 (0x00A8FEC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624 (0x00A8FE50) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625 (0x00A8FEC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625 (0x00A8FE54) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626 (0x00A8FEC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626 (0x00A8FE58) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627 (0x00A8FECC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627 (0x00A8FE5C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628 (0x00A8FED0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628 (0x00A8FE60) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629 (0x00A8FED4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629 (0x00A8FE64) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630 (0x00A8FED8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630 (0x00A8FE68) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631 (0x00A8FEDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631 (0x00A8FE6C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632 (0x00A8FEE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632 (0x00A8FE70) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633 (0x00A8FEE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633 (0x00A8FE74) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634 (0x00A8FEE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634 (0x00A8FE78) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635 (0x00A8FEEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635 (0x00A8FE7C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636 (0x00A8FEF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636 (0x00A8FE80) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637 (0x00A8FEF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637 (0x00A8FE84) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638 (0x00A8FEF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638 (0x00A8FE88) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639 (0x00A8FEFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639 (0x00A8FE8C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640 (0x00A8FF00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640 (0x00A8FE90) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641 (0x00A8FF04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641 (0x00A8FE94) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642 (0x00A8FF08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642 (0x00A8FE98) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643 (0x00A8FF0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643 (0x00A8FE9C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644 (0x00A8FF10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644 (0x00A8FEA0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645 (0x00A8FF14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645 (0x00A8FEA4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646 (0x00A8FF18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646 (0x00A8FEA8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647 (0x00A8FF1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647 (0x00A8FEAC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648 (0x00A8FF20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648 (0x00A8FEB0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649 (0x00A8FF24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649 (0x00A8FEB4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650 (0x00A8FF28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650 (0x00A8FEB8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651 (0x00A8FF2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651 (0x00A8FEBC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652 (0x00A8FF30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652 (0x00A8FEC0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653 (0x00A8FF34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653 (0x00A8FEC4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654 (0x00A8FF38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654 (0x00A8FEC8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655 (0x00A8FF3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655 (0x00A8FECC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656 (0x00A8FF40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656 (0x00A8FED0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657 (0x00A8FF44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657 (0x00A8FED4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658 (0x00A8FF48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658 (0x00A8FED8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659 (0x00A8FF4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659 (0x00A8FEDC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660 (0x00A8FF50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660 (0x00A8FEE0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661 (0x00A8FF54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661 (0x00A8FEE4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662 (0x00A8FF58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662 (0x00A8FEE8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663 (0x00A8FF5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663 (0x00A8FEEC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664 (0x00A8FF60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664 (0x00A8FEF0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665 (0x00A8FF64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665 (0x00A8FEF4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666 (0x00A8FF68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666 (0x00A8FEF8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667 (0x00A8FF6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667 (0x00A8FEFC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668 (0x00A8FF70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668 (0x00A8FF00) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669 (0x00A8FF74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669 (0x00A8FF04) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670 (0x00A8FF78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670 (0x00A8FF08) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671 (0x00A8FF7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671 (0x00A8FF0C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672 (0x00A8FF80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672 (0x00A8FF10) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673 (0x00A8FF84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673 (0x00A8FF14) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674 (0x00A8FF88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674 (0x00A8FF18) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675 (0x00A8FF8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675 (0x00A8FF1C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676 (0x00A8FF90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676 (0x00A8FF20) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677 (0x00A8FF94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677 (0x00A8FF24) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678 (0x00A8FF98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678 (0x00A8FF28) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679 (0x00A8FF9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679 (0x00A8FF2C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680 (0x00A8FFA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680 (0x00A8FF30) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681 (0x00A8FFA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681 (0x00A8FF34) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682 (0x00A8FFA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682 (0x00A8FF38) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683 (0x00A8FFAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683 (0x00A8FF3C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684 (0x00A8FFB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684 (0x00A8FF40) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685 (0x00A8FFB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685 (0x00A8FF44) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686 (0x00A8FFB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686 (0x00A8FF48) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687 (0x00A8FFBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687 (0x00A8FF4C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688 (0x00A8FFC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688 (0x00A8FF50) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689 (0x00A8FFC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689 (0x00A8FF54) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690 (0x00A8FFC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690 (0x00A8FF58) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691 (0x00A8FFCC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691 (0x00A8FF5C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692 (0x00A8FFD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692 (0x00A8FF60) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693 (0x00A8FFD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693 (0x00A8FF64) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694 (0x00A8FFD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694 (0x00A8FF68) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695 (0x00A8FFDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695 (0x00A8FF6C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696 (0x00A8FFE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696 (0x00A8FF70) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697 (0x00A8FFE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697 (0x00A8FF74) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698 (0x00A8FFE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698 (0x00A8FF78) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699 (0x00A8FFEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699 (0x00A8FF7C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700 (0x00A8FFF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700 (0x00A8FF80) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701 (0x00A8FFF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701 (0x00A8FF84) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702 (0x00A8FFF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702 (0x00A8FF88) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703 (0x00A8FFFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703 (0x00A8FF8C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704 (0x00A90000) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704 (0x00A8FF90) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705 (0x00A90004) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705 (0x00A8FF94) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706 (0x00A90008) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706 (0x00A8FF98) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707 (0x00A9000C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707 (0x00A8FF9C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708 (0x00A90010) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708 (0x00A8FFA0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709 (0x00A90014) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709 (0x00A8FFA4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710 (0x00A90018) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710 (0x00A8FFA8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711 (0x00A9001C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711 (0x00A8FFAC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712 (0x00A90020) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712 (0x00A8FFB0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713 (0x00A90024) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713 (0x00A8FFB4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714 (0x00A90028) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714 (0x00A8FFB8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715 (0x00A9002C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715 (0x00A8FFBC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716 (0x00A90030) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716 (0x00A8FFC0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717 (0x00A90034) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717 (0x00A8FFC4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718 (0x00A90038) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718 (0x00A8FFC8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719 (0x00A9003C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719 (0x00A8FFCC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720 (0x00A90040) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720 (0x00A8FFD0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721 (0x00A90044) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721 (0x00A8FFD4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722 (0x00A90048) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722 (0x00A8FFD8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723 (0x00A9004C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723 (0x00A8FFDC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724 (0x00A90050) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724 (0x00A8FFE0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725 (0x00A90054) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725 (0x00A8FFE4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726 (0x00A90058) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726 (0x00A8FFE8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727 (0x00A9005C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727 (0x00A8FFEC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728 (0x00A90060) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728 (0x00A8FFF0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729 (0x00A90064) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729 (0x00A8FFF4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730 (0x00A90068) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730 (0x00A8FFF8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731 (0x00A9006C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731 (0x00A8FFFC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732 (0x00A90070) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732 (0x00A90000) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733 (0x00A90074) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733 (0x00A90004) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734 (0x00A90078) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734 (0x00A90008) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735 (0x00A9007C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735 (0x00A9000C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736 (0x00A90080) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736 (0x00A90010) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737 (0x00A90084) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737 (0x00A90014) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738 (0x00A90088) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738 (0x00A90018) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739 (0x00A9008C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739 (0x00A9001C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740 (0x00A90090) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740 (0x00A90020) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741 (0x00A90094) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741 (0x00A90024) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742 (0x00A90098) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742 (0x00A90028) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743 (0x00A9009C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743 (0x00A9002C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744 (0x00A900A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744 (0x00A90030) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745 (0x00A900A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745 (0x00A90034) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746 (0x00A900A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746 (0x00A90038) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747 (0x00A900AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747 (0x00A9003C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748 (0x00A900B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748 (0x00A90040) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749 (0x00A900B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749 (0x00A90044) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750 (0x00A900B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750 (0x00A90048) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751 (0x00A900BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751 (0x00A9004C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752 (0x00A900C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752 (0x00A90050) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753 (0x00A900C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753 (0x00A90054) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754 (0x00A900C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754 (0x00A90058) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755 (0x00A900CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755 (0x00A9005C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756 (0x00A900D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756 (0x00A90060) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757 (0x00A900D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757 (0x00A90064) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758 (0x00A900D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758 (0x00A90068) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759 (0x00A900DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759 (0x00A9006C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760 (0x00A900E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760 (0x00A90070) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761 (0x00A900E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761 (0x00A90074) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762 (0x00A900E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762 (0x00A90078) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763 (0x00A900EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763 (0x00A9007C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764 (0x00A900F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764 (0x00A90080) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765 (0x00A900F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765 (0x00A90084) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766 (0x00A900F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766 (0x00A90088) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767 (0x00A900FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767 (0x00A9008C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768 (0x00A90100) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768 (0x00A90090) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769 (0x00A90104) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769 (0x00A90094) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770 (0x00A90108) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770 (0x00A90098) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771 (0x00A9010C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771 (0x00A9009C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772 (0x00A90110) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772 (0x00A900A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773 (0x00A90114) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773 (0x00A900A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774 (0x00A90118) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774 (0x00A900A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775 (0x00A9011C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775 (0x00A900AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776 (0x00A90120) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776 (0x00A900B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777 (0x00A90124) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777 (0x00A900B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778 (0x00A90128) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778 (0x00A900B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779 (0x00A9012C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779 (0x00A900BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780 (0x00A90130) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780 (0x00A900C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781 (0x00A90134) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781 (0x00A900C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782 (0x00A90138) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782 (0x00A900C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783 (0x00A9013C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783 (0x00A900CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784 (0x00A90140) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784 (0x00A900D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785 (0x00A90144) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785 (0x00A900D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786 (0x00A90148) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786 (0x00A900D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787 (0x00A9014C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787 (0x00A900DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788 (0x00A90150) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788 (0x00A900E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789 (0x00A90154) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789 (0x00A900E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790 (0x00A90158) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790 (0x00A900E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791 (0x00A9015C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791 (0x00A900EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792 (0x00A90160) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792 (0x00A900F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793 (0x00A90164) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793 (0x00A900F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794 (0x00A90168) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794 (0x00A900F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795 (0x00A9016C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795 (0x00A900FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796 (0x00A90170) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796 (0x00A90100) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797 (0x00A90174) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797 (0x00A90104) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798 (0x00A90178) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798 (0x00A90108) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799 (0x00A9017C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799 (0x00A9010C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800 (0x00A90180) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800 (0x00A90110) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801 (0x00A90184) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801 (0x00A90114) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802 (0x00A90188) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802 (0x00A90118) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803 (0x00A9018C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803 (0x00A9011C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804 (0x00A90190) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804 (0x00A90120) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805 (0x00A90194) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805 (0x00A90124) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806 (0x00A90198) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806 (0x00A90128) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807 (0x00A9019C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807 (0x00A9012C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808 (0x00A901A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808 (0x00A90130) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809 (0x00A901A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809 (0x00A90134) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810 (0x00A901A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810 (0x00A90138) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811 (0x00A901AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811 (0x00A9013C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812 (0x00A901B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812 (0x00A90140) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813 (0x00A901B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813 (0x00A90144) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814 (0x00A901B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814 (0x00A90148) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815 (0x00A901BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815 (0x00A9014C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816 (0x00A901C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816 (0x00A90150) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817 (0x00A901C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817 (0x00A90154) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818 (0x00A901C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818 (0x00A90158) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819 (0x00A901CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819 (0x00A9015C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820 (0x00A901D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820 (0x00A90160) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821 (0x00A901D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821 (0x00A90164) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822 (0x00A901D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822 (0x00A90168) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823 (0x00A901DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823 (0x00A9016C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824 (0x00A901E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824 (0x00A90170) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825 (0x00A901E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825 (0x00A90174) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826 (0x00A901E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826 (0x00A90178) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827 (0x00A901EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827 (0x00A9017C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828 (0x00A901F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828 (0x00A90180) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829 (0x00A901F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829 (0x00A90184) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830 (0x00A901F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830 (0x00A90188) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831 (0x00A901FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831 (0x00A9018C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832 (0x00A90200) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832 (0x00A90190) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833 (0x00A90204) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833 (0x00A90194) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834 (0x00A90208) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834 (0x00A90198) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835 (0x00A9020C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835 (0x00A9019C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836 (0x00A90210) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836 (0x00A901A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837 (0x00A90214) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837 (0x00A901A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838 (0x00A90218) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838 (0x00A901A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839 (0x00A9021C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839 (0x00A901AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840 (0x00A90220) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840 (0x00A901B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841 (0x00A90224) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841 (0x00A901B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842 (0x00A90228) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842 (0x00A901B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843 (0x00A9022C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843 (0x00A901BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844 (0x00A90230) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844 (0x00A901C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845 (0x00A90234) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845 (0x00A901C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846 (0x00A90238) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846 (0x00A901C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847 (0x00A9023C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847 (0x00A901CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848 (0x00A90240) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848 (0x00A901D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849 (0x00A90244) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849 (0x00A901D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850 (0x00A90248) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850 (0x00A901D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851 (0x00A9024C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851 (0x00A901DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852 (0x00A90250) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852 (0x00A901E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853 (0x00A90254) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853 (0x00A901E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854 (0x00A90258) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854 (0x00A901E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855 (0x00A9025C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855 (0x00A901EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856 (0x00A90260) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856 (0x00A901F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857 (0x00A90264) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857 (0x00A901F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858 (0x00A90268) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858 (0x00A901F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859 (0x00A9026C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859 (0x00A901FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860 (0x00A90270) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860 (0x00A90200) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861 (0x00A90274) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861 (0x00A90204) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862 (0x00A90278) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862 (0x00A90208) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863 (0x00A9027C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863 (0x00A9020C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864 (0x00A90280) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864 (0x00A90210) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865 (0x00A90284) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865 (0x00A90214) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866 (0x00A90288) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866 (0x00A90218) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867 (0x00A9028C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867 (0x00A9021C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868 (0x00A90290) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868 (0x00A90220) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869 (0x00A90294) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869 (0x00A90224) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870 (0x00A90298) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870 (0x00A90228) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871 (0x00A9029C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871 (0x00A9022C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872 (0x00A902A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872 (0x00A90230) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873 (0x00A902A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873 (0x00A90234) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874 (0x00A902A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874 (0x00A90238) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875 (0x00A902AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875 (0x00A9023C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876 (0x00A902B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876 (0x00A90240) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877 (0x00A902B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877 (0x00A90244) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878 (0x00A902B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878 (0x00A90248) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879 (0x00A902BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879 (0x00A9024C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880 (0x00A902C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880 (0x00A90250) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881 (0x00A902C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881 (0x00A90254) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882 (0x00A902C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882 (0x00A90258) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883 (0x00A902CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883 (0x00A9025C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884 (0x00A902D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884 (0x00A90260) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885 (0x00A902D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885 (0x00A90264) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886 (0x00A902D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886 (0x00A90268) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887 (0x00A902DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887 (0x00A9026C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888 (0x00A902E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888 (0x00A90270) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889 (0x00A902E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889 (0x00A90274) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890 (0x00A902E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890 (0x00A90278) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891 (0x00A902EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891 (0x00A9027C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892 (0x00A902F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892 (0x00A90280) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893 (0x00A902F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893 (0x00A90284) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894 (0x00A902F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894 (0x00A90288) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895 (0x00A902FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895 (0x00A9028C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896 (0x00A90300) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896 (0x00A90290) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897 (0x00A90304) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897 (0x00A90294) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898 (0x00A90308) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898 (0x00A90298) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899 (0x00A9030C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899 (0x00A9029C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900 (0x00A90310) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900 (0x00A902A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901 (0x00A90314) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901 (0x00A902A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902 (0x00A90318) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902 (0x00A902A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903 (0x00A9031C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903 (0x00A902AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904 (0x00A90320) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904 (0x00A902B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905 (0x00A90324) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905 (0x00A902B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906 (0x00A90328) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906 (0x00A902B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907 (0x00A9032C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907 (0x00A902BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908 (0x00A90330) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908 (0x00A902C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909 (0x00A90334) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909 (0x00A902C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910 (0x00A90338) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910 (0x00A902C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911 (0x00A9033C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911 (0x00A902CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912 (0x00A90340) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912 (0x00A902D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913 (0x00A90344) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913 (0x00A902D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914 (0x00A90348) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914 (0x00A902D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915 (0x00A9034C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915 (0x00A902DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916 (0x00A90350) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916 (0x00A902E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917 (0x00A90354) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917 (0x00A902E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918 (0x00A90358) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918 (0x00A902E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919 (0x00A9035C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919 (0x00A902EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920 (0x00A90360) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920 (0x00A902F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921 (0x00A90364) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921 (0x00A902F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922 (0x00A90368) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922 (0x00A902F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923 (0x00A9036C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923 (0x00A902FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924 (0x00A90370) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924 (0x00A90300) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925 (0x00A90374) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925 (0x00A90304) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926 (0x00A90378) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926 (0x00A90308) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927 (0x00A9037C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927 (0x00A9030C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928 (0x00A90380) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928 (0x00A90310) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929 (0x00A90384) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929 (0x00A90314) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930 (0x00A90388) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930 (0x00A90318) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931 (0x00A9038C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931 (0x00A9031C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932 (0x00A90390) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932 (0x00A90320) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933 (0x00A90394) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933 (0x00A90324) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934 (0x00A90398) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934 (0x00A90328) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935 (0x00A9039C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935 (0x00A9032C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936 (0x00A903A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936 (0x00A90330) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937 (0x00A903A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937 (0x00A90334) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938 (0x00A903A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938 (0x00A90338) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939 (0x00A903AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939 (0x00A9033C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940 (0x00A903B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940 (0x00A90340) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941 (0x00A903B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941 (0x00A90344) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942 (0x00A903B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942 (0x00A90348) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943 (0x00A903BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943 (0x00A9034C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944 (0x00A903C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944 (0x00A90350) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945 (0x00A903C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945 (0x00A90354) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946 (0x00A903C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946 (0x00A90358) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947 (0x00A903CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947 (0x00A9035C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948 (0x00A903D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948 (0x00A90360) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949 (0x00A903D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949 (0x00A90364) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950 (0x00A903D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950 (0x00A90368) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951 (0x00A903DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951 (0x00A9036C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952 (0x00A903E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952 (0x00A90370) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953 (0x00A903E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953 (0x00A90374) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954 (0x00A903E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954 (0x00A90378) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955 (0x00A903EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955 (0x00A9037C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956 (0x00A903F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956 (0x00A90380) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957 (0x00A903F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957 (0x00A90384) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958 (0x00A903F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958 (0x00A90388) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959 (0x00A903FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959 (0x00A9038C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960 (0x00A90400) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960 (0x00A90390) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961 (0x00A90404) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961 (0x00A90394) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962 (0x00A90408) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962 (0x00A90398) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963 (0x00A9040C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963 (0x00A9039C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964 (0x00A90410) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964 (0x00A903A0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965 (0x00A90414) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965 (0x00A903A4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966 (0x00A90418) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966 (0x00A903A8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967 (0x00A9041C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967 (0x00A903AC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968 (0x00A90420) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968 (0x00A903B0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969 (0x00A90424) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969 (0x00A903B4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970 (0x00A90428) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970 (0x00A903B8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971 (0x00A9042C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971 (0x00A903BC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972 (0x00A90430) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972 (0x00A903C0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973 (0x00A90434) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973 (0x00A903C4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974 (0x00A90438) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974 (0x00A903C8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975 (0x00A9043C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975 (0x00A903CC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976 (0x00A90440) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976 (0x00A903D0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977 (0x00A90444) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977 (0x00A903D4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978 (0x00A90448) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978 (0x00A903D8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979 (0x00A9044C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979 (0x00A903DC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980 (0x00A90450) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980 (0x00A903E0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981 (0x00A90454) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981 (0x00A903E4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982 (0x00A90458) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982 (0x00A903E8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983 (0x00A9045C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983 (0x00A903EC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984 (0x00A90460) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984 (0x00A903F0) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985 (0x00A90464) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985 (0x00A903F4) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986 (0x00A90468) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986 (0x00A903F8) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987 (0x00A9046C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987 (0x00A903FC) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988 (0x00A90470) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988 (0x00A90400) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989 (0x00A90474) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989 (0x00A90404) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990 (0x00A90478) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990 (0x00A90408) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991 (0x00A9047C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991 (0x00A9040C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992 (0x00A90480) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992 (0x00A90410) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993 (0x00A90484) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993 (0x00A90414) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994 (0x00A90488) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994 (0x00A90418) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995 (0x00A9048C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995 (0x00A9041C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996 (0x00A90490) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996 (0x00A90420) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997 (0x00A90494) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997 (0x00A90424) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998 (0x00A90498) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998 (0x00A90428) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999 (0x00A9049C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999 (0x00A9042C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000 (0x00A904A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000 (0x00A90430) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001 (0x00A904A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001 (0x00A90434) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002 (0x00A904A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002 (0x00A90438) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003 (0x00A904AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003 (0x00A9043C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004 (0x00A904B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004 (0x00A90440) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005 (0x00A904B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005 (0x00A90444) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006 (0x00A904B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006 (0x00A90448) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007 (0x00A904BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007 (0x00A9044C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008 (0x00A904C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008 (0x00A90450) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009 (0x00A904C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009 (0x00A90454) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010 (0x00A904C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010 (0x00A90458) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011 (0x00A904CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011 (0x00A9045C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012 (0x00A904D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012 (0x00A90460) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013 (0x00A904D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013 (0x00A90464) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014 (0x00A904D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014 (0x00A90468) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015 (0x00A904DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015 (0x00A9046C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016 (0x00A904E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016 (0x00A90470) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017 (0x00A904E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017 (0x00A90474) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018 (0x00A904E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018 (0x00A90478) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019 (0x00A904EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019 (0x00A9047C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020 (0x00A904F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020 (0x00A90480) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021 (0x00A904F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021 (0x00A90484) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022 (0x00A904F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022 (0x00A90488) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022__DATA___S 0 -#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023 (0x00A904FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023 (0x00A9048C) #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023__DATA___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023__DATA___S 0 -#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE (0x00A90500) +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE (0x00A90490) #define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___POR 0x00000000 #define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE__VALUE___POR 0x0000 @@ -326491,7 +335177,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___M 0x0000FFFF #define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___S 0 -#define WMAC0_TXPCU_R0_PHY_ACK_STATUS (0x00A90504) +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS (0x00A90494) #define WMAC0_TXPCU_R0_PHY_ACK_STATUS___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PHY_ACK_STATUS___POR 0x00000000 #define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYRX_CBF_READ_ACK_RCVD___POR 0x0 @@ -326542,7 +335228,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_PHY_ACK_STATUS___M 0x00007FFF #define WMAC0_TXPCU_R0_PHY_ACK_STATUS___S 0 -#define WMAC0_TXPCU_R0_ABORT_REQ_ACK (0x00A90508) +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK (0x00A90498) #define WMAC0_TXPCU_R0_ABORT_REQ_ACK___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_ABORT_REQ_ACK___POR 0x00000030 #define WMAC0_TXPCU_R0_ABORT_REQ_ACK__DELAY___POR 0x0030 @@ -326551,7 +335237,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_ABORT_REQ_ACK___M 0x0000FFFF #define WMAC0_TXPCU_R0_ABORT_REQ_ACK___S 0 -#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE (0x00A9050C) +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE (0x00A9049C) #define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___POR 0x01000100 #define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_ON_ACK_DELAY___POR 0x0100 @@ -326563,7 +335249,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___S 0 -#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE (0x00A90510) +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE (0x00A904A0) #define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___POR 0x01000100 #define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_ON_ACK_DELAY___POR 0x0100 @@ -326575,7 +335261,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___S 0 -#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE (0x00A90514) +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE (0x00A904A4) #define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___POR 0x00000100 #define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE__PHY_NAP_ACK_DELAY___POR 0x0100 @@ -326584,7 +335270,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___M 0x0000FFFF #define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0 (0x00A90518) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0 (0x00A904A8) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0__VALUE___POR 0x00000000 @@ -326593,7 +335279,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1 (0x00A9051C) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1 (0x00A904AC) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1__VALUE___POR 0x00000000 @@ -326602,7 +335288,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2 (0x00A90520) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2 (0x00A904B0) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2__VALUE___POR 0x00000000 @@ -326611,7 +335297,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3 (0x00A90524) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3 (0x00A904B4) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3__VALUE___POR 0x00000000 @@ -326620,7 +335306,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4 (0x00A90528) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4 (0x00A904B8) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4__VALUE___POR 0x00000000 @@ -326629,7 +335315,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5 (0x00A9052C) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5 (0x00A904BC) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5__VALUE___POR 0x00000000 @@ -326638,7 +335324,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6 (0x00A90530) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6 (0x00A904C0) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6__VALUE___POR 0x00000000 @@ -326647,7 +335333,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7 (0x00A90534) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7 (0x00A904C4) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7__VALUE___POR 0x00000000 @@ -326656,7 +335342,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8 (0x00A90538) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8 (0x00A904C8) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8__VALUE___POR 0x00000000 @@ -326665,7 +335351,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9 (0x00A9053C) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9 (0x00A904CC) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9__VALUE___POR 0x00000000 @@ -326674,7 +335360,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10 (0x00A90540) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10 (0x00A904D0) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10__VALUE___POR 0x00000000 @@ -326683,7 +335369,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11 (0x00A90544) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11 (0x00A904D4) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11__VALUE___POR 0x00000000 @@ -326692,7 +335378,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12 (0x00A90548) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12 (0x00A904D8) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12__VALUE___POR 0x00000000 @@ -326701,7 +335387,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13 (0x00A9054C) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13 (0x00A904DC) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13__VALUE___POR 0x00000000 @@ -326710,7 +335396,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14 (0x00A90550) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14 (0x00A904E0) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14__VALUE___POR 0x00000000 @@ -326719,7 +335405,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___S 0 -#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15 (0x00A90554) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15 (0x00A904E4) #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___POR 0x00000000 #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15__VALUE___POR 0x00000000 @@ -326728,7 +335414,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___S 0 -#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK (0x00A90558) +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK (0x00A904E8) #define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___POR 0x00000000 #define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBAR___POR 0x0 @@ -326743,7 +335429,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___M 0x00000007 #define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___S 0 -#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP (0x00A9055C) +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP (0x00A904EC) #define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___POR 0x00000000 #define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP__VAL___POR 0x000000 @@ -326752,7 +335438,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___M 0x00FFFFFF #define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___S 0 -#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP (0x00A90560) +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP (0x00A904F0) #define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___POR 0x00000000 #define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__PSPOLL_SHIFT_BACK_ENA___POR 0x0 @@ -326764,7 +335450,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___M 0x0003FFFF #define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___S 0 -#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0 (0x00A90564) +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0 (0x00A904F4) #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___POR 0x00000000 #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0__VALUE___POR 0x00000000 @@ -326773,7 +335459,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___S 0 -#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32 (0x00A90568) +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32 (0x00A904F8) #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___POR 0x00000000 #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32__VALUE___POR 0x00000000 @@ -326782,7 +335468,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___S 0 -#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0 (0x00A9056C) +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0 (0x00A904FC) #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___POR 0x00000000 #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___POR 0x00000000 @@ -326791,7 +335477,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___S 0 -#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32 (0x00A90570) +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32 (0x00A90500) #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___POR 0x00000000 #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___POR 0x00000000 @@ -326800,7 +335486,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___S 0 -#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0 (0x00A90574) +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0 (0x00A90504) #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___POR 0x00000000 #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0__VALUE___POR 0x00000000 @@ -326809,7 +335495,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___S 0 -#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32 (0x00A90578) +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32 (0x00A90508) #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___POR 0x00000000 #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32__VALUE___POR 0x00000000 @@ -326818,7 +335504,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___S 0 -#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0 (0x00A9057C) +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0 (0x00A9050C) #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___POR 0x00000000 #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___POR 0x00000000 @@ -326827,7 +335513,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___S 0 -#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32 (0x00A90580) +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32 (0x00A90510) #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___POR 0x00000000 #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___POR 0x00000000 @@ -326836,7 +335522,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___S 0 -#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0 (0x00A90588) +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0 (0x00A90514) #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___POR 0x000000FF #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__NEXT_RX_DURATION___POR 0x0000 @@ -326848,7 +335534,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___S 0 -#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1 (0x00A9058C) +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1 (0x00A90518) #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___POR 0x000000FF #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__ENABLE_EARLY_TX_STATUS_TLV___POR 0x0 @@ -326860,7 +335546,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___M 0x0001FFFF #define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___S 0 -#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1 (0x00A90590) +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1 (0x00A9051C) #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___POR 0x00249249 #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH3_CS_MASK___POR 0x09 @@ -326878,7 +335564,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___M 0x00FFFFFF #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___S 0 -#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2 (0x00A90594) +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2 (0x00A90520) #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___POR 0x00249249 #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH7_CS_MASK___POR 0x09 @@ -326896,7 +335582,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___M 0x00FFFFFF #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___S 0 -#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3 (0x00A90598) +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3 (0x00A90524) #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___POR 0x01800000 #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__CHK_POINT___POR 0x3 @@ -326908,7 +335594,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___M 0x01FFFFFF #define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___S 0 -#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT (0x00A9059C) +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT (0x00A90528) #define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___POR 0x00003019 #define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__RX_FRAME_MU_CTS_TIMEOUT___POR 0x30 @@ -326920,7 +335606,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___M 0x0000FFFF #define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___S 0 -#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY (0x00A905A0) +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY (0x00A9052C) #define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___POR 0x15001E00 #define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_ACTION_FIELD___POR 0x15 @@ -326938,7 +335624,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n(n) (0x00A905A4+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n(n) (0x00A90530+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_nMAX 3 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_ELEM 4 @@ -326949,24 +335635,24 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0 (0x00A905A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0 (0x00A90530) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1 (0x00A905A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1 (0x00A90534) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2 (0x00A905AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2 (0x00A90538) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3 (0x00A905B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3 (0x00A9053C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n(n) (0x00A905B4+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n(n) (0x00A90540+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_nMAX 3 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_ELEM 4 @@ -326977,24 +335663,24 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0 (0x00A905B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0 (0x00A90540) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1 (0x00A905B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1 (0x00A90544) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2 (0x00A905BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2 (0x00A90548) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3 (0x00A905C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3 (0x00A9054C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n(n) (0x00A905C4+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n(n) (0x00A90550+0x4*(n)) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_nMIN 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_nMAX 13 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_ELEM 14 @@ -327005,64 +335691,64 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n__VALUE___S 0 #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0 (0x00A905C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0 (0x00A90550) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1 (0x00A905C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1 (0x00A90554) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2 (0x00A905CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2 (0x00A90558) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3 (0x00A905D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3 (0x00A9055C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4 (0x00A905D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4 (0x00A90560) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5 (0x00A905D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5 (0x00A90564) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6 (0x00A905DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6 (0x00A90568) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7 (0x00A905E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7 (0x00A9056C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8 (0x00A905E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8 (0x00A90570) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9 (0x00A905E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9 (0x00A90574) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10 (0x00A905EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10 (0x00A90578) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11 (0x00A905F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11 (0x00A9057C) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12 (0x00A905F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12 (0x00A90580) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12__VALUE___S 0 -#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13 (0x00A905F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13 (0x00A90584) #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13__VALUE___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13__VALUE___S 0 -#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL (0x00A905FC) +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL (0x00A90588) #define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___POR 0x00000000 #define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL__CTS_3DB_BOOST_ENABLE___POR 0x0 @@ -327071,7 +335757,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___M 0x00000001 #define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___S 0 -#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL (0x00A90600) +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL (0x00A9058C) #define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___POR 0x00000000 #define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL__CAPTURE_AT_START_TX___POR 0x0 @@ -327080,7 +335766,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___M 0x00000001 #define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___S 0 -#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL (0x00A90604) +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL (0x00A90590) #define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___POR 0x00000002 #define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UPH_RSV_BITS___POR 0x0 @@ -327092,7 +335778,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___M 0x0000007F #define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___S 0 -#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL (0x00A90608) +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL (0x00A90594) #define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___POR 0x00000003 #define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL__CBF_HT_CONTROL___POR 0x00000003 @@ -327101,7 +335787,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___M 0xFFFFFFFF #define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___S 0 -#define WMAC0_TXPCU_R0_SPR_FLOPS (0x00A906CC) +#define WMAC0_TXPCU_R0_SPR_FLOPS (0x00A90598) #define WMAC0_TXPCU_R0_SPR_FLOPS___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_SPR_FLOPS___POR 0x00000000 #define WMAC0_TXPCU_R0_SPR_FLOPS__SPR_FLOPS___POR 0x0000 @@ -327110,10 +335796,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_SPR_FLOPS___M 0x0000FFFF #define WMAC0_TXPCU_R0_SPR_FLOPS___S 0 -#define WMAC0_TXPCU_R0_FLUSH_HANDLER (0x00A906D0) +#define WMAC0_TXPCU_R0_FLUSH_HANDLER (0x00A9059C) #define WMAC0_TXPCU_R0_FLUSH_HANDLER___RWC QCSR_REG_RW -#define WMAC0_TXPCU_R0_FLUSH_HANDLER___POR 0x000001F0 -#define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_SELECTIVE_ABORT_ON_FLUSH___POR 0x1 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER___POR 0x000000F0 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_SELECTIVE_ABORT_ON_FLUSH___POR 0x0 #define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_ABORT_ON_FLUSH_CODE___POR 0xF #define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_COEX___POR 0x0 #define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_PDG___POR 0x0 @@ -327134,7 +335820,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_FLUSH_HANDLER___M 0x000001FF #define WMAC0_TXPCU_R0_FLUSH_HANDLER___S 0 -#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP (0x00A906D4) +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP (0x00A905A0) #define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___RWC QCSR_REG_RW #define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___POR 0x00FAC688 #define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_7___POR 0x7 @@ -327164,7 +335850,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___M 0x00FFFFFF #define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___S 0 -#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL (0x00A91584) +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL (0x00A91000) #define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___POR 0x00000000 #define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__COEX_TX_STATUS_TX_ENA___POR 0x0 @@ -327176,7 +335862,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___M 0x0001FFFF #define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___S 0 -#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT (0x00A9160C) +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT (0x00A91004) #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B2___POR 0x00 @@ -327191,7 +335877,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___M 0x00FFFFFF #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT (0x00A91610) +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT (0x00A91008) #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B1___POR 0x00 @@ -327203,7 +335889,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___M 0x0000FFFF #define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT (0x00A91614) +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT (0x00A9100C) #define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B1___POR 0x00 @@ -327215,7 +335901,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___M 0x0000FFFF #define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT (0x00A91618) +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT (0x00A91010) #define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT__VALUE___POR 0x00 @@ -327224,7 +335910,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_STATE (0x00A9161C) +#define WMAC0_TXPCU_R1_DEBUG_STATE (0x00A91014) #define WMAC0_TXPCU_R1_DEBUG_STATE___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_STATE___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_STATE__TX_DMA_STATE___POR 0x0 @@ -327254,7 +335940,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_STATE___M 0x3FFFFFFF #define WMAC0_TXPCU_R1_DEBUG_STATE___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0 (0x00A91620) +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0 (0x00A91018) #define WMAC0_TXPCU_R1_DEBUG_TX_FES_0___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TX_FES_0___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TX_FES_0__INFORMATION___POR 0x00000000 @@ -327263,7 +335949,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TX_FES_0___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_TX_FES_0___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1 (0x00A91624) +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1 (0x00A9101C) #define WMAC0_TXPCU_R1_DEBUG_TX_FES_1___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TX_FES_1___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TX_FES_1__INFORMATION___POR 0x00000000 @@ -327272,7 +335958,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TX_FES_1___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_TX_FES_1___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2 (0x00A91628) +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2 (0x00A91020) #define WMAC0_TXPCU_R1_DEBUG_TX_FES_2___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TX_FES_2___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TX_FES_2__INFORMATION___POR 0x00000000 @@ -327281,7 +335967,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TX_FES_2___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_TX_FES_2___S 0 -#define WMAC0_TXPCU_R1_TRACEBUS_CTRL (0x00A9162C) +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL (0x00A91024) #define WMAC0_TXPCU_R1_TRACEBUS_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_TRACEBUS_CTRL___POR 0x00000000 #define WMAC0_TXPCU_R1_TRACEBUS_CTRL__SELECT___POR 0x00000000 @@ -327290,7 +335976,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_TRACEBUS_CTRL___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_TRACEBUS_CTRL___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER (0x00A91630) +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER (0x00A91028) #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___POR 0x08000000 #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER__VALUE___POR 0x08000000 @@ -327299,7 +335985,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER (0x00A91634) +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER (0x00A9102C) #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER__VALUE___POR 0x00 @@ -327308,7 +335994,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___S 0 -#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT (0x00A91638) +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT (0x00A91030) #define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT__VALUE___POR 0x00 @@ -327317,7 +336003,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT (0x00A9163C) +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT (0x00A91034) #define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT__VALUE___POR 0x00 @@ -327326,7 +336012,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT (0x00A91640) +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT (0x00A91038) #define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT__VALUE___POR 0x00 @@ -327335,7 +336021,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT (0x00A91644) +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT (0x00A9103C) #define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT__VALUE___POR 0x00 @@ -327344,7 +336030,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT (0x00A91648) +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT (0x00A91040) #define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT__VALUE___POR 0x00 @@ -327353,7 +336039,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT (0x00A9164C) +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT (0x00A91044) #define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT__VALUE___POR 0x00 @@ -327362,7 +336048,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT (0x00A91650) +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT (0x00A91048) #define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT__VALUE___POR 0x00 @@ -327371,7 +336057,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT (0x00A91654) +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT (0x00A9104C) #define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT__VALUE___POR 0x00 @@ -327380,7 +336066,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT (0x00A91658) +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT (0x00A91050) #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT__VALUE___POR 0x00 @@ -327389,7 +336075,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT (0x00A9165C) +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT (0x00A91054) #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT__VALUE___POR 0x00 @@ -327398,7 +336084,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT (0x00A91660) +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT (0x00A91058) #define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT__VALUE___POR 0x00 @@ -327407,7 +336093,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___M 0x000000FF #define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___S 0 -#define WMAC0_TXPCU_R1_EVENTMASK_IX_0 (0x00A91664) +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0 (0x00A9105C) #define WMAC0_TXPCU_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_EVENTMASK_IX_0___POR 0xFFFFFFFF #define WMAC0_TXPCU_R1_EVENTMASK_IX_0__VALUE___POR 0xFFFFFFFF @@ -327416,7 +336102,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_EVENTMASK_IX_0___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_EVENTMASK_IX_0___S 0 -#define WMAC0_TXPCU_R1_EVENTMASK_IX_1 (0x00A91668) +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1 (0x00A91060) #define WMAC0_TXPCU_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_EVENTMASK_IX_1___POR 0xFFFFFFFF #define WMAC0_TXPCU_R1_EVENTMASK_IX_1__VALUE___POR 0xFFFFFFFF @@ -327425,7 +336111,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_EVENTMASK_IX_1___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_EVENTMASK_IX_1___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV (0x00A9166C) +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV (0x00A91064) #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__SENT_COUNT___POR 0x0000 @@ -327437,7 +336123,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0 (0x00A91670) +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0 (0x00A91068) #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_OFF_CNT___POR 0x00 @@ -327455,7 +336141,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1 (0x00A91674) +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1 (0x00A9106C) #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_SYNTH_OFF_ACK_CNT___POR 0x00 @@ -327473,7 +336159,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___S 0 -#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2 (0x00A91678) +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2 (0x00A91070) #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_ACK_CNT___POR 0x00 @@ -327491,7 +336177,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0 (0x00A9167C) +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0 (0x00A91074) #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_REQ_CNT___POR 0x00 @@ -327509,7 +336195,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1 (0x00A91680) +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1 (0x00A91078) #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_ON_CNT___POR 0x00 @@ -327527,7 +336213,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___S 0 -#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR (0x00A91684) +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR (0x00A9107C) #define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR__VALUE___POR 0x0000 @@ -327536,7 +336222,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___M 0x0000FFFF #define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___S 0 -#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS (0x00A91688) +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS (0x00A91080) #define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__PHY_RDY_VIOLATED___POR 0x0 @@ -327569,7 +336255,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___M 0x000001FF #define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE (0x00A9168C) +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE (0x00A91084) #define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE__MODULE_ID___POR 0x00 @@ -327578,7 +336264,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___M 0x0000003F #define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___S 0 -#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT (0x00A91690) +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT (0x00A91088) #define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_WITHIN_MPDU_CNT___POR 0x0000 @@ -327590,7 +336276,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT (0x00A91694) +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT (0x00A9108C) #define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT__MPDU_TX_CNT___POR 0x00000000 @@ -327599,7 +336285,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT (0x00A91698) +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT (0x00A91090) #define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT__AMPDU_TX_CNT___POR 0x00000000 @@ -327608,7 +336294,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT (0x00A9169C) +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT (0x00A91094) #define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT__CORRUPT_DMA_DATA_CNT___POR 0x00000000 @@ -327617,7 +336303,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL (0x00A916A0) +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL (0x00A91098) #define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MISC_GROUP___POR 0x0 @@ -327713,7 +336399,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___M 0x3FFFFFFF #define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___S 0 -#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS (0x00A916A4) +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS (0x00A9109C) #define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___POR 0x007C0000 #define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___POR 0x1F @@ -327776,7 +336462,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___M 0x007FFFFF #define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK (0x00A916A8) +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK (0x00A910A0) #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__GLOBAL_UNDERRUN_FLAG_MASK___POR 0x0 @@ -327827,7 +336513,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___M 0x00007FFF #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___S 0 -#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS (0x00A916AC) +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS (0x00A910A4) #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___POR 0x0000001F #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__ERR_OR_INT_DATA___POR 0x000000 @@ -327842,7 +336528,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL (0x00A916B0) +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL (0x00A910A8) #define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___POR 0x00100040 #define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_SECOND_USER_SELECT___POR 0x01 @@ -327866,7 +336552,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___M 0x03FFFFFF #define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___S 0 -#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS (0x00A916B4) +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS (0x00A910AC) #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_REQ_GT_DATA_RESP___POR 0x00 @@ -327881,7 +336567,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS (0x00A916B8) +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS (0x00A910B0) #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__DATA_RESP_GT_RCVD_REQ___POR 0x00 @@ -327896,7 +336582,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS (0x00A916BC) +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS (0x00A910B4) #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___POR 0x00200000 #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_REQ_GT_DATA_RESP___POR 0x00 @@ -327911,7 +336597,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS (0x00A916C0) +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS (0x00A910B8) #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___POR 0x00200000 #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__DATA_RESP_GT_RCVD_REQ___POR 0x00 @@ -327926,7 +336612,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS (0x00A916C4) +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS (0x00A910BC) #define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__USER_ID___POR 0x00 @@ -327938,7 +336624,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___M 0x1FFFFFFF #define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS (0x00A916C8) +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS (0x00A910C0) #define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___POR 0x00800000 #define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__USER_ID___POR 0x01 @@ -327950,7 +336636,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___M 0x1FFFFFFF #define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___S 0 -#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0 (0x00A916D8) +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0 (0x00A910C4) #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0__VALUE___POR 0x00000000 @@ -327959,7 +336645,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___S 0 -#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1 (0x00A916DC) +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1 (0x00A910C8) #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1__VALUE___POR 0x00000000 @@ -327968,7 +336654,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___S 0 -#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL (0x00A916E0) +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL (0x00A910CC) #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___RWC QCSR_REG_RW #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PRESET_BITMAP___POR 0x0000000 @@ -327983,7 +336669,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___M 0xFFFFFFFF #define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___S 0 -#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER (0x00A916E4) +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER (0x00A910D0) #define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___RWC QCSR_REG_RO #define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___POR 0x00000000 #define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_PKT_END_RCVD___POR 0x0 @@ -333762,7 +342448,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL (0x00A95118) #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___RWC QCSR_REG_RW -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___POR 0x0003E068 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___POR 0x0003E090 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__LIMIT___POR 0xF #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_MSDU_DROP_CHECK___POR 0x1 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_DECRYPT_ERR_CHECK___POR 0x0 @@ -333770,11 +342456,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_QOS_CHECK___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TA_CHECK___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TID_CHECK___POR 0x0 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___POR 0x0 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___POR 0x1 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___POR 0x1 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___POR 0x0 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_L4_CHECKSUM_FIX___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__SUBTRACT_IPV4_FIXED_HDR_LEN___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__SUBTRACT_IPV6_FIXED_HDR_LEN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__TCP_UDP_HDR_LEN_FIX_DISABLE___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__IPSEC_SKIP_SEARCH___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ENABLE___POR 0x0 @@ -333794,14 +342480,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TID_CHECK___S 8 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___M 0x00000080 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___S 7 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___M 0x00000040 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___S 6 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___M 0x00000020 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___S 5 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___M 0x00000010 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___S 4 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___M 0x00000008 -#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___S 3 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_L4_CHECKSUM_FIX___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_L4_CHECKSUM_FIX___S 6 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__SUBTRACT_IPV4_FIXED_HDR_LEN___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__SUBTRACT_IPV4_FIXED_HDR_LEN___S 5 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__SUBTRACT_IPV6_FIXED_HDR_LEN___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__SUBTRACT_IPV6_FIXED_HDR_LEN___S 4 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__TCP_UDP_HDR_LEN_FIX_DISABLE___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__TCP_UDP_HDR_LEN_FIX_DISABLE___S 3 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___M 0x00000004 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___S 2 #define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__IPSEC_SKIP_SEARCH___M 0x00000002 @@ -333838,6 +342524,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___POR 0x00000 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_HW_UPDATE___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__ASE___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_READ___POR 0x0 @@ -333853,8 +342540,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___S 31 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 -#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___M 0x3FFFF800 -#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___S 11 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___M 0x3FFFF000 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___S 12 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_HW_UPDATE___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_HW_UPDATE___S 11 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___M 0x00000400 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___S 10 #define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__ASE___M 0x00000200 @@ -333883,10 +342572,13 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG (0x00A95128) #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___RWC QCSR_REG_RW #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___POR 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__PER_PEER_HASH_BASED_ROUTING_EN___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___POR 0x0C #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__OVERRIDE_MSDU_END_FIELDS___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_2_OR_4___POR 0x0 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__PER_PEER_HASH_BASED_ROUTING_EN___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__PER_PEER_HASH_BASED_ROUTING_EN___S 9 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___M 0x000001F0 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___S 4 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__OVERRIDE_MSDU_END_FIELDS___M 0x00000004 @@ -333895,12 +342587,14 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_2_OR_4___S 1 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___M 0x00000001 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___S 0 -#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___M 0x000001F7 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___M 0x000003F7 #define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___S 0 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG (0x00A9512C) #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___RWC QCSR_REG_RW -#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___POR 0x00000606 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___POR 0x00000E06 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__RAW_MODE_FIRST_SECTION_READ_SIZE_OPT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FWD_RX_PRE_PPDU_START_EN___POR 0x1 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___POR 0x1 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__ENABLE_USEC_TIMEOUT___POR 0x1 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FLUSH_ON_WDOG___POR 0x0 @@ -333912,6 +342606,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX2_ENABLE___POR 0x1 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX1_ENABLE___POR 0x1 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__RAW_MODE_FIRST_SECTION_READ_SIZE_OPT___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__RAW_MODE_FIRST_SECTION_READ_SIZE_OPT___S 12 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FWD_RX_PRE_PPDU_START_EN___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FWD_RX_PRE_PPDU_START_EN___S 11 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___M 0x00000400 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___S 10 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__ENABLE_USEC_TIMEOUT___M 0x00000200 @@ -333934,7 +342632,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX1_ENABLE___S 1 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___M 0x00000001 #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___S 0 -#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___M 0x000007FF +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___M 0x00001FFF #define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___S 0 #define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0 (0x00A95130) @@ -338892,7 +347590,16 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_CRYPTO_R0_USER_SWITCH_CNT___M 0x0000FFFF #define WMAC0_CRYPTO_R0_USER_SWITCH_CNT___S 0 -#define WMAC0_CRYPTO_R0_ARBITER_CTRL (0x00AA7080) +#define WMAC0_CRYPTO_R0_TX_RX_OVERLAP_FIX (0x00AA7080) +#define WMAC0_CRYPTO_R0_TX_RX_OVERLAP_FIX___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_TX_RX_OVERLAP_FIX___POR 0x0000000A +#define WMAC0_CRYPTO_R0_TX_RX_OVERLAP_FIX__RX_PACKET_INCR_MARGIN___POR 0x0A +#define WMAC0_CRYPTO_R0_TX_RX_OVERLAP_FIX__RX_PACKET_INCR_MARGIN___M 0x0000003F +#define WMAC0_CRYPTO_R0_TX_RX_OVERLAP_FIX__RX_PACKET_INCR_MARGIN___S 0 +#define WMAC0_CRYPTO_R0_TX_RX_OVERLAP_FIX___M 0x0000003F +#define WMAC0_CRYPTO_R0_TX_RX_OVERLAP_FIX___S 0 + +#define WMAC0_CRYPTO_R0_ARBITER_CTRL (0x00AA7084) #define WMAC0_CRYPTO_R0_ARBITER_CTRL___RWC QCSR_REG_RW #define WMAC0_CRYPTO_R0_ARBITER_CTRL___POR 0x00010000 #define WMAC0_CRYPTO_R0_ARBITER_CTRL__ARBITER_ENABLE___POR 0x1 @@ -338907,7 +347614,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_CRYPTO_R0_ARBITER_CTRL___M 0x0001FFFF #define WMAC0_CRYPTO_R0_ARBITER_CTRL___S 0 -#define WMAC0_CRYPTO_R0_SPARE_CTRL (0x00AA7084) +#define WMAC0_CRYPTO_R0_SPARE_CTRL (0x00AA7088) #define WMAC0_CRYPTO_R0_SPARE_CTRL___RWC QCSR_REG_RW #define WMAC0_CRYPTO_R0_SPARE_CTRL___POR 0x0000FF01 #define WMAC0_CRYPTO_R0_SPARE_CTRL__SPARE_BITS___POR 0x7F80 @@ -338919,7 +347626,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_CRYPTO_R0_SPARE_CTRL___M 0x0000FFFF #define WMAC0_CRYPTO_R0_SPARE_CTRL___S 0 -#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL (0x00AA7088) +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL (0x00AA708C) #define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___RWC QCSR_REG_RW #define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___POR 0x00000007 #define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__SPARE_BITS___POR 0x0000 @@ -340524,12 +349231,18 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL (0x00AAA174) #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___POR 0x0877500F +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_CURR_OBSSNAV_CHK_ALL_UPDATES___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_CURR_INBSSNAV_CHK_ALL_UPDATES___POR 0x0 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___POR 0x0 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__FES_FAIL_AUTO_FLUSH_LATE_MPDU_INFO___POR 0x1 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_11B_TO_LIMIT___POR 0x0EE #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__ENABLE_CCA_SENSING_IN_PIFS_BURST___POR 0x1 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_NAV_BASED_ON_RTS_VALID___POR 0x1 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___POR 0x00F +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_CURR_OBSSNAV_CHK_ALL_UPDATES___M 0x80000000 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_CURR_OBSSNAV_CHK_ALL_UPDATES___S 31 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_CURR_INBSSNAV_CHK_ALL_UPDATES___M 0x40000000 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_CURR_INBSSNAV_CHK_ALL_UPDATES___S 30 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___M 0x30000000 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___S 28 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__FES_FAIL_AUTO_FLUSH_LATE_MPDU_INFO___M 0x08000000 @@ -340542,7 +349255,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_NAV_BASED_ON_RTS_VALID___S 12 #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___M 0x00000FFF #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___S 0 -#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___M 0x3FFFDFFF +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___M 0xFFFFDFFF #define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___S 0 #define WMAC0_HWSCH_R0_PREBKOFF_LIMITS (0x00AAA178) @@ -341453,11 +350166,11 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_TESTBUS_CTRL___POR 0x00000000 #define WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___POR 0x00 #define WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___POR 0x0 -#define WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___M 0x000003F0 -#define WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___S 4 +#define WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___M 0x000007E0 +#define WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___S 5 #define WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___M 0x0000000F #define WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___S 0 -#define WMAC0_HWSCH_R0_TESTBUS_CTRL___M 0x000003FF +#define WMAC0_HWSCH_R0_TESTBUS_CTRL___M 0x000007EF #define WMAC0_HWSCH_R0_TESTBUS_CTRL___S 0 #define WMAC0_HWSCH_R0_TESTBUS_n(n) (0x00AAA2E4+0x4*(n)) @@ -351198,8 +359911,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n(n) (0x00AAC5E0+0x4*(n)) #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_nMIN 0 -#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_nMAX 9 -#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_ELEM 10 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_nMAX 10 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_ELEM 11 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___POR 0x00000000 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n__CNT_VALUE___POR 0x00000000 @@ -351247,8 +359960,12 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_9___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_9__CNT_VALUE___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_9__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_10 (0x00AAC608) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_10__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_10__CNT_VALUE___S 0 -#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK (0x00AAC608) +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK (0x00AAC60C) #define WMAC0_HWSCH_R0_TQM_FLUSH_ACK___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_TQM_FLUSH_ACK___POR 0x00000000 #define WMAC0_HWSCH_R0_TQM_FLUSH_ACK__VALUE___POR 0x0 @@ -351257,7 +359974,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_TQM_FLUSH_ACK___M 0x00000001 #define WMAC0_HWSCH_R0_TQM_FLUSH_ACK___S 0 -#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR (0x00AAC60C) +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR (0x00AAC610) #define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___POR 0x00000000 #define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR__VALUE___POR 0x00000000 @@ -351266,7 +359983,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___S 0 -#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB (0x00AAC610) +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB (0x00AAC614) #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___POR 0x00000000 #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB__VALUE___POR 0x00 @@ -351275,7 +359992,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___M 0x000000FF #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___S 0 -#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB (0x00AAC614) +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB (0x00AAC618) #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___POR 0x00000000 #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB__VALUE___POR 0x00000000 @@ -351284,7 +360001,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___S 0 -#define WMAC0_HWSCH_R0_SFM_BLK_CTRL (0x00AAC618) +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL (0x00AAC61C) #define WMAC0_HWSCH_R0_SFM_BLK_CTRL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SFM_BLK_CTRL___POR 0x00040020 #define WMAC0_HWSCH_R0_SFM_BLK_CTRL__FES_STAT_PACKING_EN___POR 0x0 @@ -351302,7 +360019,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SFM_BLK_CTRL___M 0x01FF01FF #define WMAC0_HWSCH_R0_SFM_BLK_CTRL___S 0 -#define WMAC0_HWSCH_R0_INBSS_NAV_CNT (0x00AAC61C) +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT (0x00AAC620) #define WMAC0_HWSCH_R0_INBSS_NAV_CNT___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_INBSS_NAV_CNT___POR 0x00000000 #define WMAC0_HWSCH_R0_INBSS_NAV_CNT__INBSS_NAV_CNT___POR 0x00000000 @@ -351311,7 +360028,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_INBSS_NAV_CNT___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_INBSS_NAV_CNT___S 0 -#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT (0x00AAC620) +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT (0x00AAC624) #define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___POR 0x00000000 #define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT__SW_MTU_SHADOW_INBSS_NAV_CNT___POR 0x00000000 @@ -351320,7 +360037,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___S 0 -#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL (0x00AAC624) +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL (0x00AAC628) #define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___POR 0x0077000F #define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_11B_TO_LIMIT___POR 0x0EE @@ -351335,7 +360052,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___M 0x07FF9FFF #define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___S 0 -#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n(n) (0x00AAC628+0x4*(n)) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n(n) (0x00AAC62C+0x4*(n)) #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_nMIN 0 #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_nMAX 4 #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_ELEM 5 @@ -351346,28 +360063,28 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n__VALUE___S 0 #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___S 0 -#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0 (0x00AAC628) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0 (0x00AAC62C) #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0___RWC QCSR_REG_RO #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0__VALUE___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0__VALUE___S 0 -#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1 (0x00AAC62C) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1 (0x00AAC630) #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1___RWC QCSR_REG_RO #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1__VALUE___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1__VALUE___S 0 -#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2 (0x00AAC630) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2 (0x00AAC634) #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2___RWC QCSR_REG_RO #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2__VALUE___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2__VALUE___S 0 -#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3 (0x00AAC634) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3 (0x00AAC638) #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3___RWC QCSR_REG_RO #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3__VALUE___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3__VALUE___S 0 -#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4 (0x00AAC638) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4 (0x00AAC63C) #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4___RWC QCSR_REG_RO #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4__VALUE___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4__VALUE___S 0 -#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU (0x00AAC63C) +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU (0x00AAC640) #define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___POR 0x0000000C #define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__LOCK_CACHE_SIZE___POR 0x06 @@ -351379,7 +360096,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___M 0x0000003F #define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___S 0 -#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR (0x00AAC640) +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR (0x00AAC644) #define WMAC0_HWSCH_R0_DEBUG_SFM_CLR___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_DEBUG_SFM_CLR___POR 0x00000000 #define WMAC0_HWSCH_R0_DEBUG_SFM_CLR__VALUE___POR 0x000000 @@ -351388,9 +360105,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_DEBUG_SFM_CLR___M 0x00FFFFFF #define WMAC0_HWSCH_R0_DEBUG_SFM_CLR___S 0 -#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL (0x00AAC644) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL (0x00AAC648) #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___POR 0x00000000 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__NAV_COUNT_CONDITION___POR 0x0 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___POR 0x0 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__LP_SR_SIGNAL_SEL___POR 0x0 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__IGNORE_NAV_CNT_IN_MED_RX_IDLE___POR 0x0 @@ -351398,6 +360116,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__RX_CLEAR_COUNT_CONDITION___POR 0x0 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__FREEZE_CNT___POR 0x0 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___POR 0x0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__NAV_COUNT_CONDITION___M 0x00000600 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__NAV_COUNT_CONDITION___S 9 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___M 0x00000100 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___S 8 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__LP_SR_SIGNAL_SEL___M 0x000000C0 @@ -351412,10 +360132,10 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__FREEZE_CNT___S 1 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___M 0x00000001 #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___S 0 -#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___M 0x000001FF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___M 0x000007FF #define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___S 0 -#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL (0x00AAC648) +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL (0x00AAC64C) #define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___POR 0x00000000 #define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL__RING_SELECT___POR 0x00000 @@ -351424,7 +360144,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___M 0x0003FFFF #define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___S 0 -#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR (0x00AAC64C) +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR (0x00AAC650) #define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___POR 0x00000000 #define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR__VALUE___POR 0x0000 @@ -351433,7 +360153,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___M 0x0000FFFF #define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___S 0 -#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE (0x00AAC650) +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE (0x00AAC654) #define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___POR 0x00000004 #define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE__VALUE___POR 0x04 @@ -351442,7 +360162,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___M 0x0000001F #define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___S 0 -#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET (0x00AAC654) +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET (0x00AAC658) #define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___POR 0x00000000 #define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET__VALUE___POR 0x0000 @@ -351451,19 +360171,22 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___M 0x00003FFF #define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___S 0 -#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE (0x00AAC658) +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE (0x00AAC65C) #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___POR 0x027FFFFB #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___POR 0x0 +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__NAV_INFO_IN_SCH_STAT_EN___POR 0x0 #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___POR 0x027FFFFB #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___M 0x80000000 #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___S 31 -#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___M 0x7FFFFFFF +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__NAV_INFO_IN_SCH_STAT_EN___M 0x40000000 +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__NAV_INFO_IN_SCH_STAT_EN___S 30 +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___M 0x3FFFFFFF #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___S 0 #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___S 0 -#define WMAC0_HWSCH_R0_SPR_REG (0x00AAC65C) +#define WMAC0_HWSCH_R0_SPR_REG (0x00AAC660) #define WMAC0_HWSCH_R0_SPR_REG___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SPR_REG___POR 0x00000009 #define WMAC0_HWSCH_R0_SPR_REG__SPR_VAL___POR 0x00000009 @@ -351472,7 +360195,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SPR_REG___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_SPR_REG___S 0 -#define WMAC0_HWSCH_R0_SPR_EXT_REG (0x00AAC660) +#define WMAC0_HWSCH_R0_SPR_EXT_REG (0x00AAC664) #define WMAC0_HWSCH_R0_SPR_EXT_REG___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SPR_EXT_REG___POR 0xFFFF0000 #define WMAC0_HWSCH_R0_SPR_EXT_REG__SPR_EXT_VAL___POR 0xFFFF0000 @@ -351481,7 +360204,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SPR_EXT_REG___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_SPR_EXT_REG___S 0 -#define WMAC0_HWSCH_R0_SPR2_REG (0x00AAC664) +#define WMAC0_HWSCH_R0_SPR2_REG (0x00AAC668) #define WMAC0_HWSCH_R0_SPR2_REG___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SPR2_REG___POR 0x00000000 #define WMAC0_HWSCH_R0_SPR2_REG__SPR_VAL___POR 0x00000000 @@ -351490,7 +360213,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SPR2_REG___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_SPR2_REG___S 0 -#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL (0x00AAC668) +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL (0x00AAC66C) #define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___POR 0x00000000 #define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL__ENABLE___POR 0x00000 @@ -351499,7 +360222,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___M 0x0003FFFF #define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___S 0 -#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF (0x00AAC66C) +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF (0x00AAC670) #define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___POR 0x00000000 #define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF__ENABLE___POR 0x00000 @@ -351508,7 +360231,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___M 0x0003FFFF #define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___S 0 -#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0 (0x00AAC670) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0 (0x00AAC674) #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___POR 0x00000000 #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING3___POR 0x00 @@ -351526,7 +360249,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___S 0 -#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1 (0x00AAC674) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1 (0x00AAC678) #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___POR 0x00000000 #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING7___POR 0x00 @@ -351544,7 +360267,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___S 0 -#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2 (0x00AAC678) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2 (0x00AAC67C) #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___POR 0x00000000 #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING11___POR 0x00 @@ -351562,7 +360285,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___S 0 -#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3 (0x00AAC67C) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3 (0x00AAC680) #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___POR 0x00000000 #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING15___POR 0x00 @@ -351580,7 +360303,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___S 0 -#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4 (0x00AAC680) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4 (0x00AAC684) #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___POR 0x00000000 #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING17___POR 0x00 @@ -351592,7 +360315,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___M 0x0000FFFF #define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___S 0 -#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0 (0x00AAC684) +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0 (0x00AAC688) #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___POR 0x00000400 #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0__SW_MTU_COEX_BKOFF_BLOCK_TIMEOUT___POR 0x0400 @@ -351601,7 +360324,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___M 0x0000FFFF #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___S 0 -#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1 (0x00AAC688) +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1 (0x00AAC68C) #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___POR 0x00000000 #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1__SW_MTU_COEX_BKOFF_BLOCK_ENABLE___POR 0x00000 @@ -351610,7 +360333,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___M 0x0003FFFF #define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___S 0 -#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL (0x00AAC68C) +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL (0x00AAC690) #define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___POR 0x00000000 #define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_CARRIER_SENSE_FOR_ALL_TRIGGERS___POR 0x0 @@ -351631,7 +360354,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___M 0x000FFFFF #define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___S 0 -#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL (0x00AAC690) +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL (0x00AAC694) #define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___POR 0x00000000 #define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR17_RBO_LKAHD_EN___POR 0x0 @@ -351691,7 +360414,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___M 0x0003FFFF #define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___S 0 -#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2 (0x00AAC694) +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2 (0x00AAC698) #define WMAC0_HWSCH_R0_CW_ACTION_CTRL2___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_CW_ACTION_CTRL2___POR 0x00000000 #define WMAC0_HWSCH_R0_CW_ACTION_CTRL2__CW_ACTION_CTRL2___POR 0x00000000 @@ -351700,7 +360423,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_CW_ACTION_CTRL2___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_CW_ACTION_CTRL2___S 0 -#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0 (0x00AAC698) +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0 (0x00AAC69C) #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___POR 0x00000000 #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL15___POR 0x0 @@ -351754,7 +360477,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___S 0 -#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1 (0x00AAC69C) +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1 (0x00AAC6A0) #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___POR 0x00000000 #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL26___POR 0x0 @@ -351793,7 +360516,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___M 0x003FFFFF #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___S 0 -#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2 (0x00AAC6A0) +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2 (0x00AAC6A4) #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___POR 0xFFFFFF03 #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM2___POR 0xFF @@ -351811,7 +360534,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___S 0 -#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3 (0x00AAC6A4) +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3 (0x00AAC6A8) #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___POR 0x00000005 #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__INCORRECT_FLREQ_FIX_ENABLE___POR 0x1 @@ -351826,7 +360549,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___M 0x00000007 #define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___S 0 -#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES (0x00AAC6A8) +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES (0x00AAC6AC) #define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___POR 0x00000010 #define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_SECURITY___POR 0x0 @@ -351850,7 +360573,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___M 0x0000003F #define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___S 0 -#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT (0x00AAC6AC) +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT (0x00AAC6B0) #define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___POR 0x000112C0 #define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_EN___POR 0x0 @@ -351865,7 +360588,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___M 0x01FFFFFF #define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___S 0 -#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0 (0x00AAC6B0) +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0 (0x00AAC6B4) #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___POR 0x00000000 #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0__LUT_VALUE___POR 0x00000000 @@ -351874,7 +360597,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___S 0 -#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1 (0x00AAC6B4) +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1 (0x00AAC6B8) #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___POR 0x00000000 #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1__LUT_VALUE___POR 0x0000 @@ -351883,7 +360606,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___M 0x0000FFFF #define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___S 0 -#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER (0x00AAC6B8) +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER (0x00AAC6BC) #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___POR 0xF0008888 #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888 @@ -351892,7 +360615,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___S 0 -#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER (0x00AAC6BC) +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER (0x00AAC6C0) #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___POR 0xF0000000 #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000 @@ -351901,7 +360624,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___S 0 -#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER (0x00AAC6C0) +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER (0x00AAC6C4) #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___POR 0xF0008888 #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888 @@ -351910,7 +360633,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___S 0 -#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER (0x00AAC6C4) +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER (0x00AAC6C8) #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___POR 0xF0000000 #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000 @@ -351919,7 +360642,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___S 0 -#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER (0x00AAC6C8) +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER (0x00AAC6CC) #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___POR 0xF0008888 #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888 @@ -351928,7 +360651,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___S 0 -#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER (0x00AAC6CC) +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER (0x00AAC6D0) #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___POR 0xF0000000 #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000 @@ -351937,7 +360660,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___S 0 -#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0 (0x00AAC6D0) +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0 (0x00AAC6D4) #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___POR 0x00000000 #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0__ASSERT_HP_SYNTH_WHEN_CMD_PENDING___POR 0x00000 @@ -351946,7 +360669,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___M 0x0003FFFF #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___S 0 -#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1 (0x00AAC6D4) +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1 (0x00AAC6D8) #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___POR 0x00000000 #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1__ASSERT_HP_SYNTH_JUST_BEFORE_TX___POR 0x00000 @@ -351955,7 +360678,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___M 0x0003FFFF #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___S 0 -#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2 (0x00AAC6D8) +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2 (0x00AAC6DC) #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___POR 0x40020020 #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_FES_END_CHK_FOR_CLR___POR 0x1 @@ -351985,7 +360708,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___M 0x7FFFFFFF #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___S 0 -#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3 (0x00AAC6DC) +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3 (0x00AAC6E0) #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___POR 0x00000009 #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3__HP_VIRCCA_PREEMPT_LIMIT___POR 0x09 @@ -351994,7 +360717,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___M 0x0000003F #define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___S 0 -#define WMAC0_HWSCH_R0_SW_MSG_CTRL (0x00AAC6E0) +#define WMAC0_HWSCH_R0_SW_MSG_CTRL (0x00AAC6E4) #define WMAC0_HWSCH_R0_SW_MSG_CTRL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SW_MSG_CTRL___POR 0x00000000 #define WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG_STATUS___POR 0x0 @@ -352006,7 +360729,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SW_MSG_CTRL___M 0x80000001 #define WMAC0_HWSCH_R0_SW_MSG_CTRL___S 0 -#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0 (0x00AAC6E4) +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0 (0x00AAC6E8) #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___POR 0x00000000 #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0__DATA___POR 0x00000000 @@ -352015,7 +360738,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___S 0 -#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1 (0x00AAC6E8) +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1 (0x00AAC6EC) #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___POR 0x00000000 #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1__DATA___POR 0x00000000 @@ -352024,7 +360747,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___S 0 -#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG (0x00AAC6EC) +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG (0x00AAC6F0) #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___POR 0x00000010 #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__MAX_PENDING_AXI_WRITE_LIMIT___POR 0x08 @@ -352036,7 +360759,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___M 0x0000003F #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___S 0 -#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS (0x00AAC6F0) +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS (0x00AAC6F4) #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___POR 0x00000000 #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__ERROR_COUNT___POR 0x00 @@ -352051,7 +360774,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___M 0x00FFFFFF #define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___S 0 -#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG (0x00AAC6F4) +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG (0x00AAC6F8) #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___POR 0x00000000 #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG__SRNG2SRNG_BUFFER_ENABLE___POR 0x0 @@ -352060,7 +360783,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___M 0x00000001 #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___S 0 -#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS (0x00AAC6F8) +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS (0x00AAC6FC) #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___POR 0x00000000 #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__ERROR_COUNT___POR 0x00 @@ -352075,7 +360798,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___M 0x00FFFFFF #define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___S 0 -#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS (0x00AAC6FC) +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS (0x00AAC700) #define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___POR 0x00000000 #define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_HARD___POR 0x0 @@ -352111,7 +360834,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___M 0x01FFFFFF #define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___S 0 -#define WMAC0_HWSCH_R0_FILTER_LUT_DATA (0x00AAC700) +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA (0x00AAC704) #define WMAC0_HWSCH_R0_FILTER_LUT_DATA___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FILTER_LUT_DATA___POR 0x00000000 #define WMAC0_HWSCH_R0_FILTER_LUT_DATA__HARD_FILTER_VALUE___POR 0x0 @@ -352129,7 +360852,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FILTER_LUT_DATA___M 0x0007FFFF #define WMAC0_HWSCH_R0_FILTER_LUT_DATA___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n(n) (0x00AAC704+0x4*(n)) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n(n) (0x00AAC708+0x4*(n)) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_nMIN 0 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_nMAX 17 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_ELEM 18 @@ -352143,116 +360866,116 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__VALID___S 0 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___M 0x0000001F #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0 (0x00AAC704) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0 (0x00AAC708) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1 (0x00AAC708) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1 (0x00AAC70C) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2 (0x00AAC70C) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2 (0x00AAC710) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3 (0x00AAC710) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3 (0x00AAC714) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4 (0x00AAC714) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4 (0x00AAC718) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5 (0x00AAC718) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5 (0x00AAC71C) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6 (0x00AAC71C) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6 (0x00AAC720) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7 (0x00AAC720) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7 (0x00AAC724) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8 (0x00AAC724) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8 (0x00AAC728) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9 (0x00AAC728) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9 (0x00AAC72C) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10 (0x00AAC72C) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10 (0x00AAC730) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11 (0x00AAC730) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11 (0x00AAC734) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12 (0x00AAC734) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12 (0x00AAC738) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13 (0x00AAC738) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13 (0x00AAC73C) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14 (0x00AAC73C) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14 (0x00AAC740) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15 (0x00AAC740) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15 (0x00AAC744) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16 (0x00AAC744) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16 (0x00AAC748) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__VALID___S 0 -#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17 (0x00AAC748) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17 (0x00AAC74C) #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__PREFERRED_AC_EXCLUSION_BITMAP___S 1 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__VALID___M 0x00000001 #define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__VALID___S 0 -#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG (0x00AAC74C) +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG (0x00AAC750) #define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___POR 0x00000010 #define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ECC_CHECK___POR 0x1 @@ -352273,7 +360996,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___M 0x0000001F #define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___S 0 -#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL (0x00AAC750) +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL (0x00AAC754) #define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___POR 0x0083C600 #define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_SRP_INFO_EN___POR 0x0 @@ -352330,7 +361053,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___S 0 -#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE (0x00AAC754) +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE (0x00AAC758) #define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___POR 0x00000000 #define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE__SRP_RESTORE_BACKOFF_EN___POR 0x00000 @@ -352339,7 +361062,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___M 0x0003FFFF #define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___S 0 -#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE (0x00AAC758) +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE (0x00AAC75C) #define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___POR 0x00000000 #define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE__SRP_REDO_AIFS_EN___POR 0x00000 @@ -352348,7 +361071,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___M 0x0003FFFF #define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___S 0 -#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION (0x00AAC75C) +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION (0x00AAC760) #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___POR 0x00800080 #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__ENABLE_LATENCY_MITIGATION___POR 0x0 @@ -352363,7 +361086,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___M 0xBFFFFFFF #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___S 0 -#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS (0x00AAC760) +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS (0x00AAC764) #define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___RWC QCSR_REG_RO #define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___POR 0x00000000 #define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_IGNORED___POR 0x0 @@ -352375,7 +361098,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___M 0x00000003 #define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___S 0 -#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER (0x00AAC764) +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER (0x00AAC768) #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___POR 0x00000000 #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IGNORE_TLV_COUNT___POR 0x0000 @@ -352390,7 +361113,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___M 0xFFFFFFFF #define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___S 0 -#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL (0x00AAC768) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL (0x00AAC76C) #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___POR 0x00000000 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL__MSG_ENABLE___POR 0x0 @@ -352399,7 +361122,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___M 0x00000001 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___S 0 -#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n(n) (0x00AAC76C+0x4*(n)) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n(n) (0x00AAC770+0x4*(n)) #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_nMIN 0 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_nMAX 3 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_ELEM 4 @@ -352413,32 +361136,32 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__FLUSH_CODE___S 0 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___M 0x00003FFF #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___S 0 -#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0 (0x00AAC76C) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0 (0x00AAC770) #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__UCODE_MSG___M 0x00003F00 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__UCODE_MSG___S 8 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__FLUSH_CODE___M 0x000000FF #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__FLUSH_CODE___S 0 -#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1 (0x00AAC770) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1 (0x00AAC774) #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__UCODE_MSG___M 0x00003F00 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__UCODE_MSG___S 8 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__FLUSH_CODE___M 0x000000FF #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__FLUSH_CODE___S 0 -#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2 (0x00AAC774) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2 (0x00AAC778) #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__UCODE_MSG___M 0x00003F00 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__UCODE_MSG___S 8 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__FLUSH_CODE___M 0x000000FF #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__FLUSH_CODE___S 0 -#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3 (0x00AAC778) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3 (0x00AAC77C) #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__UCODE_MSG___M 0x00003F00 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__UCODE_MSG___S 8 #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__FLUSH_CODE___M 0x000000FF #define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__FLUSH_CODE___S 0 -#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP (0x00AAC77C) +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP (0x00AAC780) #define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___POR 0x00010001 #define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_UNASSOC_WILDCARD_RESPONSE_ENABLE___POR 0x1 @@ -352450,7 +361173,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___M 0x0001FFFF #define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___S 0 -#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT (0x00AAC780) +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT (0x00AAC784) #define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___POR 0xFF17FFFF #define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SRP_INFO_TLV_TIMEOUT___POR 0xFF @@ -352477,7 +361200,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___M 0xFF1FFFFF #define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___S 0 -#define WMAC0_HWSCH_R0_SR_ERR_STATUS (0x00AAC784) +#define WMAC0_HWSCH_R0_SR_ERR_STATUS (0x00AAC788) #define WMAC0_HWSCH_R0_SR_ERR_STATUS___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_SR_ERR_STATUS___POR 0x00000000 #define WMAC0_HWSCH_R0_SR_ERR_STATUS__SRP_INFO_TLV_TIMEOUT_STATUS_P___POR 0x0 @@ -352495,7 +361218,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_SR_ERR_STATUS___M 0x0000000F #define WMAC0_HWSCH_R0_SR_ERR_STATUS___S 0 -#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0 (0x00AAC788) +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0 (0x00AAC78C) #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___POR 0x000FFFFF #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING19___POR 0x1 @@ -352561,7 +361284,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___M 0x000FFFFF #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___S 0 -#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1 (0x00AAC78C) +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1 (0x00AAC790) #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___POR 0x00007FFF #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_EGRESS___POR 0x1 @@ -352612,7 +361335,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___M 0x00007FFF #define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___S 0 -#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0 (0x00AAC790) +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0 (0x00AAC794) #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___POR 0x00000000 #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0__POSTRX_DMZ_WIN_LIMIT___POR 0x00000 @@ -352621,7 +361344,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___M 0x0003FFFF #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___S 0 -#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1 (0x00AAC794) +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1 (0x00AAC798) #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___POR 0x00000000 #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1__POSTRX_DMZ_RING_SELECT___POR 0x00000 @@ -352630,7 +361353,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___M 0x0003FFFF #define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___S 0 -#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0 (0x00AAC798) +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0 (0x00AAC79C) #define WMAC0_HWSCH_R0_ILP_CTRL_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ILP_CTRL_IX_0___POR 0x00000000 #define WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_RX_ABORT_OFFSET___POR 0x00 @@ -352642,7 +361365,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ILP_CTRL_IX_0___M 0x0000FFFF #define WMAC0_HWSCH_R0_ILP_CTRL_IX_0___S 0 -#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1 (0x00AAC79C) +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1 (0x00AAC7A0) #define WMAC0_HWSCH_R0_ILP_CTRL_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ILP_CTRL_IX_1___POR 0x00000000 #define WMAC0_HWSCH_R0_ILP_CTRL_IX_1__L0_REQ_RX_ABORT_OFFSET_EN___POR 0x00000 @@ -352651,22 +361374,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ILP_CTRL_IX_1___M 0x0003FFFF #define WMAC0_HWSCH_R0_ILP_CTRL_IX_1___S 0 -#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL (0x00AAC7A0) +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL (0x00AAC7A4) #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___POR 0x00000006 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_CMD_BASED_AUTO_FLUSH___POR 0x0 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___POR 0x1 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___POR 0x1 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___POR 0x0 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_CMD_BASED_AUTO_FLUSH___M 0x00000008 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_CMD_BASED_AUTO_FLUSH___S 3 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___M 0x00000004 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___S 2 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___M 0x00000002 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___S 1 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___M 0x00000001 #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___S 0 -#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___M 0x00000007 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___M 0x0000000F #define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___S 0 -#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0 (0x00AAC7A4) +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0 (0x00AAC7A8) #define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___POR 0x00000000 #define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0__EN___POR 0x00000 @@ -352675,7 +361401,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___M 0x0003FFFF #define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___S 0 -#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1 (0x00AAC7A8) +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1 (0x00AAC7AC) #define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___RWC QCSR_REG_RW #define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___POR 0x00000000 #define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1__DIS___POR 0x00000 @@ -353939,7 +362665,25 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___M 0xFFFFFFFF #define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___S 0 -#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER (0x00AB003C) +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG (0x00AB003C) +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__WR_REMAP_EN___POR 0x0 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__RD_REMAP_EN___POR 0x0 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__REMAP_SEC___POR 0x0 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__REMAP_ADDR___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__WR_REMAP_EN___M 0x80000000 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__WR_REMAP_EN___S 31 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__RD_REMAP_EN___M 0x40000000 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__RD_REMAP_EN___S 30 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__REMAP_SEC___M 0x20000000 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__REMAP_SEC___S 29 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__REMAP_ADDR___M 0x1FFFFFFF +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG__REMAP_ADDR___S 0 +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_NULL_REMAP_REG___S 0 + +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER (0x00AB0040) #define WMAC0_MXI_R0_MXI_S_PARE_REGISTER___RWC QCSR_REG_RW #define WMAC0_MXI_R0_MXI_S_PARE_REGISTER___POR 0x00000000 #define WMAC0_MXI_R0_MXI_S_PARE_REGISTER__VAL___POR 0x00000000 @@ -353948,7 +362692,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_MXI_S_PARE_REGISTER___M 0xFFFFFFFF #define WMAC0_MXI_R0_MXI_S_PARE_REGISTER___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER (0x00AB0040) +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER (0x00AB0044) #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___RWC QCSR_REG_RO #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000 @@ -353957,7 +362701,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___M 0xFFFFFFFF #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER (0x00AB0044) +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER (0x00AB0048) #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___RWC QCSR_REG_RO #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER__VALUE___POR 0x00 @@ -353966,7 +362710,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___M 0x000000FF #define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0 (0x00AB0048) +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0 (0x00AB004C) #define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___RWC QCSR_REG_RO #define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___POR 0x00000211 #define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1 @@ -353981,7 +362725,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___M 0x00000FFF #define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK (0x00AB004C) +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK (0x00AB0050) #define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 @@ -353990,7 +362734,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___M 0x00000001 #define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE (0x00AB0050) +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE (0x00AB0054) #define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0 @@ -354035,7 +362779,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF #define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS (0x00AB0054) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS (0x00AB0058) #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___RWC QCSR_REG_RO #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0 @@ -354053,7 +362797,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___M 0x01010101 #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS (0x00AB0058) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS (0x00AB005C) #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___RWC QCSR_REG_RO #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00 @@ -354068,7 +362812,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___M 0x003F3F3F #define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL (0x00AB005C) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL (0x00AB0060) #define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00 @@ -354086,7 +362830,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F #define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL (0x00AB0060) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL (0x00AB0064) #define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00 @@ -354104,7 +362848,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F #define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL (0x00AB0064) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL (0x00AB0068) #define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___POR 0x00240000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0 @@ -354140,7 +362884,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___M 0x0FFFFFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL (0x00AB0068) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL (0x00AB006C) #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF @@ -354152,7 +362896,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___M 0xFFFF0001 #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS (0x00AB006C) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS (0x00AB0070) #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___RWC QCSR_REG_RO #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000 @@ -354161,7 +362905,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___M 0x0000FFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS (0x00AB0070) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS (0x00AB0074) #define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___RWC QCSR_REG_RO #define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000 @@ -354173,7 +362917,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___M 0xFFFFFFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL (0x00AB0074) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL (0x00AB0078) #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 @@ -354188,7 +362932,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL (0x00AB0078) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL (0x00AB007C) #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 @@ -354203,7 +362947,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00AB007C) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00AB0080) #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 @@ -354212,7 +362956,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00AB0080) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00AB0084) #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 @@ -354221,7 +362965,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00AB0084) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00AB0088) #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 @@ -354230,7 +362974,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00AB0088) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00AB008C) #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 @@ -354239,7 +362983,7 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF #define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S 0 -#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL (0x00AB008C) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL (0x00AB0090) #define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW #define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000 #define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0 @@ -354648,8 +363392,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL (0x00AB30D0) #define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___RWC QCSR_REG_RO -#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___POR 0x00000100 -#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___POR 0x100 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___POR 0x00000320 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___POR 0x320 #define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___M 0x000003FF #define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___S 0 #define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___M 0x000003FF @@ -355539,8 +364283,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_SFM_R0_CLK_GATE_DISABLE (0x00AB3890) #define WMAC0_SFM_R0_CLK_GATE_DISABLE___RWC QCSR_REG_RW -#define WMAC0_SFM_R0_CLK_GATE_DISABLE___POR 0x80000000 -#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x1 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE___POR 0x00000000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_GATE_DIS_HW_INTF_UPDT___POR 0x0 #define WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___POR 0x00 #define WMAC0_SFM_R0_CLK_GATE_DISABLE__BMGR___POR 0x0 #define WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM___POR 0x0 @@ -355565,8 +364309,8 @@ enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; #define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT2___POR 0x0 #define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT1___POR 0x0 #define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT0___POR 0x0 -#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000 -#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S 31 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_GATE_DIS_HW_INTF_UPDT___M 0x80000000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_GATE_DIS_HW_INTF_UPDT___S 31 #define WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___M 0x7F800000 #define WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___S 23 #define WMAC0_SFM_R0_CLK_GATE_DISABLE__BMGR___M 0x00400000 diff --git a/hw/qca6750/v1/mac_tcl_reg_seq_hwioreg.h b/hw/qca6750/v1/mac_tcl_reg_seq_hwioreg.h index b4600515f2c7..f1631cd65288 100644 --- a/hw/qca6750/v1/mac_tcl_reg_seq_hwioreg.h +++ b/hw/qca6750/v1/mac_tcl_reg_seq_hwioreg.h @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 11/13/2019 -// User Name:sanjdas +// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 11/12/2019 +// User Name:pparekh // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // @@ -1075,10 +1075,35 @@ #define HWIO_TCL_R0_S_PARE_REGISTER_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_S_PARE_REGISTER_VAL_SHFT 0x0 +//// Register TCL_R0_MISC_CTRL //// + +#define HWIO_TCL_R0_MISC_CTRL_ADDR(x) (x+0x00000690) +#define HWIO_TCL_R0_MISC_CTRL_PHYS(x) (x+0x00000690) +#define HWIO_TCL_R0_MISC_CTRL_RMSK 0x00000003 +#define HWIO_TCL_R0_MISC_CTRL_SHFT 0 +#define HWIO_TCL_R0_MISC_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_MISC_CTRL_ADDR(x), HWIO_TCL_R0_MISC_CTRL_RMSK) +#define HWIO_TCL_R0_MISC_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_MISC_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_MISC_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_MISC_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_MISC_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_MISC_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_MISC_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_BMSK 0x00000002 +#define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_SHFT 0x1 + +#define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_BMSK 0x00000001 +#define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_SHFT 0x0 + //// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000690) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000690) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000694) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000694) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ @@ -1099,8 +1124,8 @@ //// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000694) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000694) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000698) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000698) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x0fffffff #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ @@ -1124,8 +1149,8 @@ //// Register TCL_R0_SW2TCL1_RING_ID //// -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x00000698) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x00000698) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x0000069c) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x0000069c) #define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ @@ -1146,8 +1171,8 @@ //// Register TCL_R0_SW2TCL1_RING_STATUS //// -#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x0000069c) -#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x0000069c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x000006a0) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x000006a0) #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ @@ -1171,8 +1196,8 @@ //// Register TCL_R0_SW2TCL1_RING_MISC //// -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000006a0) -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000006a0) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000006a4) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000006a4) #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ @@ -1223,8 +1248,8 @@ //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000006ac) -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000006ac) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000006b0) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000006b0) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ @@ -1245,8 +1270,8 @@ //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000006b0) -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000006b0) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000006b4) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000006b4) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ @@ -1267,8 +1292,8 @@ //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000006c0) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000006c0) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000006c4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000006c4) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ @@ -1295,8 +1320,8 @@ //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000006c4) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000006c4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000006c8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000006c8) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ @@ -1317,8 +1342,8 @@ //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000006c8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000006c8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000006cc) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000006cc) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ @@ -1345,8 +1370,8 @@ //// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000006cc) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000006cc) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000006d0) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000006d0) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ @@ -1367,8 +1392,8 @@ //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000006d0) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000006d0) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000006d4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000006d4) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ @@ -1389,8 +1414,8 @@ //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000006d4) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000006d4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000006d8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000006d8) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ @@ -1414,8 +1439,8 @@ //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006d8) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006d8) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006dc) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006dc) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ @@ -1436,8 +1461,8 @@ //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006dc) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006dc) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006e0) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006e0) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ @@ -1461,8 +1486,8 @@ //// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006e0) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006e0) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006e4) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006e4) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ @@ -1483,8 +1508,8 @@ //// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006e4) -#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006e4) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006e8) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006e8) #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -1505,8 +1530,8 @@ //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x000006e8) -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x000006e8) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x000006ec) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x000006ec) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ @@ -1527,8 +1552,8 @@ //// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x000006ec) -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x000006ec) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x000006f0) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x000006f0) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x0fffffff #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ @@ -1552,8 +1577,8 @@ //// Register TCL_R0_SW2TCL2_RING_ID //// -#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x000006f0) -#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x000006f0) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x000006f4) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x000006f4) #define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ @@ -1574,8 +1599,8 @@ //// Register TCL_R0_SW2TCL2_RING_STATUS //// -#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x000006f4) -#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x000006f4) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x000006f8) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x000006f8) #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ @@ -1599,8 +1624,8 @@ //// Register TCL_R0_SW2TCL2_RING_MISC //// -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x000006f8) -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x000006f8) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x000006fc) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x000006fc) #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ @@ -1651,8 +1676,8 @@ //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// -#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000704) -#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000704) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000708) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000708) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ @@ -1673,8 +1698,8 @@ //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// -#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000708) -#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000708) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000070c) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000070c) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ @@ -1695,8 +1720,8 @@ //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000718) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000718) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000071c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000071c) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ @@ -1723,8 +1748,8 @@ //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000071c) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000071c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000720) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000720) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ @@ -1745,8 +1770,8 @@ //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000720) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000720) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000724) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000724) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ @@ -1773,8 +1798,8 @@ //// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000724) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000724) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000728) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000728) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ @@ -1795,8 +1820,8 @@ //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000728) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000728) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000072c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000072c) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ @@ -1817,8 +1842,8 @@ //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000072c) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000072c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000730) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000730) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ @@ -1842,8 +1867,8 @@ //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000730) -#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000730) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000734) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000734) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ @@ -1864,8 +1889,8 @@ //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000734) -#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000734) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000738) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000738) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ @@ -1889,8 +1914,8 @@ //// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// -#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x00000738) -#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x00000738) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x0000073c) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x0000073c) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ @@ -1911,8 +1936,8 @@ //// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000073c) -#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000073c) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000740) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000740) #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -1933,8 +1958,8 @@ //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// -#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000740) -#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000740) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000744) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000744) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ @@ -1955,8 +1980,8 @@ //// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// -#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000744) -#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000744) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000748) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000748) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x0fffffff #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ @@ -1980,8 +2005,8 @@ //// Register TCL_R0_SW2TCL3_RING_ID //// -#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x00000748) -#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x00000748) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000074c) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000074c) #define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ @@ -2002,8 +2027,8 @@ //// Register TCL_R0_SW2TCL3_RING_STATUS //// -#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x0000074c) -#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x0000074c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x00000750) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x00000750) #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ @@ -2027,8 +2052,8 @@ //// Register TCL_R0_SW2TCL3_RING_MISC //// -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000750) -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000750) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000754) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000754) #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ @@ -2079,8 +2104,8 @@ //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// -#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000075c) -#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000075c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000760) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000760) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ @@ -2101,8 +2126,8 @@ //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// -#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000760) -#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000760) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000764) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000764) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ @@ -2123,8 +2148,8 @@ //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000770) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000770) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000774) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000774) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ @@ -2151,8 +2176,8 @@ //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000774) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000774) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000778) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000778) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ @@ -2173,8 +2198,8 @@ //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000778) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000778) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000077c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000077c) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ @@ -2201,8 +2226,8 @@ //// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000077c) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000077c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000780) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000780) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ @@ -2223,8 +2248,8 @@ //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000780) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000780) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000784) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000784) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ @@ -2245,8 +2270,8 @@ //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000784) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000784) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000788) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000788) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ @@ -2270,8 +2295,8 @@ //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000788) -#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000788) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000078c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000078c) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ @@ -2292,8 +2317,8 @@ //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000078c) -#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000078c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000790) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000790) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ @@ -2317,8 +2342,8 @@ //// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// -#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x00000790) -#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x00000790) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x00000794) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x00000794) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ @@ -2339,8 +2364,8 @@ //// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000794) -#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000794) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000798) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000798) #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -2361,8 +2386,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) (x+0x00000798) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) (x+0x00000798) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) (x+0x0000079c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) (x+0x0000079c) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x) \ @@ -2383,8 +2408,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) (x+0x0000079c) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) (x+0x0000079c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) (x+0x000007a0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) (x+0x000007a0) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK 0x0fffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x) \ @@ -2408,8 +2433,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_ID //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) (x+0x000007a0) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) (x+0x000007a0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) (x+0x000007a4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) (x+0x000007a4) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x) \ @@ -2430,8 +2455,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_STATUS //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) (x+0x000007a4) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) (x+0x000007a4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) (x+0x000007a8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) (x+0x000007a8) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x) \ @@ -2455,8 +2480,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_MISC //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) (x+0x000007a8) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) (x+0x000007a8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) (x+0x000007ac) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) (x+0x000007ac) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK 0x003fffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x) \ @@ -2507,8 +2532,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) (x+0x000007b4) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) (x+0x000007b4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) (x+0x000007b8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) (x+0x000007b8) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x) \ @@ -2529,8 +2554,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) (x+0x000007b8) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) (x+0x000007b8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) (x+0x000007bc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) (x+0x000007bc) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x) \ @@ -2551,8 +2576,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000007c8) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000007c8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000007cc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000007cc) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ @@ -2579,8 +2604,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000007cc) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000007cc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000007d0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000007d0) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ @@ -2601,8 +2626,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000007d0) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000007d0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000007d4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000007d4) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x) \ @@ -2629,8 +2654,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000007d4) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000007d4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000007d8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000007d8) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ @@ -2651,8 +2676,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000007d8) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000007d8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000007dc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000007dc) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ @@ -2673,8 +2698,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000007dc) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000007dc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000007e0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000007e0) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ @@ -2698,8 +2723,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007e0) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007e0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007e4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007e4) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x) \ @@ -2720,8 +2745,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007e4) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007e4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007e8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007e8) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x) \ @@ -2745,8 +2770,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) (x+0x000007e8) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) (x+0x000007e8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) (x+0x000007ec) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) (x+0x000007ec) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x) \ @@ -2767,8 +2792,8 @@ //// Register TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007ec) -#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007ec) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007f0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007f0) #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -2789,8 +2814,8 @@ //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// -#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000007f0) -#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000007f0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000007f4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000007f4) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ @@ -2811,8 +2836,8 @@ //// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// -#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000007f4) -#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000007f4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000007f8) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000007f8) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ @@ -2836,8 +2861,8 @@ //// Register TCL_R0_FW2TCL1_RING_ID //// -#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x000007f8) -#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x000007f8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x000007fc) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x000007fc) #define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ @@ -2858,8 +2883,8 @@ //// Register TCL_R0_FW2TCL1_RING_STATUS //// -#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x000007fc) -#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x000007fc) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x00000800) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x00000800) #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ @@ -2883,8 +2908,8 @@ //// Register TCL_R0_FW2TCL1_RING_MISC //// -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000800) -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000800) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000804) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000804) #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ @@ -2935,8 +2960,8 @@ //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// -#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000080c) -#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000080c) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000810) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000810) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ @@ -2957,8 +2982,8 @@ //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// -#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000810) -#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000810) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000814) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000814) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ @@ -2979,8 +3004,8 @@ //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000820) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000820) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000824) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000824) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ @@ -3007,8 +3032,8 @@ //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000824) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000824) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000828) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000828) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ @@ -3029,8 +3054,8 @@ //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000828) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000828) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000082c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000082c) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ @@ -3057,8 +3082,8 @@ //// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000082c) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000082c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000830) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000830) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ @@ -3079,8 +3104,8 @@ //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000830) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000830) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000834) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000834) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ @@ -3101,8 +3126,8 @@ //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000834) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000834) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000838) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000838) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ @@ -3126,8 +3151,8 @@ //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000838) -#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000838) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000083c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000083c) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ @@ -3148,8 +3173,8 @@ //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000083c) -#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000083c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000840) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000840) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ @@ -3173,8 +3198,8 @@ //// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// -#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000840) -#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000840) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000844) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000844) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ @@ -3195,8 +3220,8 @@ //// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000844) -#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000844) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000848) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000848) #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -3217,8 +3242,8 @@ //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// -#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x00000848) -#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x00000848) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x0000084c) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x0000084c) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ @@ -3239,8 +3264,8 @@ //// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// -#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x0000084c) -#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x0000084c) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x00000850) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x00000850) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ @@ -3264,8 +3289,8 @@ //// Register TCL_R0_TCL2TQM_RING_ID //// -#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000850) -#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000850) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000854) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000854) #define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ @@ -3289,8 +3314,8 @@ //// Register TCL_R0_TCL2TQM_RING_STATUS //// -#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000854) -#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000854) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000858) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000858) #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ @@ -3314,8 +3339,8 @@ //// Register TCL_R0_TCL2TQM_RING_MISC //// -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x00000858) -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x00000858) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x0000085c) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x0000085c) #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ @@ -3369,8 +3394,8 @@ //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// -#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000085c) -#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000085c) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000860) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000860) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ @@ -3391,8 +3416,8 @@ //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// -#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000860) -#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000860) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000864) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000864) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ @@ -3413,8 +3438,8 @@ //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000086c) -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000086c) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000870) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000870) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ @@ -3441,8 +3466,8 @@ //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000870) -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000870) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000874) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000874) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ @@ -3469,8 +3494,8 @@ //// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000874) -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000874) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000878) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000878) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ @@ -3491,8 +3516,8 @@ //// Register TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000890) -#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000890) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000894) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000894) #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x) \ @@ -3513,8 +3538,8 @@ //// Register TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000894) -#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000894) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000898) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000898) #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x) \ @@ -3538,8 +3563,8 @@ //// Register TCL_R0_TCL2TQM_RING_MSI1_DATA //// -#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) (x+0x00000898) -#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) (x+0x00000898) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) (x+0x0000089c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) (x+0x0000089c) #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x) \ @@ -3560,8 +3585,8 @@ //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000089c) -#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000089c) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008a0) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008a0) #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -3582,8 +3607,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000008a0) -#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000008a0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000008a4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000008a4) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ @@ -3604,8 +3629,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000008a4) -#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000008a4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000008a8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000008a8) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ @@ -3629,8 +3654,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_ID //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000008a8) -#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000008a8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000008ac) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000008ac) #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ @@ -3654,8 +3679,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_STATUS //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000008ac) -#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000008ac) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000008b0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000008b0) #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ @@ -3679,8 +3704,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_MISC //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000008b0) -#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000008b0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000008b4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000008b4) #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ @@ -3734,8 +3759,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008b4) -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008b4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008b8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008b8) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ @@ -3756,8 +3781,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008b8) -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008b8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008bc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008bc) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ @@ -3778,8 +3803,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008c4) -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008c4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008c8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008c8) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ @@ -3806,8 +3831,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008c8) -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008c8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008cc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008cc) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ @@ -3834,8 +3859,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008cc) -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008cc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008d0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008d0) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ @@ -3856,8 +3881,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008e8) -#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008e8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008ec) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008ec) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ @@ -3878,8 +3903,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008ec) -#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008ec) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008f0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008f0) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ @@ -3903,8 +3928,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x000008f0) -#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x000008f0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x000008f4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x000008f4) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ @@ -3925,8 +3950,8 @@ //// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008f4) -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008f4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008f8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008f8) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -3947,8 +3972,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x000008f8) -#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x000008f8) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x000008fc) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x000008fc) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ @@ -3969,8 +3994,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x000008fc) -#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x000008fc) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x00000900) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x00000900) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ @@ -3994,8 +4019,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_ID //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000900) -#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000900) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000904) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000904) #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ @@ -4019,8 +4044,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_STATUS //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000904) -#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000904) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000908) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000908) #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ @@ -4044,8 +4069,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_MISC //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x00000908) -#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x00000908) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x0000090c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x0000090c) #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ @@ -4099,8 +4124,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000090c) -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000090c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000910) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000910) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ @@ -4121,8 +4146,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000910) -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000910) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000914) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000914) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ @@ -4143,8 +4168,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000091c) -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000091c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000920) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000920) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ @@ -4171,8 +4196,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000920) -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000920) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000924) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000924) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ @@ -4199,8 +4224,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000924) -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000924) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000928) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000928) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ @@ -4221,8 +4246,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000940) -#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000940) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000944) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000944) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ @@ -4243,8 +4268,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000944) -#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000944) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000948) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000948) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ @@ -4268,8 +4293,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x00000948) -#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x00000948) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x0000094c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x0000094c) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ @@ -4290,8 +4315,8 @@ //// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000094c) -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000094c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000950) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000950) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -4312,8 +4337,8 @@ //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// -#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000950) -#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000950) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000954) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000954) #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ @@ -4334,8 +4359,8 @@ //// Register TCL_R0_TCL2FW_RING_BASE_MSB //// -#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000954) -#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000954) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000958) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000958) #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ @@ -4359,8 +4384,8 @@ //// Register TCL_R0_TCL2FW_RING_ID //// -#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x00000958) -#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x00000958) +#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x0000095c) +#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x0000095c) #define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ @@ -4384,8 +4409,8 @@ //// Register TCL_R0_TCL2FW_RING_STATUS //// -#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x0000095c) -#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x0000095c) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x00000960) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x00000960) #define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ @@ -4409,8 +4434,8 @@ //// Register TCL_R0_TCL2FW_RING_MISC //// -#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000960) -#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000960) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000964) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000964) #define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff #define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ @@ -4464,8 +4489,8 @@ //// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// -#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000964) -#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000964) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000968) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000968) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ @@ -4486,8 +4511,8 @@ //// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// -#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000968) -#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000968) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000096c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000096c) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ @@ -4508,8 +4533,8 @@ //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000974) -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000974) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000978) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000978) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ @@ -4536,8 +4561,8 @@ //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000978) -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000978) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000097c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000097c) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ @@ -4564,8 +4589,8 @@ //// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000097c) -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000097c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000980) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000980) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ @@ -4586,8 +4611,8 @@ //// Register TCL_R0_TCL2FW_RING_MSI1_BASE_LSB //// -#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000998) -#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000998) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000099c) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000099c) #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x) \ @@ -4608,8 +4633,8 @@ //// Register TCL_R0_TCL2FW_RING_MSI1_BASE_MSB //// -#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000099c) -#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000099c) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000009a0) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000009a0) #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x) \ @@ -4633,8 +4658,8 @@ //// Register TCL_R0_TCL2FW_RING_MSI1_DATA //// -#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x) (x+0x000009a0) -#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_PHYS(x) (x+0x000009a0) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x) (x+0x000009a4) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_PHYS(x) (x+0x000009a4) #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x) \ @@ -4655,8 +4680,8 @@ //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// -#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009a4) -#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009a4) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009a8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009a8) #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ @@ -4677,8 +4702,8 @@ //// Register TCL_R0_GXI_TESTBUS_LOWER //// -#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000009a8) -#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000009a8) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000009ac) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000009ac) #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ @@ -4699,8 +4724,8 @@ //// Register TCL_R0_GXI_TESTBUS_UPPER //// -#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000009ac) -#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000009ac) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000009b0) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000009b0) #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ @@ -4721,8 +4746,8 @@ //// Register TCL_R0_GXI_SM_STATES_IX_0 //// -#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000009b0) -#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000009b0) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000009b4) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000009b4) #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ @@ -4749,8 +4774,8 @@ //// Register TCL_R0_GXI_END_OF_TEST_CHECK //// -#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000009b4) -#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000009b4) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000009b8) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000009b8) #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ @@ -4771,8 +4796,8 @@ //// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// -#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000009b8) -#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000009b8) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000009bc) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000009bc) #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ @@ -4829,8 +4854,8 @@ //// Register TCL_R0_GXI_GXI_ERR_INTS //// -#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000009bc) -#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000009bc) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000009c0) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000009c0) #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ @@ -4860,8 +4885,8 @@ //// Register TCL_R0_GXI_GXI_ERR_STATS //// -#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000009c0) -#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000009c0) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000009c4) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000009c4) #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ @@ -4888,8 +4913,8 @@ //// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// -#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000009c4) -#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000009c4) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000009c8) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000009c8) #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ @@ -4919,8 +4944,8 @@ //// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// -#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000009c8) -#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000009c8) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000009cc) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000009cc) #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ @@ -4950,8 +4975,8 @@ //// Register TCL_R0_GXI_GXI_MISC_CONTROL //// -#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000009cc) -#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000009cc) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000009d0) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000009d0) #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ @@ -4999,8 +5024,8 @@ //// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// -#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000009d0) -#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000009d0) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000009d4) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000009d4) #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ @@ -5024,8 +5049,8 @@ //// Register TCL_R0_GXI_GXI_WDOG_STATUS //// -#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000009d4) -#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000009d4) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000009d8) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000009d8) #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ @@ -5046,8 +5071,8 @@ //// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// -#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000009d8) -#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000009d8) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000009dc) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000009dc) #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ @@ -5071,8 +5096,8 @@ //// Register TCL_R0_GXI_GXI_RD_LATENCY_CTRL //// -#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x000009dc) -#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x000009dc) +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x000009e0) +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x000009e0) #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ @@ -5099,8 +5124,8 @@ //// Register TCL_R0_GXI_GXI_WR_LATENCY_CTRL //// -#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x000009e0) -#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x000009e0) +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x000009e4) +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x000009e4) #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ @@ -5127,8 +5152,8 @@ //// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// -#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009e4) -#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009e4) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009e8) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009e8) #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ @@ -5149,8 +5174,8 @@ //// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// -#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009e8) -#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009e8) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009ec) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009ec) #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ @@ -5171,8 +5196,8 @@ //// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// -#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009ec) -#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009ec) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009f0) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009f0) #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ @@ -5193,8 +5218,8 @@ //// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// -#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009f0) -#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009f0) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009f4) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009f4) #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ @@ -5215,8 +5240,8 @@ //// Register TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL //// -#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000009f4) -#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000009f4) +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000009f8) +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000009f8) #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ @@ -5246,8 +5271,8 @@ //// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// -#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x000009f8) -#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x000009f8) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x000009fc) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x000009fc) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ @@ -5268,8 +5293,8 @@ //// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// -#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x000009fc) -#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x000009fc) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000a00) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000a00) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ @@ -5290,8 +5315,8 @@ //// Register TCL_R0_ASE_GST_SIZE //// -#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000a00) -#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000a00) +#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000a04) +#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000a04) #define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff #define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ @@ -5312,8 +5337,8 @@ //// Register TCL_R0_ASE_SEARCH_CTRL //// -#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x00000a04) -#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x00000a04) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x00000a08) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x00000a08) #define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff3fff #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ @@ -5355,8 +5380,8 @@ //// Register TCL_R0_ASE_WATCHDOG //// -#define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000a08) -#define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000a08) +#define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000a0c) +#define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000a0c) #define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff #define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ @@ -5380,8 +5405,8 @@ //// Register TCL_R0_ASE_CLKGATE_DISABLE //// -#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000a0c) -#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000a0c) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000a10) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000a10) #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ @@ -5435,8 +5460,8 @@ //// Register TCL_R0_ASE_WRITE_BACK_PENDING //// -#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000a10) -#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000a10) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000a14) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000a14) #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ @@ -5484,7 +5509,7 @@ #define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001004) #define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001004) -#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff +#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x3fffffff #define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) @@ -5499,10 +5524,13 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 -#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_RES_WR_BMSK 0x30000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_RES_WR_SHFT 0x1c -#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x0e000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x19 + +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x01e00000 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 @@ -5530,7 +5558,7 @@ #define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001008) #define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001008) -#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x0003ffff +#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x001fffff #define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) @@ -5545,6 +5573,9 @@ HWIO_INTFREE();\ } while (0) +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_BMSK 0x001c0000 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_SHFT 0x12 + #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x00038000 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 0xf @@ -5563,10 +5594,110 @@ #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 +//// Register TCL_R1_STATUS //// + +#define HWIO_TCL_R1_STATUS_ADDR(x) (x+0x0000100c) +#define HWIO_TCL_R1_STATUS_PHYS(x) (x+0x0000100c) +#define HWIO_TCL_R1_STATUS_RMSK 0x07ffffff +#define HWIO_TCL_R1_STATUS_SHFT 0 +#define HWIO_TCL_R1_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_STATUS_ADDR(x), HWIO_TCL_R1_STATUS_RMSK) +#define HWIO_TCL_R1_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_STATUS_ADDR(x), mask) +#define HWIO_TCL_R1_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_STATUS_ADDR(x), val) +#define HWIO_TCL_R1_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_STATUS_ADDR(x), mask, val, HWIO_TCL_R1_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_BMSK 0x04000000 +#define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_SHFT 0x1a + +#define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_BMSK 0x02000000 +#define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_SHFT 0x19 + +#define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_BMSK 0x01000000 +#define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_SHFT 0x18 + +#define HWIO_TCL_R1_STATUS_PROD_RING_BUNC_FIFO_CTRL_IDLE_BMSK 0x00800000 +#define HWIO_TCL_R1_STATUS_PROD_RING_BUNC_FIFO_CTRL_IDLE_SHFT 0x17 + +#define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_BMSK 0x00400000 +#define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_SHFT 0x16 + +#define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_BMSK 0x00200000 +#define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_SHFT 0x15 + +#define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_BMSK 0x00100000 +#define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_SHFT 0x14 + +#define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_BMSK 0x00080000 +#define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_SHFT 0x13 + +#define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_BMSK 0x00040000 +#define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_SHFT 0x12 + +#define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_BMSK 0x00020000 +#define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_SHFT 0x11 + +#define HWIO_TCL_R1_STATUS_ASE_IDLE_BMSK 0x00010000 +#define HWIO_TCL_R1_STATUS_ASE_IDLE_SHFT 0x10 + +#define HWIO_TCL_R1_STATUS_PARSER_IDLE_BMSK 0x00008000 +#define HWIO_TCL_R1_STATUS_PARSER_IDLE_SHFT 0xf + +#define HWIO_TCL_R1_STATUS_TCL_STATUS2_PROD_IDLE_BMSK 0x00004000 +#define HWIO_TCL_R1_STATUS_TCL_STATUS2_PROD_IDLE_SHFT 0xe + +#define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_BMSK 0x00002000 +#define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_SHFT 0xd + +#define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_BMSK 0x00001000 +#define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_SHFT 0xc + +#define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_BMSK 0x00000800 +#define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_SHFT 0xb + +#define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_BMSK 0x00000400 +#define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_SHFT 0xa + +#define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_BMSK 0x00000200 +#define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_SHFT 0x9 + +#define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_BMSK 0x00000100 +#define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_SHFT 0x8 + +#define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_BMSK 0x00000040 +#define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_SHFT 0x6 + +#define HWIO_TCL_R1_STATUS_GXI_IDLE_BMSK 0x00000020 +#define HWIO_TCL_R1_STATUS_GXI_IDLE_SHFT 0x5 + +#define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_BMSK 0x00000010 +#define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_SHFT 0x4 + +#define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_BMSK 0x00000008 +#define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_SHFT 0x3 + +#define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_BMSK 0x00000004 +#define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_SHFT 0x2 + +#define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_BMSK 0x00000002 +#define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_SHFT 0x1 + +#define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_BMSK 0x00000001 +#define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_SHFT 0x0 + //// Register TCL_R1_TESTBUS_CTRL_0 //// -#define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x0000100c) -#define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x0000100c) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001010) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001010) #define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x3fffffff #define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ @@ -5605,8 +5736,8 @@ //// Register TCL_R1_TESTBUS_LOW //// -#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x00001010) -#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x00001010) +#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x00001014) +#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x00001014) #define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff #define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ @@ -5627,8 +5758,8 @@ //// Register TCL_R1_TESTBUS_HIGH //// -#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001014) -#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001014) +#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001018) +#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001018) #define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff #define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ @@ -5649,8 +5780,8 @@ //// Register TCL_R1_EVENTMASK_IX_0 //// -#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001018) -#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001018) +#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x0000101c) +#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x0000101c) #define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff #define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ @@ -5671,8 +5802,8 @@ //// Register TCL_R1_EVENTMASK_IX_1 //// -#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x0000101c) -#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x0000101c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001020) +#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001020) #define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff #define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ @@ -5693,8 +5824,8 @@ //// Register TCL_R1_EVENTMASK_IX_2 //// -#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00001020) -#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00001020) +#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00001024) +#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00001024) #define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff #define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ @@ -5715,8 +5846,8 @@ //// Register TCL_R1_EVENTMASK_IX_3 //// -#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001024) -#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001024) +#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001028) +#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001028) #define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff #define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ @@ -5737,8 +5868,8 @@ //// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// -#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001028) -#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001028) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x0000102c) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x0000102c) #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ @@ -5768,8 +5899,8 @@ //// Register TCL_R1_SPARE_REGISTER //// -#define HWIO_TCL_R1_SPARE_REGISTER_ADDR(x) (x+0x0000102c) -#define HWIO_TCL_R1_SPARE_REGISTER_PHYS(x) (x+0x0000102c) +#define HWIO_TCL_R1_SPARE_REGISTER_ADDR(x) (x+0x00001030) +#define HWIO_TCL_R1_SPARE_REGISTER_PHYS(x) (x+0x00001030) #define HWIO_TCL_R1_SPARE_REGISTER_RMSK 0xffffffff #define HWIO_TCL_R1_SPARE_REGISTER_SHFT 0 #define HWIO_TCL_R1_SPARE_REGISTER_IN(x) \ @@ -5790,8 +5921,8 @@ //// Register TCL_R1_END_OF_TEST_CHECK //// -#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001030) -#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001030) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001034) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001034) #define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 #define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ @@ -5812,8 +5943,8 @@ //// Register TCL_R1_ASE_END_OF_TEST_CHECK //// -#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x00001034) -#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x00001034) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x00001038) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x00001038) #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ @@ -5834,8 +5965,8 @@ //// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// -#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001038) -#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001038) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x0000103c) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x0000103c) #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ @@ -5856,8 +5987,8 @@ //// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// -#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x0000103c) -#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x0000103c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001040) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001040) #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ @@ -5878,8 +6009,8 @@ //// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// -#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001040) -#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001040) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001044) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001044) #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ @@ -5900,8 +6031,8 @@ //// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// -#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x00001044) -#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x00001044) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x00001048) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x00001048) #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ @@ -5925,8 +6056,8 @@ //// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// -#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001048) -#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001048) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x0000104c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x0000104c) #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ @@ -5953,8 +6084,8 @@ //// Register TCL_R1_ASE_SM_STATES //// -#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x0000104c) -#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x0000104c) +#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001050) +#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001050) #define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fff0f #define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ @@ -5993,8 +6124,8 @@ //// Register TCL_R1_ASE_CACHE_DEBUG //// -#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001050) -#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001050) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001054) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001054) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff #define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ @@ -6015,8 +6146,8 @@ //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// -#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x00001054) -#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x00001054) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x00001058) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x00001058) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ @@ -6046,8 +6177,8 @@ //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// -#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1058+0x4*n) -#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1058+0x4*n) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x105C+0x4*n) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x105C+0x4*n) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 diff --git a/hw/qca6750/v1/reo_reg_seq_hwioreg.h b/hw/qca6750/v1/reo_reg_seq_hwioreg.h index 2369c0a2ba7a..807c4515f36c 100644 --- a/hw/qca6750/v1/reo_reg_seq_hwioreg.h +++ b/hw/qca6750/v1/reo_reg_seq_hwioreg.h @@ -8464,14 +8464,8 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_DESC_TYPE_BITMAP_BMSK 0x01fe0000 -#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_DESC_TYPE_BITMAP_SHFT 0x11 - -#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_EMPTY_THRESHOLD_SET2_BMSK 0x0001fe00 -#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_EMPTY_THRESHOLD_SET2_SHFT 0x9 - -#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_LINE_USE_NUM_SET2_BMSK 0x000001ff -#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_LINE_USE_NUM_SET2_SHFT 0x0 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x01ffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0x0 //// Register REO_R0_CACHE_CTL_SET_SIZE //// @@ -9023,10 +9017,128 @@ #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 +//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1 //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) (x+0x00002040) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) (x+0x00002040) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x000007ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x000007f8 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 0x3 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x00000004 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 0x2 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x00000002 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 0x1 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2 //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) (x+0x00002044) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) (x+0x00002044) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3 //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) (x+0x00002048) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) (x+0x00002048) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0x000000ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0x000000ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) (x+0x0000204c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) (x+0x0000204c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 0x16 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x003ff000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 0xc + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x00000800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 0xb + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x00000600 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 0x9 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x000001e0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 0x5 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x0000001c +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 0x2 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x00000002 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 0x1 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0x0 + //// Register REO_R1_END_OF_TEST_CHECK //// -#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002040) -#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002040) +#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002050) +#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002050) #define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 #define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ @@ -9047,8 +9159,8 @@ //// Register REO_R1_SM_ALL_IDLE //// -#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x00002044) -#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x00002044) +#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x00002054) +#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x00002054) #define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 #define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 #define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ @@ -9075,8 +9187,8 @@ //// Register REO_R1_TESTBUS_CTRL //// -#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002048) -#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002048) +#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002058) +#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002058) #define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f #define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 #define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ @@ -9097,8 +9209,8 @@ //// Register REO_R1_TESTBUS_LOWER //// -#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x0000204c) -#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x0000204c) +#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x0000205c) +#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x0000205c) #define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff #define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 #define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ @@ -9119,8 +9231,8 @@ //// Register REO_R1_TESTBUS_HIGHER //// -#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002050) -#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002050) +#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002060) +#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002060) #define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff #define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ @@ -9141,8 +9253,8 @@ //// Register REO_R1_SM_STATES_IX_0 //// -#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002054) -#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002054) +#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002064) +#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002064) #define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 #define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ @@ -9163,8 +9275,8 @@ //// Register REO_R1_SM_STATES_IX_1 //// -#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002058) -#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002058) +#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002068) +#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002068) #define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 #define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ @@ -9185,8 +9297,8 @@ //// Register REO_R1_SM_STATES_IX_2 //// -#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x0000205c) -#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x0000205c) +#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x0000206c) +#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x0000206c) #define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 #define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ @@ -9207,8 +9319,8 @@ //// Register REO_R1_SM_STATES_IX_3 //// -#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002060) -#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002060) +#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002070) +#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002070) #define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 #define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ @@ -9229,8 +9341,8 @@ //// Register REO_R1_SM_STATES_IX_4 //// -#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x00002064) -#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x00002064) +#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x00002074) +#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x00002074) #define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 #define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ @@ -9251,8 +9363,8 @@ //// Register REO_R1_SM_STATES_IX_5 //// -#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002068) -#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002068) +#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002078) +#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002078) #define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 #define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ @@ -9273,8 +9385,8 @@ //// Register REO_R1_SM_STATES_IX_6 //// -#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x0000206c) -#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x0000206c) +#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x0000207c) +#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x0000207c) #define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 #define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ @@ -9295,8 +9407,8 @@ //// Register REO_R1_IDLE_STATES_IX_0 //// -#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002070) -#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002070) +#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002080) +#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002080) #define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff #define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ @@ -9317,8 +9429,8 @@ //// Register REO_R1_INVALID_APB_ACCESS //// -#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x00002074) -#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x00002074) +#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x00002084) +#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x00002084) #define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff #define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ diff --git a/hw/qca6750/v1/rx_mpdu_info.h b/hw/qca6750/v1/rx_mpdu_info.h index 159d09602572..cfeb3f5e2a85 100644 --- a/hw/qca6750/v1/rx_mpdu_info.h +++ b/hw/qca6750/v1/rx_mpdu_info.h @@ -1571,7 +1571,7 @@ mpdu_ht_control_field This LMAC/peer-based routing is not supported in Hastings80 and HastingsPrime. - + */ #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 diff --git a/hw/qca6750/v1/rx_mpdu_start.h b/hw/qca6750/v1/rx_mpdu_start.h index 5a7cca70b880..1ea39b3cdc3e 100644 --- a/hw/qca6750/v1/rx_mpdu_start.h +++ b/hw/qca6750/v1/rx_mpdu_start.h @@ -160,7 +160,7 @@ struct rx_mpdu_info rx_mpdu_info_details This LMAC/peer-based routing is not supported in Hastings80 and HastingsPrime. - + */ #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 diff --git a/hw/qca6750/v1/rxpt_classify_info.h b/hw/qca6750/v1/rxpt_classify_info.h index 362cd300a52f..5755c6c7709f 100644 --- a/hw/qca6750/v1/rxpt_classify_info.h +++ b/hw/qca6750/v1/rxpt_classify_info.h @@ -149,7 +149,7 @@ lmac_peer_id_msb This LMAC/peer-based routing is not supported in Hastings80 and HastingsPrime. - + use_flow_id_toeplitz_clfy @@ -370,7 +370,7 @@ reserved_0b This LMAC/peer-based routing is not supported in Hastings80 and HastingsPrime. - + */ #define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET 0x00000000 #define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB 5 diff --git a/hw/qca6750/v1/tlv_hdr.h b/hw/qca6750/v1/tlv_hdr.h index 0e9f29b705af..921fc2ca92c9 100644 --- a/hw/qca6750/v1/tlv_hdr.h +++ b/hw/qca6750/v1/tlv_hdr.h @@ -17,65 +17,128 @@ */ // + // DO NOT EDIT! This file is automatically generated + // These definitions are tied to a particular hardware layout + + #ifndef _TLV_HDR_H_ + #define _TLV_HDR_H_ + #if !defined(__ASSEMBLER__) + #endif + + struct tlv_usr_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_usrid : 6; + }; + + struct tlv_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_reserved : 6; + }; + + struct tlv_usr_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6; + }; + + struct tlv_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 6; + }; + + struct tlv_usr_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6, + tlv_reserved : 10, + pad_42to64_bit : 22; + }; + + struct tlv_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 16, + pad_42to64_bit : 22; + }; + + struct tlv_usr_c_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_ctag : 3, + tlv_usrid : 6, + tlv_cdata : 32, + pad_42to64_bit : 22; + }; + + #endif + diff --git a/hw/qca6750/v1/wcss_version.h b/hw/qca6750/v1/wcss_version.h index 8352a76daac7..adc55608af21 100644 --- a/hw/qca6750/v1/wcss_version.h +++ b/hw/qca6750/v1/wcss_version.h @@ -16,4 +16,4 @@ * PERFORMANCE OF THIS SOFTWARE. */ -#define WCSS_VERSION 1052 /* E1.5 */ +#define WCSS_VERSION 29 /* E1.5 */