From 2356c682aa28631a0803838c0fcc761b1fd445a3 Mon Sep 17 00:00:00 2001
From: Vivek Kumar <vivekuma@qti.qualcomm.com>
Date: Wed, 14 Oct 2020 11:08:34 +0530
Subject: [PATCH] ARM: dts: msm: Add device-tree entry for IMEM for Direwolf
 SoC

Add device-tree entry for system IMEM to read or write various
system level configurations for Direwolf.

Change-Id: Id16806eb9a7202c72d6980ec9109e3adb3be9e0c
---
 qcom/direwolf.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi
index a75072d5dcde..b779e0798746 100644
--- a/qcom/direwolf.dtsi
+++ b/qcom/direwolf.dtsi
@@ -414,6 +414,49 @@
 		};
 	};
 
+	qcom,msm-imem@146bf000 {
+		compatible = "qcom,msm-imem";
+		reg = <0x146bf000 0x1000>;
+		ranges = <0x0 0x146bf000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mem_dump_table@10 {
+			compatible = "qcom,msm-imem-mem_dump_table";
+			reg = <0x10 0x8>;
+		};
+
+		restart_reason@65c {
+			compatible = "qcom,msm-imem-restart_reason";
+			reg = <0x65c 0x4>;
+		};
+
+		dload_type@1c {
+			compatible = "qcom,msm-imem-dload-type";
+			reg = <0x1c 0x4>;
+		};
+
+		boot_stats@6b0 {
+			compatible = "qcom,msm-imem-boot_stats";
+			reg = <0x6b0 0x20>;
+		};
+
+		kaslr_offset@6d0 {
+			compatible = "qcom,msm-imem-kaslr_offset";
+			reg = <0x6d0 0xc>;
+		};
+
+		pil@94c {
+			compatible = "qcom,msm-imem-pil";
+			reg = <0x94c 0xc8>;
+		};
+
+		diag_dload@c8 {
+			compatible = "qcom,msm-imem-diag-dload";
+			reg = <0xc8 0xc8>;
+		};
+	};
+
 	tlmm: pinctrl@f000000 {
 		compatible = "qcom,direwolf-pinctrl";
 		reg = <0x0F000000 0x1000000>;