mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
Merge branch 'kbuild/rc-fixes' into kbuild/kconfig
We need to revert the temporary hack in 71ebc01, hence the merge.
This commit is contained in:
Michal Marek
commit
239060b93b
8483 changed files with 523357 additions and 574807 deletions
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@ -43,10 +43,6 @@ config GENERIC_CALIBRATE_DELAY
|
|||
bool
|
||||
default y
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||||
|
||||
config GENERIC_TIME
|
||||
bool
|
||||
default y
|
||||
|
||||
config GENERIC_CMOS_UPDATE
|
||||
def_bool y
|
||||
|
||||
|
|
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|||
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|
@ -1,926 +1,76 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.9-rc2
|
||||
# Sat Sep 25 15:38:35 2004
|
||||
#
|
||||
CONFIG_ALPHA=y
|
||||
CONFIG_64BIT=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_GENERIC_ISA_DMA=y
|
||||
# CONFIG_GENERIC_IOMAP is not set
|
||||
|
||||
#
|
||||
# Code maturity level options
|
||||
#
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_CLEAN_COMPILE=y
|
||||
CONFIG_BROKEN_ON_SMP=y
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_SWAP=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
CONFIG_SYSCTL=y
|
||||
# CONFIG_AUDIT is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
# CONFIG_HOTPLUG is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
# CONFIG_EMBEDDED is not set
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
CONFIG_FUTEX=y
|
||||
CONFIG_EPOLL=y
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
CONFIG_IOSCHED_AS=y
|
||||
CONFIG_IOSCHED_DEADLINE=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SHMEM=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
|
||||
#
|
||||
# Loadable module support
|
||||
#
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_MODULE_FORCE_UNLOAD is not set
|
||||
CONFIG_OBSOLETE_MODPARM=y
|
||||
# CONFIG_MODVERSIONS is not set
|
||||
CONFIG_KMOD=y
|
||||
|
||||
#
|
||||
# System setup
|
||||
#
|
||||
CONFIG_ALPHA_GENERIC=y
|
||||
# CONFIG_ALPHA_ALCOR is not set
|
||||
# CONFIG_ALPHA_XL is not set
|
||||
# CONFIG_ALPHA_BOOK1 is not set
|
||||
# CONFIG_ALPHA_AVANTI_CH is not set
|
||||
# CONFIG_ALPHA_CABRIOLET is not set
|
||||
# CONFIG_ALPHA_DP264 is not set
|
||||
# CONFIG_ALPHA_EB164 is not set
|
||||
# CONFIG_ALPHA_EB64P_CH is not set
|
||||
# CONFIG_ALPHA_EB66 is not set
|
||||
# CONFIG_ALPHA_EB66P is not set
|
||||
# CONFIG_ALPHA_EIGER is not set
|
||||
# CONFIG_ALPHA_JENSEN is not set
|
||||
# CONFIG_ALPHA_LX164 is not set
|
||||
# CONFIG_ALPHA_LYNX is not set
|
||||
# CONFIG_ALPHA_MARVEL is not set
|
||||
# CONFIG_ALPHA_MIATA is not set
|
||||
# CONFIG_ALPHA_MIKASA is not set
|
||||
# CONFIG_ALPHA_NAUTILUS is not set
|
||||
# CONFIG_ALPHA_NONAME_CH is not set
|
||||
# CONFIG_ALPHA_NORITAKE is not set
|
||||
# CONFIG_ALPHA_PC164 is not set
|
||||
# CONFIG_ALPHA_P2K is not set
|
||||
# CONFIG_ALPHA_RAWHIDE is not set
|
||||
# CONFIG_ALPHA_RUFFIAN is not set
|
||||
# CONFIG_ALPHA_RX164 is not set
|
||||
# CONFIG_ALPHA_SX164 is not set
|
||||
# CONFIG_ALPHA_SABLE is not set
|
||||
# CONFIG_ALPHA_SHARK is not set
|
||||
# CONFIG_ALPHA_TAKARA is not set
|
||||
# CONFIG_ALPHA_TITAN is not set
|
||||
# CONFIG_ALPHA_WILDFIRE is not set
|
||||
CONFIG_ISA=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_ALPHA_CORE_AGP=y
|
||||
CONFIG_ALPHA_BROKEN_IRQ_MASK=y
|
||||
CONFIG_EISA=y
|
||||
# CONFIG_SMP is not set
|
||||
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
|
||||
CONFIG_VERBOSE_MCHECK=y
|
||||
CONFIG_VERBOSE_MCHECK_ON=1
|
||||
CONFIG_PCI_LEGACY_PROC=y
|
||||
CONFIG_PCI_NAMES=y
|
||||
CONFIG_EISA_PCI_EISA=y
|
||||
CONFIG_EISA_VIRTUAL_ROOT=y
|
||||
CONFIG_EISA_NAMES=y
|
||||
CONFIG_SRM_ENV=m
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_BINFMT_AOUT is not set
|
||||
# CONFIG_BINFMT_EM86 is not set
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_DEBUG_DRIVER is not set
|
||||
|
||||
#
|
||||
# Memory Technology Devices (MTD)
|
||||
#
|
||||
# CONFIG_MTD is not set
|
||||
|
||||
#
|
||||
# Parallel port support
|
||||
#
|
||||
# CONFIG_PARPORT is not set
|
||||
|
||||
#
|
||||
# Plug and Play support
|
||||
#
|
||||
CONFIG_PNP=y
|
||||
# CONFIG_PNP_DEBUG is not set
|
||||
|
||||
#
|
||||
# Protocols
|
||||
#
|
||||
CONFIG_ISAPNP=y
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||||
|
||||
#
|
||||
# Block devices
|
||||
#
|
||||
CONFIG_BLK_DEV_FD=y
|
||||
# CONFIG_BLK_DEV_XD is not set
|
||||
# CONFIG_BLK_CPQ_DA is not set
|
||||
# CONFIG_BLK_CPQ_CISS_DA is not set
|
||||
# CONFIG_BLK_DEV_DAC960 is not set
|
||||
# CONFIG_BLK_DEV_UMEM is not set
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_SX8 is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
|
||||
#
|
||||
# ATA/ATAPI/MFM/RLL support
|
||||
#
|
||||
CONFIG_IDE=y
|
||||
CONFIG_IDE_MAX_HWIFS=4
|
||||
CONFIG_BLK_DEV_IDE=y
|
||||
|
||||
#
|
||||
# Please see Documentation/ide.txt for help/info on IDE drives
|
||||
#
|
||||
# CONFIG_BLK_DEV_IDE_SATA is not set
|
||||
CONFIG_BLK_DEV_IDEDISK=y
|
||||
CONFIG_IDEDISK_MULTI_MODE=y
|
||||
CONFIG_BLK_DEV_IDECD=y
|
||||
# CONFIG_BLK_DEV_IDETAPE is not set
|
||||
# CONFIG_BLK_DEV_IDEFLOPPY is not set
|
||||
# CONFIG_BLK_DEV_IDESCSI is not set
|
||||
# CONFIG_IDE_TASK_IOCTL is not set
|
||||
# CONFIG_IDE_TASKFILE_IO is not set
|
||||
|
||||
#
|
||||
# IDE chipset support/bugfixes
|
||||
#
|
||||
CONFIG_IDE_GENERIC=y
|
||||
# CONFIG_BLK_DEV_IDEPNP is not set
|
||||
CONFIG_BLK_DEV_IDEPCI=y
|
||||
# CONFIG_IDEPCI_SHARE_IRQ is not set
|
||||
# CONFIG_BLK_DEV_OFFBOARD is not set
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
# CONFIG_BLK_DEV_OPTI621 is not set
|
||||
CONFIG_BLK_DEV_IDEDMA_PCI=y
|
||||
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
|
||||
CONFIG_IDEDMA_PCI_AUTO=y
|
||||
# CONFIG_IDEDMA_ONLYDISK is not set
|
||||
# CONFIG_BLK_DEV_AEC62XX is not set
|
||||
CONFIG_BLK_DEV_ALI15X3=y
|
||||
# CONFIG_WDC_ALI15X3 is not set
|
||||
# CONFIG_BLK_DEV_AMD74XX is not set
|
||||
CONFIG_BLK_DEV_CMD64X=y
|
||||
# CONFIG_BLK_DEV_TRIFLEX is not set
|
||||
CONFIG_BLK_DEV_CY82C693=y
|
||||
# CONFIG_BLK_DEV_CS5520 is not set
|
||||
# CONFIG_BLK_DEV_CS5530 is not set
|
||||
# CONFIG_BLK_DEV_HPT34X is not set
|
||||
# CONFIG_BLK_DEV_HPT366 is not set
|
||||
# CONFIG_BLK_DEV_SC1200 is not set
|
||||
# CONFIG_BLK_DEV_PIIX is not set
|
||||
# CONFIG_BLK_DEV_NS87415 is not set
|
||||
# CONFIG_BLK_DEV_PDC202XX_OLD is not set
|
||||
# CONFIG_BLK_DEV_PDC202XX_NEW is not set
|
||||
# CONFIG_BLK_DEV_SVWKS is not set
|
||||
# CONFIG_BLK_DEV_SIIMAGE is not set
|
||||
# CONFIG_BLK_DEV_SLC90E66 is not set
|
||||
# CONFIG_BLK_DEV_TRM290 is not set
|
||||
# CONFIG_BLK_DEV_VIA82CXXX is not set
|
||||
# CONFIG_IDE_ARM is not set
|
||||
# CONFIG_IDE_CHIPSETS is not set
|
||||
CONFIG_BLK_DEV_IDEDMA=y
|
||||
# CONFIG_IDEDMA_IVB is not set
|
||||
CONFIG_IDEDMA_AUTO=y
|
||||
# CONFIG_BLK_DEV_HD is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_PROC_FS=y
|
||||
|
||||
#
|
||||
# SCSI support type (disk, tape, CD-ROM)
|
||||
#
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_CHR_DEV_ST is not set
|
||||
# CONFIG_CHR_DEV_OSST is not set
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_BLK_DEV_SR_VENDOR=y
|
||||
# CONFIG_CHR_DEV_SG is not set
|
||||
|
||||
#
|
||||
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
|
||||
#
|
||||
# CONFIG_SCSI_MULTI_LUN is not set
|
||||
# CONFIG_SCSI_CONSTANTS is not set
|
||||
# CONFIG_SCSI_LOGGING is not set
|
||||
|
||||
#
|
||||
# SCSI Transport Attributes
|
||||
#
|
||||
# CONFIG_SCSI_SPI_ATTRS is not set
|
||||
# CONFIG_SCSI_FC_ATTRS is not set
|
||||
|
||||
#
|
||||
# SCSI low-level drivers
|
||||
#
|
||||
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
|
||||
# CONFIG_SCSI_3W_9XXX is not set
|
||||
# CONFIG_SCSI_7000FASST is not set
|
||||
# CONFIG_SCSI_ACARD is not set
|
||||
# CONFIG_SCSI_AHA1542 is not set
|
||||
# CONFIG_SCSI_AHA1740 is not set
|
||||
# CONFIG_SCSI_AACRAID is not set
|
||||
CONFIG_SCSI_AIC7XXX=m
|
||||
CONFIG_AIC7XXX_CMDS_PER_DEVICE=253
|
||||
CONFIG_AIC7XXX_RESET_DELAY_MS=5000
|
||||
# CONFIG_AIC7XXX_PROBE_EISA_VL is not set
|
||||
# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
|
||||
CONFIG_AIC7XXX_DEBUG_MASK=0
|
||||
CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
|
||||
# CONFIG_SCSI_AIC7XXX_OLD is not set
|
||||
# CONFIG_SCSI_AIC79XX is not set
|
||||
# CONFIG_SCSI_IN2000 is not set
|
||||
# CONFIG_MEGARAID_NEWGEN is not set
|
||||
# CONFIG_MEGARAID_LEGACY is not set
|
||||
# CONFIG_SCSI_SATA is not set
|
||||
# CONFIG_SCSI_BUSLOGIC is not set
|
||||
# CONFIG_SCSI_DMX3191D is not set
|
||||
# CONFIG_SCSI_DTC3280 is not set
|
||||
# CONFIG_SCSI_EATA is not set
|
||||
# CONFIG_SCSI_EATA_PIO is not set
|
||||
# CONFIG_SCSI_FUTURE_DOMAIN is not set
|
||||
# CONFIG_SCSI_GDTH is not set
|
||||
# CONFIG_SCSI_GENERIC_NCR5380 is not set
|
||||
# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
|
||||
# CONFIG_SCSI_IPS is not set
|
||||
# CONFIG_SCSI_INIA100 is not set
|
||||
# CONFIG_SCSI_NCR53C406A is not set
|
||||
# CONFIG_SCSI_SYM53C8XX_2 is not set
|
||||
# CONFIG_SCSI_IPR is not set
|
||||
# CONFIG_SCSI_PAS16 is not set
|
||||
# CONFIG_SCSI_PSI240I is not set
|
||||
# CONFIG_SCSI_QLOGIC_FAS is not set
|
||||
# CONFIG_SCSI_QLOGIC_ISP is not set
|
||||
# CONFIG_SCSI_QLOGIC_FC is not set
|
||||
# CONFIG_SCSI_QLOGIC_1280 is not set
|
||||
CONFIG_SCSI_QLA2XXX=y
|
||||
# CONFIG_SCSI_QLA21XX is not set
|
||||
# CONFIG_SCSI_QLA22XX is not set
|
||||
# CONFIG_SCSI_QLA2300 is not set
|
||||
# CONFIG_SCSI_QLA2322 is not set
|
||||
# CONFIG_SCSI_QLA6312 is not set
|
||||
# CONFIG_SCSI_QLA6322 is not set
|
||||
# CONFIG_SCSI_SIM710 is not set
|
||||
# CONFIG_SCSI_SYM53C416 is not set
|
||||
# CONFIG_SCSI_DC395x is not set
|
||||
# CONFIG_SCSI_DC390T is not set
|
||||
# CONFIG_SCSI_T128 is not set
|
||||
# CONFIG_SCSI_U14_34F is not set
|
||||
# CONFIG_SCSI_DEBUG is not set
|
||||
|
||||
#
|
||||
# Old CD-ROM drivers (not SCSI, not IDE)
|
||||
#
|
||||
# CONFIG_CD_NO_IDESCSI is not set
|
||||
|
||||
#
|
||||
# Multi-device support (RAID and LVM)
|
||||
#
|
||||
# CONFIG_MD is not set
|
||||
|
||||
#
|
||||
# Fusion MPT device support
|
||||
#
|
||||
# CONFIG_FUSION is not set
|
||||
|
||||
#
|
||||
# IEEE 1394 (FireWire) support
|
||||
#
|
||||
# CONFIG_IEEE1394 is not set
|
||||
|
||||
#
|
||||
# I2O device support
|
||||
#
|
||||
# CONFIG_I2O is not set
|
||||
|
||||
#
|
||||
# Networking support
|
||||
#
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_NETLINK_DEV=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
# CONFIG_IP_PNP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_IP_MROUTE is not set
|
||||
# CONFIG_ARPD is not set
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
|
||||
#
|
||||
# IP: Virtual Server Configuration
|
||||
#
|
||||
# CONFIG_IP_VS is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_NETFILTER_DEBUG is not set
|
||||
|
||||
#
|
||||
# IP: Netfilter Configuration
|
||||
#
|
||||
CONFIG_IP_NF_CONNTRACK=m
|
||||
# CONFIG_IP_NF_CT_ACCT is not set
|
||||
# CONFIG_IP_NF_CT_PROTO_SCTP is not set
|
||||
CONFIG_IP_NF_FTP=m
|
||||
CONFIG_IP_NF_IRC=m
|
||||
# CONFIG_IP_NF_TFTP is not set
|
||||
# CONFIG_IP_NF_AMANDA is not set
|
||||
CONFIG_IP_NF_QUEUE=m
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
# CONFIG_IP_NF_MATCH_LIMIT is not set
|
||||
# CONFIG_IP_NF_MATCH_IPRANGE is not set
|
||||
# CONFIG_IP_NF_MATCH_MAC is not set
|
||||
# CONFIG_IP_NF_MATCH_PKTTYPE is not set
|
||||
# CONFIG_IP_NF_MATCH_MARK is not set
|
||||
# CONFIG_IP_NF_MATCH_MULTIPORT is not set
|
||||
# CONFIG_IP_NF_MATCH_TOS is not set
|
||||
# CONFIG_IP_NF_MATCH_RECENT is not set
|
||||
# CONFIG_IP_NF_MATCH_ECN is not set
|
||||
# CONFIG_IP_NF_MATCH_DSCP is not set
|
||||
# CONFIG_IP_NF_MATCH_AH_ESP is not set
|
||||
# CONFIG_IP_NF_MATCH_LENGTH is not set
|
||||
# CONFIG_IP_NF_MATCH_TTL is not set
|
||||
# CONFIG_IP_NF_MATCH_TCPMSS is not set
|
||||
# CONFIG_IP_NF_MATCH_HELPER is not set
|
||||
# CONFIG_IP_NF_MATCH_STATE is not set
|
||||
# CONFIG_IP_NF_MATCH_CONNTRACK is not set
|
||||
# CONFIG_IP_NF_MATCH_OWNER is not set
|
||||
# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
|
||||
# CONFIG_IP_NF_MATCH_REALM is not set
|
||||
# CONFIG_IP_NF_MATCH_SCTP is not set
|
||||
# CONFIG_IP_NF_MATCH_COMMENT is not set
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
# CONFIG_IP_NF_TARGET_REJECT is not set
|
||||
# CONFIG_IP_NF_TARGET_LOG is not set
|
||||
# CONFIG_IP_NF_TARGET_ULOG is not set
|
||||
# CONFIG_IP_NF_TARGET_TCPMSS is not set
|
||||
CONFIG_IP_NF_NAT=m
|
||||
CONFIG_IP_NF_NAT_NEEDED=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=m
|
||||
# CONFIG_IP_NF_TARGET_REDIRECT is not set
|
||||
# CONFIG_IP_NF_TARGET_NETMAP is not set
|
||||
# CONFIG_IP_NF_TARGET_SAME is not set
|
||||
# CONFIG_IP_NF_NAT_SNMP_BASIC is not set
|
||||
CONFIG_IP_NF_NAT_IRC=m
|
||||
CONFIG_IP_NF_NAT_FTP=m
|
||||
# CONFIG_IP_NF_MANGLE is not set
|
||||
# CONFIG_IP_NF_RAW is not set
|
||||
# CONFIG_IP_NF_ARPTABLES is not set
|
||||
CONFIG_IP_NF_COMPAT_IPCHAINS=y
|
||||
CONFIG_XFRM=y
|
||||
CONFIG_XFRM_USER=m
|
||||
|
||||
#
|
||||
# SCTP Configuration (EXPERIMENTAL)
|
||||
#
|
||||
# CONFIG_IP_SCTP is not set
|
||||
# CONFIG_ATM is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
CONFIG_VLAN_8021Q=m
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_X25 is not set
|
||||
# CONFIG_LAPB is not set
|
||||
# CONFIG_NET_DIVERT is not set
|
||||
# CONFIG_ECONET is not set
|
||||
# CONFIG_WAN_ROUTER is not set
|
||||
# CONFIG_NET_HW_FLOWCONTROL is not set
|
||||
|
||||
#
|
||||
# QoS and/or fair queueing
|
||||
#
|
||||
# CONFIG_NET_SCHED is not set
|
||||
# CONFIG_NET_CLS_ROUTE is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
#
|
||||
# CONFIG_NET_PKTGEN is not set
|
||||
# CONFIG_NETPOLL is not set
|
||||
# CONFIG_NET_POLL_CONTROLLER is not set
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
CONFIG_PNP=y
|
||||
CONFIG_ISAPNP=y
|
||||
CONFIG_BLK_DEV_FD=y
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECD=y
|
||||
CONFIG_IDE_GENERIC=y
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_ALI15X3=y
|
||||
CONFIG_BLK_DEV_CMD64X=y
|
||||
CONFIG_BLK_DEV_CY82C693=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_BLK_DEV_SR_VENDOR=y
|
||||
CONFIG_SCSI_AIC7XXX=m
|
||||
CONFIG_AIC7XXX_CMDS_PER_DEVICE=253
|
||||
# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=m
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
# CONFIG_TUN is not set
|
||||
# CONFIG_ETHERTAP is not set
|
||||
# CONFIG_NET_SB1000 is not set
|
||||
|
||||
#
|
||||
# ARCnet devices
|
||||
#
|
||||
# CONFIG_ARCNET is not set
|
||||
|
||||
#
|
||||
# Ethernet (10 or 100Mbit)
|
||||
#
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
# CONFIG_HAPPYMEAL is not set
|
||||
# CONFIG_SUNGEM is not set
|
||||
CONFIG_NET_VENDOR_3COM=y
|
||||
# CONFIG_EL1 is not set
|
||||
# CONFIG_EL2 is not set
|
||||
# CONFIG_ELPLUS is not set
|
||||
# CONFIG_EL16 is not set
|
||||
# CONFIG_EL3 is not set
|
||||
# CONFIG_3C515 is not set
|
||||
CONFIG_VORTEX=y
|
||||
# CONFIG_TYPHOON is not set
|
||||
# CONFIG_LANCE is not set
|
||||
# CONFIG_NET_VENDOR_SMC is not set
|
||||
# CONFIG_NET_VENDOR_RACAL is not set
|
||||
|
||||
#
|
||||
# Tulip family network device support
|
||||
#
|
||||
CONFIG_NET_TULIP=y
|
||||
CONFIG_DE2104X=m
|
||||
CONFIG_TULIP=y
|
||||
# CONFIG_TULIP_MWI is not set
|
||||
CONFIG_TULIP_MMIO=y
|
||||
# CONFIG_TULIP_NAPI is not set
|
||||
# CONFIG_DE4X5 is not set
|
||||
# CONFIG_WINBOND_840 is not set
|
||||
# CONFIG_DM9102 is not set
|
||||
# CONFIG_AT1700 is not set
|
||||
# CONFIG_DEPCA is not set
|
||||
# CONFIG_HP100 is not set
|
||||
# CONFIG_NET_ISA is not set
|
||||
CONFIG_NET_PCI=y
|
||||
# CONFIG_PCNET32 is not set
|
||||
# CONFIG_AMD8111_ETH is not set
|
||||
# CONFIG_ADAPTEC_STARFIRE is not set
|
||||
# CONFIG_AC3200 is not set
|
||||
# CONFIG_APRICOT is not set
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_FORCEDETH is not set
|
||||
# CONFIG_CS89x0 is not set
|
||||
# CONFIG_DGRS is not set
|
||||
# CONFIG_EEPRO100 is not set
|
||||
# CONFIG_E100 is not set
|
||||
# CONFIG_LNE390 is not set
|
||||
# CONFIG_FEALNX is not set
|
||||
# CONFIG_NATSEMI is not set
|
||||
# CONFIG_NE2K_PCI is not set
|
||||
# CONFIG_NE3210 is not set
|
||||
# CONFIG_ES3210 is not set
|
||||
# CONFIG_8139CP is not set
|
||||
# CONFIG_8139TOO is not set
|
||||
# CONFIG_SIS900 is not set
|
||||
# CONFIG_EPIC100 is not set
|
||||
# CONFIG_SUNDANCE is not set
|
||||
# CONFIG_VIA_RHINE is not set
|
||||
# CONFIG_VIA_VELOCITY is not set
|
||||
# CONFIG_NET_POCKET is not set
|
||||
|
||||
#
|
||||
# Ethernet (1000 Mbit)
|
||||
#
|
||||
# CONFIG_ACENIC is not set
|
||||
# CONFIG_DL2K is not set
|
||||
# CONFIG_E1000 is not set
|
||||
# CONFIG_NS83820 is not set
|
||||
# CONFIG_HAMACHI is not set
|
||||
CONFIG_YELLOWFIN=y
|
||||
# CONFIG_R8169 is not set
|
||||
# CONFIG_SK98LIN is not set
|
||||
# CONFIG_TIGON3 is not set
|
||||
|
||||
#
|
||||
# Ethernet (10000 Mbit)
|
||||
#
|
||||
# CONFIG_IXGB is not set
|
||||
# CONFIG_S2IO is not set
|
||||
|
||||
#
|
||||
# Token Ring devices
|
||||
#
|
||||
# CONFIG_TR is not set
|
||||
|
||||
#
|
||||
# Wireless LAN (non-hamradio)
|
||||
#
|
||||
# CONFIG_NET_RADIO is not set
|
||||
|
||||
#
|
||||
# Wan interfaces
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_FDDI is not set
|
||||
# CONFIG_HIPPI is not set
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
# CONFIG_NET_FC is not set
|
||||
# CONFIG_SHAPER is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
|
||||
#
|
||||
# ISDN subsystem
|
||||
#
|
||||
# CONFIG_ISDN is not set
|
||||
|
||||
#
|
||||
# Telephony Support
|
||||
#
|
||||
# CONFIG_PHONE is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_TSDEV is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input I/O drivers
|
||||
#
|
||||
# CONFIG_GAMEPORT is not set
|
||||
CONFIG_SOUND_GAMEPORT=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_I8042=y
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
# CONFIG_SERIO_CT82C710 is not set
|
||||
# CONFIG_SERIO_PCIPS2 is not set
|
||||
# CONFIG_SERIO_RAW is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_KEYBOARD_ATKBD=y
|
||||
# CONFIG_KEYBOARD_SUNKBD is not set
|
||||
# CONFIG_KEYBOARD_LKKBD is not set
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_NEWTON is not set
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_MOUSE_PS2=y
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
# CONFIG_MOUSE_INPORT is not set
|
||||
# CONFIG_MOUSE_LOGIBM is not set
|
||||
# CONFIG_MOUSE_PC110PAD is not set
|
||||
# CONFIG_MOUSE_VSXXXAA is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
# CONFIG_SERIAL_8250_EXTENDED is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
|
||||
|
||||
#
|
||||
# IPMI
|
||||
#
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
|
||||
#
|
||||
# Watchdog Cards
|
||||
#
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_RTC=y
|
||||
# CONFIG_DTLK is not set
|
||||
# CONFIG_R3964 is not set
|
||||
# CONFIG_APPLICOM is not set
|
||||
|
||||
#
|
||||
# Ftape, the floppy tape device driver
|
||||
#
|
||||
# CONFIG_FTAPE is not set
|
||||
# CONFIG_AGP is not set
|
||||
# CONFIG_DRM is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
# CONFIG_I2C is not set
|
||||
|
||||
#
|
||||
# Dallas's 1-wire bus
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
|
||||
#
|
||||
# Digital Video Broadcasting Devices
|
||||
#
|
||||
# CONFIG_DVB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_FB is not set
|
||||
|
||||
#
|
||||
# Console display driver support
|
||||
#
|
||||
CONFIG_VGA_CONSOLE=y
|
||||
# CONFIG_MDA_CONSOLE is not set
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
# CONFIG_USB is not set
|
||||
|
||||
#
|
||||
# USB Gadget Support
|
||||
#
|
||||
# CONFIG_USB_GADGET is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
CONFIG_EXT2_FS=y
|
||||
# CONFIG_EXT2_FS_XATTR is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_JBD is not set
|
||||
CONFIG_REISERFS_FS=m
|
||||
# CONFIG_REISERFS_CHECK is not set
|
||||
# CONFIG_REISERFS_PROC_INFO is not set
|
||||
# CONFIG_REISERFS_FS_XATTR is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_QUOTA is not set
|
||||
CONFIG_AUTOFS_FS=m
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
CONFIG_ISO9660_FS=y
|
||||
# CONFIG_JOLIET is not set
|
||||
# CONFIG_ZISOFS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
CONFIG_FAT_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_FAT_DEFAULT_CODEPAGE=437
|
||||
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_SYSFS=y
|
||||
# CONFIG_DEVFS_FS is not set
|
||||
# CONFIG_DEVPTS_FS_XATTR is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
CONFIG_RAMFS=y
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
|
||||
#
|
||||
# Network File Systems
|
||||
#
|
||||
CONFIG_NFS_FS=m
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V4 is not set
|
||||
# CONFIG_NFS_DIRECTIO is not set
|
||||
CONFIG_NFSD=m
|
||||
CONFIG_NFSD_V3=y
|
||||
# CONFIG_NFSD_V4 is not set
|
||||
CONFIG_NFSD_TCP=y
|
||||
CONFIG_LOCKD=m
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_EXPORTFS=m
|
||||
CONFIG_SUNRPC=m
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_OSF_PARTITION=y
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
|
||||
#
|
||||
# Native Language Support
|
||||
#
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_DEFAULT="iso8859-1"
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
# CONFIG_NLS_CODEPAGE_737 is not set
|
||||
# CONFIG_NLS_CODEPAGE_775 is not set
|
||||
# CONFIG_NLS_CODEPAGE_850 is not set
|
||||
# CONFIG_NLS_CODEPAGE_852 is not set
|
||||
# CONFIG_NLS_CODEPAGE_855 is not set
|
||||
# CONFIG_NLS_CODEPAGE_857 is not set
|
||||
# CONFIG_NLS_CODEPAGE_860 is not set
|
||||
# CONFIG_NLS_CODEPAGE_861 is not set
|
||||
# CONFIG_NLS_CODEPAGE_862 is not set
|
||||
# CONFIG_NLS_CODEPAGE_863 is not set
|
||||
# CONFIG_NLS_CODEPAGE_864 is not set
|
||||
# CONFIG_NLS_CODEPAGE_865 is not set
|
||||
# CONFIG_NLS_CODEPAGE_866 is not set
|
||||
# CONFIG_NLS_CODEPAGE_869 is not set
|
||||
# CONFIG_NLS_CODEPAGE_936 is not set
|
||||
# CONFIG_NLS_CODEPAGE_950 is not set
|
||||
# CONFIG_NLS_CODEPAGE_932 is not set
|
||||
# CONFIG_NLS_CODEPAGE_949 is not set
|
||||
# CONFIG_NLS_CODEPAGE_874 is not set
|
||||
# CONFIG_NLS_ISO8859_8 is not set
|
||||
# CONFIG_NLS_CODEPAGE_1250 is not set
|
||||
# CONFIG_NLS_CODEPAGE_1251 is not set
|
||||
# CONFIG_NLS_ASCII is not set
|
||||
# CONFIG_NLS_ISO8859_1 is not set
|
||||
# CONFIG_NLS_ISO8859_2 is not set
|
||||
# CONFIG_NLS_ISO8859_3 is not set
|
||||
# CONFIG_NLS_ISO8859_4 is not set
|
||||
# CONFIG_NLS_ISO8859_5 is not set
|
||||
# CONFIG_NLS_ISO8859_6 is not set
|
||||
# CONFIG_NLS_ISO8859_7 is not set
|
||||
# CONFIG_NLS_ISO8859_9 is not set
|
||||
# CONFIG_NLS_ISO8859_13 is not set
|
||||
# CONFIG_NLS_ISO8859_14 is not set
|
||||
# CONFIG_NLS_ISO8859_15 is not set
|
||||
# CONFIG_NLS_KOI8_R is not set
|
||||
# CONFIG_NLS_KOI8_U is not set
|
||||
# CONFIG_NLS_UTF8 is not set
|
||||
|
||||
#
|
||||
# Profiling support
|
||||
#
|
||||
# CONFIG_PROFILING is not set
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_DEBUG_SLAB is not set
|
||||
# CONFIG_DEBUG_SPINLOCK is not set
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
# CONFIG_DEBUG_SEMAPHORE is not set
|
||||
CONFIG_ALPHA_LEGACY_START_ADDRESS=y
|
||||
CONFIG_MATHEMU=y
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
# CONFIG_CRYPTO_NULL is not set
|
||||
# CONFIG_CRYPTO_MD4 is not set
|
||||
CONFIG_CRYPTO_MD5=m
|
||||
CONFIG_CRYPTO_SHA1=m
|
||||
# CONFIG_CRYPTO_SHA256 is not set
|
||||
# CONFIG_CRYPTO_SHA512 is not set
|
||||
# CONFIG_CRYPTO_WHIRLPOOL is not set
|
||||
CONFIG_CRYPTO_DES=m
|
||||
# CONFIG_CRYPTO_BLOWFISH is not set
|
||||
# CONFIG_CRYPTO_TWOFISH is not set
|
||||
# CONFIG_CRYPTO_SERPENT is not set
|
||||
# CONFIG_CRYPTO_AES is not set
|
||||
# CONFIG_CRYPTO_CAST5 is not set
|
||||
# CONFIG_CRYPTO_CAST6 is not set
|
||||
# CONFIG_CRYPTO_TEA is not set
|
||||
# CONFIG_CRYPTO_ARC4 is not set
|
||||
# CONFIG_CRYPTO_KHAZAD is not set
|
||||
# CONFIG_CRYPTO_DEFLATE is not set
|
||||
# CONFIG_CRYPTO_MICHAEL_MIC is not set
|
||||
# CONFIG_CRYPTO_CRC32C is not set
|
||||
# CONFIG_CRYPTO_TEST is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
|
|
|
|||
|
|
@ -1,11 +1,10 @@
|
|||
include include/asm-generic/Kbuild.asm
|
||||
|
||||
header-y += compiler.h
|
||||
header-y += console.h
|
||||
header-y += fpu.h
|
||||
header-y += gentrap.h
|
||||
header-y += regdef.h
|
||||
header-y += pal.h
|
||||
header-y += reg.h
|
||||
|
||||
unifdef-y += console.h
|
||||
unifdef-y += fpu.h
|
||||
unifdef-y += sysinfo.h
|
||||
unifdef-y += compiler.h
|
||||
header-y += regdef.h
|
||||
header-y += sysinfo.h
|
||||
|
|
|
|||
|
|
@ -41,9 +41,7 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
|
|||
|
||||
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
|
||||
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
|
||||
#define dma_is_consistent(d, h) (1)
|
||||
|
||||
#define dma_cache_sync(dev, va, size, dir) ((void)0)
|
||||
#define dma_get_cache_alignment() L1_CACHE_BYTES
|
||||
|
||||
#endif /* _ALPHA_DMA_MAPPING_H */
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
|
||||
|
||||
extern volatile unsigned long irq_err_count;
|
||||
DECLARE_PER_CPU(unsigned long, irq_pmi_count);
|
||||
|
||||
#ifdef CONFIG_ALPHA_GENERIC
|
||||
#define ACTUAL_NR_IRQS alpha_mv.nr_irqs
|
||||
|
|
|
|||
|
|
@ -80,6 +80,7 @@
|
|||
# define TIOCPKT_START 8
|
||||
# define TIOCPKT_NOSTOP 16
|
||||
# define TIOCPKT_DOSTOP 32
|
||||
# define TIOCPKT_IOCTL 64
|
||||
|
||||
|
||||
#define TIOCNOTTY 0x5422
|
||||
|
|
@ -91,6 +92,7 @@
|
|||
#define TIOCGSID 0x5429 /* Return the session ID of FD */
|
||||
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
|
||||
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
|
||||
#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */
|
||||
|
||||
#define TIOCSERCONFIG 0x5453
|
||||
#define TIOCSERGWILD 0x5454
|
||||
|
|
@ -106,7 +108,5 @@
|
|||
|
||||
#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
|
||||
#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
|
||||
#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */
|
||||
#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */
|
||||
|
||||
#endif /* _ASM_ALPHA_IOCTLS_H */
|
||||
|
|
|
|||
1
arch/alpha/include/asm/local64.h
Normal file
1
arch/alpha/include/asm/local64.h
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include <asm-generic/local64.h>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
/* $Id: md.h,v 1.1 1997/12/15 15:11:48 jj Exp $
|
||||
* md.h: High speed xor_block operation for RAID4/5
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MD_H
|
||||
#define __ASM_MD_H
|
||||
|
||||
/* #define HAVE_ARCH_XORBLOCK */
|
||||
|
||||
#define MD_XORBLOCK_ALIGNMENT sizeof(long)
|
||||
|
||||
#endif /* __ASM_MD_H */
|
||||
|
|
@ -2,8 +2,14 @@
|
|||
#define __ASM_ALPHA_PERF_EVENT_H
|
||||
|
||||
/* Alpha only supports software events through this interface. */
|
||||
static inline void set_perf_event_pending(void) { }
|
||||
extern void set_perf_event_pending(void);
|
||||
|
||||
#define PERF_EVENT_INDEX_OFFSET 0
|
||||
|
||||
#ifdef CONFIG_PERF_EVENTS
|
||||
extern void init_hw_perf_events(void);
|
||||
#else
|
||||
static inline void init_hw_perf_events(void) { }
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ALPHA_PERF_EVENT_H */
|
||||
|
|
|
|||
|
|
@ -3,6 +3,4 @@
|
|||
|
||||
#include <asm-generic/scatterlist.h>
|
||||
|
||||
#define ISA_DMA_THRESHOLD (~0UL)
|
||||
|
||||
#endif /* !(_ALPHA_SCATTERLIST_H) */
|
||||
|
|
|
|||
|
|
@ -180,6 +180,7 @@ struct ktermios {
|
|||
#define FLUSHO 0x00800000
|
||||
#define PENDIN 0x20000000
|
||||
#define IEXTEN 0x00000400
|
||||
#define EXTPROC 0x10000000
|
||||
|
||||
/* Values for the ACTION argument to `tcflow'. */
|
||||
#define TCOOFF 0
|
||||
|
|
|
|||
93
arch/alpha/include/asm/wrperfmon.h
Normal file
93
arch/alpha/include/asm/wrperfmon.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Definitions for use with the Alpha wrperfmon PAL call.
|
||||
*/
|
||||
|
||||
#ifndef __ALPHA_WRPERFMON_H
|
||||
#define __ALPHA_WRPERFMON_H
|
||||
|
||||
/* Following commands are implemented on all CPUs */
|
||||
#define PERFMON_CMD_DISABLE 0
|
||||
#define PERFMON_CMD_ENABLE 1
|
||||
#define PERFMON_CMD_DESIRED_EVENTS 2
|
||||
#define PERFMON_CMD_LOGGING_OPTIONS 3
|
||||
/* Following commands on EV5/EV56/PCA56 only */
|
||||
#define PERFMON_CMD_INT_FREQ 4
|
||||
#define PERFMON_CMD_ENABLE_CLEAR 7
|
||||
/* Following commands are on EV5 and better CPUs */
|
||||
#define PERFMON_CMD_READ 5
|
||||
#define PERFMON_CMD_WRITE 6
|
||||
/* Following command are on EV6 and better CPUs */
|
||||
#define PERFMON_CMD_ENABLE_WRITE 7
|
||||
/* Following command are on EV67 and better CPUs */
|
||||
#define PERFMON_CMD_I_STAT 8
|
||||
#define PERFMON_CMD_PMPC 9
|
||||
|
||||
|
||||
/* EV5/EV56/PCA56 Counters */
|
||||
#define EV5_PCTR_0 (1UL<<0)
|
||||
#define EV5_PCTR_1 (1UL<<1)
|
||||
#define EV5_PCTR_2 (1UL<<2)
|
||||
|
||||
#define EV5_PCTR_0_COUNT_SHIFT 48
|
||||
#define EV5_PCTR_1_COUNT_SHIFT 32
|
||||
#define EV5_PCTR_2_COUNT_SHIFT 16
|
||||
|
||||
#define EV5_PCTR_0_COUNT_MASK 0xffffUL
|
||||
#define EV5_PCTR_1_COUNT_MASK 0xffffUL
|
||||
#define EV5_PCTR_2_COUNT_MASK 0x3fffUL
|
||||
|
||||
/* EV6 Counters */
|
||||
#define EV6_PCTR_0 (1UL<<0)
|
||||
#define EV6_PCTR_1 (1UL<<1)
|
||||
|
||||
#define EV6_PCTR_0_COUNT_SHIFT 28
|
||||
#define EV6_PCTR_1_COUNT_SHIFT 6
|
||||
|
||||
#define EV6_PCTR_0_COUNT_MASK 0xfffffUL
|
||||
#define EV6_PCTR_1_COUNT_MASK 0xfffffUL
|
||||
|
||||
/* EV67 (and subsequent) counters */
|
||||
#define EV67_PCTR_0 (1UL<<0)
|
||||
#define EV67_PCTR_1 (1UL<<1)
|
||||
|
||||
#define EV67_PCTR_0_COUNT_SHIFT 28
|
||||
#define EV67_PCTR_1_COUNT_SHIFT 6
|
||||
|
||||
#define EV67_PCTR_0_COUNT_MASK 0xfffffUL
|
||||
#define EV67_PCTR_1_COUNT_MASK 0xfffffUL
|
||||
|
||||
|
||||
/*
|
||||
* The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint
|
||||
* in Table E-23 regarding the bits that set the event PCTR 1 counts.
|
||||
* Hopefully what we have here is correct.
|
||||
*/
|
||||
#define EV6_PCTR_0_EVENT_MASK 0x10UL
|
||||
#define EV6_PCTR_1_EVENT_MASK 0x0fUL
|
||||
|
||||
/* EV6 Events */
|
||||
#define EV6_PCTR_0_CYCLES (0UL << 4)
|
||||
#define EV6_PCTR_0_INSTRUCTIONS (1UL << 4)
|
||||
|
||||
#define EV6_PCTR_1_CYCLES 0
|
||||
#define EV6_PCTR_1_BRANCHES 1
|
||||
#define EV6_PCTR_1_BRANCH_MISPREDICTS 2
|
||||
#define EV6_PCTR_1_DTB_SINGLE_MISSES 3
|
||||
#define EV6_PCTR_1_DTB_DOUBLE_MISSES 4
|
||||
#define EV6_PCTR_1_ITB_MISSES 5
|
||||
#define EV6_PCTR_1_UNALIGNED_TRAPS 6
|
||||
#define EV6_PCTR_1_REPLY_TRAPS 7
|
||||
|
||||
/* From the Alpha Architecture Reference Manual, 4th edn., 2002 */
|
||||
#define EV67_PCTR_MODE_MASK 0x10UL
|
||||
#define EV67_PCTR_EVENT_MASK 0x0CUL
|
||||
|
||||
#define EV67_PCTR_MODE_PROFILEME (1UL<<4)
|
||||
#define EV67_PCTR_MODE_AGGREGATE (0UL<<4)
|
||||
|
||||
#define EV67_PCTR_INSTR_CYCLES (0UL<<2)
|
||||
#define EV67_PCTR_CYCLES_UNDEF (1UL<<2)
|
||||
#define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)
|
||||
#define EV67_PCTR_CYCLES_MBOX (3UL<<2)
|
||||
|
||||
#endif
|
||||
|
|
@ -15,6 +15,7 @@ obj-$(CONFIG_SMP) += smp.o
|
|||
obj-$(CONFIG_PCI) += pci.o pci_iommu.o pci-sysfs.o
|
||||
obj-$(CONFIG_SRM_ENV) += srm_env.o
|
||||
obj-$(CONFIG_MODULES) += module.o
|
||||
obj-$(CONFIG_PERF_EVENTS) += perf_event.o
|
||||
|
||||
ifdef CONFIG_ALPHA_GENERIC
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#include <asm/uaccess.h>
|
||||
|
||||
volatile unsigned long irq_err_count;
|
||||
DEFINE_PER_CPU(unsigned long, irq_pmi_count);
|
||||
|
||||
void ack_bad_irq(unsigned int irq)
|
||||
{
|
||||
|
|
@ -63,9 +64,7 @@ int irq_select_affinity(unsigned int irq)
|
|||
int
|
||||
show_interrupts(struct seq_file *p, void *v)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
int j;
|
||||
#endif
|
||||
int irq = *(loff_t *) v;
|
||||
struct irqaction * action;
|
||||
unsigned long flags;
|
||||
|
|
@ -112,6 +111,10 @@ unlock:
|
|||
seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
|
||||
seq_putc(p, '\n');
|
||||
#endif
|
||||
seq_puts(p, "PMI: ");
|
||||
for_each_online_cpu(j)
|
||||
seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
|
||||
seq_puts(p, " Performance Monitoring\n");
|
||||
seq_printf(p, "ERR: %10lu\n", irq_err_count);
|
||||
}
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
|
||||
#include <asm/machvec.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/perf_event.h>
|
||||
|
||||
#include "proto.h"
|
||||
#include "irq_impl.h"
|
||||
|
|
@ -111,6 +112,8 @@ init_IRQ(void)
|
|||
wrent(entInt, 0);
|
||||
|
||||
alpha_mv.init_irq();
|
||||
|
||||
init_hw_perf_events();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -234,17 +234,17 @@ linux_to_osf_statfs(struct kstatfs *linux_stat, struct osf_statfs __user *osf_st
|
|||
}
|
||||
|
||||
static int
|
||||
do_osf_statfs(struct dentry * dentry, struct osf_statfs __user *buffer,
|
||||
do_osf_statfs(struct path *path, struct osf_statfs __user *buffer,
|
||||
unsigned long bufsiz)
|
||||
{
|
||||
struct kstatfs linux_stat;
|
||||
int error = vfs_statfs(dentry, &linux_stat);
|
||||
int error = vfs_statfs(path, &linux_stat);
|
||||
if (!error)
|
||||
error = linux_to_osf_statfs(&linux_stat, buffer, bufsiz);
|
||||
return error;
|
||||
}
|
||||
|
||||
SYSCALL_DEFINE3(osf_statfs, char __user *, pathname,
|
||||
SYSCALL_DEFINE3(osf_statfs, const char __user *, pathname,
|
||||
struct osf_statfs __user *, buffer, unsigned long, bufsiz)
|
||||
{
|
||||
struct path path;
|
||||
|
|
@ -252,7 +252,7 @@ SYSCALL_DEFINE3(osf_statfs, char __user *, pathname,
|
|||
|
||||
retval = user_path(pathname, &path);
|
||||
if (!retval) {
|
||||
retval = do_osf_statfs(path.dentry, buffer, bufsiz);
|
||||
retval = do_osf_statfs(&path buffer, bufsiz);
|
||||
path_put(&path);
|
||||
}
|
||||
return retval;
|
||||
|
|
@ -267,7 +267,7 @@ SYSCALL_DEFINE3(osf_fstatfs, unsigned long, fd,
|
|||
retval = -EBADF;
|
||||
file = fget(fd);
|
||||
if (file) {
|
||||
retval = do_osf_statfs(file->f_path.dentry, buffer, bufsiz);
|
||||
retval = do_osf_statfs(&file->f_path, buffer, bufsiz);
|
||||
fput(file);
|
||||
}
|
||||
return retval;
|
||||
|
|
@ -358,7 +358,7 @@ osf_procfs_mount(char *dirname, struct procfs_args __user *args, int flags)
|
|||
return do_mount("", dirname, "proc", flags, NULL);
|
||||
}
|
||||
|
||||
SYSCALL_DEFINE4(osf_mount, unsigned long, typenr, char __user *, path,
|
||||
SYSCALL_DEFINE4(osf_mount, unsigned long, typenr, const char __user *, path,
|
||||
int, flag, void __user *, data)
|
||||
{
|
||||
int retval;
|
||||
|
|
@ -932,7 +932,7 @@ SYSCALL_DEFINE3(osf_setitimer, int, which, struct itimerval32 __user *, in,
|
|||
|
||||
}
|
||||
|
||||
SYSCALL_DEFINE2(osf_utimes, char __user *, filename,
|
||||
SYSCALL_DEFINE2(osf_utimes, const char __user *, filename,
|
||||
struct timeval32 __user *, tvs)
|
||||
{
|
||||
struct timespec tv[2];
|
||||
|
|
|
|||
842
arch/alpha/kernel/perf_event.c
Normal file
842
arch/alpha/kernel/perf_event.c
Normal file
|
|
@ -0,0 +1,842 @@
|
|||
/*
|
||||
* Hardware performance events for the Alpha.
|
||||
*
|
||||
* We implement HW counts on the EV67 and subsequent CPUs only.
|
||||
*
|
||||
* (C) 2010 Michael J. Cree
|
||||
*
|
||||
* Somewhat based on the Sparc code, and to a lesser extent the PowerPC and
|
||||
* ARM code, which are copyright by their respective authors.
|
||||
*/
|
||||
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/kprobes.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/kdebug.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#include <asm/hwrpb.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/pal.h>
|
||||
#include <asm/wrperfmon.h>
|
||||
#include <asm/hw_irq.h>
|
||||
|
||||
|
||||
/* The maximum number of PMCs on any Alpha CPU whatsoever. */
|
||||
#define MAX_HWEVENTS 3
|
||||
#define PMC_NO_INDEX -1
|
||||
|
||||
/* For tracking PMCs and the hw events they monitor on each CPU. */
|
||||
struct cpu_hw_events {
|
||||
int enabled;
|
||||
/* Number of events scheduled; also number entries valid in arrays below. */
|
||||
int n_events;
|
||||
/* Number events added since last hw_perf_disable(). */
|
||||
int n_added;
|
||||
/* Events currently scheduled. */
|
||||
struct perf_event *event[MAX_HWEVENTS];
|
||||
/* Event type of each scheduled event. */
|
||||
unsigned long evtype[MAX_HWEVENTS];
|
||||
/* Current index of each scheduled event; if not yet determined
|
||||
* contains PMC_NO_INDEX.
|
||||
*/
|
||||
int current_idx[MAX_HWEVENTS];
|
||||
/* The active PMCs' config for easy use with wrperfmon(). */
|
||||
unsigned long config;
|
||||
/* The active counters' indices for easy use with wrperfmon(). */
|
||||
unsigned long idx_mask;
|
||||
};
|
||||
DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* A structure to hold the description of the PMCs available on a particular
|
||||
* type of Alpha CPU.
|
||||
*/
|
||||
struct alpha_pmu_t {
|
||||
/* Mapping of the perf system hw event types to indigenous event types */
|
||||
const int *event_map;
|
||||
/* The number of entries in the event_map */
|
||||
int max_events;
|
||||
/* The number of PMCs on this Alpha */
|
||||
int num_pmcs;
|
||||
/*
|
||||
* All PMC counters reside in the IBOX register PCTR. This is the
|
||||
* LSB of the counter.
|
||||
*/
|
||||
int pmc_count_shift[MAX_HWEVENTS];
|
||||
/*
|
||||
* The mask that isolates the PMC bits when the LSB of the counter
|
||||
* is shifted to bit 0.
|
||||
*/
|
||||
unsigned long pmc_count_mask[MAX_HWEVENTS];
|
||||
/* The maximum period the PMC can count. */
|
||||
unsigned long pmc_max_period[MAX_HWEVENTS];
|
||||
/*
|
||||
* The maximum value that may be written to the counter due to
|
||||
* hardware restrictions is pmc_max_period - pmc_left.
|
||||
*/
|
||||
long pmc_left[3];
|
||||
/* Subroutine for allocation of PMCs. Enforces constraints. */
|
||||
int (*check_constraints)(struct perf_event **, unsigned long *, int);
|
||||
};
|
||||
|
||||
/*
|
||||
* The Alpha CPU PMU description currently in operation. This is set during
|
||||
* the boot process to the specific CPU of the machine.
|
||||
*/
|
||||
static const struct alpha_pmu_t *alpha_pmu;
|
||||
|
||||
|
||||
#define HW_OP_UNSUPPORTED -1
|
||||
|
||||
/*
|
||||
* The hardware description of the EV67, EV68, EV69, EV7 and EV79 PMUs
|
||||
* follow. Since they are identical we refer to them collectively as the
|
||||
* EV67 henceforth.
|
||||
*/
|
||||
|
||||
/*
|
||||
* EV67 PMC event types
|
||||
*
|
||||
* There is no one-to-one mapping of the possible hw event types to the
|
||||
* actual codes that are used to program the PMCs hence we introduce our
|
||||
* own hw event type identifiers.
|
||||
*/
|
||||
enum ev67_pmc_event_type {
|
||||
EV67_CYCLES = 1,
|
||||
EV67_INSTRUCTIONS,
|
||||
EV67_BCACHEMISS,
|
||||
EV67_MBOXREPLAY,
|
||||
EV67_LAST_ET
|
||||
};
|
||||
#define EV67_NUM_EVENT_TYPES (EV67_LAST_ET-EV67_CYCLES)
|
||||
|
||||
|
||||
/* Mapping of the hw event types to the perf tool interface */
|
||||
static const int ev67_perfmon_event_map[] = {
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = EV67_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] = EV67_INSTRUCTIONS,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = EV67_BCACHEMISS,
|
||||
};
|
||||
|
||||
struct ev67_mapping_t {
|
||||
int config;
|
||||
int idx;
|
||||
};
|
||||
|
||||
/*
|
||||
* The mapping used for one event only - these must be in same order as enum
|
||||
* ev67_pmc_event_type definition.
|
||||
*/
|
||||
static const struct ev67_mapping_t ev67_mapping[] = {
|
||||
{EV67_PCTR_INSTR_CYCLES, 1}, /* EV67_CYCLES, */
|
||||
{EV67_PCTR_INSTR_CYCLES, 0}, /* EV67_INSTRUCTIONS */
|
||||
{EV67_PCTR_INSTR_BCACHEMISS, 1}, /* EV67_BCACHEMISS */
|
||||
{EV67_PCTR_CYCLES_MBOX, 1} /* EV67_MBOXREPLAY */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Check that a group of events can be simultaneously scheduled on to the
|
||||
* EV67 PMU. Also allocate counter indices and config.
|
||||
*/
|
||||
static int ev67_check_constraints(struct perf_event **event,
|
||||
unsigned long *evtype, int n_ev)
|
||||
{
|
||||
int idx0;
|
||||
unsigned long config;
|
||||
|
||||
idx0 = ev67_mapping[evtype[0]-1].idx;
|
||||
config = ev67_mapping[evtype[0]-1].config;
|
||||
if (n_ev == 1)
|
||||
goto success;
|
||||
|
||||
BUG_ON(n_ev != 2);
|
||||
|
||||
if (evtype[0] == EV67_MBOXREPLAY || evtype[1] == EV67_MBOXREPLAY) {
|
||||
/* MBOX replay traps must be on PMC 1 */
|
||||
idx0 = (evtype[0] == EV67_MBOXREPLAY) ? 1 : 0;
|
||||
/* Only cycles can accompany MBOX replay traps */
|
||||
if (evtype[idx0] == EV67_CYCLES) {
|
||||
config = EV67_PCTR_CYCLES_MBOX;
|
||||
goto success;
|
||||
}
|
||||
}
|
||||
|
||||
if (evtype[0] == EV67_BCACHEMISS || evtype[1] == EV67_BCACHEMISS) {
|
||||
/* Bcache misses must be on PMC 1 */
|
||||
idx0 = (evtype[0] == EV67_BCACHEMISS) ? 1 : 0;
|
||||
/* Only instructions can accompany Bcache misses */
|
||||
if (evtype[idx0] == EV67_INSTRUCTIONS) {
|
||||
config = EV67_PCTR_INSTR_BCACHEMISS;
|
||||
goto success;
|
||||
}
|
||||
}
|
||||
|
||||
if (evtype[0] == EV67_INSTRUCTIONS || evtype[1] == EV67_INSTRUCTIONS) {
|
||||
/* Instructions must be on PMC 0 */
|
||||
idx0 = (evtype[0] == EV67_INSTRUCTIONS) ? 0 : 1;
|
||||
/* By this point only cycles can accompany instructions */
|
||||
if (evtype[idx0^1] == EV67_CYCLES) {
|
||||
config = EV67_PCTR_INSTR_CYCLES;
|
||||
goto success;
|
||||
}
|
||||
}
|
||||
|
||||
/* Otherwise, darn it, there is a conflict. */
|
||||
return -1;
|
||||
|
||||
success:
|
||||
event[0]->hw.idx = idx0;
|
||||
event[0]->hw.config_base = config;
|
||||
if (n_ev == 2) {
|
||||
event[1]->hw.idx = idx0 ^ 1;
|
||||
event[1]->hw.config_base = config;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static const struct alpha_pmu_t ev67_pmu = {
|
||||
.event_map = ev67_perfmon_event_map,
|
||||
.max_events = ARRAY_SIZE(ev67_perfmon_event_map),
|
||||
.num_pmcs = 2,
|
||||
.pmc_count_shift = {EV67_PCTR_0_COUNT_SHIFT, EV67_PCTR_1_COUNT_SHIFT, 0},
|
||||
.pmc_count_mask = {EV67_PCTR_0_COUNT_MASK, EV67_PCTR_1_COUNT_MASK, 0},
|
||||
.pmc_max_period = {(1UL<<20) - 1, (1UL<<20) - 1, 0},
|
||||
.pmc_left = {16, 4, 0},
|
||||
.check_constraints = ev67_check_constraints
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Helper routines to ensure that we read/write only the correct PMC bits
|
||||
* when calling the wrperfmon PALcall.
|
||||
*/
|
||||
static inline void alpha_write_pmc(int idx, unsigned long val)
|
||||
{
|
||||
val &= alpha_pmu->pmc_count_mask[idx];
|
||||
val <<= alpha_pmu->pmc_count_shift[idx];
|
||||
val |= (1<<idx);
|
||||
wrperfmon(PERFMON_CMD_WRITE, val);
|
||||
}
|
||||
|
||||
static inline unsigned long alpha_read_pmc(int idx)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = wrperfmon(PERFMON_CMD_READ, 0);
|
||||
val >>= alpha_pmu->pmc_count_shift[idx];
|
||||
val &= alpha_pmu->pmc_count_mask[idx];
|
||||
return val;
|
||||
}
|
||||
|
||||
/* Set a new period to sample over */
|
||||
static int alpha_perf_event_set_period(struct perf_event *event,
|
||||
struct hw_perf_event *hwc, int idx)
|
||||
{
|
||||
long left = atomic64_read(&hwc->period_left);
|
||||
long period = hwc->sample_period;
|
||||
int ret = 0;
|
||||
|
||||
if (unlikely(left <= -period)) {
|
||||
left = period;
|
||||
atomic64_set(&hwc->period_left, left);
|
||||
hwc->last_period = period;
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
if (unlikely(left <= 0)) {
|
||||
left += period;
|
||||
atomic64_set(&hwc->period_left, left);
|
||||
hwc->last_period = period;
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Hardware restrictions require that the counters must not be
|
||||
* written with values that are too close to the maximum period.
|
||||
*/
|
||||
if (unlikely(left < alpha_pmu->pmc_left[idx]))
|
||||
left = alpha_pmu->pmc_left[idx];
|
||||
|
||||
if (left > (long)alpha_pmu->pmc_max_period[idx])
|
||||
left = alpha_pmu->pmc_max_period[idx];
|
||||
|
||||
atomic64_set(&hwc->prev_count, (unsigned long)(-left));
|
||||
|
||||
alpha_write_pmc(idx, (unsigned long)(-left));
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Calculates the count (the 'delta') since the last time the PMC was read.
|
||||
*
|
||||
* As the PMCs' full period can easily be exceeded within the perf system
|
||||
* sampling period we cannot use any high order bits as a guard bit in the
|
||||
* PMCs to detect overflow as is done by other architectures. The code here
|
||||
* calculates the delta on the basis that there is no overflow when ovf is
|
||||
* zero. The value passed via ovf by the interrupt handler corrects for
|
||||
* overflow.
|
||||
*
|
||||
* This can be racey on rare occasions -- a call to this routine can occur
|
||||
* with an overflowed counter just before the PMI service routine is called.
|
||||
* The check for delta negative hopefully always rectifies this situation.
|
||||
*/
|
||||
static unsigned long alpha_perf_event_update(struct perf_event *event,
|
||||
struct hw_perf_event *hwc, int idx, long ovf)
|
||||
{
|
||||
long prev_raw_count, new_raw_count;
|
||||
long delta;
|
||||
|
||||
again:
|
||||
prev_raw_count = atomic64_read(&hwc->prev_count);
|
||||
new_raw_count = alpha_read_pmc(idx);
|
||||
|
||||
if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
|
||||
new_raw_count) != prev_raw_count)
|
||||
goto again;
|
||||
|
||||
delta = (new_raw_count - (prev_raw_count & alpha_pmu->pmc_count_mask[idx])) + ovf;
|
||||
|
||||
/* It is possible on very rare occasions that the PMC has overflowed
|
||||
* but the interrupt is yet to come. Detect and fix this situation.
|
||||
*/
|
||||
if (unlikely(delta < 0)) {
|
||||
delta += alpha_pmu->pmc_max_period[idx] + 1;
|
||||
}
|
||||
|
||||
atomic64_add(delta, &event->count);
|
||||
atomic64_sub(delta, &hwc->period_left);
|
||||
|
||||
return new_raw_count;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Collect all HW events into the array event[].
|
||||
*/
|
||||
static int collect_events(struct perf_event *group, int max_count,
|
||||
struct perf_event *event[], unsigned long *evtype,
|
||||
int *current_idx)
|
||||
{
|
||||
struct perf_event *pe;
|
||||
int n = 0;
|
||||
|
||||
if (!is_software_event(group)) {
|
||||
if (n >= max_count)
|
||||
return -1;
|
||||
event[n] = group;
|
||||
evtype[n] = group->hw.event_base;
|
||||
current_idx[n++] = PMC_NO_INDEX;
|
||||
}
|
||||
list_for_each_entry(pe, &group->sibling_list, group_entry) {
|
||||
if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) {
|
||||
if (n >= max_count)
|
||||
return -1;
|
||||
event[n] = pe;
|
||||
evtype[n] = pe->hw.event_base;
|
||||
current_idx[n++] = PMC_NO_INDEX;
|
||||
}
|
||||
}
|
||||
return n;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Check that a group of events can be simultaneously scheduled on to the PMU.
|
||||
*/
|
||||
static int alpha_check_constraints(struct perf_event **events,
|
||||
unsigned long *evtypes, int n_ev)
|
||||
{
|
||||
|
||||
/* No HW events is possible from hw_perf_group_sched_in(). */
|
||||
if (n_ev == 0)
|
||||
return 0;
|
||||
|
||||
if (n_ev > alpha_pmu->num_pmcs)
|
||||
return -1;
|
||||
|
||||
return alpha_pmu->check_constraints(events, evtypes, n_ev);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* If new events have been scheduled then update cpuc with the new
|
||||
* configuration. This may involve shifting cycle counts from one PMC to
|
||||
* another.
|
||||
*/
|
||||
static void maybe_change_configuration(struct cpu_hw_events *cpuc)
|
||||
{
|
||||
int j;
|
||||
|
||||
if (cpuc->n_added == 0)
|
||||
return;
|
||||
|
||||
/* Find counters that are moving to another PMC and update */
|
||||
for (j = 0; j < cpuc->n_events; j++) {
|
||||
struct perf_event *pe = cpuc->event[j];
|
||||
|
||||
if (cpuc->current_idx[j] != PMC_NO_INDEX &&
|
||||
cpuc->current_idx[j] != pe->hw.idx) {
|
||||
alpha_perf_event_update(pe, &pe->hw, cpuc->current_idx[j], 0);
|
||||
cpuc->current_idx[j] = PMC_NO_INDEX;
|
||||
}
|
||||
}
|
||||
|
||||
/* Assign to counters all unassigned events. */
|
||||
cpuc->idx_mask = 0;
|
||||
for (j = 0; j < cpuc->n_events; j++) {
|
||||
struct perf_event *pe = cpuc->event[j];
|
||||
struct hw_perf_event *hwc = &pe->hw;
|
||||
int idx = hwc->idx;
|
||||
|
||||
if (cpuc->current_idx[j] != PMC_NO_INDEX) {
|
||||
cpuc->idx_mask |= (1<<cpuc->current_idx[j]);
|
||||
continue;
|
||||
}
|
||||
|
||||
alpha_perf_event_set_period(pe, hwc, idx);
|
||||
cpuc->current_idx[j] = idx;
|
||||
cpuc->idx_mask |= (1<<cpuc->current_idx[j]);
|
||||
}
|
||||
cpuc->config = cpuc->event[0]->hw.config_base;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Schedule perf HW event on to PMU.
|
||||
* - this function is called from outside this module via the pmu struct
|
||||
* returned from perf event initialisation.
|
||||
*/
|
||||
static int alpha_pmu_enable(struct perf_event *event)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
int n0;
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* The Sparc code has the IRQ disable first followed by the perf
|
||||
* disable, however this can lead to an overflowed counter with the
|
||||
* PMI disabled on rare occasions. The alpha_perf_event_update()
|
||||
* routine should detect this situation by noting a negative delta,
|
||||
* nevertheless we disable the PMCs first to enable a potential
|
||||
* final PMI to occur before we disable interrupts.
|
||||
*/
|
||||
perf_disable();
|
||||
local_irq_save(flags);
|
||||
|
||||
/* Default to error to be returned */
|
||||
ret = -EAGAIN;
|
||||
|
||||
/* Insert event on to PMU and if successful modify ret to valid return */
|
||||
n0 = cpuc->n_events;
|
||||
if (n0 < alpha_pmu->num_pmcs) {
|
||||
cpuc->event[n0] = event;
|
||||
cpuc->evtype[n0] = event->hw.event_base;
|
||||
cpuc->current_idx[n0] = PMC_NO_INDEX;
|
||||
|
||||
if (!alpha_check_constraints(cpuc->event, cpuc->evtype, n0+1)) {
|
||||
cpuc->n_events++;
|
||||
cpuc->n_added++;
|
||||
ret = 0;
|
||||
}
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
perf_enable();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Disable performance monitoring unit
|
||||
* - this function is called from outside this module via the pmu struct
|
||||
* returned from perf event initialisation.
|
||||
*/
|
||||
static void alpha_pmu_disable(struct perf_event *event)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
unsigned long flags;
|
||||
int j;
|
||||
|
||||
perf_disable();
|
||||
local_irq_save(flags);
|
||||
|
||||
for (j = 0; j < cpuc->n_events; j++) {
|
||||
if (event == cpuc->event[j]) {
|
||||
int idx = cpuc->current_idx[j];
|
||||
|
||||
/* Shift remaining entries down into the existing
|
||||
* slot.
|
||||
*/
|
||||
while (++j < cpuc->n_events) {
|
||||
cpuc->event[j - 1] = cpuc->event[j];
|
||||
cpuc->evtype[j - 1] = cpuc->evtype[j];
|
||||
cpuc->current_idx[j - 1] =
|
||||
cpuc->current_idx[j];
|
||||
}
|
||||
|
||||
/* Absorb the final count and turn off the event. */
|
||||
alpha_perf_event_update(event, hwc, idx, 0);
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
cpuc->idx_mask &= ~(1UL<<idx);
|
||||
cpuc->n_events--;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
perf_enable();
|
||||
}
|
||||
|
||||
|
||||
static void alpha_pmu_read(struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
alpha_perf_event_update(event, hwc, hwc->idx, 0);
|
||||
}
|
||||
|
||||
|
||||
static void alpha_pmu_unthrottle(struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
|
||||
cpuc->idx_mask |= 1UL<<hwc->idx;
|
||||
wrperfmon(PERFMON_CMD_ENABLE, (1UL<<hwc->idx));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check that CPU performance counters are supported.
|
||||
* - currently support EV67 and later CPUs.
|
||||
* - actually some later revisions of the EV6 have the same PMC model as the
|
||||
* EV67 but we don't do suffiently deep CPU detection to detect them.
|
||||
* Bad luck to the very few people who might have one, I guess.
|
||||
*/
|
||||
static int supported_cpu(void)
|
||||
{
|
||||
struct percpu_struct *cpu;
|
||||
unsigned long cputype;
|
||||
|
||||
/* Get cpu type from HW */
|
||||
cpu = (struct percpu_struct *)((char *)hwrpb + hwrpb->processor_offset);
|
||||
cputype = cpu->type & 0xffffffff;
|
||||
/* Include all of EV67, EV68, EV7, EV79 and EV69 as supported. */
|
||||
return (cputype >= EV67_CPU) && (cputype <= EV69_CPU);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void hw_perf_event_destroy(struct perf_event *event)
|
||||
{
|
||||
/* Nothing to be done! */
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int __hw_perf_event_init(struct perf_event *event)
|
||||
{
|
||||
struct perf_event_attr *attr = &event->attr;
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct perf_event *evts[MAX_HWEVENTS];
|
||||
unsigned long evtypes[MAX_HWEVENTS];
|
||||
int idx_rubbish_bin[MAX_HWEVENTS];
|
||||
int ev;
|
||||
int n;
|
||||
|
||||
/* We only support a limited range of HARDWARE event types with one
|
||||
* only programmable via a RAW event type.
|
||||
*/
|
||||
if (attr->type == PERF_TYPE_HARDWARE) {
|
||||
if (attr->config >= alpha_pmu->max_events)
|
||||
return -EINVAL;
|
||||
ev = alpha_pmu->event_map[attr->config];
|
||||
} else if (attr->type == PERF_TYPE_HW_CACHE) {
|
||||
return -EOPNOTSUPP;
|
||||
} else if (attr->type == PERF_TYPE_RAW) {
|
||||
ev = attr->config & 0xff;
|
||||
} else {
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
if (ev < 0) {
|
||||
return ev;
|
||||
}
|
||||
|
||||
/* The EV67 does not support mode exclusion */
|
||||
if (attr->exclude_kernel || attr->exclude_user
|
||||
|| attr->exclude_hv || attr->exclude_idle) {
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
/*
|
||||
* We place the event type in event_base here and leave calculation
|
||||
* of the codes to programme the PMU for alpha_pmu_enable() because
|
||||
* it is only then we will know what HW events are actually
|
||||
* scheduled on to the PMU. At that point the code to programme the
|
||||
* PMU is put into config_base and the PMC to use is placed into
|
||||
* idx. We initialise idx (below) to PMC_NO_INDEX to indicate that
|
||||
* it is yet to be determined.
|
||||
*/
|
||||
hwc->event_base = ev;
|
||||
|
||||
/* Collect events in a group together suitable for calling
|
||||
* alpha_check_constraints() to verify that the group as a whole can
|
||||
* be scheduled on to the PMU.
|
||||
*/
|
||||
n = 0;
|
||||
if (event->group_leader != event) {
|
||||
n = collect_events(event->group_leader,
|
||||
alpha_pmu->num_pmcs - 1,
|
||||
evts, evtypes, idx_rubbish_bin);
|
||||
if (n < 0)
|
||||
return -EINVAL;
|
||||
}
|
||||
evtypes[n] = hwc->event_base;
|
||||
evts[n] = event;
|
||||
|
||||
if (alpha_check_constraints(evts, evtypes, n + 1))
|
||||
return -EINVAL;
|
||||
|
||||
/* Indicate that PMU config and idx are yet to be determined. */
|
||||
hwc->config_base = 0;
|
||||
hwc->idx = PMC_NO_INDEX;
|
||||
|
||||
event->destroy = hw_perf_event_destroy;
|
||||
|
||||
/*
|
||||
* Most architectures reserve the PMU for their use at this point.
|
||||
* As there is no existing mechanism to arbitrate usage and there
|
||||
* appears to be no other user of the Alpha PMU we just assume
|
||||
* that we can just use it, hence a NO-OP here.
|
||||
*
|
||||
* Maybe an alpha_reserve_pmu() routine should be implemented but is
|
||||
* anything else ever going to use it?
|
||||
*/
|
||||
|
||||
if (!hwc->sample_period) {
|
||||
hwc->sample_period = alpha_pmu->pmc_max_period[0];
|
||||
hwc->last_period = hwc->sample_period;
|
||||
atomic64_set(&hwc->period_left, hwc->sample_period);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pmu pmu = {
|
||||
.enable = alpha_pmu_enable,
|
||||
.disable = alpha_pmu_disable,
|
||||
.read = alpha_pmu_read,
|
||||
.unthrottle = alpha_pmu_unthrottle,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Main entry point to initialise a HW performance event.
|
||||
*/
|
||||
const struct pmu *hw_perf_event_init(struct perf_event *event)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (!alpha_pmu)
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
/* Do the real initialisation work. */
|
||||
err = __hw_perf_event_init(event);
|
||||
|
||||
if (err)
|
||||
return ERR_PTR(err);
|
||||
|
||||
return &pmu;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Main entry point - enable HW performance counters.
|
||||
*/
|
||||
void hw_perf_enable(void)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
|
||||
if (cpuc->enabled)
|
||||
return;
|
||||
|
||||
cpuc->enabled = 1;
|
||||
barrier();
|
||||
|
||||
if (cpuc->n_events > 0) {
|
||||
/* Update cpuc with information from any new scheduled events. */
|
||||
maybe_change_configuration(cpuc);
|
||||
|
||||
/* Start counting the desired events. */
|
||||
wrperfmon(PERFMON_CMD_LOGGING_OPTIONS, EV67_PCTR_MODE_AGGREGATE);
|
||||
wrperfmon(PERFMON_CMD_DESIRED_EVENTS, cpuc->config);
|
||||
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Main entry point - disable HW performance counters.
|
||||
*/
|
||||
|
||||
void hw_perf_disable(void)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
|
||||
if (!cpuc->enabled)
|
||||
return;
|
||||
|
||||
cpuc->enabled = 0;
|
||||
cpuc->n_added = 0;
|
||||
|
||||
wrperfmon(PERFMON_CMD_DISABLE, cpuc->idx_mask);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Main entry point - don't know when this is called but it
|
||||
* obviously dumps debug info.
|
||||
*/
|
||||
void perf_event_print_debug(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long pcr;
|
||||
int pcr0, pcr1;
|
||||
int cpu;
|
||||
|
||||
if (!supported_cpu())
|
||||
return;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
cpu = smp_processor_id();
|
||||
|
||||
pcr = wrperfmon(PERFMON_CMD_READ, 0);
|
||||
pcr0 = (pcr >> alpha_pmu->pmc_count_shift[0]) & alpha_pmu->pmc_count_mask[0];
|
||||
pcr1 = (pcr >> alpha_pmu->pmc_count_shift[1]) & alpha_pmu->pmc_count_mask[1];
|
||||
|
||||
pr_info("CPU#%d: PCTR0[%06x] PCTR1[%06x]\n", cpu, pcr0, pcr1);
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Performance Monitoring Interrupt Service Routine called when a PMC
|
||||
* overflows. The PMC that overflowed is passed in la_ptr.
|
||||
*/
|
||||
static void alpha_perf_event_irq_handler(unsigned long la_ptr,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
struct cpu_hw_events *cpuc;
|
||||
struct perf_sample_data data;
|
||||
struct perf_event *event;
|
||||
struct hw_perf_event *hwc;
|
||||
int idx, j;
|
||||
|
||||
__get_cpu_var(irq_pmi_count)++;
|
||||
cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
|
||||
/* Completely counting through the PMC's period to trigger a new PMC
|
||||
* overflow interrupt while in this interrupt routine is utterly
|
||||
* disastrous! The EV6 and EV67 counters are sufficiently large to
|
||||
* prevent this but to be really sure disable the PMCs.
|
||||
*/
|
||||
wrperfmon(PERFMON_CMD_DISABLE, cpuc->idx_mask);
|
||||
|
||||
/* la_ptr is the counter that overflowed. */
|
||||
if (unlikely(la_ptr >= perf_max_events)) {
|
||||
/* This should never occur! */
|
||||
irq_err_count++;
|
||||
pr_warning("PMI: silly index %ld\n", la_ptr);
|
||||
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask);
|
||||
return;
|
||||
}
|
||||
|
||||
idx = la_ptr;
|
||||
|
||||
perf_sample_data_init(&data, 0);
|
||||
for (j = 0; j < cpuc->n_events; j++) {
|
||||
if (cpuc->current_idx[j] == idx)
|
||||
break;
|
||||
}
|
||||
|
||||
if (unlikely(j == cpuc->n_events)) {
|
||||
/* This can occur if the event is disabled right on a PMC overflow. */
|
||||
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask);
|
||||
return;
|
||||
}
|
||||
|
||||
event = cpuc->event[j];
|
||||
|
||||
if (unlikely(!event)) {
|
||||
/* This should never occur! */
|
||||
irq_err_count++;
|
||||
pr_warning("PMI: No event at index %d!\n", idx);
|
||||
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask);
|
||||
return;
|
||||
}
|
||||
|
||||
hwc = &event->hw;
|
||||
alpha_perf_event_update(event, hwc, idx, alpha_pmu->pmc_max_period[idx]+1);
|
||||
data.period = event->hw.last_period;
|
||||
|
||||
if (alpha_perf_event_set_period(event, hwc, idx)) {
|
||||
if (perf_event_overflow(event, 1, &data, regs)) {
|
||||
/* Interrupts coming too quickly; "throttle" the
|
||||
* counter, i.e., disable it for a little while.
|
||||
*/
|
||||
cpuc->idx_mask &= ~(1UL<<idx);
|
||||
}
|
||||
}
|
||||
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Init call to initialise performance events at kernel startup.
|
||||
*/
|
||||
void __init init_hw_perf_events(void)
|
||||
{
|
||||
pr_info("Performance events: ");
|
||||
|
||||
if (!supported_cpu()) {
|
||||
pr_cont("No support for your CPU.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pr_cont("Supported CPU type!\n");
|
||||
|
||||
/* Override performance counter IRQ vector */
|
||||
|
||||
perf_irq = alpha_perf_event_irq_handler;
|
||||
|
||||
/* And set up PMU specification */
|
||||
alpha_pmu = &ev67_pmu;
|
||||
perf_max_events = alpha_pmu->num_pmcs;
|
||||
}
|
||||
|
||||
|
|
@ -387,7 +387,7 @@ EXPORT_SYMBOL(dump_elf_task_fp);
|
|||
* sys_execve() executes a new program.
|
||||
*/
|
||||
asmlinkage int
|
||||
do_sys_execve(char __user *ufilename, char __user * __user *argv,
|
||||
do_sys_execve(const char __user *ufilename, char __user * __user *argv,
|
||||
char __user * __user *envp, struct pt_regs *regs)
|
||||
{
|
||||
int error;
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/bcd.h>
|
||||
#include <linux/profile.h>
|
||||
#include <linux/perf_event.h>
|
||||
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/io.h>
|
||||
|
|
@ -82,6 +83,26 @@ static struct {
|
|||
|
||||
unsigned long est_cycle_freq;
|
||||
|
||||
#ifdef CONFIG_PERF_EVENTS
|
||||
|
||||
DEFINE_PER_CPU(u8, perf_event_pending);
|
||||
|
||||
#define set_perf_event_pending_flag() __get_cpu_var(perf_event_pending) = 1
|
||||
#define test_perf_event_pending() __get_cpu_var(perf_event_pending)
|
||||
#define clear_perf_event_pending() __get_cpu_var(perf_event_pending) = 0
|
||||
|
||||
void set_perf_event_pending(void)
|
||||
{
|
||||
set_perf_event_pending_flag();
|
||||
}
|
||||
|
||||
#else /* CONFIG_PERF_EVENTS */
|
||||
|
||||
#define test_perf_event_pending() 0
|
||||
#define clear_perf_event_pending()
|
||||
|
||||
#endif /* CONFIG_PERF_EVENTS */
|
||||
|
||||
|
||||
static inline __u32 rpcc(void)
|
||||
{
|
||||
|
|
@ -175,6 +196,11 @@ irqreturn_t timer_interrupt(int irq, void *dev)
|
|||
update_process_times(user_mode(get_irq_regs()));
|
||||
#endif
|
||||
|
||||
if (test_perf_event_pending()) {
|
||||
clear_perf_event_pending();
|
||||
perf_event_do_pending();
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue