From 2a29e84f1c631bf8e819bf6dd26acaadc8230c92 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Tue, 5 Jan 2021 10:35:42 -0800 Subject: [PATCH 1/3] ARM: dts: msm: Add bindings for ARM performance measuring unit Add initial bindings for ARM PMU driver. This enables measurement of events like cycles, cache misses etc. Change-Id: I80521c085b90b851e38abf8af03da68711aa8120 --- bindings/arm/pmu.txt | 70 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 bindings/arm/pmu.txt diff --git a/bindings/arm/pmu.txt b/bindings/arm/pmu.txt new file mode 100644 index 000000000000..13611a8199bb --- /dev/null +++ b/bindings/arm/pmu.txt @@ -0,0 +1,70 @@ +* ARM Performance Monitor Units + +ARM cores often have a PMU for counting cpu and cache events like cache misses +and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU +representation in the device tree should be done as under:- + +Required properties: + +- compatible : should be one of + "apm,potenza-pmu" + "arm,armv8-pmuv3" + "arm,cortex-a73-pmu" + "arm,cortex-a72-pmu" + "arm,cortex-a57-pmu" + "arm,cortex-a53-pmu" + "arm,cortex-a35-pmu" + "arm,cortex-a17-pmu" + "arm,cortex-a15-pmu" + "arm,cortex-a12-pmu" + "arm,cortex-a9-pmu" + "arm,cortex-a8-pmu" + "arm,cortex-a7-pmu" + "arm,cortex-a5-pmu" + "arm,arm11mpcore-pmu" + "arm,arm1176-pmu" + "arm,arm1136-pmu" + "brcm,vulcan-pmu" + "cavium,thunder-pmu" + "qcom,scorpion-pmu" + "qcom,scorpion-mp-pmu" + "qcom,krait-pmu" +- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu + interrupt (PPI) then 1 interrupt should be specified. + +Optional properties: + +- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of + the SPIs listed in the interrupts property. + + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property, unless this is already specified + by the PPI interrupt specifier itself (in which case + the interrupt-affinity property shouldn't be present). + + This property should be present when there is more than + a single SPI. + + +- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd + events. + +- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register + (SDER) is accessible. This will cause the driver to do + any setup required that is only possible in ARMv7 secure + state. If not present the ARMv7 SDER will not be touched, + which means the PMU may fail to operate unless external + code (bootloader or security monitor) has performed the + appropriate initialisation. Note that this property is + not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux + in Non-secure state. + +Example: + +pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <100 101>; +}; From 043c3d60b4f45da1f1fef764e3c74f60eef443f9 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Mon, 4 Jan 2021 17:19:56 -0800 Subject: [PATCH 2/3] ARM: dts: msm: Add device node for ARM PMU for Olympic Add the ARM CPU Performace measuring unit device tree node to measure various hardware events like cache misses, cycles etc. Change-Id: If0d1f358757586e7774ce2810c4683dbc152da66 --- qcom/sdxlemur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f833437c3762..cdc92be053cd 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -257,6 +257,11 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + qcom,msm-imem@1468f000 { compatible = "qcom,msm-imem"; reg = <0x1468f000 0x1000>; /* Address and size of IMEM */ From 5d0dac9fe45db2e96b155a3ca1d7422794b40029 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Thu, 17 Dec 2020 13:57:00 -0800 Subject: [PATCH 3/3] ARM: dts: msm: Add support for ddr scaling on sdxlemur Add ddr bandwidth table and other dt nodes to support ddr bandwidth scaling for sdxlemur target. Change-Id: I9580bd0bb7d78019b2750a2bb7f8df273560dce0 --- qcom/sdxlemur.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index cdc92be053cd..d9276398b37b 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -10,6 +10,9 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + / { #address-cells = <1>; #size-cells = <1>; @@ -437,6 +440,50 @@ status = "disabled"; }; + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 100, 4); /* 381 MB/s */ + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */ + }; + + cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { + compatible = "qcom,devfreq-icc"; + governor = "compute"; + interconnects = <&mem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_tbl: qcom,cpu0-cpu-ddr-tbl { + qcom,core-dev-table = + < 345600 MHZ_TO_MBPS( 300, 4) >, + < 576000 MHZ_TO_MBPS( 768, 4) >, + < 1440000 MHZ_TO_MBPS(1555, 4) >, + < 1497600 MHZ_TO_MBPS(2092, 4) >; + }; + + memlat_cpugrp: qcom,memlat-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0>; + + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_ddr_lat>; + qcom,core-dev-table = <&cpu0_cpu_ddr_tbl>; + }; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>;