From 23e33a0c4d44e8240e7baac0ec96466a76a14722 Mon Sep 17 00:00:00 2001 From: Vlad Karpovich Date: Wed, 4 Apr 2018 16:53:28 -0500 Subject: [PATCH] ASoC: wm_adsp: Update Cirrus ADSP driver Add support for HALO DSP Core. Change-Id: Iae25b559d2277bd40241f85d265d1fc2ac9280a6 Reviewed-on: https://gerrit.mot.com/1166692 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Yuesheng Huang Reviewed-by: Guobin Zhang Submit-Approved: Jira Key --- sound/soc/codecs/wm_adsp.c | 2095 ++++++++++++++++++++++++++++++------ sound/soc/codecs/wm_adsp.h | 113 +- sound/soc/codecs/wmfw.h | 35 + 3 files changed, 1868 insertions(+), 375 deletions(-) diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index 8e24ad33d104..12dc93059c0a 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -111,22 +112,22 @@ #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ -#define ADSP2_CONTROL 0x0 -#define ADSP2_CLOCKING 0x1 -#define ADSP2V2_CLOCKING 0x2 -#define ADSP2_STATUS1 0x4 -#define ADSP2_WDMA_CONFIG_1 0x30 -#define ADSP2_WDMA_CONFIG_2 0x31 -#define ADSP2V2_WDMA_CONFIG_2 0x32 -#define ADSP2_RDMA_CONFIG_1 0x34 +#define ADSP2_CONTROL 0x0 +#define ADSP2_CLOCKING 0x1 +#define ADSP2V2_CLOCKING 0x2 +#define ADSP2_STATUS1 0x4 +#define ADSP2_WDMA_CONFIG_1 0x30 +#define ADSP2_WDMA_CONFIG_2 0x31 +#define ADSP2V2_WDMA_CONFIG_2 0x32 +#define ADSP2_RDMA_CONFIG_1 0x34 -#define ADSP2_SCRATCH0 0x40 -#define ADSP2_SCRATCH1 0x41 -#define ADSP2_SCRATCH2 0x42 -#define ADSP2_SCRATCH3 0x43 +#define ADSP2_SCRATCH0 0x40 +#define ADSP2_SCRATCH1 0x41 +#define ADSP2_SCRATCH2 0x42 +#define ADSP2_SCRATCH3 0x43 -#define ADSP2V2_SCRATCH0_1 0x40 -#define ADSP2V2_SCRATCH2_3 0x42 +#define ADSP2V2_SCRATCH0_1 0x40 +#define ADSP2V2_SCRATCH2_3 0x42 /* * ADSP2 Control @@ -159,13 +160,13 @@ /* * ADSP2V2 clocking */ -#define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ -#define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ -#define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ -#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ -#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ -#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ +#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ +#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ +#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ /* * ADSP2 Status 1 @@ -208,6 +209,230 @@ #define ADSP_MAX_STD_CTRL_SIZE 512 +#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100 +#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10 +#define WM_ADSP_ACKED_CTL_MIN_VALUE 0 +#define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF + +/* + * Event control messages + */ +#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001 + +/* + * HALO system info + */ +#define HALO_SYS_INFO_XM_SRAM_SIZE 0x00010 +#define HALO_SYS_INFO_YM_SRAM_SIZE 0x00018 +#define HALO_SYS_INFO_XM_BANK_SIZE 0x00038 +#define HALO_SYS_INFO_YM_BANK_SIZE 0x0003c +#define HALO_AHBM_WINDOW_DEBUG_0 0x02040 +#define HALO_AHBM_WINDOW_DEBUG_1 0x02044 + +/* + * HALO core + */ +#define HALO_SAMPLE_RATE_RX1 0x00080 +#define HALO_SAMPLE_RATE_TX1 0x00280 +#define HALO_SCRATCH1 0x005c0 +#define HALO_CCM_CORE_CONTROL 0x41000 + +/* + * HALO Lock support + */ +#define HALO_MPU_UNLOCK_CODE_0 0x5555 +#define HALO_MPU_UNLOCK_CODE_1 0xaaaa + +/* + * HALO MPU banks + */ +#define HALO_MPU_XMEM_ACCESS_0 0x43000 +#define HALO_MPU_YMEM_ACCESS_0 0x43004 +#define HALO_MPU_WINDOW_ACCESS_0 0x43008 +#define HALO_MPU_XREG_ACCESS_0 0x4300C +#define HALO_MPU_YREG_ACCESS_0 0x43014 +#define HALO_MPU_XMEM_ACCESS_1 0x43018 +#define HALO_MPU_YMEM_ACCESS_1 0x4301C +#define HALO_MPU_WINDOW_ACCESS_1 0x43020 +#define HALO_MPU_XREG_ACCESS_1 0x43024 +#define HALO_MPU_YREG_ACCESS_1 0x4302C +#define HALO_MPU_XMEM_ACCESS_2 0x43030 +#define HALO_MPU_YMEM_ACCESS_2 0x43034 +#define HALO_MPU_WINDOW_ACCESS_2 0x43038 +#define HALO_MPU_XREG_ACCESS_2 0x4303C +#define HALO_MPU_YREG_ACCESS_2 0x43044 +#define HALO_MPU_XMEM_ACCESS_3 0x43048 +#define HALO_MPU_YMEM_ACCESS_3 0x4304C +#define HALO_MPU_WINDOW_ACCESS_3 0x43050 +#define HALO_MPU_XREG_ACCESS_3 0x43054 +#define HALO_MPU_YREG_ACCESS_3 0x4305C +#define HALO_MPU_XM_VIO_ADDR 0x43100 +#define HALO_MPU_XM_VIO_STATUS 0x43104 +#define HALO_MPU_YM_VIO_ADDR 0x43108 +#define HALO_MPU_YM_VIO_STATUS 0x4310C +#define HALO_MPU_PM_VIO_ADDR 0x43110 +#define HALO_MPU_PM_VIO_STATUS 0x43114 +#define HALO_MPU_LOCK_CONFIG 0x43140 + +/* + * HALO stream arb + */ +#define HALO_STREAM_ARB_MSTR0_CONFIG_0 0x45000 +#define HALO_STREAM_ARB_MSTR0_CONFIG_1 0x45004 +#define HALO_STREAM_ARB_MSTR0_CONFIG_2 0x45008 +#define HALO_STREAM_ARB_MSTR1_CONFIG_0 0x45010 +#define HALO_STREAM_ARB_MSTR1_CONFIG_1 0x45014 +#define HALO_STREAM_ARB_MSTR1_CONFIG_2 0x45018 +#define HALO_STREAM_ARB_MSTR2_CONFIG_0 0x45020 +#define HALO_STREAM_ARB_MSTR2_CONFIG_1 0x45024 +#define HALO_STREAM_ARB_MSTR2_CONFIG_2 0x45028 +#define HALO_STREAM_ARB_MSTR3_CONFIG_0 0x45030 +#define HALO_STREAM_ARB_MSTR3_CONFIG_1 0x45034 +#define HALO_STREAM_ARB_MSTR3_CONFIG_2 0x45038 +#define HALO_STREAM_ARB_MSTR4_CONFIG_0 0x45040 +#define HALO_STREAM_ARB_MSTR4_CONFIG_1 0x45044 +#define HALO_STREAM_ARB_MSTR4_CONFIG_2 0x45048 +#define HALO_STREAM_ARB_MSTR5_CONFIG_0 0x45050 +#define HALO_STREAM_ARB_MSTR5_CONFIG_1 0x45054 +#define HALO_STREAM_ARB_MSTR5_CONFIG_2 0x45058 + +#define HALO_STREAM_ARB_TX1_CONFIG_0 0x45200 +#define HALO_STREAM_ARB_TX1_CONFIG_1 0x45204 +#define HALO_STREAM_ARB_TX2_CONFIG_0 0x45208 +#define HALO_STREAM_ARB_TX2_CONFIG_1 0x4520C +#define HALO_STREAM_ARB_TX3_CONFIG_0 0x45210 +#define HALO_STREAM_ARB_TX3_CONFIG_1 0x45214 +#define HALO_STREAM_ARB_TX4_CONFIG_0 0x45218 +#define HALO_STREAM_ARB_TX4_CONFIG_1 0x4521C +#define HALO_STREAM_ARB_TX5_CONFIG_0 0x45220 +#define HALO_STREAM_ARB_TX5_CONFIG_1 0x45224 +#define HALO_STREAM_ARB_TX6_CONFIG_0 0x45228 +#define HALO_STREAM_ARB_TX6_CONFIG_1 0x4522C +#define HALO_STREAM_ARB_TX7_CONFIG_0 0x45230 +#define HALO_STREAM_ARB_TX7_CONFIG_1 0x45234 +#define HALO_STREAM_ARB_TX8_CONFIG_0 0x45238 +#define HALO_STREAM_ARB_TX8_CONFIG_1 0x4523C +#define HALO_STREAM_ARB_RX1_CONFIG_0 0x45400 +#define HALO_STREAM_ARB_RX1_CONFIG_1 0x45404 +#define HALO_STREAM_ARB_RX2_CONFIG_0 0x45408 +#define HALO_STREAM_ARB_RX2_CONFIG_1 0x4540C +#define HALO_STREAM_ARB_RX3_CONFIG_0 0x45410 +#define HALO_STREAM_ARB_RX3_CONFIG_1 0x45414 +#define HALO_STREAM_ARB_RX4_CONFIG_0 0x45418 +#define HALO_STREAM_ARB_RX4_CONFIG_1 0x4541C +#define HALO_STREAM_ARB_RX5_CONFIG_0 0x45420 +#define HALO_STREAM_ARB_RX5_CONFIG_1 0x45424 +#define HALO_STREAM_ARB_RX6_CONFIG_0 0x45428 +#define HALO_STREAM_ARB_RX6_CONFIG_1 0x4542C +#define HALO_STREAM_ARB_RX7_CONFIG_0 0x45430 +#define HALO_STREAM_ARB_RX7_CONFIG_1 0x45434 +#define HALO_STREAM_ARB_RX8_CONFIG_0 0x45438 +#define HALO_STREAM_ARB_RX8_CONFIG_1 0x4543C + +#define HALO_STREAM_ARB_IRQ0_CONFIG_0 0x45600 +#define HALO_STREAM_ARB_IRQ0_CONFIG_1 0x45604 +#define HALO_STREAM_ARB_IRQ0_CONFIG_2 0x45608 +#define HALO_STREAM_ARB_IRQ1_CONFIG_0 0x45610 +#define HALO_STREAM_ARB_IRQ1_CONFIG_1 0x45614 +#define HALO_STREAM_ARB_IRQ1_CONFIG_2 0x45618 +#define HALO_STREAM_ARB_IRQ2_CONFIG_0 0x45620 +#define HALO_STREAM_ARB_IRQ2_CONFIG_1 0x45624 +#define HALO_STREAM_ARB_IRQ2_CONFIG_2 0x45628 +#define HALO_STREAM_ARB_IRQ3_CONFIG_0 0x45630 +#define HALO_STREAM_ARB_IRQ3_CONFIG_1 0x45634 +#define HALO_STREAM_ARB_IRQ3_CONFIG_2 0x45638 +#define HALO_STREAM_ARB_IRQ4_CONFIG_0 0x45640 +#define HALO_STREAM_ARB_IRQ4_CONFIG_1 0x45644 +#define HALO_STREAM_ARB_IRQ4_CONFIG_2 0x45648 +#define HALO_STREAM_ARB_IRQ5_CONFIG_0 0x45650 +#define HALO_STREAM_ARB_IRQ5_CONFIG_1 0x45654 +#define HALO_STREAM_ARB_IRQ5_CONFIG_2 0x45658 +#define HALO_STREAM_ARB_IRQ6_CONFIG_0 0x45660 +#define HALO_STREAM_ARB_IRQ6_CONFIG_1 0x45664 +#define HALO_STREAM_ARB_IRQ6_CONFIG_2 0x45668 +#define HALO_STREAM_ARB_IRQ7_CONFIG_0 0x45670 +#define HALO_STREAM_ARB_IRQ7_CONFIG_1 0x45674 +#define HALO_STREAM_ARB_IRQ7_CONFIG_2 0x45678 + +#define HALO_INTP_CTL_NMI_CONTROL 0x46008 + +/* + * HALO_AHBM_WINDOW_DEBUG_1 + */ +#define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00 +#define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8 +#define HALO_AHBM_ADDR_ERR_MASK 0x00000080 +#define HALO_AHBM_LOCKED_ERR_MASK 0x00000040 +#define HALO_AHBM_SIZE_ERR_MASK 0x00000020 +#define HALO_AHBM_MODE_ERR_MASK 0x00000010 +#define HALO_AHBM_AHB_ERR_MASK 0x00000001 + +/* + * HALO_SAMPLE_RATE_[RX|TX]n + */ +#define HALO_DSP_RATE_SHIFT 0 +#define HALO_DSP_RATE_MASK 0x1f + +/* + * HALO_CCM_CORE_CONTROL + */ +#define HALO_CORE_EN 0x00000001 +#define HALO_CORE_EN_MASK 0x00000001 +#define HALO_CORE_EN_SHIFT 0 +#define HALO_CORE_EN_WIDTH 1 +#define HALO_CORE_RESET 0x00000200 + +/* + * HALO_MPU_?M_VIO_STATUS + */ +#define HALO_MPU_VIO_STS_MASK 0x007e0000 +#define HALO_MPU_VIO_STS_SHIFT 17 +#define HALO_MPU_VIO_ERR_MASK 0x00010000 +#define HALO_MPU_VIO_ERR_SHIFT 16 +#define HALO_MPU_VIO_ERR_WR_MASK 0x00008000 +#define HALO_MPU_VIO_ERR_WR_SHIFT 15 +#define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff +#define HALO_MPU_VIO_ERR_SRC_SHIFT 0 + +#define HALO_MPU_VIO_SRAM 0x01 +#define HALO_MPU_VIO_REG 0x02 +#define HALO_MPU_VIO_AHB 0x04 +#define HALO_MPU_VIO_EREG 0x08 +#define HALO_MPU_VIO_EXTERNAL_MEM 0x10 +#define HALO_MPU_VIO_NON_EXIST 0x20 + +/* + * HALO_STREAM_ARB_MSTRn_CONFIG_0 + */ +#define HALO_STREAM_ARB_MSTR_EN_MASK 0x1 + +/* + * HALO_STREAM_ARB_[TX|RX]n_CONFIG_0 + * HALO_STREAM_ARB_IRQn_CONFIG_0 + */ +#define HALO_STREAM_ARB_MSTR_SEL_DEFAULT 0xfc + +static const unsigned int halo_mpu_access[18] = { + HALO_MPU_WINDOW_ACCESS_0, + HALO_MPU_XREG_ACCESS_0, + HALO_MPU_YREG_ACCESS_0, + HALO_MPU_XMEM_ACCESS_1, + HALO_MPU_YMEM_ACCESS_1, + HALO_MPU_WINDOW_ACCESS_1, + HALO_MPU_XREG_ACCESS_1, + HALO_MPU_YREG_ACCESS_1, + HALO_MPU_XMEM_ACCESS_2, + HALO_MPU_YMEM_ACCESS_2, + HALO_MPU_WINDOW_ACCESS_2, + HALO_MPU_XREG_ACCESS_2, + HALO_MPU_YREG_ACCESS_2, + HALO_MPU_XMEM_ACCESS_3, + HALO_MPU_YMEM_ACCESS_3, + HALO_MPU_WINDOW_ACCESS_3, + HALO_MPU_XREG_ACCESS_3, + HALO_MPU_YREG_ACCESS_3, +}; + struct wm_adsp_buf { struct list_head list; void *buf; @@ -286,6 +511,12 @@ struct wm_adsp_system_config_xm_hdr { __be32 build_job_number; }; +struct wm_halo_system_config_xm_hdr { + __be32 halo_heartbeat; + __be32 build_job_name[3]; + __be32 build_job_number; +}; + struct wm_adsp_alg_xm_struct { __be32 magic; __be32 smoothing; @@ -326,6 +557,7 @@ struct wm_adsp_compr_buf { struct wm_adsp_buffer_region *regions; u32 host_buf_ptr; + u32 error; u32 irq_count; int read_index; @@ -359,13 +591,7 @@ struct wm_adsp_buffer_region { unsigned int base_addr; }; -struct wm_adsp_buffer_region_def { - unsigned int mem_type; - unsigned int base_offset; - unsigned int size_offset; -}; - -static const struct wm_adsp_buffer_region_def default_regions[] = { +static struct wm_adsp_buffer_region_def default_regions[] = { { .mem_type = WMFW_ADSP2_XM, .base_offset = HOST_BUFFER_FIELD(X_buf_base), @@ -383,14 +609,7 @@ static const struct wm_adsp_buffer_region_def default_regions[] = { }, }; -struct wm_adsp_fw_caps { - u32 id; - struct snd_codec_desc desc; - int num_regions; - const struct wm_adsp_buffer_region_def *region_defs; -}; - -static const struct wm_adsp_fw_caps ctrl_caps[] = { +static struct wm_adsp_fw_caps ctrl_caps[] = { { .id = SND_AUDIOCODEC_BESPOKE, .desc = { @@ -404,7 +623,7 @@ static const struct wm_adsp_fw_caps ctrl_caps[] = { }, }; -static const struct wm_adsp_fw_caps trace_caps[] = { +static struct wm_adsp_fw_caps trace_caps[] = { { .id = SND_AUDIOCODEC_BESPOKE, .desc = { @@ -422,13 +641,7 @@ static const struct wm_adsp_fw_caps trace_caps[] = { }, }; -static const struct { - const char *file; - int compr_direction; - int num_caps; - const struct wm_adsp_fw_caps *caps; - bool voice_trigger; -} wm_adsp_fw[WM_ADSP_NUM_FW] = { +static struct wm_adsp_fw_defs wm_adsp_fw[WM_ADSP_NUM_FW] = { [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" }, [WM_ADSP_FW_HIFI] = { .file = "hifi" }, [WM_ADSP_FW_TX] = { .file = "tx" }, @@ -458,8 +671,6 @@ struct wm_coeff_ctl_ops { struct snd_ctl_elem_value *ucontrol); int (*xput)(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); - int (*xinfo)(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_info *uinfo); }; struct wm_coeff_ctl { @@ -474,11 +685,35 @@ struct wm_coeff_ctl { unsigned int offset; size_t len; unsigned int set:1; - struct snd_kcontrol *kcontrol; struct soc_bytes_ext bytes_ext; unsigned int flags; + unsigned int type; }; +static const char *wm_adsp_mem_region_name(unsigned int type) +{ + switch (type) { + case WMFW_ADSP1_PM: + return "PM"; + case WMFW_HALO_PM_PACKED: + return "PM_PACKED"; + case WMFW_ADSP1_DM: + return "DM"; + case WMFW_ADSP2_XM: + return "XM"; + case WMFW_HALO_XM_PACKED: + return "XM_PACKED"; + case WMFW_ADSP2_YM: + return "YM"; + case WMFW_HALO_YM_PACKED: + return "YM_PACKED"; + case WMFW_ADSP1_ZM: + return "ZM"; + default: + return NULL; + } +} + #ifdef CONFIG_DEBUG_FS static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s) { @@ -513,7 +748,7 @@ static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file, mutex_lock(&dsp->pwr_lock); - if (!dsp->wmfw_file_name || !dsp->running) + if (!dsp->wmfw_file_name || !dsp->booted) ret = 0; else ret = simple_read_from_buffer(user_buf, count, ppos, @@ -533,7 +768,7 @@ static ssize_t wm_adsp_debugfs_bin_read(struct file *file, mutex_lock(&dsp->pwr_lock); - if (!dsp->bin_file_name || !dsp->running) + if (!dsp->bin_file_name || !dsp->booted) ret = 0; else ret = simple_read_from_buffer(user_buf, count, ppos, @@ -587,6 +822,9 @@ static void wm_adsp2_init_debugfs(struct wm_adsp *dsp, if (!root) goto err; + if (!debugfs_create_bool("booted", S_IRUGO, root, &dsp->booted)) + goto err; + if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running)) goto err; @@ -670,7 +908,7 @@ static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, mutex_lock(&dsp[e->shift_l].pwr_lock); - if (dsp[e->shift_l].running || dsp[e->shift_l].compr[0]) + if (dsp[e->shift_l].booted || dsp[e->shift_l].compr[0]) ret = -EBUSY; else dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0]; @@ -680,7 +918,7 @@ static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, return ret; } -static const struct soc_enum wm_adsp_fw_enum[] = { +static struct soc_enum wm_adsp_fw_enum[] = { SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), @@ -708,6 +946,11 @@ const struct snd_kcontrol_new wm_adsp_fw_controls[] = { }; EXPORT_SYMBOL_GPL(wm_adsp_fw_controls); +static const struct snd_kcontrol_new wm_adsp_ao_fw_controls[] = { + SOC_ENUM_EXT("DSP1AO Firmware", wm_adsp_fw_enum[0], + wm_adsp_fw_get, wm_adsp_fw_put), +}; + static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, int type) { @@ -720,24 +963,48 @@ static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, return NULL; } -static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem, - unsigned int offset) +static unsigned int wm_adsp_region_to_reg(struct wm_adsp *dsp, + struct wm_adsp_region const *mem, + unsigned int offset) { if (WARN_ON(!mem)) return offset; - switch (mem->type) { - case WMFW_ADSP1_PM: - return mem->base + (offset * 3); - case WMFW_ADSP1_DM: - return mem->base + (offset * 2); - case WMFW_ADSP2_XM: - return mem->base + (offset * 2); - case WMFW_ADSP2_YM: - return mem->base + (offset * 2); - case WMFW_ADSP1_ZM: - return mem->base + (offset * 2); + switch (dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + switch (mem->type) { + case WMFW_ADSP1_PM: + return mem->base + (offset * 3); + case WMFW_ADSP1_DM: + return mem->base + (offset * 2); + case WMFW_ADSP2_XM: + return mem->base + (offset * 2); + case WMFW_ADSP2_YM: + return mem->base + (offset * 2); + case WMFW_ADSP1_ZM: + return mem->base + (offset * 2); + default: + WARN(1, "Unknown memory region type"); + return offset; + } + case WMFW_HALO: + switch (mem->type) { + case WMFW_ADSP2_XM: + return mem->base + (offset * 4); + case WMFW_ADSP2_YM: + return mem->base + (offset * 4); + case WMFW_HALO_XM_PACKED: + return (mem->base + (offset * 3)) & ~0x3; + case WMFW_HALO_YM_PACKED: + return (mem->base + (offset * 3)) & ~0x3; + case WMFW_HALO_PM_PACKED: + return mem->base + (offset * 5); + default: + WARN(1, "Unknown memory region type"); + return offset; + } default: - WARN(1, "Unknown memory region type"); + WARN(1, "Unknown DSP type"); return offset; } } @@ -767,7 +1034,7 @@ static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) int ret; ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1, - scratch, sizeof(scratch)); + scratch, sizeof(scratch)); if (ret) { adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); @@ -784,11 +1051,49 @@ static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) scratch[1] >> 16); } +static void wm_halo_show_fw_status(struct wm_adsp *dsp) +{ + u32 scratch[4]; + int ret; + + ret = regmap_raw_read(dsp->regmap, dsp->base + HALO_SCRATCH1, + scratch, sizeof(scratch)); + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); + return; + } + + adsp_dbg(dsp, "FW SCRATCH 1:0x%x 2:0x%x 3:0x%x 4:0x%x\n", + be32_to_cpu(scratch[0]), + be32_to_cpu(scratch[1]), + be32_to_cpu(scratch[2]), + be32_to_cpu(scratch[3])); +} + static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext) { return container_of(ext, struct wm_coeff_ctl, bytes_ext); } +static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg) +{ + const struct wm_adsp_alg_region *alg_region = &ctl->alg_region; + struct wm_adsp *dsp = ctl->dsp; + const struct wm_adsp_region *mem; + + mem = wm_adsp_find_region(dsp, alg_region->type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", + alg_region->type); + return -EINVAL; + } + + *reg = wm_adsp_region_to_reg(dsp, mem, + ctl->alg_region.base + ctl->offset); + + return 0; +} + static int wm_coeff_info(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo) { @@ -796,30 +1101,94 @@ static int wm_coeff_info(struct snd_kcontrol *kctl, (struct soc_bytes_ext *)kctl->private_value; struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); - uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; - uinfo->count = ctl->len; + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE; + uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE; + uinfo->value.integer.step = 1; + uinfo->count = 1; + break; + default: + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = ctl->len; + break; + } + return 0; } +static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl, + unsigned int event_id) +{ + struct wm_adsp *dsp = ctl->dsp; + u32 val = cpu_to_be32(event_id); + unsigned int reg; + int i, ret; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", + event_id, ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); + + ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to write %x: %d\n", reg, ret); + return ret; + } + + /* + * Poll for ack, we initially poll at ~1ms intervals for firmwares + * that respond quickly, then go to ~10ms polls. A firmware is unlikely + * to ack instantly so we do the first 1ms delay before reading the + * control to avoid a pointless bus transaction + */ + for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) { + switch (i) { + case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1: + usleep_range(1000, 2000); + i++; + break; + default: + usleep_range(10000, 20000); + i += 10; + break; + } + + ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to read %x: %d\n", reg, ret); + return ret; + } + + if (val == 0) { + adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); + return 0; + } + } + + adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", + reg, ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), + ctl->offset); + + return -ETIMEDOUT; +} + static int wm_coeff_write_control(struct wm_coeff_ctl *ctl, const void *buf, size_t len) { - struct wm_adsp_alg_region *alg_region = &ctl->alg_region; - const struct wm_adsp_region *mem; struct wm_adsp *dsp = ctl->dsp; void *scratch; int ret; unsigned int reg; - mem = wm_adsp_find_region(dsp, alg_region->type); - if (!mem) { - adsp_err(dsp, "No base for region %x\n", - alg_region->type); - return -EINVAL; - } - - reg = ctl->alg_region.base + ctl->offset; - reg = wm_adsp_region_to_reg(mem, reg); + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA); if (!scratch) @@ -890,25 +1259,41 @@ static int wm_coeff_tlv_put(struct snd_kcontrol *kctl, return ret; } +static int wm_coeff_put_acked(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + unsigned int val = ucontrol->value.integer.value[0]; + int ret; + + if (val == 0) + return 0; /* 0 means no event */ + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_acked_control(ctl, val); + else + ret = -EPERM; + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + static int wm_coeff_read_control(struct wm_coeff_ctl *ctl, void *buf, size_t len) { - struct wm_adsp_alg_region *alg_region = &ctl->alg_region; - const struct wm_adsp_region *mem; struct wm_adsp *dsp = ctl->dsp; void *scratch; int ret; unsigned int reg; - mem = wm_adsp_find_region(dsp, alg_region->type); - if (!mem) { - adsp_err(dsp, "No base for region %x\n", - alg_region->type); - return -EINVAL; - } - - reg = ctl->alg_region.base + ctl->offset; - reg = wm_adsp_region_to_reg(mem, reg); + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); if (!scratch) @@ -941,12 +1326,12 @@ static int wm_coeff_get(struct snd_kcontrol *kctl, mutex_lock(&ctl->dsp->pwr_lock); if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { - if (ctl->enabled) + if (ctl->enabled && ctl->dsp->running) ret = wm_coeff_read_control(ctl, p, ctl->len); else ret = -EPERM; } else { - if (!ctl->flags && ctl->enabled) + if (!ctl->flags && ctl->enabled && ctl->dsp->running) ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); memcpy(p, ctl->cache, ctl->len); @@ -968,12 +1353,12 @@ static int wm_coeff_tlv_get(struct snd_kcontrol *kctl, mutex_lock(&ctl->dsp->pwr_lock); if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { - if (ctl->enabled) + if (ctl->enabled && ctl->dsp->running) ret = wm_coeff_read_control(ctl, ctl->cache, size); else ret = -EPERM; } else { - if (!ctl->flags && ctl->enabled) + if (!ctl->flags && ctl->enabled && ctl->dsp->running) ret = wm_coeff_read_control(ctl, ctl->cache, size); } @@ -985,6 +1370,21 @@ static int wm_coeff_tlv_get(struct snd_kcontrol *kctl, return ret; } +static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* + * Although it's not useful to read an acked control, we must satisfy + * user-side assumptions that all controls are readable and that a + * write of the same value should be filtered out (it's valid to send + * the same event number again to the firmware). We therefore return 0, + * meaning "no event" so valid event numbers will always be a change + */ + ucontrol->value.integer.value[0] = 0; + + return 0; +} + struct wmfw_ctl_work { struct wm_adsp *dsp; struct wm_coeff_ctl *ctl; @@ -1034,30 +1434,35 @@ static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl) kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL); if (!kcontrol) return -ENOMEM; - kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; kcontrol->name = ctl->name; kcontrol->info = wm_coeff_info; - kcontrol->get = wm_coeff_get; - kcontrol->put = wm_coeff_put; kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; kcontrol->tlv.c = snd_soc_bytes_tlv_callback; kcontrol->private_value = (unsigned long)&ctl->bytes_ext; - - ctl->bytes_ext.max = ctl->len; - ctl->bytes_ext.get = wm_coeff_tlv_get; - ctl->bytes_ext.put = wm_coeff_tlv_put; - kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len); - ret = snd_soc_add_card_controls(dsp->card, kcontrol, 1); + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + kcontrol->get = wm_coeff_get_acked; + kcontrol->put = wm_coeff_put_acked; + break; + default: + kcontrol->get = wm_coeff_get; + kcontrol->put = wm_coeff_put; + + ctl->bytes_ext.max = ctl->len; + ctl->bytes_ext.get = wm_coeff_tlv_get; + ctl->bytes_ext.put = wm_coeff_tlv_put; + break; + } + + ret = snd_soc_add_codec_controls(dsp->codec, kcontrol, 1); if (ret < 0) goto err_kcontrol; kfree(kcontrol); - ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card, ctl->name); - return 0; err_kcontrol: @@ -1076,9 +1481,16 @@ static int wm_coeff_init_control_caches(struct wm_adsp *dsp) if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) continue; - ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); - if (ret < 0) - return ret; + /* + * For readable controls populate the cache from the DSP memory. + * For non-readable controls the cache was zero-filled when + * created so we don't need to do anything. + */ + if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) { + ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); + if (ret < 0) + return ret; + } } return 0; @@ -1102,6 +1514,27 @@ static int wm_coeff_sync_controls(struct wm_adsp *dsp) return 0; } +static void wm_adsp_signal_event_controls(struct wm_adsp *dsp, + unsigned int event) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) + continue; + + if (!ctl->enabled) + continue; + + ret = wm_coeff_write_acked_control(ctl, event); + if (ret) + adsp_warn(dsp, + "Failed to send 0x%x event to alg 0x%x (%d)\n", + event, ctl->alg_region.alg, ret); + } +} + static void wm_adsp_ctl_work(struct work_struct *work) { struct wmfw_ctl_work *ctl_work = container_of(work, @@ -1123,34 +1556,16 @@ static int wm_adsp_create_control(struct wm_adsp *dsp, const struct wm_adsp_alg_region *alg_region, unsigned int offset, unsigned int len, const char *subname, unsigned int subname_len, - unsigned int flags) + unsigned int flags, unsigned int type) { struct wm_coeff_ctl *ctl; struct wmfw_ctl_work *ctl_work; char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; - char *region_name; + const char *region_name; int ret; - if (flags & WMFW_CTL_FLAG_SYS) - return 0; - - switch (alg_region->type) { - case WMFW_ADSP1_PM: - region_name = "PM"; - break; - case WMFW_ADSP1_DM: - region_name = "DM"; - break; - case WMFW_ADSP2_XM: - region_name = "XM"; - break; - case WMFW_ADSP2_YM: - region_name = "YM"; - break; - case WMFW_ADSP1_ZM: - region_name = "ZM"; - break; - default: + region_name = wm_adsp_mem_region_name(alg_region->type); + if (!region_name) { adsp_err(dsp, "Unknown region type: %d\n", alg_region->type); return -EINVAL; } @@ -1164,7 +1579,8 @@ static int wm_adsp_create_control(struct wm_adsp *dsp, default: ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d%c %.12s %x", dsp->num, *region_name, - wm_adsp_fw_text[dsp->fw], alg_region->alg); + wm_adsp_fw_enum[dsp->num - 1].texts[dsp->fw], + alg_region->alg); /* Truncate the subname from the start if it is too long */ if (subname) { @@ -1192,7 +1608,7 @@ static int wm_adsp_create_control(struct wm_adsp *dsp, ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); if (!ctl) return -ENOMEM; - ctl->fw_name = wm_adsp_fw_text[dsp->fw]; + ctl->fw_name = wm_adsp_fw_enum[dsp->num - 1].texts[dsp->fw]; ctl->alg_region = *alg_region; ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL); if (!ctl->name) { @@ -1206,6 +1622,7 @@ static int wm_adsp_create_control(struct wm_adsp *dsp, ctl->dsp = dsp; ctl->flags = flags; + ctl->type = type; ctl->offset = offset; ctl->len = len; ctl->cache = kzalloc(ctl->len, GFP_KERNEL); @@ -1216,6 +1633,9 @@ static int wm_adsp_create_control(struct wm_adsp *dsp, list_add(&ctl->list, &dsp->ctl_list); + if (flags & WMFW_CTL_FLAG_SYS) + return 0; + ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL); if (!ctl_work) { ret = -ENOMEM; @@ -1246,6 +1666,44 @@ struct wm_coeff_parsed_alg { int ncoeff; }; +int wm_adsp_handle_fw_event(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret = 0, serviced = 0; + u32 val = 0; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_FWEVENT) + continue; + if (!dsp->fwevent_cb) { + adsp_err(dsp, + "FW event callback not registered: %s\n", + ctl->name); + return -EINVAL; + } + + ret = wm_coeff_read_control(ctl, &val, ctl->len); + if (ret < 0) + return ret; + + val = be32_to_cpu(val); + if (val == 0xFFFFFFu) + continue; + + dsp->fwevent_cb(dsp, val); + + val = cpu_to_be32(0xFFFFFFu); + ret = wm_coeff_write_control(ctl, &val, ctl->len); + if (ret < 0) + return ret; + serviced++; + + } + + return serviced; +} +EXPORT_SYMBOL_GPL(wm_adsp_handle_fw_event); + struct wm_coeff_parsed_coeff { int offset; int mem_type; @@ -1375,6 +1833,21 @@ static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data, adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); } +static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp, + const struct wm_coeff_parsed_coeff *coeff_blk, + unsigned int f_required, + unsigned int f_illegal) +{ + if ((coeff_blk->flags & f_illegal) || + ((coeff_blk->flags & f_required) != f_required)) { + adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", + coeff_blk->flags, coeff_blk->ctl_type); + return -EINVAL; + } + + return 0; +} + static int wm_adsp_parse_coeff(struct wm_adsp *dsp, const struct wmfw_region *region) { @@ -1391,6 +1864,29 @@ static int wm_adsp_parse_coeff(struct wm_adsp *dsp, switch (coeff_blk.ctl_type) { case SNDRV_CTL_ELEM_TYPE_BYTES: break; + case WMFW_CTL_TYPE_ACKED: + if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) + continue; /* ignore */ + + ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + case WMFW_CTL_TYPE_HOSTEVENT: + case WMFW_CTL_TYPE_FWEVENT: + ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, + WMFW_CTL_FLAG_SYS | + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; default: adsp_err(dsp, "Unknown control type: %d\n", coeff_blk.ctl_type); @@ -1405,7 +1901,8 @@ static int wm_adsp_parse_coeff(struct wm_adsp *dsp, coeff_blk.len, coeff_blk.name, coeff_blk.name_len, - coeff_blk.flags); + coeff_blk.flags, + coeff_blk.ctl_type); if (ret < 0) adsp_err(dsp, "Failed to create control: %.*s, %d\n", coeff_blk.name_len, coeff_blk.name, ret); @@ -1427,7 +1924,7 @@ static int wm_adsp_load(struct wm_adsp *dsp) const struct wmfw_region *region; const struct wm_adsp_region *mem; const char *region_name; - char *file, *text; + char *file, *text = NULL; struct wm_adsp_buf *buf; unsigned int reg; int regions = 0; @@ -1437,17 +1934,14 @@ static int wm_adsp_load(struct wm_adsp *dsp) if (file == NULL) return -ENOMEM; - if (dsp->wmfw_file) - memcpy(file, dsp->wmfw_file, PAGE_SIZE); + if (dsp->firmwares[dsp->fw].fullname) + snprintf(file, PAGE_SIZE, "%s", dsp->firmwares[dsp->fw].file); else - snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", - dsp->part, dsp->num, - wm_adsp_fw[dsp->fw].file); + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, + dsp->num, dsp->firmwares[dsp->fw].file); file[PAGE_SIZE - 1] = '\0'; - mutex_lock(dsp->fw_lock); ret = request_firmware(&firmware, file, dsp->dev); - mutex_unlock(dsp->fw_lock); if (ret != 0) { adsp_err(dsp, "Failed to request '%s'\n", file); goto out; @@ -1468,18 +1962,42 @@ static int wm_adsp_load(struct wm_adsp *dsp) goto out_fw; } - switch (header->ver) { - case 0: - adsp_warn(dsp, "%s: Depreciated file format %d\n", - file, header->ver); + switch (dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + switch (header->ver) { + case 0: + adsp_warn(dsp, "%s: Deprecated file format %d\n", + file, header->ver); + break; + case 1: + case 2: + break; + default: + adsp_err(dsp, "%s: unknown file format %d\n", + file, header->ver); + goto out_fw; + } break; - case 1: - case 2: - break; - default: - adsp_err(dsp, "%s: unknown file format %d\n", - file, header->ver); - goto out_fw; + case WMFW_HALO: + switch (header->ver) { + case 1: + case 2: + /* + * we are required to load these for testing purposes + * but this format is not allowed for production fw + */ + adsp_warn(dsp, + "%s: Not a production firmware (deprecated file format %d)\n", + file, header->ver); + break; + case 3: + break; + default: + adsp_err(dsp, "%s: unknown file format %d\n", + file, header->ver); + goto out_fw; + } } adsp_info(dsp, "Firmware version: %d\n", header->ver); @@ -1504,6 +2022,7 @@ static int wm_adsp_load(struct wm_adsp *dsp) le32_to_cpu(adsp1_sizes->zm)); break; + case WMFW_HALO: case WMFW_ADSP2: pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer); adsp2_sizes = (void *)&(header[1]); @@ -1533,7 +2052,7 @@ static int wm_adsp_load(struct wm_adsp *dsp) le64_to_cpu(footer->timestamp)); while (pos < firmware->size && - pos - firmware->size > sizeof(*region)) { + sizeof(*region) < firmware->size - pos) { region = (void *)&(firmware->data[pos]); region_name = "Unknown"; reg = 0; @@ -1564,24 +2083,15 @@ static int wm_adsp_load(struct wm_adsp *dsp) reg = offset; break; case WMFW_ADSP1_PM: - region_name = "PM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; case WMFW_ADSP1_DM: - region_name = "DM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; case WMFW_ADSP2_XM: - region_name = "XM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; case WMFW_ADSP2_YM: - region_name = "YM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; case WMFW_ADSP1_ZM: - region_name = "ZM"; - reg = wm_adsp_region_to_reg(mem, offset); + case WMFW_HALO_PM_PACKED: + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + region_name = wm_adsp_mem_region_name(type); + reg = wm_adsp_region_to_reg(dsp, mem, offset); break; default: adsp_warn(dsp, @@ -1594,10 +2104,21 @@ static int wm_adsp_load(struct wm_adsp *dsp) regions, le32_to_cpu(region->len), offset, region_name); + if (le32_to_cpu(region->len) > + firmware->size - pos - sizeof(*region)) { + adsp_err(dsp, + "%s.%d: %s region len %d bytes exceeds file length %zu\n", + file, regions, region_name, + le32_to_cpu(region->len), firmware->size); + ret = -EINVAL; + goto out_fw; + } + if (text) { memcpy(text, region->data, le32_to_cpu(region->len)); adsp_info(dsp, "%s: %s\n", file, text); kfree(text); + text = NULL; } if (reg) { @@ -1656,6 +2177,7 @@ out_fw: regmap_async_complete(regmap); wm_adsp_buf_free(&buf_list); release_firmware(firmware); + kfree(text); out: kfree(file); @@ -1668,7 +2190,11 @@ static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl; list_for_each_entry(ctl, &dsp->ctl_list, list) { - if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] && + const char *fw_name; + + fw_name = wm_adsp_fw_enum[dsp->num - 1].texts[dsp->fw]; + + if (ctl->fw_name == fw_name && alg_region->alg == ctl->alg_region.alg && alg_region->type == ctl->alg_region.type) { ctl->alg_region.base = alg_region->base; @@ -1702,7 +2228,7 @@ static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs, } if (be32_to_cpu(val) != 0xbedead) - adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n", + adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", pos + len, be32_to_cpu(val)); alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA); @@ -1837,7 +2363,8 @@ static int wm_adsp1_setup_algs(struct wm_adsp *dsp) len -= be32_to_cpu(adsp1_alg[i].dm); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, - len, NULL, 0, 0); + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region DM with ID %x\n", be32_to_cpu(adsp1_alg[i].alg.id)); @@ -1857,7 +2384,8 @@ static int wm_adsp1_setup_algs(struct wm_adsp *dsp) len -= be32_to_cpu(adsp1_alg[i].zm); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, - len, NULL, 0, 0); + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", be32_to_cpu(adsp1_alg[i].alg.id)); @@ -1895,6 +2423,7 @@ static int wm_adsp2_setup_algs(struct wm_adsp *dsp) n_algs = be32_to_cpu(adsp2_id.n_algs); dsp->fw_id = be32_to_cpu(adsp2_id.fw.id); dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver); + dsp->fw_vendor_id = 0; adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, @@ -1912,13 +2441,21 @@ static int wm_adsp2_setup_algs(struct wm_adsp *dsp) if (IS_ERR(alg_region)) return PTR_ERR(alg_region); - alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, - adsp2_id.fw.id, adsp2_id.zm); - if (IS_ERR(alg_region)) - return PTR_ERR(alg_region); + switch (dsp->type) { + case WMFW_HALO: + pos = sizeof(adsp2_id); + len = sizeof(*adsp2_alg) * n_algs; + break; + default: + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, + adsp2_id.fw.id, adsp2_id.zm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); - pos = sizeof(adsp2_id) / 2; - len = (sizeof(*adsp2_alg) * n_algs) / 2; + pos = sizeof(adsp2_id) / 2; + len = (sizeof(*adsp2_alg) * n_algs) / 2; + break; + } adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len); if (IS_ERR(adsp2_alg)) @@ -1948,7 +2485,8 @@ static int wm_adsp2_setup_algs(struct wm_adsp *dsp) len -= be32_to_cpu(adsp2_alg[i].xm); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, - len, NULL, 0, 0); + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region XM with ID %x\n", be32_to_cpu(adsp2_alg[i].alg.id)); @@ -1968,13 +2506,18 @@ static int wm_adsp2_setup_algs(struct wm_adsp *dsp) len -= be32_to_cpu(adsp2_alg[i].ym); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, - len, NULL, 0, 0); + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region YM with ID %x\n", be32_to_cpu(adsp2_alg[i].alg.id)); } } + /* no ZM on HALO */ + if (dsp->type == WMFW_HALO) + continue; + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, adsp2_alg[i].alg.id, adsp2_alg[i].zm); @@ -1988,7 +2531,8 @@ static int wm_adsp2_setup_algs(struct wm_adsp *dsp) len -= be32_to_cpu(adsp2_alg[i].zm); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, - len, NULL, 0, 0); + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", be32_to_cpu(adsp2_alg[i].alg.id)); @@ -2001,6 +2545,125 @@ out: return ret; } +static int wm_halo_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_halo_id_hdr halo_id; + struct wmfw_halo_alg_hdr *halo_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len, block_rev; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, + sizeof(halo_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", + ret); + return ret; + } + + block_rev = be32_to_cpu(halo_id.fw.block_rev) >> 16; + switch (block_rev) { + case 3: + break; + default: + adsp_err(dsp, "Unknown firmware ID block version 0x%x\n", + block_rev); + return -EINVAL; + } + + n_algs = be32_to_cpu(halo_id.n_algs); + dsp->fw_id = be32_to_cpu(halo_id.fw.id); + dsp->fw_id_version = be32_to_cpu(halo_id.fw.ver); + dsp->fw_vendor_id = be32_to_cpu(halo_id.fw.vendor_id); + adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %zu algorithms\n", + dsp->fw_id, + dsp->fw_vendor_id, + (dsp->fw_id_version & 0xff0000) >> 16, + (dsp->fw_id_version & 0xff00) >> 8, + dsp->fw_id_version & 0xff, + n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + halo_id.fw.id, halo_id.xm_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_HALO_XM_PACKED, + halo_id.fw.id, halo_id.xm_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + halo_id.fw.id, halo_id.ym_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_HALO_YM_PACKED, + halo_id.fw.id, halo_id.ym_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + pos = sizeof(halo_id); + len = (sizeof(*halo_alg) * n_algs); + + halo_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len); + if (IS_ERR(halo_alg)) + return PTR_ERR(halo_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, + "%d: ID %x v%d.%d.%d XM@%x YM@%x\n", + i, be32_to_cpu(halo_alg[i].alg.id), + (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(halo_alg[i].alg.ver) & 0xff, + be32_to_cpu(halo_alg[i].xm_base), + be32_to_cpu(halo_alg[i].ym_base)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + halo_alg[i].alg.id, + halo_alg[i].xm_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_HALO_XM_PACKED, + halo_alg[i].alg.id, + halo_alg[i].xm_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + halo_alg[i].alg.id, + halo_alg[i].ym_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_HALO_YM_PACKED, + halo_alg[i].alg.id, + halo_alg[i].ym_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + } + +out: + kfree(halo_alg); + return ret; +} + static int wm_adsp_load_coeff(struct wm_adsp *dsp) { LIST_HEAD(buf_list); @@ -2015,21 +2678,26 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) char *file; struct wm_adsp_buf *buf; + if (dsp->firmwares[dsp->fw].binfile && + !(strcmp(dsp->firmwares[dsp->fw].binfile, "None"))) + return 0; + file = kzalloc(PAGE_SIZE, GFP_KERNEL); if (file == NULL) return -ENOMEM; - if (dsp->bin_file) - memcpy(file, dsp->bin_file, PAGE_SIZE); + if (dsp->firmwares[dsp->fw].fullname && dsp->firmwares[dsp->fw].binfile) + snprintf(file, PAGE_SIZE, "%s", + dsp->firmwares[dsp->fw].binfile); + else if (dsp->firmwares[dsp->fw].binfile) + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, + dsp->num, dsp->firmwares[dsp->fw].binfile); else - snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", - dsp->part, dsp->num, - wm_adsp_fw[dsp->fw].file); + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, + dsp->num, dsp->firmwares[dsp->fw].file); file[PAGE_SIZE - 1] = '\0'; - mutex_lock(dsp->fw_lock); ret = request_firmware(&firmware, file, dsp->dev); - mutex_unlock(dsp->fw_lock); if (ret != 0) { adsp_warn(dsp, "Failed to request '%s'\n", file); ret = 0; @@ -2068,7 +2736,7 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) blocks = 0; while (pos < firmware->size && - pos - firmware->size > sizeof(*blk)) { + sizeof(*blk) < firmware->size - pos) { blk = (void *)(&firmware->data[pos]); type = le16_to_cpu(blk->type); @@ -2101,7 +2769,7 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) adsp_err(dsp, "No ZM\n"); break; } - reg = wm_adsp_region_to_reg(mem, 0); + reg = wm_adsp_region_to_reg(dsp, mem, 0); } else { region_name = "register"; @@ -2113,6 +2781,9 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) case WMFW_ADSP1_ZM: case WMFW_ADSP2_XM: case WMFW_ADSP2_YM: + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + case WMFW_HALO_PM_PACKED: adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", file, blocks, le32_to_cpu(blk->len), type, le32_to_cpu(blk->id)); @@ -2127,7 +2798,7 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) le32_to_cpu(blk->id)); if (alg_region) { reg = alg_region->base; - reg = wm_adsp_region_to_reg(mem, reg); + reg = wm_adsp_region_to_reg(dsp, mem, reg); reg += offset; } else { adsp_err(dsp, "No %x for algorithm %x\n", @@ -2142,6 +2813,17 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) } if (reg) { + if (le32_to_cpu(blk->len) > + firmware->size - pos - sizeof(*blk)) { + adsp_err(dsp, + "%s.%d: %s region len %d bytes exceeds file length %zu\n", + file, blocks, region_name, + le32_to_cpu(blk->len), + firmware->size); + ret = -EINVAL; + goto out_fw; + } + buf = wm_adsp_buf_alloc(blk->data, le32_to_cpu(blk->len), &buf_list); @@ -2207,7 +2889,7 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w, int ret; unsigned int val; - dsp->card = codec->component.card; + dsp->codec = codec; mutex_lock(&dsp->pwr_lock); @@ -2262,13 +2944,20 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w, if (ret != 0) goto err_ena; + dsp->booted = true; + /* Start the core running */ regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, ADSP1_CORE_ENA | ADSP1_START, ADSP1_CORE_ENA | ADSP1_START); + + dsp->running = true; break; case SND_SOC_DAPM_PRE_PMD: + dsp->running = false; + dsp->booted = false; + /* Halt the core */ regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, ADSP1_CORE_ENA | ADSP1_START, 0); @@ -2323,40 +3012,34 @@ static int wm_adsp2_ena(struct wm_adsp *dsp) switch (dsp->rev) { case 0: ret = regmap_update_bits_async(dsp->regmap, - dsp->base + ADSP2_CONTROL, - ADSP2_SYS_ENA, ADSP2_SYS_ENA); + dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, ADSP2_SYS_ENA); if (ret != 0) return ret; - - /* Wait for the RAM to start, should be near instantaneous */ - for (count = 0; count < 10; ++count) { - ret = regmap_read(dsp->regmap, - dsp->base + ADSP2_STATUS1, &val); - if (ret != 0) - return ret; - - if (val & ADSP2_RAM_RDY) - break; - - usleep_range(1000, 1010); - } - - if (!(val & ADSP2_RAM_RDY)) { - adsp_err(dsp, "Failed to start DSP RAM\n"); - return -EBUSY; - } - adsp_dbg(dsp, "RAM ready after %d polls\n", count); break; default: - ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, - ADSP2_MEM_ENA, ADSP2_MEM_ENA); + break; + } + /* Wait for the RAM to start, should be near instantaneous */ + for (count = 0; count < 10; ++count) { + ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); if (ret != 0) return ret; - break; + if (val & ADSP2_RAM_RDY) + break; + + usleep_range(250, 500); } + if (!(val & ADSP2_RAM_RDY)) { + adsp_err(dsp, "Failed to start DSP RAM\n"); + return -EBUSY; + } + + adsp_dbg(dsp, "RAM ready after %d polls\n", count); + return 0; } @@ -2369,10 +3052,15 @@ static void wm_adsp2_boot_work(struct work_struct *work) mutex_lock(&dsp->pwr_lock); - ret = wm_adsp2_ena(dsp); + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, ADSP2_MEM_ENA); if (ret != 0) goto err_mutex; + ret = wm_adsp2_ena(dsp); + if (ret != 0) + goto err_mem; + ret = wm_adsp_load(dsp); if (ret != 0) goto err_ena; @@ -2390,12 +3078,19 @@ static void wm_adsp2_boot_work(struct work_struct *work) if (ret != 0) goto err_ena; - /* Sync set controls */ - ret = wm_coeff_sync_controls(dsp); - if (ret != 0) - goto err_ena; + switch (dsp->rev) { + case 0: + /* Turn DSP back off until we are ready to run */ + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, 0); + if (ret != 0) + goto err_ena; + break; + default: + break; + } - dsp->running = true; + dsp->booted = true; mutex_unlock(&dsp->pwr_lock); @@ -2404,20 +3099,268 @@ static void wm_adsp2_boot_work(struct work_struct *work) err_ena: regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); +err_mem: + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); err_mutex: mutex_unlock(&dsp->pwr_lock); } +static int wm_halo_set_rate_block(struct wm_adsp *dsp, + unsigned int rate_base, + unsigned int n_rates, + const u8 *rate_cache) +{ + unsigned int addr = dsp->base + rate_base, val; + int ret, i; + + mutex_lock(dsp->rate_lock); + + for (i = 0; i < n_rates; ++i) { + val = rate_cache[i] << HALO_DSP_RATE_SHIFT; + + ret = regmap_update_bits(dsp->regmap, + addr + (i * 8), + HALO_DSP_RATE_MASK, + val); + if (ret) { + adsp_err(dsp, "Failed to set rate: %d\n", ret); + mutex_unlock(dsp->rate_lock); + return ret; + } + + adsp_dbg(dsp, "Set rate %d to 0x%x\n", i, val); + } + + udelay(300); + + mutex_unlock(dsp->rate_lock); + + return 0; +} + +static int wm_halo_clear_stream_arb(struct wm_adsp *dsp) +{ + struct regmap *regmap = dsp->regmap; + unsigned int dspbase = dsp->base, reg, begin, end; + u32 values[3] = {0, 0, 0}; + int ret; + + /* disable stream arbiter masters */ + for (reg = dspbase + HALO_STREAM_ARB_MSTR0_CONFIG_0; + reg <= dspbase + HALO_STREAM_ARB_MSTR5_CONFIG_0; + reg += 0x10) { + ret = regmap_update_bits(regmap, reg, + HALO_STREAM_ARB_MSTR_EN_MASK, 0); + if (ret) + goto error; + } + + /* clear stream arbiter masters */ + for (reg = dspbase + HALO_STREAM_ARB_MSTR0_CONFIG_0; + reg <= dspbase + HALO_STREAM_ARB_MSTR5_CONFIG_0; + reg += 0x10) { + ret = regmap_bulk_write(regmap, reg, values, 3); + if (ret) + goto error; + } + + /* clear stream arbiter channel configs */ + begin = dspbase + HALO_STREAM_ARB_TX1_CONFIG_0; + end = begin + dsp->n_tx_channels * 0x8; + for (reg = begin; reg < end; reg += 0x8) { + ret = regmap_write(regmap, reg, + HALO_STREAM_ARB_MSTR_SEL_DEFAULT); + if (ret) + goto error; + } + begin = dspbase + HALO_STREAM_ARB_RX1_CONFIG_0; + end = begin + dsp->n_rx_channels * 0x8; + for (reg = begin; reg < end; reg += 0x8) { + ret = regmap_write(regmap, reg, + HALO_STREAM_ARB_MSTR_SEL_DEFAULT); + if (ret) + goto error; + } + + /* clear stream arbiter interrupt registers */ + values[0] = HALO_STREAM_ARB_MSTR_SEL_DEFAULT; + for (reg = dspbase + HALO_STREAM_ARB_IRQ0_CONFIG_0; + reg <= dspbase + HALO_STREAM_ARB_IRQ7_CONFIG_1; + reg += 0x10) { + ret = regmap_bulk_write(regmap, reg, values, 2); + if (ret) + goto error; + } + return 0; + +error: + adsp_err(dsp, + "Error while clearing stream arbiter config (reg 0x%x): %d\n", + reg, ret); + return ret; +} + +static int wm_halo_configure_mpu(struct wm_adsp *dsp) +{ + struct regmap *regmap = dsp->regmap; + int i = 0, len = 0, ret; + unsigned int sysinfo_base = dsp->base_sysinfo, dsp_base = dsp->base; + unsigned int xm_sz, xm_bank_sz, ym_sz, ym_bank_sz; + unsigned int xm_acc_cfg, ym_acc_cfg; + unsigned int lock_cfg; + + ret = regmap_read(regmap, sysinfo_base + HALO_SYS_INFO_XM_BANK_SIZE, + &xm_bank_sz); + if (ret) { + adsp_err(dsp, "Failed to read XM bank size.\n"); + goto err; + } + + if (!xm_bank_sz) { + adsp_err(dsp, "Failed to configure MPU (XM_BANK_SIZE = 0)\n"); + goto err; + } + + ret = regmap_read(regmap, sysinfo_base + HALO_SYS_INFO_YM_BANK_SIZE, + &ym_bank_sz); + if (ret) { + adsp_err(dsp, "Failed to read YM bank size.\n"); + goto err; + } + + if (!ym_bank_sz) { + adsp_err(dsp, "Failed to configure MPU (YM_BANK_SIZE = 0)\n"); + goto err; + } + + ret = regmap_read(regmap, sysinfo_base + HALO_SYS_INFO_XM_SRAM_SIZE, + &xm_sz); + if (ret) { + adsp_err(dsp, "Failed to read XM size.\n"); + goto err; + } + + ret = regmap_read(regmap, sysinfo_base + HALO_SYS_INFO_YM_SRAM_SIZE, + &ym_sz); + if (ret) { + adsp_err(dsp, "Failed to read YM size.\n"); + goto err; + } + + adsp_dbg(dsp, + "XM size 0x%x XM bank size 0x%x YM size 0x%x YM bank size 0x%x\n", + xm_sz, xm_bank_sz, ym_sz, ym_bank_sz); + + /* calculate amount of banks to unlock */ + xm_acc_cfg = (1 << (xm_sz / xm_bank_sz)) - 1; + ym_acc_cfg = (1 << (ym_sz / ym_bank_sz)) - 1; + + /* unlock MPU */ + ret = regmap_write(regmap, dsp_base + HALO_MPU_LOCK_CONFIG, + HALO_MPU_UNLOCK_CODE_0); + if (ret) { + adsp_err(dsp, "Error while unlocking MPU: %d\n", ret); + goto err; + } + + ret = regmap_write(regmap, dsp_base + HALO_MPU_LOCK_CONFIG, + HALO_MPU_UNLOCK_CODE_1); + if (ret) { + adsp_err(dsp, "Error while unlocking MPU: %d\n", ret); + goto err; + } + + adsp_dbg(dsp, "Unlocking XM (cfg: %x) and YM (cfg: %x)", + xm_acc_cfg, ym_acc_cfg); + + /* unlock XMEM and YMEM */ + ret = regmap_write(regmap, dsp_base + HALO_MPU_XMEM_ACCESS_0, + xm_acc_cfg); + if (ret) + goto err; + + ret = regmap_write(regmap, dsp_base + HALO_MPU_YMEM_ACCESS_0, + ym_acc_cfg); + if (ret) + goto err; + + len = sizeof(halo_mpu_access) / sizeof(halo_mpu_access[0]); + /* configure all other banks */ + lock_cfg = (dsp->unlock_all) ? 0xFFFFFFFF : 0; + for (i = 0; i < len; i++) { /* TODO: think if can be done without LUT */ + ret = regmap_write(regmap, dsp_base + halo_mpu_access[i], + lock_cfg); + if (ret) + goto err; + } + + /* lock MPU */ + ret = regmap_write(regmap, dsp_base + HALO_MPU_LOCK_CONFIG, 0); + if (ret) + adsp_err(dsp, "Error while locking MPU: %d\n", ret); + +err: + return ret; +} + +static void wm_halo_boot_work(struct work_struct *work) +{ + struct wm_adsp *dsp = container_of(work, + struct wm_adsp, + boot_work); + int ret; + + mutex_lock(&dsp->pwr_lock); + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err; + + switch (dsp->fw_ver) { + case 1: + case 2: + ret = wm_adsp2_setup_algs(dsp); + if (ret != 0) + goto err; + break; + default: + ret = wm_halo_setup_algs(dsp); + if (ret != 0) + goto err; + break; + } + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err; + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err; + + dsp->booted = true; + +err: + mutex_unlock(&dsp->pwr_lock); +} + static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq) { int ret; switch (dsp->rev) { case 0: - ret = regmap_update_bits(dsp->regmap, - dsp->base + ADSP2_CLOCKING, - ADSP2_CLK_SEL_MASK, - freq << ADSP2_CLK_SEL_SHIFT); + ret = regmap_update_bits_async(dsp->regmap, + dsp->base + ADSP2_CLOCKING, + ADSP2_CLK_SEL_MASK, + freq << ADSP2_CLK_SEL_SHIFT); if (ret) { adsp_err(dsp, "Failed to set clock rate: %d\n", ret); return; @@ -2429,31 +3372,49 @@ static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq) } } -int wm_adsp2_early_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event, - unsigned int freq) +int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) { - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); - struct wm_adsp *dsp = &dsps[w->shift]; + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); - dsp->card = codec->component.card; - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - wm_adsp2_set_dspclk(dsp, freq); - - queue_work(system_unbound_wq, &dsp->boot_work); - break; - default: - break; - } + ucontrol->value.integer.value[0] = dsp->preloaded; return 0; } -EXPORT_SYMBOL_GPL(wm_adsp2_early_event); +EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get); -static inline void wm_adsp_stop_watchdog(struct wm_adsp *dsp) +int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + char preload[32]; + + if (codec->component.name_prefix) + snprintf(preload, ARRAY_SIZE(preload), "%s DSP%u%s Preload", + codec->component.name_prefix, mc->shift, dsp->suffix); + else + snprintf(preload, ARRAY_SIZE(preload), "DSP%u%s Preload", + mc->shift, dsp->suffix); + + dsp->preloaded = ucontrol->value.integer.value[0]; + + if (ucontrol->value.integer.value[0]) + snd_soc_dapm_force_enable_pin(dapm, preload); + else + snd_soc_dapm_disable_pin(dapm, preload); + + snd_soc_dapm_sync(dapm); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put); + +static void wm_adsp_stop_watchdog(struct wm_adsp *dsp) { switch (dsp->rev) { case 0: @@ -2465,21 +3426,116 @@ static inline void wm_adsp_stop_watchdog(struct wm_adsp *dsp) } } +int wm_adsp2_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event, + unsigned int freq) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + wm_adsp2_set_dspclk(dsp, freq); + queue_work(system_unbound_wq, &dsp->boot_work); + break; + case SND_SOC_DAPM_PRE_PMD: + mutex_lock(&dsp->pwr_lock); + + wm_adsp_debugfs_clear(dsp); + + dsp->fw_id = 0; + dsp->fw_id_version = 0; + + dsp->booted = false; + + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); + + list_for_each_entry(ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Shutdown complete\n"); + break; + default: + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_early_event); + +int wm_halo_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + queue_work(system_unbound_wq, &dsp->boot_work); + break; + case SND_SOC_DAPM_PRE_PMD: + mutex_lock(&dsp->pwr_lock); + + wm_adsp_debugfs_clear(dsp); + + dsp->fw_id = 0; + dsp->fw_id_version = 0; + + dsp->booted = false; + + list_for_each_entry(ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Shutdown complete\n"); + break; + default: + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_halo_early_event); + int wm_adsp2_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); struct wm_adsp *dsp = &dsps[w->shift]; - struct wm_coeff_ctl *ctl; int ret; switch (event) { case SND_SOC_DAPM_POST_PMU: flush_work(&dsp->boot_work); - if (!dsp->running) - return -EIO; + mutex_lock(&dsp->pwr_lock); + + if (!dsp->booted) { + ret = -EIO; + goto err; + } + + ret = wm_adsp2_ena(dsp); + if (ret != 0) + goto err; + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err; wm_adsp2_lock(dsp, dsp->lock_regions); @@ -2490,16 +3546,24 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, if (ret != 0) goto err; - mutex_lock(&dsp->pwr_lock); - - if (wm_adsp_fw[dsp->fw].num_caps != 0) + if (dsp->firmwares[dsp->fw].num_caps != 0) { ret = wm_adsp_buffer_init(dsp); + if (ret < 0) + goto err; + } + + dsp->running = true; mutex_unlock(&dsp->pwr_lock); break; case SND_SOC_DAPM_PRE_PMD: + /* Tell the firmware to cleanup */ + wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN); + + wm_adsp_stop_watchdog(dsp); + /* Log firmware state, it can be useful for analysis */ switch (dsp->rev) { case 0: @@ -2512,20 +3576,15 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, mutex_lock(&dsp->pwr_lock); - wm_adsp_stop_watchdog(dsp); - wm_adsp_debugfs_clear(dsp); - - dsp->fw_id = 0; - dsp->fw_id_version = 0; dsp->running = false; + regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, 0); + + /* Make sure DMAs are quiesced */ switch (dsp->rev) { case 0: - regmap_update_bits(dsp->regmap, - dsp->base + ADSP2_CONTROL, - ADSP2_CORE_ENA | ADSP2_START, 0); - - /* Make sure DMAs are quiesced */ regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); regmap_write(dsp->regmap, @@ -2538,36 +3597,21 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, ADSP2_SYS_ENA, 0); break; default: - regmap_update_bits(dsp->regmap, - dsp->base + ADSP2_CONTROL, - ADSP2_CORE_ENA | ADSP2_START, 0); - - /* Make sure DMAs are quiesced */ regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); - - regmap_update_bits(dsp->regmap, - dsp->base + ADSP2_CONTROL, - ADSP2_SYS_ENA | ADSP2_MEM_ENA, 0); - break; } - list_for_each_entry(ctl, &dsp->ctl_list, list) - ctl->enabled = 0; - - wm_adsp_free_alg_regions(dsp); - - if (wm_adsp_fw[dsp->fw].num_caps != 0) + if (dsp->firmwares[dsp->fw].num_caps != 0) wm_adsp_buffer_free(dsp); mutex_unlock(&dsp->pwr_lock); - adsp_dbg(dsp, "Shutdown complete\n"); + adsp_dbg(dsp, "Execution stopped\n"); break; default: @@ -2578,19 +3622,156 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, err: regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); + mutex_unlock(&dsp->pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp2_event); -int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec) +int wm_halo_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event) { - dsp->codec = codec; + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + flush_work(&dsp->boot_work); + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->booted) { + ret = -EIO; + goto err; + } + + ret = regmap_update_bits(dsp->regmap, + dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_RESET, HALO_CORE_RESET); + if (ret != 0) { + adsp_err(dsp, "Error while resetting core: %d\n", ret); + return ret; + } + + adsp_dbg(dsp, "Setting RX rates.\n"); + ret = wm_halo_set_rate_block(dsp, HALO_SAMPLE_RATE_RX1, + dsp->n_rx_channels, + dsp->rx_rate_cache); + if (ret) { + adsp_err(dsp, "Failed to set RX rates.\n"); + goto err; + } + + adsp_dbg(dsp, "Setting TX rates.\n"); + ret = wm_halo_set_rate_block(dsp, HALO_SAMPLE_RATE_TX1, + dsp->n_tx_channels, + dsp->tx_rate_cache); + if (ret) { + adsp_err(dsp, "Failed to set TX rates.\n"); + goto err; + } + + ret = wm_halo_clear_stream_arb(dsp); + if (ret != 0) + goto err; + + /* disable NMI */ + ret = regmap_write(dsp->regmap, + dsp->base + HALO_INTP_CTL_NMI_CONTROL, + 0); + if (ret != 0) { + adsp_err(dsp, "Error while disabling NMI: %d\n", ret); + goto err; + } + + ret = wm_halo_configure_mpu(dsp); + if (ret != 0) + goto err; + + ret = regmap_update_bits(dsp->regmap, + dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, HALO_CORE_EN); + if (ret != 0) + goto err; + + if (wm_adsp_fw[dsp->fw].num_caps != 0) { + ret = wm_adsp_buffer_init(dsp); + if (ret < 0) + goto err; + } + + dsp->running = true; + + mutex_unlock(&dsp->pwr_lock); + break; + case SND_SOC_DAPM_PRE_PMD: + /* Tell the firmware to cleanup */ + wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN); + + /* Log firmware state, it can be useful for analysis */ + wm_halo_show_fw_status(dsp); + + mutex_lock(&dsp->pwr_lock); + + dsp->running = false; + + regmap_update_bits(dsp->regmap, + dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, 0); + + wm_halo_clear_stream_arb(dsp); + + if (wm_adsp_fw[dsp->fw].num_caps != 0) + wm_adsp_buffer_free(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_info(dsp, "Execution stopped\n"); + break; + default: + break; + } + + return 0; +err: + mutex_unlock(&dsp->pwr_lock); + regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, 0); + return ret; +} +EXPORT_SYMBOL_GPL(wm_halo_event); + +int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec, + bool ao_dsp) +{ + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + char preload[32]; + int ret; + + if (codec->component.name_prefix) + snprintf(preload, ARRAY_SIZE(preload), "%s DSP%d%s Preload", + codec->component.name_prefix, dsp->num, dsp->suffix); + else + snprintf(preload, ARRAY_SIZE(preload), "DSP%d%s Preload", + dsp->num, dsp->suffix); + + snd_soc_dapm_disable_pin(dapm, preload); wm_adsp2_init_debugfs(dsp, codec); - return snd_soc_add_codec_controls(codec, - &wm_adsp_fw_controls[dsp->num - 1], - 1); + dsp->codec = codec; + + if (ao_dsp) + ret = snd_soc_add_codec_controls(codec, + &wm_adsp_ao_fw_controls[dsp->num - 1], + 1); + else + ret = snd_soc_add_codec_controls(codec, + &wm_adsp_fw_controls[dsp->num - 1], + 1); + + return ret; } EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe); @@ -2603,12 +3784,63 @@ int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec) EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove); #ifdef CONFIG_OF +static int wm_adsp_of_parse_caps(struct wm_adsp *dsp, + struct device_node *np, + struct wm_adsp_fw_defs *fw) +{ + const char *prop = "cirrus,compr-caps"; + int i; + int len_prop; + u32 of_cap; + + if (!of_get_property(np, prop, &len_prop)) + return -EINVAL; + + len_prop /= sizeof(u32); + + if (len_prop < 5 || len_prop > 4 + MAX_NUM_SAMPLE_RATES) + return -EOVERFLOW; + + fw->num_caps = 1; + fw->caps = devm_kzalloc(dsp->dev, + sizeof(struct wm_adsp_fw_caps), + GFP_KERNEL); + if (!fw->caps) + return -ENOMEM; + + fw->caps->num_regions = ARRAY_SIZE(default_regions); + fw->caps->region_defs = devm_kzalloc(dsp->dev, + sizeof(default_regions), + GFP_KERNEL); + if (!fw->caps->region_defs) + return -ENOMEM; + + memcpy(fw->caps->region_defs, default_regions, sizeof(default_regions)); + + of_property_read_u32_index(np, prop, 0, &of_cap); + fw->caps->id = of_cap; + of_property_read_u32_index(np, prop, 1, &of_cap); + fw->caps->desc.max_ch = of_cap; + of_property_read_u32_index(np, prop, 2, &of_cap); + fw->caps->desc.formats = of_cap; + of_property_read_u32_index(np, prop, 3, &of_cap); + fw->compr_direction = of_cap; + + for (i = 4; i < len_prop; ++i) { + of_property_read_u32_index(np, prop, i, &of_cap); + fw->caps->desc.sample_rates[i - 4] = of_cap; + } + fw->caps->desc.num_sample_rates = i - 4; + + return 0; +} static int wm_adsp_of_parse_firmware(struct wm_adsp *dsp, struct device_node *np) { struct device_node *fws = of_get_child_by_name(np, "firmware"); struct device_node *fw = NULL; + const char **ctl_names; int ret; int i; @@ -2616,31 +3848,56 @@ static int wm_adsp_of_parse_firmware(struct wm_adsp *dsp, return 0; i = 0; - while ((fw = of_get_next_child(fws, fw)) != NULL) { + while ((fw = of_get_next_child(fws, fw)) != NULL) + i++; - ret = of_property_read_string(fw, "wlf,wmfw-file", - &dsp->wmfw_file); + if (i == 0) + return 0; + + dsp->num_firmwares = i; + + dsp->firmwares = devm_kzalloc(dsp->dev, + i * sizeof(struct wm_adsp_fw_defs), + GFP_KERNEL); + if (!dsp->firmwares) + return -ENOMEM; + + ctl_names = devm_kzalloc(dsp->dev, + i * sizeof(const char *), + GFP_KERNEL); + if (!ctl_names) + return -ENOMEM; + + i = 0; + while ((fw = of_get_next_child(fws, fw)) != NULL) { + ctl_names[i] = fw->name; + + ret = of_property_read_string(fw, "cirrus,wmfw-file", + &dsp->firmwares[i].file); if (ret < 0) { - adsp_err(dsp, - "Firmware filename missing/malformed: %d\n", - ret); + dev_err(dsp->dev, + "Firmware filename missing/malformed: %d\n", + ret); return ret; } - ret = of_property_read_string(fw, "wlf,bin-file", - &dsp->bin_file); + ret = of_property_read_string(fw, "cirrus,bin-file", + &dsp->firmwares[i].binfile); if (ret < 0) - adsp_err(dsp, - "Adsp bin file name missing/malformed: %d\n", - ret); + dsp->firmwares[i].binfile = NULL; + + dsp->firmwares[i].fullname = + of_property_read_bool(fw, "cirrus,full-name"); + + wm_adsp_of_parse_caps(dsp, fw, &dsp->firmwares[i]); - adsp_info(dsp, - "DSP FW name %s,Bin file name: %s\n", - dsp->wmfw_file, dsp->bin_file); i++; } - return 0; + wm_adsp_fw_enum[dsp->num - 1].items = dsp->num_firmwares; + wm_adsp_fw_enum[dsp->num - 1].texts = ctl_names; + + return dsp->num_firmwares; } static int wm_adsp_of_parse_adsp(struct wm_adsp *dsp) @@ -2657,9 +3914,9 @@ static int wm_adsp_of_parse_adsp(struct wm_adsp *dsp) while ((core = of_get_next_child(np, core)) != NULL) { ret = of_property_read_u32(core, "reg", &addr); if (ret < 0) { - adsp_err(dsp, - "Failed to get ADSP base address: %d\n", - ret); + dev_err(dsp->dev, + "Failed to get ADSP base address: %d\n", + ret); return ret; } @@ -2672,23 +3929,23 @@ static int wm_adsp_of_parse_adsp(struct wm_adsp *dsp) return wm_adsp_of_parse_firmware(dsp, core); } - #else static inline int wm_adsp_of_parse_adsp(struct wm_adsp *dsp) { return 0; } #endif -int wm_adsp2_init(struct wm_adsp *dsp, struct mutex *fw_lock) + +int wm_adsp2_init(struct wm_adsp *dsp) { int ret; switch (dsp->rev) { case 0: /* - * Disable the DSP memory by default when in reset for a small - * power saving. - */ + * Disable the DSP memory by default when in reset for a small + * power saving. + */ ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_MEM_ENA, 0); if (ret) { @@ -2707,15 +3964,38 @@ int wm_adsp2_init(struct wm_adsp *dsp, struct mutex *fw_lock) mutex_init(&dsp->pwr_lock); - dsp->fw_lock = fw_lock; - - if (dsp->dev->of_node) - wm_adsp_of_parse_adsp(dsp); + if (!dsp->dev->of_node || wm_adsp_of_parse_adsp(dsp) <= 0) { + dsp->num_firmwares = ARRAY_SIZE(wm_adsp_fw); + dsp->firmwares = wm_adsp_fw; + } return 0; } EXPORT_SYMBOL_GPL(wm_adsp2_init); +int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock) +{ + INIT_LIST_HEAD(&dsp->alg_regions); + INIT_LIST_HEAD(&dsp->ctl_list); + INIT_WORK(&dsp->boot_work, wm_halo_boot_work); + + mutex_init(&dsp->pwr_lock); + + dsp->rate_lock = rate_lock; + dsp->rx_rate_cache = kcalloc(dsp->n_rx_channels, sizeof(u8), + GFP_KERNEL); + dsp->tx_rate_cache = kcalloc(dsp->n_tx_channels, sizeof(u8), + GFP_KERNEL); + + if (!dsp->dev->of_node || wm_adsp_of_parse_adsp(dsp) <= 0) { + dsp->num_firmwares = ARRAY_SIZE(wm_adsp_fw); + dsp->firmwares = wm_adsp_fw; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_halo_init); + void wm_adsp2_remove(struct wm_adsp *dsp) { struct wm_coeff_ctl *ctl; @@ -2726,6 +4006,9 @@ void wm_adsp2_remove(struct wm_adsp *dsp) list_del(&ctl->list); wm_adsp_free_ctl_blk(ctl); } + + kfree(dsp->rx_rate_cache); + kfree(dsp->tx_rate_cache); } EXPORT_SYMBOL_GPL(wm_adsp2_remove); @@ -2774,13 +4057,13 @@ int wm_adsp_compr_open(struct wm_adsp *dsp, mutex_lock(&dsp->pwr_lock); - if (wm_adsp_fw[dsp->fw].num_caps == 0) { + if (dsp->firmwares[dsp->fw].num_caps == 0) { adsp_err(dsp, "Firmware does not support compressed API\n"); ret = -ENXIO; goto out; } - if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) { + if (dsp->firmwares[dsp->fw].compr_direction != stream->direction) { adsp_err(dsp, "Firmware does not support stream direction\n"); ret = -EINVAL; goto out; @@ -2855,8 +4138,8 @@ static int wm_adsp_compr_check_params(struct snd_compr_stream *stream, return -EINVAL; } - for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) { - caps = &wm_adsp_fw[dsp->fw].caps[i]; + for (i = 0; i < dsp->firmwares[dsp->fw].num_caps; i++) { + caps = &dsp->firmwares[dsp->fw].caps[i]; desc = &caps->desc; if (caps->id != params->codec.id) @@ -2920,15 +4203,16 @@ int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, struct snd_compr_caps *caps) { struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; int fw = compr->dsp->fw; int i; - if (wm_adsp_fw[fw].caps) { - for (i = 0; i < wm_adsp_fw[fw].num_caps; i++) - caps->codecs[i] = wm_adsp_fw[fw].caps[i].id; + if (dsp->firmwares[fw].caps) { + for (i = 0; i < dsp->firmwares[fw].num_caps; i++) + caps->codecs[i] = dsp->firmwares[fw].caps[i].id; caps->num_codecs = i; - caps->direction = wm_adsp_fw[fw].compr_direction; + caps->direction = dsp->firmwares[fw].compr_direction; caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE; caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE; @@ -2951,7 +4235,7 @@ static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type, if (!mem) return -EINVAL; - reg = wm_adsp_region_to_reg(mem, mem_addr); + reg = wm_adsp_region_to_reg(dsp, mem, mem_addr); ret = regmap_raw_read(dsp->regmap, reg, data, sizeof(*data) * num_words); @@ -2979,7 +4263,7 @@ static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type, if (!mem) return -EINVAL; - reg = wm_adsp_region_to_reg(mem, mem_addr); + reg = wm_adsp_region_to_reg(dsp, mem, mem_addr); data = cpu_to_be32(data & 0x00ffffffu); @@ -3008,7 +4292,19 @@ static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf) int i, ret, two_bufs = 0; alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id); - xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32); + switch (dsp->type) { + case WMFW_ADSP2: + xmalg = sizeof(struct wm_adsp_system_config_xm_hdr); + xmalg /= sizeof(__be32); + break; + case WMFW_HALO: + xmalg = sizeof(struct wm_halo_system_config_xm_hdr); + xmalg /= sizeof(__be32); + break; + default: + WARN(1, "Unknown DSP type"); + return -ENODEV; + } addr = alg_region->base + xmalg + ALG_XM_FIELD(magic); ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic); @@ -3055,7 +4351,8 @@ static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf) static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf) { - const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps; + struct wm_adsp *dsp = buf->dsp; + const struct wm_adsp_fw_caps *caps = dsp->firmwares[dsp->fw].caps; struct wm_adsp_buffer_region *region; u32 offset = 0; int i, ret; @@ -3111,7 +4408,7 @@ static int wm_adsp_buffer_init(struct wm_adsp *dsp) if (ret == 1) two_bufs = 1; - buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions, + buf->regions = kcalloc(dsp->firmwares[dsp->fw].caps->num_regions, sizeof(*buf->regions), GFP_KERNEL); if (!buf->regions) { ret = -ENOMEM; @@ -3245,7 +4542,8 @@ EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger); static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf) { - int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1; + struct wm_adsp *dsp = buf->dsp; + int last_region = dsp->firmwares[dsp->fw].caps->num_regions - 1; return buf->regions[last_region].cumulative_size; } @@ -3393,17 +4691,10 @@ int wm_adsp_compr_pointer(struct snd_compr_stream *stream, mutex_lock(&dsp->pwr_lock); - tstamp->copied_total = compr->copied_total; - tstamp->sampling_rate = compr->sample_rate; - buf = compr->buf; - if (!compr->buf) { - ret = -ENXIO; - goto out; - } - - if (compr->buf->error) { + if (!compr->buf || compr->buf->error) { + snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN); ret = -EIO; goto out; } @@ -3421,8 +4712,12 @@ int wm_adsp_compr_pointer(struct snd_compr_stream *stream, */ if (buf->avail < wm_adsp_compr_frag_words(compr)) { ret = wm_adsp_buffer_get_error(buf); - if (ret < 0) + if (ret < 0) { + if (compr->buf->error) + snd_compr_stop_error(stream, + SNDRV_PCM_STATE_XRUN); goto out; + } ret = wm_adsp_buffer_reenable_irq(buf); if (ret < 0) { @@ -3434,16 +4729,13 @@ int wm_adsp_compr_pointer(struct snd_compr_stream *stream, } } + tstamp->copied_total = compr->copied_total; tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE; + tstamp->sampling_rate = compr->sample_rate; out: mutex_unlock(&dsp->pwr_lock); - /* On error get user-space to issue a read so it can detect the error */ - if (ret < 0) - tstamp->copied_total += wm_adsp_compr_frag_words(compr) * - WM_ADSP_DATA_WORD_SIZE; - return ret; } EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer); @@ -3451,6 +4743,7 @@ EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer); static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target) { struct wm_adsp_compr_buf *buf = compr->buf; + struct wm_adsp *dsp = buf->dsp; u8 *pack_in = (u8 *)compr->raw_buf; u8 *pack_out = (u8 *)compr->raw_buf; unsigned int adsp_addr; @@ -3458,11 +4751,11 @@ static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target) int i, j, ret; /* Calculate read parameters */ - for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i) + for (i = 0; i < dsp->firmwares[dsp->fw].caps->num_regions; ++i) if (buf->read_index < buf->regions[i].cumulative_size) break; - if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions) + if (i == dsp->firmwares[dsp->fw].caps->num_regions) return -EINVAL; mem_type = buf->regions[i].mem_type; @@ -3520,11 +4813,10 @@ static int wm_adsp_compr_read(struct wm_adsp_compr *compr, adsp_dbg(dsp, "Requested read of %zu bytes\n", count); - if (!compr->buf) - return -ENXIO; - - if (compr->buf->error) + if (!compr->buf || compr->buf->error) { + snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN); return -EIO; + } count /= WM_ADSP_DATA_WORD_SIZE; @@ -3615,7 +4907,7 @@ irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp) if (ret) { adsp_err(dsp, "Failed to read Region Lock Ctrl register: %d\n", ret); - goto exit; + return IRQ_HANDLED; } if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { @@ -3629,30 +4921,29 @@ irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp) else adsp_err(dsp, "bus error: region lock error\n"); - ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, - &val); + ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); if (ret) { adsp_err(dsp, - "Failed to read Bus Err Addr register: %d\n", - ret); - goto exit; + "Failed to read Bus Err Addr register: %d\n", + ret); + return IRQ_HANDLED; } adsp_err(dsp, "bus error address = 0x%x\n", - (val & ADSP2_BUS_ERR_ADDR_MASK)); + val & ADSP2_BUS_ERR_ADDR_MASK); ret = regmap_read(regmap, dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, &val); if (ret) { adsp_err(dsp, - "Failed to read Pmem Xmem Err Addr register: %d\n", + "Failed to read Pmem Xmem Err Addr register: %d\n", ret); - goto exit; + return IRQ_HANDLED; } adsp_err(dsp, "xmem error address = 0x%x\n", - (val & ADSP2_XMEM_ERR_ADDR_MASK)); + val & ADSP2_XMEM_ERR_ADDR_MASK); adsp_err(dsp, "pmem error address = 0x%x\n", (val & ADSP2_PMEM_ERR_ADDR_MASK) >> ADSP2_PMEM_ERR_ADDR_SHIFT); @@ -3660,9 +4951,105 @@ irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp) regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); -exit: + return IRQ_HANDLED; } EXPORT_SYMBOL_GPL(wm_adsp2_bus_error); +static void wm_halo_dump_fault_info(struct wm_adsp *dsp, const char *region, + unsigned int addr, unsigned int status) +{ + unsigned int write = status & HALO_MPU_VIO_ERR_WR_MASK; + unsigned int type = (status & HALO_MPU_VIO_STS_MASK) >> + HALO_MPU_VIO_STS_SHIFT; + unsigned int src = (status & HALO_MPU_VIO_ERR_SRC_MASK) >> + HALO_MPU_VIO_ERR_SRC_SHIFT; + + adsp_warn(dsp, "%s: FAULT_ADDR:0x%x FAULT_STATUS:0x%x %s\n", + region, addr, status, + write ? "write" : "read"); + + switch (src) { + case 0: + adsp_warn(dsp, "%s: SRC=HALO\n", region); + break; + default: + adsp_warn(dsp, "%s: SRC=Requestor%u\n", region, src); + break; + } + + adsp_warn(dsp, "%s: %s %s %s %s %s %s\n", + region, + (type & HALO_MPU_VIO_SRAM) ? "SRAM" : "", + (type & HALO_MPU_VIO_REG) ? "REG" : "", + (type & HALO_MPU_VIO_AHB) ? "AHB" : "", + (type & HALO_MPU_VIO_EREG) ? "EREG" : "", + (type & HALO_MPU_VIO_EXTERNAL_MEM) ? "ExtMem" : "", + (type & HALO_MPU_VIO_NON_EXIST) ? "NotExist" : ""); +} + +irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp) +{ + struct regmap *regmap = dsp->regmap; + unsigned int fault[6], ahb_sts, reg; + int ret; + + mutex_lock(&dsp->pwr_lock); + + /* Ensure we log the fault even if we fail to read the fault info */ + adsp_warn(dsp, "MPU FAULT\n"); + + ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, + &ahb_sts); + if (ret) { + adsp_warn(dsp, "Failed to read AHB DEBUG_1 (%d)\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "AHB WINDOW: ADDR: 0x%x STATUS: 0x%x\n", + (ahb_sts & HALO_AHBM_CORE_ERR_ADDR_MASK) >> + HALO_AHBM_CORE_ERR_ADDR_SHIFT, + ahb_sts); + adsp_warn(dsp, "AHB WINDOW: %s %s %s %s\n", + (ahb_sts & HALO_AHBM_ADDR_ERR_MASK) ? "ADDR" : "", + (ahb_sts & HALO_AHBM_LOCKED_ERR_MASK) ? "LOCKED" : "", + (ahb_sts & HALO_AHBM_SIZE_ERR_MASK) ? "SIZE" : "", + (ahb_sts & HALO_AHBM_MODE_ERR_MASK) ? "MODE" : ""); + + ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, + &ahb_sts); + if (ret) { + adsp_warn(dsp, "Failed to read AHB DEBUG_0 (%d)\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "AHB SYS_ADDR: 0x%x\n", ahb_sts); + + ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, + fault, ARRAY_SIZE(fault)); + if (ret) { + adsp_warn(dsp, "Failed to read MPU fault info (%d)\n", ret); + goto exit_unlock; + } + + wm_halo_dump_fault_info(dsp, "XM", fault[0], fault[1]); + wm_halo_dump_fault_info(dsp, "YM", fault[2], fault[3]); + wm_halo_dump_fault_info(dsp, "PM", fault[4], fault[5]); + + /* Clear fault status */ + for (reg = HALO_MPU_XM_VIO_STATUS; reg <= HALO_MPU_PM_VIO_STATUS; + reg += 8) { + ret = regmap_write(regmap, dsp->base + reg, 0); + if (ret) + adsp_warn(dsp, "Failed to clear MPU status @0x%x (%d)\n", + reg, ret); + } + +exit_unlock: + mutex_unlock(&dsp->pwr_lock); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_halo_bus_error); + MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h index ac295b81e453..e6cad087cd48 100644 --- a/sound/soc/codecs/wm_adsp.h +++ b/sound/soc/codecs/wm_adsp.h @@ -56,17 +56,41 @@ struct wm_adsp_alg_region { struct wm_adsp_compr; struct wm_adsp_compr_buf; +struct wm_adsp_buffer_region_def { + unsigned int mem_type; + unsigned int base_offset; + unsigned int size_offset; +}; + +struct wm_adsp_fw_caps { + u32 id; + struct snd_codec_desc desc; + int num_regions; + struct wm_adsp_buffer_region_def *region_defs; +}; + +struct wm_adsp_fw_defs { + const char *file; + const char *binfile; + bool fullname; + int compr_direction; + int num_caps; + struct wm_adsp_fw_caps *caps; + bool voice_trigger; +}; + struct wm_adsp { const char *part; int rev; int num; int type; + const char *suffix; struct device *dev; struct regmap *regmap; - struct snd_soc_card *card; struct snd_soc_codec *codec; int base; + int base_sysinfo; int sysclk_reg; int sysclk_mask; int sysclk_shift; @@ -75,14 +99,21 @@ struct wm_adsp { unsigned int fw_id; unsigned int fw_id_version; + unsigned int fw_vendor_id; const struct wm_adsp_region *mem; int num_mems; int fw; int fw_ver; + + bool preloaded; + bool booted; bool running; + int num_firmwares; + struct wm_adsp_fw_defs *firmwares; + struct list_head ctl_list; struct work_struct boot_work; @@ -92,16 +123,24 @@ struct wm_adsp { struct wm_adsp_compr_buf *buffer[WM_ADSP_MAX_CHANNEL_PER_DSP]; struct mutex pwr_lock; - struct mutex *fw_lock; + + unsigned int lock_regions; + bool unlock_all; + + unsigned int n_rx_channels; + unsigned int n_tx_channels; + + struct mutex *rate_lock; + u8 *rx_rate_cache; + u8 *tx_rate_cache; #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_root; char *wmfw_file_name; char *bin_file_name; #endif - const char *wmfw_file; - const char *bin_file; - unsigned int lock_regions; + + void (*fwevent_cb)(struct wm_adsp *dsp, int eventid); }; struct wm_adsp_compr { @@ -122,46 +161,78 @@ struct wm_adsp_compr { SND_SOC_DAPM_PGA_E(wname, SND_SOC_NOPM, num, 0, NULL, 0, \ wm_adsp1_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD) +#define WM_ADSP2_PRELOAD_SWITCH(wname, num) \ + SOC_SINGLE_EXT(wname " Preload Switch", SND_SOC_NOPM, num, 1, 0, \ + wm_adsp2_preloader_get, wm_adsp2_preloader_put) + #define WM_ADSP2(wname, num, event_fn) \ -{ .id = snd_soc_dapm_dai_link, .name = wname " Preloader", \ + SND_SOC_DAPM_SPK(wname " Preload", NULL), \ +{ .id = snd_soc_dapm_supply, .name = wname " Preloader", \ .reg = SND_SOC_NOPM, .shift = num, .event = event_fn, \ - .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD }, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \ + .subseq = 100, /* Ensure we run after SYSCLK supply widget */ }, \ { .id = snd_soc_dapm_out_drv, .name = wname, \ .reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp2_event, \ .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD } +#define WM_HALO(wname, num, event_fn) \ + SND_SOC_DAPM_SPK(wname " Preload", NULL), \ +{ .id = snd_soc_dapm_supply, .name = wname " Preloader", \ + .reg = SND_SOC_NOPM, .shift = num, .event = event_fn, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \ + .subseq = 100, /* Ensure we run after SYSCLK supply widget */ }, \ +{ .id = snd_soc_dapm_out_drv, .name = wname, \ + .reg = SND_SOC_NOPM, .shift = num, .event = wm_halo_event, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD } + extern const struct snd_kcontrol_new wm_adsp_fw_controls[]; int wm_adsp1_init(struct wm_adsp *dsp); -int wm_adsp2_init(struct wm_adsp *dsp, struct mutex *fw_lock); +int wm_adsp2_init(struct wm_adsp *dsp); void wm_adsp2_remove(struct wm_adsp *dsp); -int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec); +int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec, + bool ao_dsp); int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec); +int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock); int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); + int wm_adsp2_early_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event, unsigned int freq); int wm_adsp2_lock(struct wm_adsp *adsp, unsigned int regions); irqreturn_t wm_adsp2_bus_error(struct wm_adsp *adsp); +irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp); int wm_adsp2_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); -extern int wm_adsp_compr_open(struct wm_adsp *dsp, +int wm_halo_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +int wm_halo_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); + +int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream, int channel); -extern int wm_adsp_compr_free(struct snd_compr_stream *stream); -extern int wm_adsp_compr_set_params(struct snd_compr_stream *stream, - struct snd_compr_params *params); -extern int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, - struct snd_compr_caps *caps); -extern int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd); -extern int wm_adsp_compr_handle_irq(struct wm_adsp *dsp, int channel); -extern int wm_adsp_compr_pointer(struct snd_compr_stream *stream, - struct snd_compr_tstamp *tstamp); -extern int wm_adsp_compr_copy(struct snd_compr_stream *stream, - char __user *buf, size_t count); +int wm_adsp_compr_free(struct snd_compr_stream *stream); +int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params); +int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps); +int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd); +int wm_adsp_compr_handle_irq(struct wm_adsp *dsp, int channel); +int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp); +int wm_adsp_compr_copy(struct snd_compr_stream *stream, + char __user *buf, size_t count); + +extern int wm_adsp_handle_fw_event(struct wm_adsp *dsp); #endif diff --git a/sound/soc/codecs/wmfw.h b/sound/soc/codecs/wmfw.h index 7613d60d62ea..c25dc878d012 100644 --- a/sound/soc/codecs/wmfw.h +++ b/sound/soc/codecs/wmfw.h @@ -26,6 +26,11 @@ #define WMFW_CTL_FLAG_WRITEABLE 0x0002 #define WMFW_CTL_FLAG_READABLE 0x0001 +/* Non-ALSA coefficient types start at 0x1000 */ +#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */ +#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */ +#define WMFW_CTL_TYPE_FWEVENT 0x1004 /* firmware event control */ + struct wmfw_header { char magic[4]; __le32 len; @@ -83,6 +88,23 @@ struct wmfw_adsp2_id_hdr { __be32 n_algs; } __packed; +struct wmfw_halo_fwid_hdr { + __be32 core_id; + __be32 block_rev; + __be32 vendor_id; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_halo_id_hdr { + struct wmfw_halo_fwid_hdr fw; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; + __be32 n_algs; +} __packed; + struct wmfw_alg_hdr { __be32 id; __be32 ver; @@ -101,6 +123,14 @@ struct wmfw_adsp2_alg_hdr { __be32 ym; } __packed; +struct wmfw_halo_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; +} __packed; + struct wmfw_adsp_alg_data { __le32 id; u8 name[WMFW_MAX_ALG_NAME]; @@ -149,6 +179,7 @@ struct wmfw_coeff_item { #define WMFW_ADSP1 1 #define WMFW_ADSP2 2 +#define WMFW_HALO 4 #define WMFW_ABSOLUTE 0xf0 #define WMFW_ALGORITHM_DATA 0xf2 @@ -164,4 +195,8 @@ struct wmfw_coeff_item { #define WMFW_ADSP2_XM 5 #define WMFW_ADSP2_YM 6 +#define WMFW_HALO_PM_PACKED 0x10 +#define WMFW_HALO_XM_PACKED 0x11 +#define WMFW_HALO_YM_PACKED 0x12 + #endif