From 24a17fca7c210a4ee3f961a313e615ed9a11b70d Mon Sep 17 00:00:00 2001
From: Mayank Grover <groverm@qti.qualcomm.com>
Date: Fri, 14 Aug 2020 12:31:56 +0530
Subject: [PATCH] ARM: dts: msm: Add support for SCM PAS for holi

The PIL drivers need to vote for bandwidth across DDR and
crypto subsytem, such that the secure world can perform
initialization and authorization of the firmware blobs.
Hence add a device-tree node indicating the corresponding
interconnect.

Change-Id: I9a0537930a246705382dc727f1014b397b982ec3
---
 qcom/holi.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi
index 436cc02c0d47..7f5ad18e0d1a 100644
--- a/qcom/holi.dtsi
+++ b/qcom/holi.dtsi
@@ -868,6 +868,11 @@
 		reg-names = "pshold-base", "tcsr-boot-misc-detect";
 	};
 
+	pil_scm_pas {
+		compatible = "qcom,pil-tz-scm-pas";
+		interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>;
+	};
+
 	qcom,msm-rtb {
 		compatible = "qcom,msm-rtb";
 		qcom,rtb-size = <0x100000>;