clk: mmp: add timer clock for pxa168/mmp2/pxa910

Timer has external fast clock, and it is a mux clock.
Add the timer clock type for timer driver.

Signed-off-by: Chao Xie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
This commit is contained in:
Chao Xie 2015-04-30 09:53:42 +08:00 • committed by Stephen Boyd
commit 24c65a02b2
6 changed files with 30 additions and 0 deletions

View file

@ -48,6 +48,7 @@
#define MMP2_CLK_SSP1 78
#define MMP2_CLK_SSP2 79
#define MMP2_CLK_SSP3 80
#define MMP2_CLK_TIMER 81
/* axi periphrals */
#define MMP2_CLK_SDH0 101

View file

@ -18,6 +18,7 @@
#define PXA168_CLK_PLL1_13_1_5 18
#define PXA168_CLK_PLL1_2_1_5 19
#define PXA168_CLK_PLL1_3_16 20
#define PXA168_CLK_PLL1_192 21
#define PXA168_CLK_UART_PLL 27
#define PXA168_CLK_USB_PLL 28
@ -41,6 +42,7 @@
#define PXA168_CLK_SSP2 76
#define PXA168_CLK_SSP3 77
#define PXA168_CLK_SSP4 78
#define PXA168_CLK_TIMER 79
/* axi periphrals */
#define PXA168_CLK_DFC 100

View file

@ -18,6 +18,7 @@
#define PXA910_CLK_PLL1_13_1_5 18
#define PXA910_CLK_PLL1_2_1_5 19
#define PXA910_CLK_PLL1_3_16 20
#define PXA910_CLK_PLL1_192 21
#define PXA910_CLK_UART_PLL 27
#define PXA910_CLK_USB_PLL 28
@ -38,6 +39,8 @@
#define PXA910_CLK_UART2 73
#define PXA910_CLK_SSP0 74
#define PXA910_CLK_SSP1 75
#define PXA910_CLK_TIMER0 76
#define PXA910_CLK_TIMER1 77
/* axi periphrals */
#define PXA910_CLK_DFC 100