From a1aba6493aba56b8a63ff8ff6b0fc29d3777f9c9 Mon Sep 17 00:00:00 2001
From: Mike Tipton <mdtipton@quicinc.com>
Date: Thu, 21 Jan 2021 10:46:40 -0800
Subject: [PATCH 1/2] dt-bindings: clock: Add qcom,critical-* properties

Add documentation for the qcom,critical-clocks and qcom,critical-devices
properties.

Change-Id: I3a03164d206644e8be1e0d846730d8183c333b52
---
 bindings/clock/qcom,gcc.txt | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index fddfd6882952..89ee69d7d28d 100644
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -53,6 +53,10 @@ For more details on the TSENS properties please refer
 Documentation/devicetree/bindings/thermal/qcom-tsens.txt
 - protected-clocks : Protected clock specifier list as per common clock
  binding.
+- qcom,critical-clocks : List of clock specifiers that should be enabled during
+  probe and not registered with the clock framework.
+- qcom,critical-devices : List of device phandles whose associated clocks
+  should be enabled during probe and not registered with the clock framework.
 
 Example:
 	clock-controller@900000 {
@@ -87,3 +91,23 @@ Example of GCC with protected-clocks properties:
 				   <GCC_LPASS_Q6_AXI_CLK>,
 				   <GCC_LPASS_SWAY_CLK>;
 	};
+
+Example of GCC with qcom,critical-clocks properties:
+	clock-controller@100000 {
+		compatible = "qcom,waipio-gcc", "syscon";
+		reg = <0x100000 0x1f4200>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		qcom,critical-clocks = <GCC_QUPV3_WRAP0_S5_CLK>,
+				       <GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				       <GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+	};
+
+Example of GCC with qcom,critical-devices properties:
+	clock-controller@100000 {
+		compatible = "qcom,waipio-gcc", "syscon";
+		reg = <0x100000 0x1f4200>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		qcom,critical-devices = <&qupv3_se5_i2c>;
+	};

From 721aa9c0335346f0c9948f7aa575f0cfa85c2266 Mon Sep 17 00:00:00 2001
From: Jagadeesh Kona <jkona@qti.qualcomm.com>
Date: Mon, 1 Feb 2021 11:39:57 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Mark PMIC QUPs as critical clock devices
 for YUPIK

To prevent deadlocks between the clock and regulator frameworks,
the QUP clocks used by I2C-connected PMICs must be enabled all
the time and not registered with the clock framework. Skipping
the registration short-circuits the I2C device's clock calls such
that they return success before grabbing the clock locks. Achieve
this behavior by setting GCC's qcom,critical-devices property.

Change-Id: Ie5017022b2d2281d6754bb527ac40bbd050673fc
---
 qcom/yupik-pmic-overlay.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/qcom/yupik-pmic-overlay.dtsi b/qcom/yupik-pmic-overlay.dtsi
index ac30b1c1045a..4ba57dd658b0 100644
--- a/qcom/yupik-pmic-overlay.dtsi
+++ b/qcom/yupik-pmic-overlay.dtsi
@@ -241,6 +241,14 @@
 	};
 };
 
+/*
+ * Each QUP device that's a parent to PMIC must be listed as a critical device
+ * to GCC
+ */
+&gcc {
+	qcom,critical-devices = <&qupv3_se1_i2c>;
+};
+
 &qupv3_se1_i2c {
 	#address-cells = <1>;
 	#size-cells = <0>;