From 456ff01d6c64eed9719e8eecf5269a10a0cd9f06 Mon Sep 17 00:00:00 2001
From: Kiran Gunda <kgunda@qti.qualcomm.com>
Date: Tue, 26 May 2020 18:04:08 +0530
Subject: [PATCH 1/2] ARM: dts: msm: add SPMI debug bus for shima

Add an SPMI debug bus device and associated child devices so that
consumers can have unrestricted access to the PMICs on
pre-production devices.  This helps to make debugging easier.

Change-Id: Id534051fef71eb84fbea3dc8976ecb2cbd9eff47
---
 qcom/shima.dtsi | 53 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index c26092c8f518..80934013f724 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/spmi/spmi.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 
@@ -1152,6 +1153,58 @@
 		qcom,ee = <0>;
 	};
 
+	spmi_debug_bus: qcom,spmi-debug@6b12000 {
+		compatible = "qcom,spmi-pmic-arb-debug";
+		reg = <0x6b12000 0x60>, <0x7820b0 0x4>;
+		reg-names = "core", "fuse";
+		clocks = <&aopcc QDSS_CLK>;
+		clock-names = "core_clk";
+		qcom,fuse-disable-bit = <24>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		qcom,pmk8350-debug@0 {
+			compatible = "qcom,spmi-pmic";
+			reg = <0 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350-debug@1 {
+			compatible = "qcom,spmi-pmic";
+			reg = <1 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350c-debug@2 {
+			compatible = "qcom,spmi-pmic";
+			reg = <2 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350b-debug@3 {
+			compatible = "qcom,spmi-pmic";
+			reg = <3 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pmr735b-debug@5 {
+			compatible = "qcom,spmi-pmic";
+			reg = <5 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+	};
+
 	qcom,chd {
 		compatible = "qcom,core-hang-detect";
 		label = "core";

From 82aef107352cfd0d1aad1a9b9bb42601a3c33ca5 Mon Sep 17 00:00:00 2001
From: Kiran Gunda <kgunda@qti.qualcomm.com>
Date: Tue, 26 May 2020 18:53:11 +0530
Subject: [PATCH 2/2] ARM: dts: msm: add PMIC Glink and clients for shima

Add PMIC Glink device and their client devices. PMIC Glink device
with name PMIC_RTR_ADSP_APPS supports the clients UCSI, battery
charger etc. PMIC Glink device with name PMIC_LOGS_ADSP_APPS
supports the client battery debug device.

Change-Id: Icf6dae33dfcc361701e1684274e3749431d451a0
---
 qcom/shima.dtsi | 69 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 80934013f724..5c14d6ae530a 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -1205,6 +1205,75 @@
 		};
 	};
 
+	qcom,pmic_glink {
+		compatible = "qcom,pmic-glink";
+		qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
+		qcom,subsys-name = "adsp";
+		qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
+
+		battery_charger: qcom,battery_charger {
+			compatible = "qcom,battery-charger";
+		};
+
+		qcom,ucsi {
+			compatible = "qcom,ucsi-glink";
+		};
+
+		altmode: qcom,altmode {
+			compatible = "qcom,altmode-glink";
+			#altmode-cells = <1>;
+		};
+	};
+
+	qcom,pmic_glink_log {
+		compatible = "qcom,pmic-glink";
+		qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
+
+		qcom,battery_debug {
+			compatible = "qcom,battery-debug";
+		};
+
+		spmi_glink_debug: qcom,spmi_glink_debug {
+			compatible = "qcom,spmi-glink-debug";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			/* Primary SPMI bus */
+			spmi@0 {
+				reg = <0>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				qcom,pm8350b-debug@3 {
+					compatible = "qcom,spmi-pmic";
+					reg = <3 SPMI_USID>;
+					qcom,can-sleep;
+				};
+			};
+
+			/* Secondary (QUP) SPMI bus */
+			spmi@1 {
+				reg = <1>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				qcom,smb1394-debug@b {
+					compatible = "qcom,spmi-pmic";
+					reg = <11 SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+				qcom,smb1394-debug@c {
+					compatible = "qcom,spmi-pmic";
+					reg = <12 SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+			};
+		};
+	};
+
 	qcom,chd {
 		compatible = "qcom,core-hang-detect";
 		label = "core";