mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 21:59:12 -04:00
Merge "firmware: qcom_scm: Order functions, definitions by svc/cmd"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
25a16eb963
5 changed files with 356 additions and 355 deletions
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@ -423,33 +423,31 @@ void __qcom_scm_cpu_power_down(u32 flags)
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flags & QCOM_SCM_FLUSH_FLAG_MASK);
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}
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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{
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struct {
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__le32 state;
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__le32 id;
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} req;
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__le32 scm_ret = 0;
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int ret;
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__le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id);
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__le32 ret_val = 0;
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
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&svc_cmd, sizeof(svc_cmd), &ret_val,
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sizeof(ret_val));
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if (ret)
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return ret;
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req.state = cpu_to_le32(state);
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req.id = cpu_to_le32(id);
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return le32_to_cpu(ret_val);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_REMOTE_STATE,
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&req, sizeof(req), &scm_ret, sizeof(scm_ret));
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return ret ? : le32_to_cpu(scm_ret);
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}
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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u32 req_cnt, u32 *resp)
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{
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE,
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req, req_cnt * sizeof(*req), resp, sizeof(*resp));
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}
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void __qcom_scm_init(void)
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int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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{
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_DLOAD_MODE,
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enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0,
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0);
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}
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bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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@ -554,38 +552,37 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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return ret ? : le32_to_cpu(out);
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}
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int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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unsigned int *val)
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{
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_DLOAD_MODE,
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enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0,
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0);
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}
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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{
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struct {
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__le32 state;
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__le32 id;
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} req;
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__le32 scm_ret = 0;
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int ret;
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req.state = cpu_to_le32(state);
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req.id = cpu_to_le32(id);
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ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr);
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if (ret >= 0)
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*val = ret;
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_REMOTE_STATE,
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&req, sizeof(req), &scm_ret, sizeof(scm_ret));
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return ret ? : le32_to_cpu(scm_ret);
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return ret < 0 ? ret : 0;
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}
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int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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size_t mem_sz, phys_addr_t src, size_t src_sz,
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phys_addr_t dest, size_t dest_sz)
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int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
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{
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return -ENODEV;
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
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addr, val);
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}
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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{
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int ret;
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__le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id);
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__le32 ret_val = 0;
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
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&svc_cmd, sizeof(svc_cmd), &ret_val,
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sizeof(ret_val));
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if (ret)
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return ret;
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return le32_to_cpu(ret_val);
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}
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int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
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@ -606,25 +603,28 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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return -ENODEV;
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}
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int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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unsigned int *val)
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int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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size_t mem_sz, phys_addr_t src, size_t src_sz,
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phys_addr_t dest, size_t dest_sz)
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{
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int ret;
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ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr);
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if (ret >= 0)
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*val = ret;
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return ret < 0 ? ret : 0;
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return -ENODEV;
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}
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int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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u32 req_cnt, u32 *resp)
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{
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return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
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addr, val);
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE,
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req, req_cnt * sizeof(*req), resp, sizeof(*resp));
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}
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int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)
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{
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return -ENODEV;
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}
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void __qcom_scm_init(void)
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{
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}
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@ -246,69 +246,35 @@ void __qcom_scm_cpu_power_down(u32 flags)
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{
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}
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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int ret;
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desc.arginfo = QCOM_SCM_ARGS(1);
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desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) |
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(ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
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desc.args[0] = state;
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desc.args[1] = id;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_REMOTE_STATE,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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u32 req_cnt, u32 *resp)
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int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
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desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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desc.args[0] = req[0].addr;
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desc.args[1] = req[0].val;
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desc.args[2] = req[1].addr;
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desc.args[3] = req[1].val;
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desc.args[4] = req[2].addr;
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desc.args[5] = req[2].val;
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desc.args[6] = req[3].addr;
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desc.args[7] = req[3].val;
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desc.args[8] = req[4].addr;
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desc.args[9] = req[4].val;
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desc.arginfo = QCOM_SCM_ARGS(10);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE, &desc,
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&res);
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*resp = res.a1;
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return ret;
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}
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void __qcom_scm_init(void)
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{
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u64 cmd;
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struct arm_smccc_res res;
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u32 function = SMCCC_FUNCNUM(QCOM_SCM_SVC_INFO,
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QCOM_SCM_INFO_IS_CALL_AVAIL);
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/* First try a SMC64 call */
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cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64,
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ARM_SMCCC_OWNER_SIP, function);
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arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)),
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0, 0, 0, 0, 0, &res);
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if (!res.a0 && res.a1)
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qcom_smccc_convention = ARM_SMCCC_SMC_64;
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else
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qcom_smccc_convention = ARM_SMCCC_SMC_32;
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return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_DLOAD_MODE,
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&desc, &res);
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}
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bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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@ -409,45 +375,48 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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return ret ? : res.a1;
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}
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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unsigned int *val)
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{
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = state;
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desc.args[1] = id;
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desc.arginfo = QCOM_SCM_ARGS(2);
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desc.args[0] = addr;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_REMOTE_STATE,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ,
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&desc, &res);
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if (ret >= 0)
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*val = res.a1;
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return ret ? : res.a1;
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return ret < 0 ? ret : 0;
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}
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int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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size_t mem_sz, phys_addr_t src, size_t src_sz,
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phys_addr_t dest, size_t dest_sz)
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int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
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{
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = addr;
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desc.args[1] = val;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
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&desc, &res);
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}
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = mem_region;
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desc.args[1] = mem_sz;
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desc.args[2] = src;
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desc.args[3] = src_sz;
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desc.args[4] = dest;
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desc.args[5] = dest_sz;
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desc.args[6] = 0;
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desc.arginfo = QCOM_SCM_ARGS(1);
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desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) |
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(ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
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desc.arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
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QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
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QCOM_SCM_VAL, QCOM_SCM_VAL);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
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QCOM_SCM_MP_ASSIGN,
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
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&desc, &res);
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return ret ? : res.a1;
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@ -511,49 +480,60 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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return ret;
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}
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int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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size_t mem_sz, phys_addr_t src, size_t src_sz,
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phys_addr_t dest, size_t dest_sz)
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{
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
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desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_DLOAD_MODE,
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&desc, &res);
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}
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int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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unsigned int *val)
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{
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = addr;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ,
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&desc, &res);
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if (ret >= 0)
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*val = res.a1;
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return ret < 0 ? ret : 0;
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}
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int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
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{
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = addr;
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desc.args[1] = val;
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desc.arginfo = QCOM_SCM_ARGS(2);
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desc.args[0] = mem_region;
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desc.args[1] = mem_sz;
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desc.args[2] = src;
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desc.args[3] = src_sz;
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desc.args[4] = dest;
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desc.args[5] = dest_sz;
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desc.args[6] = 0;
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return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
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&desc, &res);
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desc.arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
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QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
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QCOM_SCM_VAL, QCOM_SCM_VAL);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
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QCOM_SCM_MP_ASSIGN,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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u32 req_cnt, u32 *resp)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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desc.args[0] = req[0].addr;
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desc.args[1] = req[0].val;
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desc.args[2] = req[1].addr;
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desc.args[3] = req[1].val;
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desc.args[4] = req[2].addr;
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desc.args[5] = req[2].val;
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desc.args[6] = req[3].addr;
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desc.args[7] = req[3].val;
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desc.args[8] = req[4].addr;
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desc.args[9] = req[4].val;
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desc.arginfo = QCOM_SCM_ARGS(10);
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|
||||
ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE, &desc,
|
||||
&res);
|
||||
*resp = res.a1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
|
||||
|
|
@ -568,3 +548,23 @@ int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
|
|||
return qcom_scm_call_atomic(dev, QCOM_SCM_SVC_SMMU_PROGRAM,
|
||||
QCOM_SCM_SMMU_CONFIG_ERRATA1, &desc, &res);
|
||||
}
|
||||
|
||||
void __qcom_scm_init(void)
|
||||
{
|
||||
u64 cmd;
|
||||
struct arm_smccc_res res;
|
||||
u32 function = SMCCC_FUNCNUM(QCOM_SCM_SVC_INFO,
|
||||
QCOM_SCM_INFO_IS_CALL_AVAIL);
|
||||
|
||||
/* First try a SMC64 call */
|
||||
cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64,
|
||||
ARM_SMCCC_OWNER_SIP, function);
|
||||
|
||||
arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)),
|
||||
0, 0, 0, 0, 0, &res);
|
||||
|
||||
if (!res.a0 && res.a1)
|
||||
qcom_smccc_convention = ARM_SMCCC_SMC_64;
|
||||
else
|
||||
qcom_smccc_convention = ARM_SMCCC_SMC_32;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -126,47 +126,34 @@ void qcom_scm_cpu_power_down(u32 flags)
|
|||
}
|
||||
EXPORT_SYMBOL(qcom_scm_cpu_power_down);
|
||||
|
||||
/**
|
||||
* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
|
||||
*
|
||||
* Return true if HDCP is supported, false if not.
|
||||
*/
|
||||
bool qcom_scm_hdcp_available(void)
|
||||
int qcom_scm_set_remote_state(u32 state, u32 id)
|
||||
{
|
||||
int ret = qcom_scm_clk_enable();
|
||||
return __qcom_scm_set_remote_state(__scm->dev, state, id);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_set_remote_state);
|
||||
|
||||
static void qcom_scm_set_download_mode(bool enable)
|
||||
{
|
||||
bool avail;
|
||||
int ret = 0;
|
||||
|
||||
avail = __qcom_scm_is_call_available(__scm->dev,
|
||||
QCOM_SCM_SVC_BOOT,
|
||||
QCOM_SCM_BOOT_SET_DLOAD_MODE);
|
||||
if (avail) {
|
||||
ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
|
||||
} else if (__scm->dload_mode_addr) {
|
||||
ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
|
||||
enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE
|
||||
: 0);
|
||||
} else {
|
||||
dev_err(__scm->dev,
|
||||
"No available mechanism for setting download mode\n");
|
||||
}
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
|
||||
QCOM_SCM_HDCP_INVOKE);
|
||||
|
||||
qcom_scm_clk_disable();
|
||||
|
||||
return ret > 0 ? true : false;
|
||||
dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_hdcp_available);
|
||||
|
||||
/**
|
||||
* qcom_scm_hdcp_req() - Send HDCP request.
|
||||
* @req: HDCP request array
|
||||
* @req_cnt: HDCP request array count
|
||||
* @resp: response buffer passed to SCM
|
||||
*
|
||||
* Write HDCP register(s) through SCM.
|
||||
*/
|
||||
int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
|
||||
{
|
||||
int ret = qcom_scm_clk_enable();
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
|
||||
qcom_scm_clk_disable();
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_hdcp_req);
|
||||
|
||||
/**
|
||||
* qcom_scm_pas_supported() - Check if the peripheral authentication service is
|
||||
|
|
@ -324,6 +311,18 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = {
|
|||
.deassert = qcom_scm_pas_reset_deassert,
|
||||
};
|
||||
|
||||
int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
|
||||
{
|
||||
return __qcom_scm_io_readl(__scm->dev, addr, val);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_io_readl);
|
||||
|
||||
int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
|
||||
{
|
||||
return __qcom_scm_io_writel(__scm->dev, addr, val);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_io_writel);
|
||||
|
||||
int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
|
||||
{
|
||||
return __qcom_scm_restore_sec_cfg(__scm->dev, device_id, spare);
|
||||
|
|
@ -342,88 +341,6 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
|
|||
}
|
||||
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
|
||||
|
||||
int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
|
||||
{
|
||||
return __qcom_scm_qsmmu500_wait_safe_toggle(__scm->dev, en);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
|
||||
|
||||
int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
|
||||
{
|
||||
return __qcom_scm_io_readl(__scm->dev, addr, val);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_io_readl);
|
||||
|
||||
int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
|
||||
{
|
||||
return __qcom_scm_io_writel(__scm->dev, addr, val);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_io_writel);
|
||||
|
||||
static void qcom_scm_set_download_mode(bool enable)
|
||||
{
|
||||
bool avail;
|
||||
int ret = 0;
|
||||
|
||||
avail = __qcom_scm_is_call_available(__scm->dev,
|
||||
QCOM_SCM_SVC_BOOT,
|
||||
QCOM_SCM_BOOT_SET_DLOAD_MODE);
|
||||
if (avail) {
|
||||
ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
|
||||
} else if (__scm->dload_mode_addr) {
|
||||
ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
|
||||
enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE
|
||||
: 0);
|
||||
} else {
|
||||
dev_err(__scm->dev,
|
||||
"No available mechanism for setting download mode\n");
|
||||
}
|
||||
|
||||
if (ret)
|
||||
dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
|
||||
}
|
||||
|
||||
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
|
||||
{
|
||||
struct device_node *tcsr;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct resource res;
|
||||
u32 offset;
|
||||
int ret;
|
||||
|
||||
tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
|
||||
if (!tcsr)
|
||||
return 0;
|
||||
|
||||
ret = of_address_to_resource(tcsr, 0, &res);
|
||||
of_node_put(tcsr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
*addr = res.start + offset;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_scm_is_available() - Checks if SCM is available
|
||||
*/
|
||||
bool qcom_scm_is_available(void)
|
||||
{
|
||||
return !!__scm;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_is_available);
|
||||
|
||||
int qcom_scm_set_remote_state(u32 state, u32 id)
|
||||
{
|
||||
return __qcom_scm_set_remote_state(__scm->dev, state, id);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_set_remote_state);
|
||||
|
||||
/**
|
||||
* qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
|
||||
* @mem_addr: mem region whose ownership need to be reassigned
|
||||
|
|
@ -506,6 +423,89 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
|||
}
|
||||
EXPORT_SYMBOL(qcom_scm_assign_mem);
|
||||
|
||||
/**
|
||||
* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
|
||||
*
|
||||
* Return true if HDCP is supported, false if not.
|
||||
*/
|
||||
bool qcom_scm_hdcp_available(void)
|
||||
{
|
||||
int ret = qcom_scm_clk_enable();
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
|
||||
QCOM_SCM_HDCP_INVOKE);
|
||||
|
||||
qcom_scm_clk_disable();
|
||||
|
||||
return ret > 0 ? true : false;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_hdcp_available);
|
||||
|
||||
/**
|
||||
* qcom_scm_hdcp_req() - Send HDCP request.
|
||||
* @req: HDCP request array
|
||||
* @req_cnt: HDCP request array count
|
||||
* @resp: response buffer passed to SCM
|
||||
*
|
||||
* Write HDCP register(s) through SCM.
|
||||
*/
|
||||
int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
|
||||
{
|
||||
int ret = qcom_scm_clk_enable();
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
|
||||
qcom_scm_clk_disable();
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_hdcp_req);
|
||||
|
||||
int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
|
||||
{
|
||||
return __qcom_scm_qsmmu500_wait_safe_toggle(__scm->dev, en);
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
|
||||
|
||||
/**
|
||||
* qcom_scm_is_available() - Checks if SCM is available
|
||||
*/
|
||||
bool qcom_scm_is_available(void)
|
||||
{
|
||||
return !!__scm;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_is_available);
|
||||
|
||||
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
|
||||
{
|
||||
struct device_node *tcsr;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct resource res;
|
||||
u32 offset;
|
||||
int ret;
|
||||
|
||||
tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
|
||||
if (!tcsr)
|
||||
return 0;
|
||||
|
||||
ret = of_address_to_resource(tcsr, 0, &res);
|
||||
of_node_put(tcsr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
*addr = res.start + offset;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_scm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_scm *scm;
|
||||
|
|
|
|||
|
|
@ -4,46 +4,26 @@
|
|||
#ifndef __QCOM_SCM_INT_H
|
||||
#define __QCOM_SCM_INT_H
|
||||
|
||||
#define QCOM_SCM_SVC_BOOT 0x1
|
||||
#define QCOM_SCM_BOOT_SET_ADDR 0x1
|
||||
#define QCOM_SCM_SVC_BOOT 0x01
|
||||
#define QCOM_SCM_BOOT_SET_ADDR 0x01
|
||||
#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
|
||||
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
|
||||
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
|
||||
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0xa
|
||||
extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
|
||||
extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
|
||||
|
||||
extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
|
||||
const cpumask_t *cpus);
|
||||
extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
|
||||
#define QCOM_SCM_BOOT_TERMINATE_PC 0x2
|
||||
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
||||
extern void __qcom_scm_cpu_power_down(u32 flags);
|
||||
extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
|
||||
extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
|
||||
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
||||
|
||||
#define QCOM_SCM_SVC_IO 0x5
|
||||
#define QCOM_SCM_IO_READ 0x1
|
||||
#define QCOM_SCM_IO_WRITE 0x2
|
||||
extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
|
||||
extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
|
||||
|
||||
#define QCOM_SCM_SVC_INFO 0x6
|
||||
#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x1
|
||||
extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
|
||||
u32 cmd_id);
|
||||
|
||||
#define QCOM_SCM_SVC_HDCP 0x11
|
||||
#define QCOM_SCM_HDCP_INVOKE 0x01
|
||||
extern int __qcom_scm_hdcp_req(struct device *dev,
|
||||
struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
|
||||
|
||||
extern void __qcom_scm_init(void);
|
||||
|
||||
#define QCOM_SCM_SVC_PIL 0x2
|
||||
#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x1
|
||||
#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x2
|
||||
#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x5
|
||||
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x6
|
||||
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x7
|
||||
#define QCOM_SCM_PIL_PAS_MSS_RESET 0xa
|
||||
#define QCOM_SCM_SVC_PIL 0x02
|
||||
#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
|
||||
#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
|
||||
#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
|
||||
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
|
||||
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
|
||||
#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
|
||||
extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
|
||||
extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
|
||||
dma_addr_t metadata_phys);
|
||||
|
|
@ -53,6 +33,46 @@ extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
|
|||
extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
|
||||
extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
|
||||
|
||||
#define QCOM_SCM_SVC_IO 0x05
|
||||
#define QCOM_SCM_IO_READ 0x01
|
||||
#define QCOM_SCM_IO_WRITE 0x02
|
||||
extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
|
||||
extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
|
||||
|
||||
#define QCOM_SCM_SVC_INFO 0x06
|
||||
#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
|
||||
extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
|
||||
u32 cmd_id);
|
||||
|
||||
#define QCOM_SCM_SVC_MP 0x0c
|
||||
#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
|
||||
#define QCOM_SCM_MP_ASSIGN 0x16
|
||||
extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
|
||||
u32 spare);
|
||||
extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
|
||||
size_t *size);
|
||||
extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
|
||||
u32 size, u32 spare);
|
||||
extern int __qcom_scm_assign_mem(struct device *dev,
|
||||
phys_addr_t mem_region, size_t mem_sz,
|
||||
phys_addr_t src, size_t src_sz,
|
||||
phys_addr_t dest, size_t dest_sz);
|
||||
|
||||
#define QCOM_SCM_SVC_HDCP 0x11
|
||||
#define QCOM_SCM_HDCP_INVOKE 0x01
|
||||
extern int __qcom_scm_hdcp_req(struct device *dev,
|
||||
struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
|
||||
|
||||
#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x3
|
||||
extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
|
||||
bool enable);
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x2
|
||||
|
||||
extern void __qcom_scm_init(void);
|
||||
|
||||
/* common error codes */
|
||||
#define QCOM_SCM_V2_EBUSY -12
|
||||
#define QCOM_SCM_ENOMEM -5
|
||||
|
|
@ -80,25 +100,4 @@ static inline int qcom_scm_remap_error(int err)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
#define QCOM_SCM_SVC_MP 0xc
|
||||
#define QCOM_SCM_MP_RESTORE_SEC_CFG 2
|
||||
extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
|
||||
u32 spare);
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 3
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 4
|
||||
#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x3
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x2
|
||||
extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
|
||||
size_t *size);
|
||||
extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
|
||||
u32 size, u32 spare);
|
||||
extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
|
||||
bool enable);
|
||||
#define QCOM_SCM_MP_ASSIGN 0x16
|
||||
extern int __qcom_scm_assign_mem(struct device *dev,
|
||||
phys_addr_t mem_region, size_t mem_sz,
|
||||
phys_addr_t src, size_t src_sz,
|
||||
phys_addr_t dest, size_t dest_sz);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
|
||||
/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
|
||||
* Copyright (C) 2015 Linaro Ltd.
|
||||
*/
|
||||
#ifndef __QCOM_SCM_H
|
||||
|
|
@ -37,10 +37,8 @@ struct qcom_scm_vmperm {
|
|||
#if IS_ENABLED(CONFIG_QCOM_SCM)
|
||||
extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
extern bool qcom_scm_is_available(void);
|
||||
extern bool qcom_scm_hdcp_available(void);
|
||||
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||
u32 *resp);
|
||||
extern void qcom_scm_cpu_power_down(u32 flags);
|
||||
extern int qcom_scm_set_remote_state(u32 state, u32 id);
|
||||
extern bool qcom_scm_pas_supported(u32 peripheral);
|
||||
extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
|
||||
size_t size);
|
||||
|
|
@ -48,58 +46,62 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
|
|||
phys_addr_t size);
|
||||
extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
|
||||
extern int qcom_scm_pas_shutdown(u32 peripheral);
|
||||
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
|
||||
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
|
||||
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
|
||||
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
|
||||
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
|
||||
extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
||||
unsigned int *src,
|
||||
const struct qcom_scm_vmperm *newvm,
|
||||
unsigned int dest_cnt);
|
||||
extern void qcom_scm_cpu_power_down(u32 flags);
|
||||
extern u32 qcom_scm_get_version(void);
|
||||
extern int qcom_scm_set_remote_state(u32 state, u32 id);
|
||||
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
|
||||
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
|
||||
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
|
||||
extern bool qcom_scm_hdcp_available(void);
|
||||
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||
u32 *resp);
|
||||
extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
|
||||
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
|
||||
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
|
||||
extern u32 qcom_scm_get_version(void);
|
||||
extern bool qcom_scm_is_available(void);
|
||||
#else
|
||||
|
||||
#include <linux/errno.h>
|
||||
|
||||
static inline
|
||||
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
{ return -ENODEV; }
|
||||
static inline
|
||||
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline bool qcom_scm_is_available(void) { return false; }
|
||||
static inline bool qcom_scm_hdcp_available(void) { return false; }
|
||||
static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||
u32 *resp) { return -ENODEV; }
|
||||
{ return -ENODEV; }
|
||||
static inline void qcom_scm_cpu_power_down(u32 flags) {}
|
||||
static inline u32 qcom_scm_set_remote_state(u32 state, u32 id)
|
||||
{ return -ENODEV; }
|
||||
static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
|
||||
static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
|
||||
size_t size) { return -ENODEV; }
|
||||
static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
|
||||
phys_addr_t size) { return -ENODEV; }
|
||||
static inline int
|
||||
qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
|
||||
static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
|
||||
static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
||||
unsigned int *src,
|
||||
const struct qcom_scm_vmperm *newvm,
|
||||
unsigned int dest_cnt) { return -ENODEV; }
|
||||
static inline void qcom_scm_cpu_power_down(u32 flags) {}
|
||||
static inline bool qcom_scm_hdcp_available(void) { return false; }
|
||||
static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||
u32 *resp) { return -ENODEV; }
|
||||
static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
|
||||
{ return -ENODEV; }
|
||||
static inline u32 qcom_scm_get_version(void) { return 0; }
|
||||
static inline u32
|
||||
qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
|
||||
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
|
||||
static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
|
||||
static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
|
||||
static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; }
|
||||
static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
|
||||
static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
|
||||
static inline bool qcom_scm_is_available(void) { return false; }
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue