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arm: tcc8k: Avoid reading clock register twice

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There is no reason why in case of PLL2 the configuration register
should be read twice, while for PLL0/1 using the value previously read
is used. Do the same for PLL2.

Signed-off-by: Oskar Schirmer <[email protected]>
Cc: [email protected]
Signed-off-by: Thomas Gleixner <[email protected]>
This commit is contained in:
Oskar Schirmer 2011-02-17 16:43:00 +01:00 • committed by Thomas Gleixner
commit 25d7a6003b
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-tcc8k/clock.c
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@ -199,7 +199,7 @@ static unsigned long get_rate_pll_div(int pll)
addr = CKC_BASE + CLKDIVC1_OFFS;
reg = __raw_readl(addr);
if (reg & CLKDIVC1_P2E)
div = __raw_readl(addr) & 0x3f;
div = reg & 0x3f;
break;
}
return get_rate_pll(pll) / (div + 1);