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drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE
Recommended by the hw team. Reviewed-and-Tested-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
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1 changed files with 0 additions and 19 deletions
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@ -1959,25 +1959,6 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
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mutex_unlock(&adev->srbm_mutex);
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gfx_v9_0_init_compute_vmid(adev);
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mutex_lock(&adev->grbm_idx_mutex);
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/*
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* making sure that the following register writes will be broadcasted
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* to all the shaders
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*/
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gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
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(adev->gfx.config.sc_prim_fifo_size_frontend <<
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PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
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(adev->gfx.config.sc_prim_fifo_size_backend <<
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PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
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(adev->gfx.config.sc_hiz_tile_fifo_size <<
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PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
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(adev->gfx.config.sc_earlyz_tile_fifo_size <<
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PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
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