From a81e6a55fe212000db22d919c0988c4c36916d5b Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 24 Jun 2020 02:00:36 +0530 Subject: [PATCH 1/2] disp: msm: dsi: Fix pll delay calculation during clock switch During clock switch, Pll delay is calculated considering escape clock to be in KHz. But escape clock is in Hz. This leads to wrong pll delay calculation. Change-Id: I616d16cc3d775a37e77c7c35bb860c23b1f9e37a Signed-off-by: Ritesh Kumar --- msm/dsi/dsi_clk.h | 8 ++++---- msm/dsi/dsi_defs.h | 2 +- msm/dsi/dsi_display.c | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/msm/dsi/dsi_clk.h b/msm/dsi/dsi_clk.h index 0859e56cad42..2a88801fa431 100644 --- a/msm/dsi/dsi_clk.h +++ b/msm/dsi/dsi_clk.h @@ -105,10 +105,10 @@ struct dsi_link_lp_clk_info { /** * struct link_clk_freq - Clock frequency information for Link clocks - * @byte_clk_rate: Frequency of DSI byte_clk in KHz. - * @byte_intf_clk_rate: Frequency of DSI byte_intf_clk in KHz. - * @pixel_clk_rate: Frequency of DSI pixel_clk in KHz. - * @esc_clk_rate: Frequency of DSI escape clock in KHz. + * @byte_clk_rate: Frequency of DSI byte_clk in Hz. + * @byte_intf_clk_rate: Frequency of DSI byte_intf_clk in Hz. + * @pixel_clk_rate: Frequency of DSI pixel_clk in Hz. + * @esc_clk_rate: Frequency of DSI escape clock in Hz. */ struct link_clk_freq { u32 byte_clk_rate; diff --git a/msm/dsi/dsi_defs.h b/msm/dsi/dsi_defs.h index f3f309635468..327af9e3b6a1 100644 --- a/msm/dsi/dsi_defs.h +++ b/msm/dsi/dsi_defs.h @@ -556,7 +556,7 @@ struct dsi_cmd_engine_cfg { * @common_config: Host configuration common to both Video and Cmd mode. * @video_engine: Video engine configuration if panel is in video mode. * @cmd_engine: Cmd engine configuration if panel is in cmd mode. - * @esc_clk_rate_khz: Esc clock frequency in Hz. + * @esc_clk_rate_hz: Esc clock frequency in Hz. * @bit_clk_rate_hz: Bit clock frequency in Hz. * @bit_clk_rate_hz_override: DSI bit clk rate override from dt/sysfs. * @video_timing: Video timing information of a frame. diff --git a/msm/dsi/dsi_display.c b/msm/dsi/dsi_display.c index 120445b8874a..d0a8418c0360 100644 --- a/msm/dsi/dsi_display.c +++ b/msm/dsi/dsi_display.c @@ -4332,12 +4332,12 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display, cfg = &(m_ctrl->phy->cfg); - esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate * 1000; - pclk_to_esc_ratio = ((dsi_ctrl->clk_freq.pix_clk_rate * 1000) / + esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate; + pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate / esc_clk_rate_hz); - byte_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 1000) / + byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate / esc_clk_rate_hz); - hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4 * 1000) / + hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) / esc_clk_rate_hz); hsync_period = dsi_h_total_dce(&mode->timing); From fc571a94aaf181d2c0c2ee8448d113ca6ee825c7 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 26 Jun 2020 12:46:53 +0530 Subject: [PATCH 2/2] disp: msm: dsi: Update pll delay calculation as per latest DSI HPG As per DSI HPG, pll delay should be 25usec for phy ver 4.0 and 100usec for phy ver 2.0 and 3.0. This change updates pll delay calculation during dynamic DSI clock switch accordingly. Change-Id: Ief5cbdc9304cf5ad025fe3bbe689b93834a1f710 Signed-off-by: Ritesh Kumar --- msm/dsi/dsi_display.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/msm/dsi/dsi_display.c b/msm/dsi/dsi_display.c index d0a8418c0360..34ba47b6e59c 100644 --- a/msm/dsi/dsi_display.c +++ b/msm/dsi/dsi_display.c @@ -4326,6 +4326,7 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display, struct dsi_display_ctrl *m_ctrl; struct dsi_ctrl *dsi_ctrl; struct dsi_phy_cfg *cfg; + int phy_ver; m_ctrl = &display->ctrl[display->clk_master_idx]; dsi_ctrl = m_ctrl->ctrl; @@ -4363,8 +4364,17 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display, ((cfg->timing.lane_v3[4] >> 1) + 1)) / hr_bit_to_esc_ratio); - /* 130 us pll delay recommended by h/w doc */ - delay->pll_delay = ((130 * esc_clk_rate_hz) / 1000000) * 2; + /* + * 100us pll delay recommended for phy ver 2.0 and 3.0 + * 25us pll delay recommended for phy ver 4.0 + */ + phy_ver = dsi_phy_get_version(m_ctrl->phy); + if (phy_ver <= DSI_PHY_VERSION_3_0) + delay->pll_delay = 100; + else + delay->pll_delay = 25; + + delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000); } static int _dsi_display_dyn_update_clks(struct dsi_display *display,