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msm: kgsl: Remove unneeded parameters for the sharedmem funcs

Browse source 
We do not need to pass a struct kgsl_device pointer to
kgsl_sharedmem_writel and kgsl_sharedmem_writeq which makes life slightly
easier when we don't have to worry about dereferencing pointers. The same
goes for kgsl_sharedmem_set too but that function is only used twice and
can be easily replaced by a memset() so just do that instead.

Change-Id: Ic0dedbadef4bfef8da9bf4c89a6a36e27e6f7da5
Signed-off-by: Jordan Crouse <[email protected]>
This commit is contained in:
Jordan Crouse 2020-02-04 14:52:21 -07:00
commit 2624c1e3d5
12 changed files with 101 additions and 141 deletions
Download patch file Download diff file Expand all files Collapse all files

8
drivers/gpu/msm/adreno.c
View file

@ -1860,9 +1860,8 @@ static void adreno_set_active_ctxs_null(struct adreno_device *adreno_dev)
kgsl_context_put(&(rb->drawctxt_active->base));
rb->drawctxt_active = NULL;
kgsl_sharedmem_writel(KGSL_DEVICE(adreno_dev),
rb->pagetable_desc, PT_INFO_OFFSET(current_rb_ptname),
0);
kgsl_sharedmem_writel(rb->pagetable_desc,
PT_INFO_OFFSET(current_rb_ptname), 0);
}
}
@ -1877,8 +1876,7 @@ static int adreno_first_open(struct kgsl_device *device)
*/
atomic_inc(&device->active_cnt);
kgsl_sharedmem_set(device, device->memstore, 0, 0,
device->memstore->size);
memset(device->memstore->hostptr, 0, device->memstore->size);
ret = adreno_init(device);
if (ret)

13
drivers/gpu/msm/adreno.h
View file

@ -1464,29 +1464,24 @@ static inline bool adreno_support_64bit(struct adreno_device *adreno_dev)
static inline void adreno_ringbuffer_set_global(
struct adreno_device *adreno_dev, int name)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
kgsl_sharedmem_writel(device,
adreno_dev->ringbuffers[0].pagetable_desc,
kgsl_sharedmem_writel(adreno_dev->ringbuffers[0].pagetable_desc,
PT_INFO_OFFSET(current_global_ptname), name);
}
static inline void adreno_ringbuffer_set_pagetable(struct adreno_ringbuffer *rb,
struct kgsl_pagetable *pt)
{
struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
unsigned long flags;
spin_lock_irqsave(&rb->preempt_lock, flags);
kgsl_sharedmem_writel(device, rb->pagetable_desc,
kgsl_sharedmem_writel(rb->pagetable_desc,
PT_INFO_OFFSET(current_rb_ptname), pt->name);
kgsl_sharedmem_writeq(device, rb->pagetable_desc,
kgsl_sharedmem_writeq(rb->pagetable_desc,
PT_INFO_OFFSET(ttbr0), kgsl_mmu_pagetable_get_ttbr0(pt));
kgsl_sharedmem_writel(device, rb->pagetable_desc,
kgsl_sharedmem_writel(rb->pagetable_desc,
PT_INFO_OFFSET(contextidr),
kgsl_mmu_pagetable_get_contextidr(pt));

36
drivers/gpu/msm/adreno_a5xx_preempt.c
View file

@ -225,15 +225,15 @@ void a5xx_preemption_trigger(struct adreno_device *adreno_dev)
kgsl_sharedmem_readl(next->pagetable_desc, &contextidr,
PT_INFO_OFFSET(contextidr));
kgsl_sharedmem_writel(device, next->preemption_desc,
kgsl_sharedmem_writel(next->preemption_desc,
PREEMPT_RECORD(wptr), next->wptr);
spin_unlock_irqrestore(&next->preempt_lock, flags);
/* And write it to the smmu info */
kgsl_sharedmem_writeq(device, iommu->smmu_info,
kgsl_sharedmem_writeq(iommu->smmu_info,
PREEMPT_SMMU_RECORD(ttbr0), ttbr0);
kgsl_sharedmem_writel(device, iommu->smmu_info,
kgsl_sharedmem_writel(iommu->smmu_info,
PREEMPT_SMMU_RECORD(context_idr), contextidr);
kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,
@ -443,15 +443,15 @@ void a5xx_preemption_start(struct adreno_device *adreno_dev)
adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
/* smmu_info is allocated and mapped in a5xx_preemption_iommu_init */
kgsl_sharedmem_writel(device, iommu->smmu_info,
kgsl_sharedmem_writel(iommu->smmu_info,
PREEMPT_SMMU_RECORD(magic), A5XX_CP_SMMU_INFO_MAGIC_REF);
kgsl_sharedmem_writeq(device, iommu->smmu_info,
kgsl_sharedmem_writeq(iommu->smmu_info,
PREEMPT_SMMU_RECORD(ttbr0), MMU_DEFAULT_TTBR0(device));
/* The CP doesn't use the asid record, so poison it */
kgsl_sharedmem_writel(device, iommu->smmu_info,
kgsl_sharedmem_writel(iommu->smmu_info,
PREEMPT_SMMU_RECORD(asid), 0xDECAFBAD);
kgsl_sharedmem_writel(device, iommu->smmu_info,
kgsl_sharedmem_writel(iommu->smmu_info,
PREEMPT_SMMU_RECORD(context_idr),
MMU_DEFAULT_CONTEXTIDR(device));
@ -466,9 +466,9 @@ void a5xx_preemption_start(struct adreno_device *adreno_dev)
* preemption_desc is allocated and mapped at init time,
* so no need to check sharedmem_writel return value
*/
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(rptr), 0);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(wptr), 0);
adreno_ringbuffer_set_pagetable(rb,
@ -490,24 +490,24 @@ static int a5xx_preemption_ringbuffer_init(struct adreno_device *adreno_dev,
if (IS_ERR(rb->preemption_desc))
return PTR_ERR(rb->preemption_desc);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(magic), A5XX_CP_CTXRECORD_MAGIC_REF);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(info), 0);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(data), 0);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(cntl), A5XX_CP_RB_CNTL_DEFAULT);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(rptr), 0);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(wptr), 0);
kgsl_sharedmem_writeq(device, rb->preemption_desc,
kgsl_sharedmem_writeq(rb->preemption_desc,
PREEMPT_RECORD(rptr_addr), SCRATCH_RPTR_GPU_ADDR(device,
rb->id));
kgsl_sharedmem_writeq(device, rb->preemption_desc,
kgsl_sharedmem_writeq(rb->preemption_desc,
PREEMPT_RECORD(rbase), rb->buffer_desc->gpuaddr);
kgsl_sharedmem_writeq(device, rb->preemption_desc,
kgsl_sharedmem_writeq(rb->preemption_desc,
PREEMPT_RECORD(counter), counteraddr);
return 0;

2
drivers/gpu/msm/adreno_a6xx.c
View file

@ -774,7 +774,7 @@ static int a6xx_send_cp_init(struct adreno_device *adreno_dev,
adreno_spin_idle_debug(adreno_dev,
"CP initialization failed to idle\n");
kgsl_sharedmem_writel(device, device->scratch,
kgsl_sharedmem_writel(device->scratch,
SCRATCH_RPTR_OFFSET(rb->id), 0);
rb->wptr = 0;
rb->_wptr = 0;

40
drivers/gpu/msm/adreno_a6xx_preempt.c
View file

@ -260,15 +260,15 @@ void a6xx_preemption_trigger(struct adreno_device *adreno_dev)
kgsl_sharedmem_readl(next->pagetable_desc, &contextidr,
PT_INFO_OFFSET(contextidr));
kgsl_sharedmem_writel(device, next->preemption_desc,
kgsl_sharedmem_writel(next->preemption_desc,
PREEMPT_RECORD(wptr), next->wptr);
spin_unlock_irqrestore(&next->preempt_lock, flags);
/* And write it to the smmu info */
kgsl_sharedmem_writeq(device, iommu->smmu_info,
kgsl_sharedmem_writeq(iommu->smmu_info,
PREEMPT_SMMU_RECORD(ttbr0), ttbr0);
kgsl_sharedmem_writel(device, iommu->smmu_info,
kgsl_sharedmem_writel(iommu->smmu_info,
PREEMPT_SMMU_RECORD(context_idr), contextidr);
kgsl_sharedmem_readq(device->scratch, &gpuaddr,
@ -560,15 +560,15 @@ void a6xx_preemption_start(struct adreno_device *adreno_dev)
adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
/* smmu_info is allocated and mapped in a6xx_preemption_iommu_init */
kgsl_sharedmem_writel(device, iommu->smmu_info,
kgsl_sharedmem_writel(iommu->smmu_info,
PREEMPT_SMMU_RECORD(magic), A6XX_CP_SMMU_INFO_MAGIC_REF);
kgsl_sharedmem_writeq(device, iommu->smmu_info,
kgsl_sharedmem_writeq(iommu->smmu_info,
PREEMPT_SMMU_RECORD(ttbr0), MMU_DEFAULT_TTBR0(device));
/* The CP doesn't use the asid record, so poison it */
kgsl_sharedmem_writel(device, iommu->smmu_info,
kgsl_sharedmem_writel(iommu->smmu_info,
PREEMPT_SMMU_RECORD(asid), 0xDECAFBAD);
kgsl_sharedmem_writel(device, iommu->smmu_info,
kgsl_sharedmem_writel(iommu->smmu_info,
PREEMPT_SMMU_RECORD(context_idr),
MMU_DEFAULT_CONTEXTIDR(device));
@ -579,13 +579,9 @@ void a6xx_preemption_start(struct adreno_device *adreno_dev)
upper_32_bits(iommu->smmu_info->gpuaddr));
FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
/*
* preemption_desc is allocated and mapped at init time,
* so no need to check sharedmem_writel return value
*/
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(rptr), 0);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(wptr), 0);
adreno_ringbuffer_set_pagetable(rb,
@ -623,24 +619,24 @@ static int a6xx_preemption_ringbuffer_init(struct adreno_device *adreno_dev,
if (IS_ERR(rb->perfcounter_save_restore_desc))
return PTR_ERR(rb->perfcounter_save_restore_desc);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(magic), A6XX_CP_CTXRECORD_MAGIC_REF);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(info), 0);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(data), 0);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(cntl), A6XX_CP_RB_CNTL_DEFAULT);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(rptr), 0);
kgsl_sharedmem_writel(device, rb->preemption_desc,
kgsl_sharedmem_writel(rb->preemption_desc,
PREEMPT_RECORD(wptr), 0);
kgsl_sharedmem_writeq(device, rb->preemption_desc,
kgsl_sharedmem_writeq(rb->preemption_desc,
PREEMPT_RECORD(rptr_addr), SCRATCH_RPTR_GPU_ADDR(device,
rb->id));
kgsl_sharedmem_writeq(device, rb->preemption_desc,
kgsl_sharedmem_writeq(rb->preemption_desc,
PREEMPT_RECORD(rbase), rb->buffer_desc->gpuaddr);
kgsl_sharedmem_writeq(device, rb->preemption_desc,
kgsl_sharedmem_writeq(rb->preemption_desc,
PREEMPT_RECORD(counter), 0);
return 0;

12
drivers/gpu/msm/adreno_dispatch.c
View file

@ -276,11 +276,11 @@ static void _retire_timestamp(struct kgsl_drawobj *drawobj)
* Write the start and end timestamp to the memstore to keep the
* accounting sane
*/
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(context->id, soptimestamp),
drawobj->timestamp);
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(context->id, eoptimestamp),
drawobj->timestamp);
@ -2190,11 +2190,11 @@ static int dispatcher_do_fault(struct adreno_device *adreno_dev)
*/
if (hung_rb != NULL) {
kgsl_sharedmem_writel(device, device->memstore,
MEMSTORE_RB_OFFSET(hung_rb, soptimestamp),
hung_rb->timestamp);
kgsl_sharedmem_writel(device->memstore,
MEMSTORE_RB_OFFSET(hung_rb, soptimestamp),
hung_rb->timestamp);
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
MEMSTORE_RB_OFFSET(hung_rb, eoptimestamp),
hung_rb->timestamp);

12
drivers/gpu/msm/adreno_drawctxt.c
View file

@ -268,11 +268,11 @@ void adreno_drawctxt_invalidate(struct kgsl_device *device,
* set the timestamp to the last value since the context is invalidated
* and we want the pending events for this context to go away
*/
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(context->id, soptimestamp),
drawctxt->timestamp);
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(context->id, eoptimestamp),
drawctxt->timestamp);
@ -396,10 +396,10 @@ adreno_drawctxt_create(struct kgsl_device_private *dev_priv,
return ERR_PTR(ret);
}
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(drawctxt->base.id, soptimestamp),
0);
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(drawctxt->base.id, eoptimestamp),
0);
@ -511,11 +511,11 @@ void adreno_drawctxt_detach(struct kgsl_context *context)
return;
}
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(context->id, soptimestamp),
drawctxt->timestamp);
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(context->id, eoptimestamp),
drawctxt->timestamp);

2
drivers/gpu/msm/adreno_iommu.c
View file

@ -388,7 +388,7 @@ void adreno_iommu_init(struct adreno_device *adreno_dev)
iommu->setstate = kgsl_allocate_global(device, PAGE_SIZE,
KGSL_MEMFLAGS_GPUREADONLY, 0, "setstate");
kgsl_sharedmem_writel(device, iommu->setstate,
kgsl_sharedmem_writel(iommu->setstate,
KGSL_IOMMU_SETSTATE_NOP_OFFSET,
cp_type3_packet(CP_NOP, 1));
}

5
drivers/gpu/msm/adreno_ringbuffer.c
View file

@ -230,10 +230,9 @@ int adreno_ringbuffer_start(struct adreno_device *adreno_dev)
/* Setup the ringbuffers state before we start */
FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
kgsl_sharedmem_set(device, rb->buffer_desc,
0, 0xAA, KGSL_RB_SIZE);
memset(rb->buffer_desc->hostptr, 0xaa, KGSL_RB_SIZE);
if (!adreno_is_a3xx(adreno_dev))
kgsl_sharedmem_writel(device, device->scratch,
kgsl_sharedmem_writel(device->scratch,
SCRATCH_RPTR_OFFSET(rb->id), 0);
rb->wptr = 0;
rb->_wptr = 0;

4
drivers/gpu/msm/kgsl.c
View file

@ -719,9 +719,9 @@ kgsl_context_destroy(struct kref *kref)
if (context->id != KGSL_CONTEXT_INVALID) {
/* Clear the timestamps in the memstore during destroy */
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(context->id, soptimestamp), 0);
kgsl_sharedmem_writel(device, device->memstore,
kgsl_sharedmem_writel(device->memstore,
KGSL_MEMSTORE_OFFSET(context->id, eoptimestamp), 0);
/* clear device power constraint */

79
drivers/gpu/msm/kgsl_sharedmem.c
View file

@ -813,38 +813,25 @@ kgsl_sharedmem_readl(const struct kgsl_memdesc *memdesc,
return 0;
}
int
kgsl_sharedmem_writel(struct kgsl_device *device,
const struct kgsl_memdesc *memdesc,
void
kgsl_sharedmem_writel(const struct kgsl_memdesc *memdesc,
uint64_t offsetbytes,
uint32_t src)
{
uint32_t *dst;
/* Quietly return if the memdesc isn't valid */
if (IS_ERR_OR_NULL(memdesc))
return -EINVAL;
if (IS_ERR_OR_NULL(memdesc) || WARN_ON(!memdesc->hostptr))
return;
if (WARN_ON(memdesc->hostptr == NULL))
return -EINVAL;
if (WARN_ON(!IS_ALIGNED(offsetbytes, sizeof(u32))))
return;
WARN_ON(offsetbytes % sizeof(uint32_t) != 0);
if (offsetbytes % sizeof(uint32_t) != 0)
return -EINVAL;
if (WARN_ON(offsetbytes > (memdesc->size - sizeof(u32))))
return;
WARN_ON(offsetbytes > (memdesc->size - sizeof(uint32_t)));
if (offsetbytes > (memdesc->size - sizeof(uint32_t)))
return -ERANGE;
dst = (uint32_t *)(memdesc->hostptr + offsetbytes);
*dst = src;
*((u32 *) (memdesc->hostptr + offsetbytes)) = src;
/*
* We are writing to shared memory between CPU and GPU.
* Make sure write above is posted immediately
*/
/* Make sure the write is posted before continuing */
wmb();
return 0;
}
int
@ -876,49 +863,25 @@ kgsl_sharedmem_readq(const struct kgsl_memdesc *memdesc,
return 0;
}
int
kgsl_sharedmem_writeq(struct kgsl_device *device,
const struct kgsl_memdesc *memdesc,
void
kgsl_sharedmem_writeq(const struct kgsl_memdesc *memdesc,
uint64_t offsetbytes,
uint64_t src)
{
uint64_t *dst;
/* Quietly return if the memdesc isn't valid */
if (IS_ERR_OR_NULL(memdesc) || WARN_ON(!memdesc->hostptr))
return;
if (WARN_ON(memdesc == NULL || memdesc->hostptr == NULL))
return -EINVAL;
if (WARN_ON(!IS_ALIGNED(offsetbytes, sizeof(u64))))
return;
WARN_ON(offsetbytes % sizeof(uint32_t) != 0);
if (offsetbytes % sizeof(uint32_t) != 0)
return -EINVAL;
if (WARN_ON(offsetbytes > (memdesc->size - sizeof(u64))))
return;
WARN_ON(offsetbytes > (memdesc->size - sizeof(uint32_t)));
if (offsetbytes > (memdesc->size - sizeof(uint32_t)))
return -ERANGE;
dst = (uint64_t *)(memdesc->hostptr + offsetbytes);
*dst = src;
*((u64 *) (memdesc->hostptr + offsetbytes)) = src;
/*
* We are writing to shared memory between CPU and GPU.
* Make sure write above is posted immediately
*/
/* Make sure the write is posted before continuing */
wmb();
return 0;
}
int
kgsl_sharedmem_set(struct kgsl_device *device,
const struct kgsl_memdesc *memdesc, uint64_t offsetbytes,
unsigned int value, uint64_t sizebytes)
{
if (WARN_ON(memdesc == NULL || memdesc->hostptr == NULL))
return -EINVAL;
if (WARN_ON(offsetbytes + sizebytes > memdesc->size))
return -EINVAL;
memset(memdesc->hostptr + offsetbytes, value, sizebytes);
return 0;
}
static const char * const memtype_str[] = {

29
drivers/gpu/msm/kgsl_sharedmem.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
*/
#ifndef __KGSL_SHAREDMEM_H
#define __KGSL_SHAREDMEM_H
@ -25,8 +25,15 @@ int kgsl_sharedmem_readl(const struct kgsl_memdesc *memdesc,
uint32_t *dst,
uint64_t offsetbytes);
int kgsl_sharedmem_writel(struct kgsl_device *device,
const struct kgsl_memdesc *memdesc,
/**
* kgsl_sharedmem_writel - write a 32 bit value to a shared memory object
* @memdesc: Pointer to a GPU memory object
* @offsetbytes: Offset inside of @memdesc to write to
* @src: Value to write
*
* Write @src to @offsetbytes from the start of @memdesc
*/
void kgsl_sharedmem_writel(const struct kgsl_memdesc *memdesc,
uint64_t offsetbytes,
uint32_t src);
@ -34,16 +41,18 @@ int kgsl_sharedmem_readq(const struct kgsl_memdesc *memdesc,
uint64_t *dst,
uint64_t offsetbytes);
int kgsl_sharedmem_writeq(struct kgsl_device *device,
const struct kgsl_memdesc *memdesc,
/**
* kgsl_sharedmem_writeq - write a 64 bit value to a shared memory object
* @memdesc: Pointer to a GPU memory object
* @offsetbytes: Offset inside of @memdesc to write to
* @src: Value to write
*
* Write @src to @offsetbytes from the start of @memdesc
*/
void kgsl_sharedmem_writeq(const struct kgsl_memdesc *memdesc,
uint64_t offsetbytes,
uint64_t src);
int kgsl_sharedmem_set(struct kgsl_device *device,
const struct kgsl_memdesc *memdesc,
uint64_t offsetbytes, unsigned int value,
uint64_t sizebytes);
int kgsl_cache_range_op(struct kgsl_memdesc *memdesc,
uint64_t offset, uint64_t size,
unsigned int op);