mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
"This is the main drm pull request for 4.6 kernel.
Overall the coolest thing here for me is the nouveau maxwell signed
firmware support from NVidia, it's taken a long while to extract this
from them.
I also wish the ARM vendors just designed one set of display IP, ARM
display block proliferation is definitely increasing.
Core:
- drm_event cleanups
- Internal API cleanup making mode_fixup optional.
- Apple GMUX vga switcheroo support.
- DP AUX testing interface
Panel:
- Refactoring of DSI core for use over more transports.
New driver:
- ARM hdlcd driver
i915:
- FBC/PSR (framebuffer compression, panel self refresh) enabled by default.
- Ongoing atomic display support work
- Ongoing runtime PM work
- Pixel clock limit checks
- VBT DSI description support
- GEM fixes
- GuC firmware scheduler enhancements
amdkfd:
- Deferred probing fixes to avoid make file or link ordering.
amdgpu/radeon:
- ACP support for i2s audio support.
- Command Submission/GPU scheduler/GPUVM optimisations
- Initial GPU reset support for amdgpu
vmwgfx:
- Support for DX10 gen mipmaps
- Pageflipping and other fixes.
exynos:
- Exynos5420 SoC support for FIMD
- Exynos5422 SoC support for MIPI-DSI
nouveau:
- GM20x secure boot support - adds acceleration for Maxwell GPUs.
- GM200 support
- GM20B clock driver support
- Power sensors work
etnaviv:
- Correctness fixes for GPU cache flushing
- Better support for i.MX6 systems.
imx-drm:
- VBlank IRQ support
- Fence support
- OF endpoint support
msm:
- HDMI support for 8996 (snapdragon 820)
- Adreno 430 support
- Timestamp queries support
virtio-gpu:
- Fixes for Android support.
rockchip:
- Add support for Innosilicion HDMI
rcar-du:
- Support for 4 crtcs
- R8A7795 support
- RCar Gen 3 support
omapdrm:
- HDMI interlace output support
- dma-buf import support
- Refactoring to remove a lot of legacy code.
tilcdc:
- Rewrite of pageflipping code
- dma-buf support
- pinctrl support
vc4:
- HDMI modesetting bug fixes
- Significant 3D performance improvement.
fsl-dcu (FreeScale):
- Lots of fixes
tegra:
- Two small fixes
sti:
- Atomic support for planes
- Improved HDMI support"
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (1063 commits)
drm/amdgpu: release_pages requires linux/pagemap.h
drm/sti: restore mode_fixup callback
drm/amdgpu/gfx7: add MTYPE definition
drm/amdgpu: removing BO_VAs shouldn't be interruptible
drm/amd/powerplay: show uvd/vce power gate enablement for tonga.
drm/amd/powerplay: show uvd/vce power gate info for fiji
drm/amdgpu: use sched fence if possible
drm/amdgpu: move ib.fence to job.fence
drm/amdgpu: give a fence param to ib_free
drm/amdgpu: include the right version of gmc header files for iceland
drm/radeon: fix indentation.
drm/amd/powerplay: add uvd/vce dpm enabling flag to fix the performance issue for CZ
drm/amdgpu: switch back to 32bit hw fences v2
drm/amdgpu: remove amdgpu_fence_is_signaled
drm/amdgpu: drop the extra fence range check v2
drm/amdgpu: signal fences directly in amdgpu_fence_process
drm/amdgpu: cleanup amdgpu_fence_wait_empty v2
drm/amdgpu: keep all fences in an RCU protected array v2
drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ring
drm/amdgpu: RCU protected amd_sched_fence_release
...
This commit is contained in:
Linus Torvalds
commit
266c73b777
686 changed files with 39067 additions and 27596 deletions
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@ -35,6 +35,12 @@ Optional properties for HDMI:
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as an interrupt/status bit in the HDMI controller
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itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
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Required properties for V3D:
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- compatible: Should be "brcm,bcm2835-v3d"
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- reg: Physical base address and length of the V3D's registers
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- interrupts: The interrupt number
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See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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Example:
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pixelvalve@7e807000 {
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compatible = "brcm,bcm2835-pixelvalve2";
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@ -60,6 +66,12 @@ hdmi: hdmi@7e902000 {
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clock-names = "pixel", "hdmi";
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};
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v3d: v3d@7ec00000 {
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compatible = "brcm,bcm2835-v3d";
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reg = <0x7ec00000 0x1000>;
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interrupts = <1 10>;
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};
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vc4: gpu {
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compatible = "brcm,bcm2835-vc4";
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};
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@ -6,6 +6,7 @@ Required properties:
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"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
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"samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
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"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
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"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
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"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
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- reg: physical base address and length of the registers set for the device
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- interrupts: should contain DSI interrupt
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@ -12,7 +12,8 @@ Required properties:
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"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
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"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
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"samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
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"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
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"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
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"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
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- reg: physical base address and length of the FIMD registers set.
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@ -44,9 +44,34 @@ Optional properties:
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- pinctrl-names: the pin control state names; should contain "default"
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- pinctrl-0: the default pinctrl state (active)
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- pinctrl-n: the "sleep" pinctrl state
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- port: DSI controller output port. This contains one endpoint subnode, with its
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remote-endpoint set to the phandle of the connected panel's endpoint.
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See Documentation/devicetree/bindings/graph.txt for device graph info.
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- port: DSI controller output port, containing one endpoint subnode.
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DSI Endpoint properties:
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- remote-endpoint: set to phandle of the connected panel's endpoint.
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See Documentation/devicetree/bindings/graph.txt for device graph info.
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- qcom,data-lane-map: this describes how the logical DSI lanes are mapped
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to the physical lanes on the given platform. The value contained in
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index n describes what logical data lane is mapped to the physical data
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lane n (DATAn, where n lies between 0 and 3).
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For example:
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qcom,data-lane-map = <3 0 1 2>;
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The above mapping describes that the logical data lane DATA3 is mapped to
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the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
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to phys DATA2 and logic DATA2 to phys DATA3.
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There are only a limited number of physical to logical mappings possible:
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"0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
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"3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
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"2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
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"1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
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"0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
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"1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
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"2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
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"3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
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DSI PHY:
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Required properties:
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@ -131,6 +156,7 @@ Example:
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port {
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dsi0_out: endpoint {
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remote-endpoint = <&panel_in>;
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lanes = <0 1 2 3>;
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};
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};
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};
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@ -11,6 +11,7 @@ Required properties:
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- reg: Physical base address and length of the controller's registers
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- reg-names: "core_physical"
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- interrupts: The interrupt signal from the hdmi block.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: device clocks
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See ../clocks/clock-bindings.txt for details.
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- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
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@ -18,6 +19,8 @@ Required properties:
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- qcom,hdmi-tx-hpd-gpio: hpd pin
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- core-vdda-supply: phandle to supply regulator
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- hdmi-mux-supply: phandle to mux regulator
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- phys: the phandle for the HDMI PHY device
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- phy-names: the name of the corresponding PHY device
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Optional properties:
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- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
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@ -27,15 +30,38 @@ Optional properties:
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- pinctrl-0: the default pinctrl state (active)
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- pinctrl-1: the "sleep" pinctrl state
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HDMI PHY:
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Required properties:
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- compatible: Could be the following
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* "qcom,hdmi-phy-8660"
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* "qcom,hdmi-phy-8960"
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* "qcom,hdmi-phy-8974"
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* "qcom,hdmi-phy-8084"
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* "qcom,hdmi-phy-8996"
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- #phy-cells: Number of cells in a PHY specifier; Should be 0.
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- reg: Physical base address and length of the registers of the PHY sub blocks.
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- reg-names: The names of register regions. The following regions are required:
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* "hdmi_phy"
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* "hdmi_pll"
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For HDMI PHY on msm8996, these additional register regions are required:
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* "hdmi_tx_l0"
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* "hdmi_tx_l1"
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* "hdmi_tx_l3"
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* "hdmi_tx_l4"
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
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- core-vdda-supply: phandle to vdda regulator device node
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Example:
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/ {
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...
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hdmi: qcom,hdmi-tx-8960@4a00000 {
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hdmi: hdmi@4a00000 {
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compatible = "qcom,hdmi-tx-8960";
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reg-names = "core_physical";
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reg = <0x04a00000 0x1000>;
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reg = <0x04a00000 0x2f0>;
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interrupts = <GIC_SPI 79 0>;
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power-domains = <&mmcc MDSS_GDSC>;
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clock-names =
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
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pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
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phys = <&hdmi_phy>;
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phy-names = "hdmi_phy";
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};
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hdmi_phy: phy@4a00400 {
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compatible = "qcom,hdmi-phy-8960";
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reg-names = "hdmi_phy",
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"hdmi_pll";
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reg = <0x4a00400 0x60>,
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<0x4a00500 0x100>;
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#phy-cells = <0>;
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power-domains = <&mmcc MDSS_GDSC>;
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clock-names = "slave_iface_clk";
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clocks = <&mmcc HDMI_S_AHB_CLK>;
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core-vdda-supply = <&pm8921_hdmi_mvs>;
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};
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};
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@ -0,0 +1,7 @@
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LG 12.0" (1920x1280 pixels) TFT LCD panel
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Required properties:
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- compatible: should be "lg,lp120up1"
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@ -0,0 +1,16 @@
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United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT LCD panel
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Supported are LVDS versions (-11T, -19T) and parallel ones
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(-T, -1T, -7T, -20T).
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Required properties:
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- compatible: should be one of:
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"urt,umsh-8596md-t",
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"urt,umsh-8596md-1t",
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"urt,umsh-8596md-7t",
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"urt,umsh-8596md-11t",
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"urt,umsh-8596md-19t",
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"urt,umsh-8596md-20t".
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@ -8,6 +8,7 @@ Required Properties:
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- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
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- "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
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- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
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- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
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- reg: A list of base address and length of each memory resource, one for
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each entry in the reg-names property.
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@ -24,7 +25,7 @@ Required Properties:
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- clock-names: Name of the clocks. This property is model-dependent.
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- R8A7779 uses a single functional clock. The clock doesn't need to be
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named.
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- R8A779[0134] use one functional clock per channel and one clock per LVDS
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- R8A779[01345] use one functional clock per channel and one clock per LVDS
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encoder (if available). The functional clocks must be named "du.x" with
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"x" being the channel numerical index. The LVDS clocks must be named
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"lvds.x" with "x" being the LVDS encoder numerical index.
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@ -41,13 +42,14 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
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The following table lists for each supported model the port number
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corresponding to each DU output.
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Port 0 Port1 Port2
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Port 0 Port1 Port2 Port3
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-----------------------------------------------------------------------------
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R8A7779 (H1) DPAD 0 DPAD 1 -
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R8A7790 (H2) DPAD LVDS 0 LVDS 1
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R8A7791 (M2-W) DPAD LVDS 0 -
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R8A7793 (M2-N) DPAD LVDS 0 -
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R8A7794 (E2) DPAD 0 DPAD 1 -
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R8A7779 (H1) DPAD 0 DPAD 1 - -
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R8A7790 (H2) DPAD LVDS 0 LVDS 1 -
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R8A7791 (M2-W) DPAD LVDS 0 - -
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R8A7793 (M2-N) DPAD LVDS 0 - -
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R8A7794 (E2) DPAD 0 DPAD 1 - -
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R8A7795 (H3) DPAD HDMI 0 HDMI 1 LVDS
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Example: R8A7790 (R-Car H2) DU
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@ -0,0 +1,50 @@
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Rockchip specific extensions to the Innosilicon HDMI
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================================
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Required properties:
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- compatible:
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"rockchip,rk3036-inno-hdmi";
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- reg:
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Physical base address and length of the controller's registers.
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- clocks, clock-names:
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Phandle to hdmi controller clock, name should be "pclk"
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- interrupts:
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HDMI interrupt number
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- ports:
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Contain one port node with endpoint definitions as defined in
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Documentation/devicetree/bindings/graph.txt.
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- pinctrl-0, pinctrl-name:
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Switch the iomux of HPD/CEC pins to HDMI function.
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Example:
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hdmi: hdmi@20034000 {
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compatible = "rockchip,rk3036-inno-hdmi";
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reg = <0x20034000 0x4000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_HDMI>;
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clock-names = "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_ctl>;
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status = "disabled";
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hdmi_in: port {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in_lcdc: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&lcdc_out_hdmi>;
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};
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};
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};
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&pinctrl {
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hdmi {
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hdmi_ctl: hdmi-ctl {
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rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
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<1 9 RK_FUNC_1 &pcfg_pull_none>,
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<1 10 RK_FUNC_1 &pcfg_pull_none>,
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<1 11 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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||||
};
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Loading…
Reference in a new issue