diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi
index 946a4e6b96c9..7ef5e8bcb93f 100644
--- a/qcom/lahaina-usb.dtsi
+++ b/qcom/lahaina-usb.dtsi
@@ -174,7 +174,7 @@
 
 		qcom,qmp-phy-init-seq =
 			/* <reg_offset, value, delay> */
-			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x0a 0
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
 			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
 			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
 			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
@@ -217,44 +217,45 @@
 			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
 			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
 			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x55 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x2A 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0
 			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
 			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0
 			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
 			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
 			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
 			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
 			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
 			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x04 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
 			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
 			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x08 0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0
 			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
 			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
 			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
 			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
 			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
 			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
 			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x3F 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x94 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0
 			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x5B 0
 			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1B 0
 			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
 			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
 			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
 			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x00 0
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
 			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
 			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
 			USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
@@ -262,44 +263,45 @@
 			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
 			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
 			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x55 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x2A 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0
 			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
 			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x02 0
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0
 			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0
 			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
 			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
 			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
 			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
 			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x04 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
 			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
 			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x08 0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0
 			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
 			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
 			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
 			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
 			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
 			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
 			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x94 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0
 			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x5B 0
 			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1B 0
 			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
 			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
 			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
 			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x00 0
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
 			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
 			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
 			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
@@ -490,27 +492,27 @@
 				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
 				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
 				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xB8 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xFF 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xB7 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x7F 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xFF 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7F 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0xBD 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xDC 0
 				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xB4 0
 				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0
 				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5C 0
 				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xDC 0
 				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xDC 0
 				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
-				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0
 				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
-				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
-				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04 0
 				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0
 				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
 				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x09 0
 				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
-				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0C 0
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0
 				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
 				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
 				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
@@ -518,13 +520,15 @@
 				USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
 				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0
 				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0
-				USB3_UNI_QSERDES_RX_GM_CAL 0x1F 0
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05 0
+				USB3_UNI_QSERDES_RX_GM_CAL 0x00 0
 				USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0
-				USB3_UNI_QSERDES_TX_LANE_MODE_1 0xD5 0
-				USB3_UNI_QSERDES_TX_LANE_MODE_2 0x80 0
-				USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0
 				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0
 				USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0
 				USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
 				USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0