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Merge tag 'LA.UM.9.14.r1-21200-LAHAINA.QSSI13.0' of https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers into android13-5.4-lahaina

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"LA.UM.9.14.r1-21200-LAHAINA.QSSI13.0"

* tag 'LA.UM.9.14.r1-21200-LAHAINA.QSSI13.0' of https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers:
  disp: msm: sde: drop suspend state if commit is skipped
  disp: msm: sde: cancel delayed idle_notify_work beginning of every commit
  disp: msm: dsi: add missing dsi ctrl mutex lock in host timing update
  disp: rsc: update mode-1 threshold config to 1 hz
  disp: msm: dsi: Handle absence of dsi select clocks in device-tree

Change-Id: I7740381b7589295c83d5fb18fbba4def0fbce8ce
This commit is contained in:
Michael Bestas 2023-03-19 17:13:03 +02:00
commit 27fc8da46b
No known key found for this signature in database
GPG key ID: CC95044519BE6669
5 changed files with 29 additions and 6 deletions
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4
techpack/display/msm/dsi/dsi_ctrl.c
View file

@ -3076,6 +3076,8 @@ int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl)
return -EINVAL;
}
mutex_lock(&dsi_ctrl->ctrl_lock);
if (dsi_ctrl->hw.ops.host_setup)
dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
&dsi_ctrl->host_config.common_config);
@ -3093,9 +3095,11 @@ int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl)
0x0, NULL);
} else {
DSI_CTRL_ERR(dsi_ctrl, "invalid panel mode for resolution switch\n");
mutex_unlock(&dsi_ctrl->ctrl_lock);
return -EINVAL;
}
mutex_unlock(&dsi_ctrl->ctrl_lock);
return 0;
}

6
techpack/display/msm/dsi/dsi_display.c
View file

@ -3558,6 +3558,12 @@ static int dsi_display_clocks_init(struct dsi_display *display)
num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
if (num_clk <= 0) {
rc = num_clk;
DSI_WARN("failed to read %s, rc = %d\n", dsi_clock_name, num_clk);
goto error;
}
DSI_DEBUG("clk count=%d\n", num_clk);
for (i = 0; i < num_clk; i++) {

8
techpack/display/msm/sde/sde_crtc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
@ -3323,6 +3323,12 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
_sde_crtc_blend_setup(crtc, old_state, true);
_sde_crtc_dest_scaler_setup(crtc);
/* cancel the idle notify delayed work */
if (sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
MSM_DISPLAY_VIDEO_MODE) &&
kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work))
SDE_DEBUG("idle notify work cancelled\n");
if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty)
sde_core_perf_crtc_update_uidle(crtc, true);

12
techpack/display/msm/sde/sde_kms.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
@ -3907,6 +3907,7 @@ retry:
DRM_ERROR("failed to get crtc %d state\n",
conn->state->crtc->base.id);
drm_connector_list_iter_end(&conn_iter);
ret = -EINVAL;
goto unlock;
}
@ -3945,6 +3946,12 @@ unlock:
drm_modeset_backoff(&ctx);
goto retry;
}
if ((ret || !num_crtcs) && sde_kms->suspend_state) {
drm_atomic_state_put(sde_kms->suspend_state);
sde_kms->suspend_state = NULL;
}
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
@ -3985,7 +3992,8 @@ static int sde_kms_pm_resume(struct device *dev)
SDE_EVT32(sde_kms->suspend_state != NULL);
drm_mode_config_reset(ddev);
if (sde_kms->suspend_state)
drm_mode_config_reset(ddev);
drm_modeset_acquire_init(&ctx, 0);
retry:

5
techpack/display/msm/sde_rsc.c
View file

@ -368,9 +368,8 @@ static u32 sde_rsc_timer_calculate(struct sde_rsc_priv *rsc,
rsc_time_slot_0_ns = div_u64(rsc_time_slot_0_ns, cxo_period_ns);
rsc->timer_config.rsc_time_slot_0_ns = (u32) rsc_time_slot_0_ns;
/* time_slot_1 for mode1 latency */
rsc_time_slot_1_ns = frame_time_ns;
rsc_time_slot_1_ns = div_u64(rsc_time_slot_1_ns, cxo_period_ns);
/* time_slot_1 for mode1 latency - 1 fps */
rsc_time_slot_1_ns = div_u64(TICKS_IN_NANO_SECOND, cxo_period_ns);
rsc->timer_config.rsc_time_slot_1_ns = (u32) rsc_time_slot_1_ns;
/* mode 2 is infinite */