mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 22:40:54 -04:00
Merge "ARM: dts: msm: add support for VDC-m on lahaina"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
2805c074cf
5 changed files with 518 additions and 1 deletions
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@ -504,7 +504,8 @@ Optional properties:
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|||
- qcom,compression-mode: Select compression mode for panel.
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"fbc" - frame buffer compression
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"dsc" - display stream compression.
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If "dsc" compression is used then config subnodes needs to be defined.
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"vdc" - VESA display compression.
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If "dsc" or "vdc" compression is used then config subnodes needs to be defined.
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- qcom,panel-supply-entries: A node that lists the elements of the supply used to
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||||
power the DSI panel. There can be more than one instance
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of this binding, in which case the entry would be appended
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@ -533,6 +534,26 @@ Optional properties:
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- qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder.
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- qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps
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instead of standard dcs type 0x0A.
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- qcom,vdc-version: An 8 bit value indicates the VDC version supported by panel. Bits[0.3]
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provides information about minor version while Bits[4.7] provides
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major version information. It supports only VDC rev 1(Major).1(Minor)
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right now.
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- qcom,vdc-version-release: An 8 bit value indicated VDC version release. This has to be set to 0.
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- qcom,vdc-slice-height: An u32 value which indicates slice height. This should be atleast 16 lines.
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- qcom,vdc-slice-width: An u32 value which indicates slice width. This should be atleast 64 pixels and
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should also be a multiple of 8
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- qcom,vdc-slice-per-pkt: An u32 value indicates the slice per dsi packet.
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- qcom,vdc-bit-per-component: An u32 value indicates the bits per component before compression.
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- qcom,vdc-bit-per-pixel: An u32 value indicates the bits per pixel after compression.
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- qcom,src-color-space: An u32 value indicating the source color space. It can either be RGB or YUV.
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Default value is assumed to be RGB
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0 - RGB
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1 - YUV
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- qcom,src-chroma-format: An u32 value indicating the source color space. It can either be 444, 420 or 422.
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Default value is assumed to be 444
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0 - 444
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1 - 422
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2 - 420
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- qcom,mdss-pps-delay-ms: An u32 value that indicates post PPS command
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delay in milliseconds. If no value is specified, it chooses zero by default.
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- qcom,display-topology: Array of u32 values which specifies the list of topologies available
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@ -812,6 +833,15 @@ Example:
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qcom,display-topology = <1 1 1>,
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<2 2 1>;
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qcom,default-topology-index = <0>;
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qcom,vdc-version = <0x11>;
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qcom,vdc-version-release = <0>;
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qcom,vdc-slice-height = <256>;
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qcom,vdc-slice-width = <720>;
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qcom,vdc-slice-per-pkt = <2>;
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qcom,vdc-bit-per-component = <8>;
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qcom,vdc-bit-per-pixel = <6>;
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qcom,src-color-space = <0>;
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qcom,src-chroma-format = <0>;
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qcom,mdss-dsi-dma-schedule-line = <5>;
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};
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};
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@ -104,6 +104,7 @@ Optional properties:
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- qcom,sde-dspp-size: A u32 value indicates the address range for each dspp.
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- qcom,sde-intf-size: A u32 value indicates the address range for each intf.
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- qcom,sde-dsc-size: A u32 value indicates the address range for each dsc.
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- qcom,sde-vdc-size: A u32 value indicates the address range for each vdc.
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- qcom,sde-cdm-size: A u32 value indicates the address range for each cdm.
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- qcom,sde-pp-size: A u32 value indicates the address range for each pingpong.
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- qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d.
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@ -186,6 +187,7 @@ Optional properties:
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- qcom,sde-smart-dma-rev: A string entry indicating the smart dma version
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supported on the device. Supported entries are
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"smart_dma_v1" and "smart_dma_v2".
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- qcom,sde-vdc-hw-rev: A string indicating the hw version of vdc.
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- qcom,sde-intf-type: Array of string provides the interface type information.
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Possible string values
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"dsi" - dsi display interface
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@ -227,6 +229,13 @@ Optional properties:
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- qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc
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block can support native 422 and native 420
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encoding.
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- qcom,sde-vdc-off: A u32 offset address for the available vdc blocks.
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This offset is calculated from register "mdp_phys"
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defined in reg property.
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- qcom,sde-vdc-enc: A u32 offset address for the vdc encoder block. This offset is
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calculated from qcom,sde-vdc-off.
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- qcom,sde-vdc-ctl: A u32 offset address for the vdc ctl block. This offset is
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calculated from qcom,sde-vdc-off.
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- qcom,sde-qdss-off: A u32 offset indicates the qdss block offset.
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- qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong.
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- qcom,sde-dither-version: A u32 value indicates the dither block version.
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@ -602,6 +611,11 @@ Example:
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qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>;
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qcom,sde-cdm-off = <0x0007a200>;
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qcom,sde-dsc-off = <0x00081000 0x00081400>;
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qcom,sde-vdc-off = <0x7C000>;
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qcom,sde-vdc-size = <0xf10>;
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qcom,sde-vdc-hw-rev = "vdc_1_1";
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qcom,sde-vdc-enc = <0x200>;
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qcom,sde-vdc-ctl = <0xf00>;
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qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
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qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;
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237
display/dsi-panel-sim-vdc-cmd.dtsi
Normal file
237
display/dsi-panel-sim-vdc-cmd.dtsi
Normal file
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@ -0,0 +1,237 @@
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&mdss_mdp {
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dsi_sim_vdc_cmd: qcom,mdss_dsi_sim_vdc_cmd {
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qcom,mdss-dsi-panel-name =
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"Simulator cmd mode VDC dsi panel";
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qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
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qcom,dsi-ctrl-num = <0>;
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qcom,dsi-phy-num = <0>;
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qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
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qcom,mdss-dsi-virtual-channel-id = <0>;
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qcom,mdss-dsi-stream = <0>;
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qcom,mdss-dsi-bpp = <24>;
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qcom,mdss-dsi-color-order = "rgb_swap_rgb";
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qcom,mdss-dsi-underflow-color = <0xff>;
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qcom,mdss-dsi-border-color = <0>;
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qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
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qcom,mdss-dsi-bllp-eof-power-mode;
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qcom,mdss-dsi-bllp-power-mode;
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qcom,mdss-dsi-lane-0-state;
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qcom,mdss-dsi-lane-1-state;
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qcom,mdss-dsi-lane-2-state;
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qcom,mdss-dsi-lane-3-state;
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qcom,mdss-dsi-dma-trigger = "trigger_sw";
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qcom,mdss-dsi-mdp-trigger = "none";
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qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,adjust-timer-wakeup-ms = <1>;
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qcom,mdss-dsi-te-pin-select = <1>;
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qcom,mdss-dsi-wr-mem-start = <0x2c>;
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qcom,mdss-dsi-wr-mem-continue = <0x3c>;
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qcom,mdss-dsi-te-dcs-command = <1>;
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qcom,mdss-dsi-te-check-enable;
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qcom,mdss-dsi-te-using-wd;
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qcom,mdss-dsi-te-using-te-pin;
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qcom,panel-ack-disabled;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,mdss-dsi-panel-framerate = <60>;
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qcom,mdss-dsi-panel-width = <1440>;
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qcom,mdss-dsi-panel-height = <2560>;
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qcom,mdss-dsi-h-front-porch = <100>;
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qcom,mdss-dsi-h-back-porch = <32>;
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qcom,mdss-dsi-h-pulse-width = <16>;
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qcom,mdss-dsi-h-sync-skew = <0>;
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qcom,mdss-dsi-v-back-porch = <8>;
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qcom,mdss-dsi-v-front-porch = <10>;
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qcom,mdss-dsi-v-pulse-width = <2>;
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qcom,mdss-dsi-h-left-border = <0>;
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qcom,mdss-dsi-h-right-border = <0>;
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qcom,mdss-dsi-v-top-border = <0>;
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qcom,mdss-dsi-v-bottom-border = <0>;
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qcom,mdss-dsi-on-command = [
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/* CMD2_P0 */
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15 01 00 00 00 00 02 ff 20
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15 01 00 00 00 00 02 fb 01
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15 01 00 00 00 00 02 00 01
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15 01 00 00 00 00 02 01 55
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15 01 00 00 00 00 02 02 45
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15 01 00 00 00 00 02 05 40
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15 01 00 00 00 00 02 06 19
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15 01 00 00 00 00 02 07 1e
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15 01 00 00 00 00 02 0b 73
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15 01 00 00 00 00 02 0c 73
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15 01 00 00 00 00 02 0e b0
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15 01 00 00 00 00 02 0f aE
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15 01 00 00 00 00 02 11 b8
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15 01 00 00 00 00 02 13 00
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15 01 00 00 00 00 02 58 80
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15 01 00 00 00 00 02 59 01
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15 01 00 00 00 00 02 5a 00
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15 01 00 00 00 00 02 5b 01
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15 01 00 00 00 00 02 5c 80
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15 01 00 00 00 00 02 5d 81
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15 01 00 00 00 00 02 5e 00
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15 01 00 00 00 00 02 5f 01
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15 01 00 00 00 00 02 72 31
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15 01 00 00 00 00 02 68 03
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/* CMD2_P4 */
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15 01 00 00 00 00 02 ff 24
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15 01 00 00 00 00 02 fb 01
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15 01 00 00 00 00 02 00 1c
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15 01 00 00 00 00 02 01 0b
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15 01 00 00 00 00 02 02 0c
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15 01 00 00 00 00 02 03 01
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15 01 00 00 00 00 02 04 0f
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15 01 00 00 00 00 02 05 10
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15 01 00 00 00 00 02 06 10
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15 01 00 00 00 00 02 07 10
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15 01 00 00 00 00 02 08 89
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15 01 00 00 00 00 02 09 8a
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15 01 00 00 00 00 02 0a 13
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15 01 00 00 00 00 02 0b 13
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15 01 00 00 00 00 02 0c 15
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15 01 00 00 00 00 02 0d 15
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15 01 00 00 00 00 02 0e 17
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15 01 00 00 00 00 02 0f 17
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15 01 00 00 00 00 02 10 1c
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15 01 00 00 00 00 02 11 0b
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15 01 00 00 00 00 02 12 0c
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15 01 00 00 00 00 02 13 01
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15 01 00 00 00 00 02 14 0f
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15 01 00 00 00 00 02 15 10
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15 01 00 00 00 00 02 16 10
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15 01 00 00 00 00 02 17 10
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15 01 00 00 00 00 02 18 89
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15 01 00 00 00 00 02 19 8a
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15 01 00 00 00 00 02 1a 13
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15 01 00 00 00 00 02 1b 13
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15 01 00 00 00 00 02 1c 15
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15 01 00 00 00 00 02 1d 15
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15 01 00 00 00 00 02 1e 17
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15 01 00 00 00 00 02 1f 17
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/* STV */
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15 01 00 00 00 00 02 20 40
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15 01 00 00 00 00 02 21 01
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15 01 00 00 00 00 02 22 00
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15 01 00 00 00 00 02 23 40
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15 01 00 00 00 00 02 24 40
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15 01 00 00 00 00 02 25 6d
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15 01 00 00 00 00 02 26 40
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15 01 00 00 00 00 02 27 40
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/* Vend */
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15 01 00 00 00 00 02 e0 00
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15 01 00 00 00 00 02 dc 21
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15 01 00 00 00 00 02 dd 22
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15 01 00 00 00 00 02 de 07
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15 01 00 00 00 00 02 df 07
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15 01 00 00 00 00 02 e3 6d
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15 01 00 00 00 00 02 e1 07
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15 01 00 00 00 00 02 e2 07
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/* UD */
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15 01 00 00 00 00 02 29 d8
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15 01 00 00 00 00 02 2a 2a
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/* CLK */
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15 01 00 00 00 00 02 4b 03
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15 01 00 00 00 00 02 4c 11
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15 01 00 00 00 00 02 4d 10
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15 01 00 00 00 00 02 4e 01
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15 01 00 00 00 00 02 4f 01
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15 01 00 00 00 00 02 50 10
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15 01 00 00 00 00 02 51 00
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15 01 00 00 00 00 02 52 80
|
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15 01 00 00 00 00 02 53 00
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15 01 00 00 00 00 02 56 00
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||||
15 01 00 00 00 00 02 54 07
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15 01 00 00 00 00 02 58 07
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15 01 00 00 00 00 02 55 25
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/* Reset XDONB */
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15 01 00 00 00 00 02 5b 43
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15 01 00 00 00 00 02 5c 00
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15 01 00 00 00 00 02 5f 73
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15 01 00 00 00 00 02 60 73
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15 01 00 00 00 00 02 63 22
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15 01 00 00 00 00 02 64 00
|
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15 01 00 00 00 00 02 67 08
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15 01 00 00 00 00 02 68 04
|
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/* Resolution:1440x2560*/
|
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15 01 00 00 00 00 02 72 02
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||||
/* mux */
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||||
15 01 00 00 00 00 02 7a 80
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||||
15 01 00 00 00 00 02 7b 91
|
||||
15 01 00 00 00 00 02 7c d8
|
||||
15 01 00 00 00 00 02 7d 60
|
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15 01 00 00 00 00 02 7f 15
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15 01 00 00 00 00 02 75 15
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/* ABOFF */
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15 01 00 00 00 00 02 b3 c0
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15 01 00 00 00 00 02 b4 00
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15 01 00 00 00 00 02 b5 00
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/* Source EQ */
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15 01 00 00 00 00 02 78 00
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15 01 00 00 00 00 02 79 00
|
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15 01 00 00 00 00 02 80 00
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15 01 00 00 00 00 02 83 00
|
||||
/* FP BP */
|
||||
15 01 00 00 00 00 02 93 0a
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15 01 00 00 00 00 02 94 0a
|
||||
/* Inversion Type */
|
||||
15 01 00 00 00 00 02 8a 00
|
||||
15 01 00 00 00 00 02 9b ff
|
||||
/* IMGSWAP =1 @PortSwap=1 */
|
||||
15 01 00 00 00 00 02 9d b0
|
||||
15 01 00 00 00 00 02 9f 63
|
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15 01 00 00 00 00 02 98 10
|
||||
/* FRM */
|
||||
15 01 00 00 00 00 02 ec 00
|
||||
/* CMD1 */
|
||||
15 01 00 00 00 00 02 ff 10
|
||||
/* VESA DSC PPS settings
|
||||
* (1440x2560 slide 16H)
|
||||
*/
|
||||
39 01 00 00 00 00 11 c1 09
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20 00 10 02 00 02 68 01 bb
|
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00 0a 06 67 04 c5
|
||||
|
||||
39 01 00 00 00 00 03 c2 10 f0
|
||||
/* C0h = 0x0(2 Port SDC)
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||||
* 0x01(1 PortA FBC)
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* 0x02(MTK) 0x03(1 PortA VESA)
|
||||
*/
|
||||
15 01 00 00 00 00 02 c0 03
|
||||
/* VBP+VSA=,VFP = 10H */
|
||||
15 01 00 00 00 00 04 3b 03 0a 0a
|
||||
/* FTE on */
|
||||
15 01 00 00 00 00 02 35 00
|
||||
/* EN_BK =1(auto black) */
|
||||
15 01 00 00 00 00 02 e5 01
|
||||
/* CMD mode(10) VDO mode(03) */
|
||||
15 01 00 00 00 00 02 bb 10
|
||||
/* Non Reload MTP */
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
/* SlpOut + DispOn */
|
||||
05 01 00 00 78 00 02 11 00
|
||||
05 01 00 00 78 00 02 29 00
|
||||
];
|
||||
qcom,mdss-dsi-off-command = [05 01 00 00 78 00
|
||||
02 28 00 05 01 00 00 78 00 02 10 00];
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "vdc";
|
||||
qcom,vdc-version = <0x11>;
|
||||
qcom,vdc-version-release = <0>;
|
||||
qcom,vdc-slice-height = <256>;
|
||||
qcom,vdc-slice-width = <720>;
|
||||
qcom,vdc-slice-per-pkt = <2>;
|
||||
qcom,vdc-bit-per-component = <8>;
|
||||
qcom,vdc-bit-per-pixel = <6>;
|
||||
qcom,src-color-space = <0>;
|
||||
qcom,src-chroma-format = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
230
display/dsi-panel-sim-vdc-vid.dtsi
Normal file
230
display/dsi-panel-sim-vdc-vid.dtsi
Normal file
|
|
@ -0,0 +1,230 @@
|
|||
&mdss_mdp {
|
||||
dsi_sim_vdc_vid: qcom,mdss_dsi_sim_vdc_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"Simulator video mode VDC dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
qcom,panel-ack-disabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <2560>;
|
||||
qcom,mdss-dsi-h-front-porch = <300>;
|
||||
qcom,mdss-dsi-h-back-porch = <48>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <10>;
|
||||
qcom,mdss-dsi-v-front-porch = <10>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-on-command = [
|
||||
/* CMD2_P0 */
|
||||
15 01 00 00 00 00 02 ff 20
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
15 01 00 00 00 00 02 00 01
|
||||
15 01 00 00 00 00 02 01 55
|
||||
15 01 00 00 00 00 02 02 45
|
||||
15 01 00 00 00 00 02 05 40
|
||||
15 01 00 00 00 00 02 06 19
|
||||
15 01 00 00 00 00 02 07 1e
|
||||
15 01 00 00 00 00 02 0b 73
|
||||
15 01 00 00 00 00 02 0c 73
|
||||
15 01 00 00 00 00 02 0e b0
|
||||
15 01 00 00 00 00 02 0f aE
|
||||
15 01 00 00 00 00 02 11 b8
|
||||
15 01 00 00 00 00 02 13 00
|
||||
15 01 00 00 00 00 02 58 80
|
||||
15 01 00 00 00 00 02 59 01
|
||||
15 01 00 00 00 00 02 5a 00
|
||||
15 01 00 00 00 00 02 5b 01
|
||||
15 01 00 00 00 00 02 5c 80
|
||||
15 01 00 00 00 00 02 5d 81
|
||||
15 01 00 00 00 00 02 5e 00
|
||||
15 01 00 00 00 00 02 5f 01
|
||||
15 01 00 00 00 00 02 72 31
|
||||
15 01 00 00 00 00 02 68 03
|
||||
/* CMD2_P4 */
|
||||
15 01 00 00 00 00 02 ff 24
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
15 01 00 00 00 00 02 00 1c
|
||||
15 01 00 00 00 00 02 01 0b
|
||||
15 01 00 00 00 00 02 02 0c
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 04 0f
|
||||
15 01 00 00 00 00 02 05 10
|
||||
15 01 00 00 00 00 02 06 10
|
||||
15 01 00 00 00 00 02 07 10
|
||||
15 01 00 00 00 00 02 08 89
|
||||
15 01 00 00 00 00 02 09 8a
|
||||
15 01 00 00 00 00 02 0a 13
|
||||
15 01 00 00 00 00 02 0b 13
|
||||
15 01 00 00 00 00 02 0c 15
|
||||
15 01 00 00 00 00 02 0d 15
|
||||
15 01 00 00 00 00 02 0e 17
|
||||
15 01 00 00 00 00 02 0f 17
|
||||
15 01 00 00 00 00 02 10 1c
|
||||
15 01 00 00 00 00 02 11 0b
|
||||
15 01 00 00 00 00 02 12 0c
|
||||
15 01 00 00 00 00 02 13 01
|
||||
15 01 00 00 00 00 02 14 0f
|
||||
15 01 00 00 00 00 02 15 10
|
||||
15 01 00 00 00 00 02 16 10
|
||||
15 01 00 00 00 00 02 17 10
|
||||
15 01 00 00 00 00 02 18 89
|
||||
15 01 00 00 00 00 02 19 8a
|
||||
15 01 00 00 00 00 02 1a 13
|
||||
15 01 00 00 00 00 02 1b 13
|
||||
15 01 00 00 00 00 02 1c 15
|
||||
15 01 00 00 00 00 02 1d 15
|
||||
15 01 00 00 00 00 02 1e 17
|
||||
15 01 00 00 00 00 02 1f 17
|
||||
/* STV */
|
||||
15 01 00 00 00 00 02 20 40
|
||||
15 01 00 00 00 00 02 21 01
|
||||
15 01 00 00 00 00 02 22 00
|
||||
15 01 00 00 00 00 02 23 40
|
||||
15 01 00 00 00 00 02 24 40
|
||||
15 01 00 00 00 00 02 25 6d
|
||||
15 01 00 00 00 00 02 26 40
|
||||
15 01 00 00 00 00 02 27 40
|
||||
/* Vend */
|
||||
15 01 00 00 00 00 02 e0 00
|
||||
15 01 00 00 00 00 02 dc 21
|
||||
15 01 00 00 00 00 02 dd 22
|
||||
15 01 00 00 00 00 02 de 07
|
||||
15 01 00 00 00 00 02 df 07
|
||||
15 01 00 00 00 00 02 e3 6d
|
||||
15 01 00 00 00 00 02 e1 07
|
||||
15 01 00 00 00 00 02 e2 07
|
||||
/* UD */
|
||||
15 01 00 00 00 00 02 29 d8
|
||||
15 01 00 00 00 00 02 2a 2a
|
||||
/* CLK */
|
||||
15 01 00 00 00 00 02 4b 03
|
||||
15 01 00 00 00 00 02 4c 11
|
||||
15 01 00 00 00 00 02 4d 10
|
||||
15 01 00 00 00 00 02 4e 01
|
||||
15 01 00 00 00 00 02 4f 01
|
||||
15 01 00 00 00 00 02 50 10
|
||||
15 01 00 00 00 00 02 51 00
|
||||
15 01 00 00 00 00 02 52 80
|
||||
15 01 00 00 00 00 02 53 00
|
||||
15 01 00 00 00 00 02 56 00
|
||||
15 01 00 00 00 00 02 54 07
|
||||
15 01 00 00 00 00 02 58 07
|
||||
15 01 00 00 00 00 02 55 25
|
||||
/* Reset XDONB */
|
||||
15 01 00 00 00 00 02 5b 43
|
||||
15 01 00 00 00 00 02 5c 00
|
||||
15 01 00 00 00 00 02 5f 73
|
||||
15 01 00 00 00 00 02 60 73
|
||||
15 01 00 00 00 00 02 63 22
|
||||
15 01 00 00 00 00 02 64 00
|
||||
15 01 00 00 00 00 02 67 08
|
||||
15 01 00 00 00 00 02 68 04
|
||||
/* Resolution:1440x2560*/
|
||||
15 01 00 00 00 00 02 72 02
|
||||
/* mux */
|
||||
15 01 00 00 00 00 02 7a 80
|
||||
15 01 00 00 00 00 02 7b 91
|
||||
15 01 00 00 00 00 02 7c d8
|
||||
15 01 00 00 00 00 02 7d 60
|
||||
15 01 00 00 00 00 02 7f 15
|
||||
15 01 00 00 00 00 02 75 15
|
||||
/* ABOFF */
|
||||
15 01 00 00 00 00 02 b3 c0
|
||||
15 01 00 00 00 00 02 b4 00
|
||||
15 01 00 00 00 00 02 b5 00
|
||||
/* Source EQ */
|
||||
15 01 00 00 00 00 02 78 00
|
||||
15 01 00 00 00 00 02 79 00
|
||||
15 01 00 00 00 00 02 80 00
|
||||
15 01 00 00 00 00 02 83 00
|
||||
/* FP BP */
|
||||
15 01 00 00 00 00 02 93 0a
|
||||
15 01 00 00 00 00 02 94 0a
|
||||
/* Inversion Type */
|
||||
15 01 00 00 00 00 02 8a 00
|
||||
15 01 00 00 00 00 02 9b ff
|
||||
/* IMGSWAP =1 @PortSwap=1 */
|
||||
15 01 00 00 00 00 02 9d b0
|
||||
15 01 00 00 00 00 02 9f 63
|
||||
15 01 00 00 00 00 02 98 10
|
||||
/* FRM */
|
||||
15 01 00 00 00 00 02 ec 00
|
||||
/* CMD1 */
|
||||
15 01 00 00 00 00 02 ff 10
|
||||
/* VESA DSC PPS settings
|
||||
* (1440x2560 slide 16H)
|
||||
*/
|
||||
39 01 00 00 00 00 11 c1 09
|
||||
20 00 10 02 00 02 68 01 bb
|
||||
00 0a 06 67 04 c5
|
||||
|
||||
39 01 00 00 00 00 03 c2 10 f0
|
||||
/* C0h = 0x0(2 Port SDC)
|
||||
* 0x01(1 PortA FBC)
|
||||
* 0x02(MTK) 0x03(1 PortA VESA)
|
||||
*/
|
||||
15 01 00 00 00 00 02 c0 03
|
||||
/* VBP+VSA=,VFP = 10H */
|
||||
15 01 00 00 00 00 04 3b 03 0a 0a
|
||||
/* FTE on */
|
||||
15 01 00 00 00 00 02 35 00
|
||||
/* EN_BK =1(auto black) */
|
||||
15 01 00 00 00 00 02 e5 01
|
||||
/* CMD mode(10) VDO mode(03) */
|
||||
15 01 00 00 00 00 02 bb 10
|
||||
/* Non Reload MTP */
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
/* SlpOut + DispOn */
|
||||
05 01 00 00 78 00 02 11 00
|
||||
05 01 00 00 78 00 02 29 00
|
||||
];
|
||||
qcom,mdss-dsi-off-command = [05 01 00 00 78 00
|
||||
02 28 00 05 01 00 00 78 00 02 10 00];
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "vdc";
|
||||
qcom,vdc-version = <0x11>;
|
||||
qcom,vdc-version-release = <0>;
|
||||
qcom,vdc-slice-height = <256>;
|
||||
qcom,vdc-slice-width = <720>;
|
||||
qcom,vdc-slice-per-pkt = <2>;
|
||||
qcom,vdc-bit-per-component = <8>;
|
||||
qcom,vdc-bit-per-pixel = <6>;
|
||||
qcom,src-chroma-format = <0>;
|
||||
qcom,src-color-space = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -104,6 +104,12 @@
|
|||
qcom,sde-dither-version = <0x00010000>;
|
||||
qcom,sde-dither-size = <0x20>;
|
||||
|
||||
qcom,sde-vdc-off = <0x7C000>;
|
||||
qcom,sde-vdc-size = <0xf10>;
|
||||
qcom,sde-vdc-hw-rev = "vdc_1_1";
|
||||
qcom,sde-vdc-enc = <0x200>;
|
||||
qcom,sde-vdc-ctl = <0xf00>;
|
||||
|
||||
qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
|
||||
"dma", "dma", "dma", "dma";
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue