mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
[ARM] 3995/1: iop13xx: add iop13xx support
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <[email protected]> Signed-off-by: Russell King <[email protected]>
This commit is contained in:
Dan Williams
Russell King
parent
4dbda6a50a
commit
285f5fa7e9
28 changed files with 3324 additions and 4 deletions
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@ -223,6 +223,12 @@ config ARCH_IOP33X
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help
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Support for Intel's IOP33X (XScale) family of processors.
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config ARCH_IOP13XX
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bool "IOP13xx-based"
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select PCI
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help
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Support for Intel's IOP13XX (XScale) family of processors.
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config ARCH_IXP4XX
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bool "IXP4xx-based"
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depends on MMU
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@ -331,6 +337,8 @@ source "arch/arm/mach-iop32x/Kconfig"
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source "arch/arm/mach-iop33x/Kconfig"
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source "arch/arm/mach-iop13xx/Kconfig"
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source "arch/arm/mach-ixp4xx/Kconfig"
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source "arch/arm/mach-ixp2000/Kconfig"
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@ -108,6 +108,7 @@ endif
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machine-$(CONFIG_ARCH_CLPS711X) := clps711x
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machine-$(CONFIG_ARCH_IOP32X) := iop32x
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machine-$(CONFIG_ARCH_IOP33X) := iop33x
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machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
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machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
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machine-$(CONFIG_ARCH_IXP2000) := ixp2000
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machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
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20
arch/arm/mach-iop13xx/Kconfig
Normal file
20
arch/arm/mach-iop13xx/Kconfig
Normal file
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@ -0,0 +1,20 @@
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if ARCH_IOP13XX
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menu "IOP13XX Implementation Options"
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comment "IOP13XX Platform Support"
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config MACH_IQ81340SC
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bool "Enable IQ81340SC Hardware Support"
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help
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Say Y here if you want to support running on the Intel IQ81340SC
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evaluation kit.
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config MACH_IQ81340MC
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bool "Enable IQ81340MC Hardware Support"
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help
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Say Y here if you want to support running on the Intel IQ81340MC
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evaluation kit.
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endmenu
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endif
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12
arch/arm/mach-iop13xx/Makefile
Normal file
12
arch/arm/mach-iop13xx/Makefile
Normal file
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@ -0,0 +1,12 @@
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obj-y :=
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obj-m :=
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obj-n :=
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obj- :=
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obj-$(CONFIG_ARCH_IOP13XX) += setup.o
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obj-$(CONFIG_ARCH_IOP13XX) += irq.o
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obj-$(CONFIG_ARCH_IOP13XX) += time.o
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obj-$(CONFIG_ARCH_IOP13XX) += pci.o
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obj-$(CONFIG_ARCH_IOP13XX) += io.o
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obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
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obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
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3
arch/arm/mach-iop13xx/Makefile.boot
Normal file
3
arch/arm/mach-iop13xx/Makefile.boot
Normal file
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@ -0,0 +1,3 @@
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zreladdr-y := 0x00008000
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params_phys-y := 0x00000100
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initrd_phys-y := 0x00800000
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93
arch/arm/mach-iop13xx/io.c
Normal file
93
arch/arm/mach-iop13xx/io.c
Normal file
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@ -0,0 +1,93 @@
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/*
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* iop13xx custom ioremap implementation
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* Copyright (c) 2005-2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
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unsigned long flags)
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{
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void __iomem * retval;
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switch (cookie) {
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case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
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if (unlikely(!iop13xx_atux_mem_base))
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retval = NULL;
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else
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retval = (void *)(iop13xx_atux_mem_base +
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(cookie - IOP13XX_PCIX_LOWER_MEM_RA));
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break;
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case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
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if (unlikely(!iop13xx_atue_mem_base))
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retval = NULL;
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else
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retval = (void *)(iop13xx_atue_mem_base +
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(cookie - IOP13XX_PCIE_LOWER_MEM_RA));
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break;
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case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
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retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
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(cookie - IOP13XX_PBI_LOWER_MEM_RA),
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size, flags);
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break;
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case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
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retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
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break;
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case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
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retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
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break;
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case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
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retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
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break;
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default:
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retval = __ioremap(cookie, size, flags);
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}
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return retval;
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}
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EXPORT_SYMBOL(__iop13xx_ioremap);
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void __iop13xx_iounmap(void __iomem *addr)
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{
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extern void __iounmap(volatile void __iomem *addr);
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if (iop13xx_atue_mem_base)
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if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
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addr < (void __iomem *) (iop13xx_atue_mem_base +
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iop13xx_atue_mem_size))
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goto skip;
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if (iop13xx_atux_mem_base)
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if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
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addr < (void __iomem *) (iop13xx_atux_mem_base +
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iop13xx_atux_mem_size))
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goto skip;
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switch ((u32) addr) {
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case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
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case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
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case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
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goto skip;
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}
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__iounmap(addr);
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skip:
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return;
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}
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EXPORT_SYMBOL(__iop13xx_iounmap);
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98
arch/arm/mach-iop13xx/iq81340mc.c
Normal file
98
arch/arm/mach-iop13xx/iq81340mc.c
Normal file
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@ -0,0 +1,98 @@
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/*
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* iq81340mc board support
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* Copyright (c) 2005-2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/pci.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/arch/pci.h>
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#include <asm/mach/time.h>
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extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
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static int __init
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iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
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{
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switch (idsel) {
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case 1:
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switch (pin) {
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case 1: return ATUX_INTB;
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case 2: return ATUX_INTC;
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case 3: return ATUX_INTD;
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case 4: return ATUX_INTA;
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default: return -1;
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}
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case 2:
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switch (pin) {
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case 1: return ATUX_INTC;
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case 2: return ATUX_INTD;
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case 3: return ATUX_INTC;
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case 4: return ATUX_INTD;
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default: return -1;
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}
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default: return -1;
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}
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}
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static struct hw_pci iq81340mc_pci __initdata = {
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.swizzle = pci_std_swizzle,
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.nr_controllers = 0,
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.setup = iop13xx_pci_setup,
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.map_irq = iq81340mc_pcix_map_irq,
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.scan = iop13xx_scan_bus,
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.preinit = iop13xx_pci_init,
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};
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static int __init iq81340mc_pci_init(void)
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{
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iop13xx_atu_select(&iq81340mc_pci);
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pci_common_init(&iq81340mc_pci);
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iop13xx_map_pci_memory();
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return 0;
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}
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static void __init iq81340mc_init(void)
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{
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iop13xx_platform_init();
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iq81340mc_pci_init();
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}
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static void __init iq81340mc_timer_init(void)
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{
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iop13xx_init_time(400000000);
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}
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static struct sys_timer iq81340mc_timer = {
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.init = iq81340mc_timer_init,
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.offset = iop13xx_gettimeoffset,
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};
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MACHINE_START(IQ81340MC, "Intel IQ81340MC")
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/* Maintainer: Dan Williams <[email protected]> */
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.phys_io = PHYS_IO,
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.io_pg_offst = IO_PG_OFFSET,
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.map_io = iop13xx_map_io,
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.init_irq = iop13xx_init_irq,
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.timer = &iq81340mc_timer,
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.boot_params = BOOT_PARAM_OFFSET,
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.init_machine = iq81340mc_init,
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MACHINE_END
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100
arch/arm/mach-iop13xx/iq81340sc.c
Normal file
100
arch/arm/mach-iop13xx/iq81340sc.c
Normal file
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@ -0,0 +1,100 @@
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/*
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* iq81340sc board support
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* Copyright (c) 2005-2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/pci.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/arch/pci.h>
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#include <asm/mach/time.h>
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extern int init_atu;
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static int __init
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iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
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{
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WARN_ON(idsel < 1 || idsel > 2);
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switch (idsel) {
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case 1:
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switch (pin) {
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case 1: return ATUX_INTB;
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case 2: return ATUX_INTC;
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case 3: return ATUX_INTD;
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case 4: return ATUX_INTA;
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default: return -1;
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}
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case 2:
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switch (pin) {
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case 1: return ATUX_INTC;
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case 2: return ATUX_INTC;
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case 3: return ATUX_INTC;
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case 4: return ATUX_INTC;
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default: return -1;
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}
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default: return -1;
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}
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}
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static struct hw_pci iq81340sc_pci __initdata = {
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.swizzle = pci_std_swizzle,
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.nr_controllers = 0,
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.setup = iop13xx_pci_setup,
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.scan = iop13xx_scan_bus,
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.map_irq = iq81340sc_atux_map_irq,
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.preinit = iop13xx_pci_init
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};
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static int __init iq81340sc_pci_init(void)
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{
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iop13xx_atu_select(&iq81340sc_pci);
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pci_common_init(&iq81340sc_pci);
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iop13xx_map_pci_memory();
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return 0;
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}
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static void __init iq81340sc_init(void)
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{
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iop13xx_platform_init();
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iq81340sc_pci_init();
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}
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static void __init iq81340sc_timer_init(void)
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{
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iop13xx_init_time(400000000);
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}
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static struct sys_timer iq81340sc_timer = {
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.init = iq81340sc_timer_init,
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.offset = iop13xx_gettimeoffset,
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};
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MACHINE_START(IQ81340SC, "Intel IQ81340SC")
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/* Maintainer: Dan Williams <[email protected]> */
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.phys_io = PHYS_IO,
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.io_pg_offst = IO_PG_OFFSET,
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.map_io = iop13xx_map_io,
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.init_irq = iop13xx_init_irq,
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.timer = &iq81340sc_timer,
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.boot_params = BOOT_PARAM_OFFSET,
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.init_machine = iq81340sc_init,
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MACHINE_END
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286
arch/arm/mach-iop13xx/irq.c
Normal file
286
arch/arm/mach-iop13xx/irq.c
Normal file
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@ -0,0 +1,286 @@
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/*
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* iop13xx IRQ handling / support functions
|
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* Copyright (c) 2005-2006, Intel Corporation.
|
||||
*
|
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
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*
|
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/sysctl.h>
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#include <asm/uaccess.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/arch/irqs.h>
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|
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/* INTCTL0 CP6 R0 Page 4
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*/
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static inline u32 read_intctl_0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
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return val;
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}
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static inline void write_intctl_0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
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}
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/* INTCTL1 CP6 R1 Page 4
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*/
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static inline u32 read_intctl_1(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
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return val;
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}
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static inline void write_intctl_1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
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}
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|
||||
/* INTCTL2 CP6 R2 Page 4
|
||||
*/
|
||||
static inline u32 read_intctl_2(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
|
||||
return val;
|
||||
}
|
||||
static inline void write_intctl_2(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
|
||||
}
|
||||
|
||||
/* INTCTL3 CP6 R3 Page 4
|
||||
*/
|
||||
static inline u32 read_intctl_3(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
|
||||
return val;
|
||||
}
|
||||
static inline void write_intctl_3(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
|
||||
}
|
||||
|
||||
/* INTSTR0 CP6 R0 Page 5
|
||||
*/
|
||||
static inline u32 read_intstr_0(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
|
||||
return val;
|
||||
}
|
||||
static inline void write_intstr_0(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
|
||||
}
|
||||
|
||||
/* INTSTR1 CP6 R1 Page 5
|
||||
*/
|
||||
static inline u32 read_intstr_1(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
|
||||
return val;
|
||||
}
|
||||
static void write_intstr_1(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
|
||||
}
|
||||
|
||||
/* INTSTR2 CP6 R2 Page 5
|
||||
*/
|
||||
static inline u32 read_intstr_2(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
|
||||
return val;
|
||||
}
|
||||
static void write_intstr_2(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
|
||||
}
|
||||
|
||||
/* INTSTR3 CP6 R3 Page 5
|
||||
*/
|
||||
static inline u32 read_intstr_3(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
|
||||
return val;
|
||||
}
|
||||
static void write_intstr_3(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
|
||||
}
|
||||
|
||||
/* INTBASE CP6 R0 Page 2
|
||||
*/
|
||||
static inline u32 read_intbase(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
|
||||
return val;
|
||||
}
|
||||
static void write_intbase(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
|
||||
}
|
||||
|
||||
/* INTSIZE CP6 R2 Page 2
|
||||
*/
|
||||
static inline u32 read_intsize(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
|
||||
return val;
|
||||
}
|
||||
static void write_intsize(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
|
||||
}
|
||||
|
||||
/* 0 = Interrupt Masked and 1 = Interrupt not masked */
|
||||
static void
|
||||
iop13xx_irq_mask0 (unsigned int irq)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
|
||||
static void
|
||||
iop13xx_irq_mask1 (unsigned int irq)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
|
||||
static void
|
||||
iop13xx_irq_mask2 (unsigned int irq)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
|
||||
static void
|
||||
iop13xx_irq_mask3 (unsigned int irq)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
|
||||
static void
|
||||
iop13xx_irq_unmask0(unsigned int irq)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
|
||||
static void
|
||||
iop13xx_irq_unmask1(unsigned int irq)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
|
||||
static void
|
||||
iop13xx_irq_unmask2(unsigned int irq)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
|
||||
static void
|
||||
iop13xx_irq_unmask3(unsigned int irq)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
|
||||
static struct irqchip iop13xx_irqchip0 = {
|
||||
.ack = iop13xx_irq_mask0,
|
||||
.mask = iop13xx_irq_mask0,
|
||||
.unmask = iop13xx_irq_unmask0,
|
||||
};
|
||||
|
||||
static struct irqchip iop13xx_irqchip1 = {
|
||||
.ack = iop13xx_irq_mask1,
|
||||
.mask = iop13xx_irq_mask1,
|
||||
.unmask = iop13xx_irq_unmask1,
|
||||
};
|
||||
|
||||
static struct irqchip iop13xx_irqchip2 = {
|
||||
.ack = iop13xx_irq_mask2,
|
||||
.mask = iop13xx_irq_mask2,
|
||||
.unmask = iop13xx_irq_unmask2,
|
||||
};
|
||||
|
||||
static struct irqchip iop13xx_irqchip3 = {
|
||||
.ack = iop13xx_irq_mask3,
|
||||
.mask = iop13xx_irq_mask3,
|
||||
.unmask = iop13xx_irq_unmask3,
|
||||
};
|
||||
|
||||
void __init iop13xx_init_irq(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
|
||||
/* disable all interrupts */
|
||||
write_intctl_0(0);
|
||||
write_intctl_1(0);
|
||||
write_intctl_2(0);
|
||||
write_intctl_3(0);
|
||||
|
||||
/* treat all as IRQ */
|
||||
write_intstr_0(0);
|
||||
write_intstr_1(0);
|
||||
write_intstr_2(0);
|
||||
write_intstr_3(0);
|
||||
|
||||
/* initialize the interrupt vector generator */
|
||||
write_intbase(INTBASE);
|
||||
write_intsize(INTSIZE_4);
|
||||
|
||||
for(i = 0; i < NR_IOP13XX_IRQS; i++) {
|
||||
if (i < 32)
|
||||
set_irq_chip(i, &iop13xx_irqchip0);
|
||||
else if (i < 64)
|
||||
set_irq_chip(i, &iop13xx_irqchip1);
|
||||
else if (i < 96)
|
||||
set_irq_chip(i, &iop13xx_irqchip2);
|
||||
else
|
||||
set_irq_chip(i, &iop13xx_irqchip3);
|
||||
|
||||
set_irq_handler(i, do_level_IRQ);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
}
|
||||
1113
arch/arm/mach-iop13xx/pci.c
Normal file
1113
arch/arm/mach-iop13xx/pci.c
Normal file
File diff suppressed because it is too large
Load diff
406
arch/arm/mach-iop13xx/setup.c
Normal file
406
arch/arm/mach-iop13xx/setup.c
Normal file
|
|
@ -0,0 +1,406 @@
|
|||
/*
|
||||
* iop13xx platform Initialization
|
||||
* Copyright (c) 2005-2006, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/serial_8250.h>
|
||||
#ifdef CONFIG_MTD_PHYSMAP
|
||||
#include <linux/mtd/physmap.h>
|
||||
#endif
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#define IOP13XX_UART_XTAL 33334000
|
||||
#define IOP13XX_SETUP_DEBUG 0
|
||||
#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
|
||||
|
||||
/* Standard IO mapping for all IOP13XX based systems
|
||||
*/
|
||||
static struct map_desc iop13xx_std_desc[] __initdata = {
|
||||
{ /* mem mapped registers */
|
||||
.virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
|
||||
.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
|
||||
.length = IOP13XX_PMMR_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, { /* PCIE IO space */
|
||||
.virtual = IOP13XX_PCIE_LOWER_IO_VA,
|
||||
.pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
|
||||
.length = IOP13XX_PCIX_IO_WINDOW_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, { /* PCIX IO space */
|
||||
.virtual = IOP13XX_PCIX_LOWER_IO_VA,
|
||||
.pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
|
||||
.length = IOP13XX_PCIX_IO_WINDOW_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource iop13xx_uart0_resources[] = {
|
||||
[0] = {
|
||||
.start = IOP13XX_UART0_PHYS,
|
||||
.end = IOP13XX_UART0_PHYS + 0x3f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_IOP13XX_UART0,
|
||||
.end = IRQ_IOP13XX_UART0,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}
|
||||
};
|
||||
|
||||
static struct resource iop13xx_uart1_resources[] = {
|
||||
[0] = {
|
||||
.start = IOP13XX_UART1_PHYS,
|
||||
.end = IOP13XX_UART1_PHYS + 0x3f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_IOP13XX_UART1,
|
||||
.end = IRQ_IOP13XX_UART1,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}
|
||||
};
|
||||
|
||||
static struct plat_serial8250_port iop13xx_uart0_data[] = {
|
||||
{
|
||||
.membase = (char*)(IOP13XX_UART0_VIRT),
|
||||
.mapbase = (IOP13XX_UART0_PHYS),
|
||||
.irq = IRQ_IOP13XX_UART0,
|
||||
.uartclk = IOP13XX_UART_XTAL,
|
||||
.regshift = 2,
|
||||
.iotype = UPIO_MEM,
|
||||
.flags = UPF_SKIP_TEST,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct plat_serial8250_port iop13xx_uart1_data[] = {
|
||||
{
|
||||
.membase = (char*)(IOP13XX_UART1_VIRT),
|
||||
.mapbase = (IOP13XX_UART1_PHYS),
|
||||
.irq = IRQ_IOP13XX_UART1,
|
||||
.uartclk = IOP13XX_UART_XTAL,
|
||||
.regshift = 2,
|
||||
.iotype = UPIO_MEM,
|
||||
.flags = UPF_SKIP_TEST,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
/* The ids are fixed up later in iop13xx_platform_init */
|
||||
static struct platform_device iop13xx_uart0 = {
|
||||
.name = "serial8250",
|
||||
.id = 0,
|
||||
.dev.platform_data = iop13xx_uart0_data,
|
||||
.num_resources = 2,
|
||||
.resource = iop13xx_uart0_resources,
|
||||
};
|
||||
|
||||
static struct platform_device iop13xx_uart1 = {
|
||||
.name = "serial8250",
|
||||
.id = 0,
|
||||
.dev.platform_data = iop13xx_uart1_data,
|
||||
.num_resources = 2,
|
||||
.resource = iop13xx_uart1_resources
|
||||
};
|
||||
|
||||
static struct resource iop13xx_i2c_0_resources[] = {
|
||||
[0] = {
|
||||
.start = IOP13XX_I2C0_PHYS,
|
||||
.end = IOP13XX_I2C0_PHYS + 0x18,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_IOP13XX_I2C_0,
|
||||
.end = IRQ_IOP13XX_I2C_0,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}
|
||||
};
|
||||
|
||||
static struct resource iop13xx_i2c_1_resources[] = {
|
||||
[0] = {
|
||||
.start = IOP13XX_I2C1_PHYS,
|
||||
.end = IOP13XX_I2C1_PHYS + 0x18,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_IOP13XX_I2C_1,
|
||||
.end = IRQ_IOP13XX_I2C_1,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}
|
||||
};
|
||||
|
||||
static struct resource iop13xx_i2c_2_resources[] = {
|
||||
[0] = {
|
||||
.start = IOP13XX_I2C2_PHYS,
|
||||
.end = IOP13XX_I2C2_PHYS + 0x18,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_IOP13XX_I2C_2,
|
||||
.end = IRQ_IOP13XX_I2C_2,
|
||||
.flags = IORESOURCE_IRQ
|
||||
}
|
||||
};
|
||||
|
||||
/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
|
||||
* we just use the same device name.
|
||||
*/
|
||||
|
||||
/* The ids are fixed up later in iop13xx_platform_init */
|
||||
static struct platform_device iop13xx_i2c_0_controller = {
|
||||
.name = "IOP3xx-I2C",
|
||||
.id = 0,
|
||||
.num_resources = 2,
|
||||
.resource = iop13xx_i2c_0_resources
|
||||
};
|
||||
|
||||
static struct platform_device iop13xx_i2c_1_controller = {
|
||||
.name = "IOP3xx-I2C",
|
||||
.id = 0,
|
||||
.num_resources = 2,
|
||||
.resource = iop13xx_i2c_1_resources
|
||||
};
|
||||
|
||||
static struct platform_device iop13xx_i2c_2_controller = {
|
||||
.name = "IOP3xx-I2C",
|
||||
.id = 0,
|
||||
.num_resources = 2,
|
||||
.resource = iop13xx_i2c_2_resources
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MTD_PHYSMAP
|
||||
/* PBI Flash Device
|
||||
*/
|
||||
static struct physmap_flash_data iq8134x_flash_data = {
|
||||
.width = 2,
|
||||
};
|
||||
|
||||
static struct resource iq8134x_flash_resource = {
|
||||
.start = IQ81340_FLASHBASE,
|
||||
.end = 0,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device iq8134x_flash = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = { .platform_data = &iq8134x_flash_data, },
|
||||
.num_resources = 1,
|
||||
.resource = &iq8134x_flash_resource,
|
||||
};
|
||||
|
||||
static unsigned long iq8134x_probe_flash_size(void)
|
||||
{
|
||||
uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
|
||||
int i;
|
||||
char query[3];
|
||||
unsigned long size = 0;
|
||||
int width = iq8134x_flash_data.width;
|
||||
|
||||
if (flash_addr) {
|
||||
/* send CFI 'query' command */
|
||||
writew(0x98, flash_addr);
|
||||
|
||||
/* check for CFI compliance */
|
||||
for (i = 0; i < 3 * width; i += width)
|
||||
query[i / width] = readb(flash_addr + (0x10 * width) + i);
|
||||
|
||||
/* read the size */
|
||||
if (memcmp(query, "QRY", 3) == 0)
|
||||
size = 1 << readb(flash_addr + (0x27 * width));
|
||||
|
||||
/* send CFI 'read array' command */
|
||||
writew(0xff, flash_addr);
|
||||
|
||||
iounmap(flash_addr);
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
#endif
|
||||
|
||||
void __init iop13xx_map_io(void)
|
||||
{
|
||||
/* Initialize the Static Page Table maps */
|
||||
iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
|
||||
}
|
||||
|
||||
static int init_uart = 0;
|
||||
static int init_i2c = 0;
|
||||
|
||||
void __init iop13xx_platform_init(void)
|
||||
{
|
||||
int i;
|
||||
u32 uart_idx, i2c_idx, plat_idx;
|
||||
struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
|
||||
|
||||
/* set the bases so we can read the device id */
|
||||
iop13xx_set_atu_mmr_bases();
|
||||
|
||||
memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
|
||||
|
||||
if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
|
||||
switch (iop13xx_dev_id()) {
|
||||
/* enable both uarts on iop341 and iop342 */
|
||||
case 0x3380:
|
||||
case 0x3384:
|
||||
case 0x3388:
|
||||
case 0x338c:
|
||||
case 0x3382:
|
||||
case 0x3386:
|
||||
case 0x338a:
|
||||
case 0x338e:
|
||||
init_uart |= IOP13XX_INIT_UART_0;
|
||||
init_uart |= IOP13XX_INIT_UART_1;
|
||||
break;
|
||||
/* only enable uart 1 */
|
||||
default:
|
||||
init_uart |= IOP13XX_INIT_UART_1;
|
||||
}
|
||||
}
|
||||
|
||||
if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
|
||||
switch (iop13xx_dev_id()) {
|
||||
/* enable all i2c units on iop341 and iop342 */
|
||||
case 0x3380:
|
||||
case 0x3384:
|
||||
case 0x3388:
|
||||
case 0x338c:
|
||||
case 0x3382:
|
||||
case 0x3386:
|
||||
case 0x338a:
|
||||
case 0x338e:
|
||||
init_i2c |= IOP13XX_INIT_I2C_0;
|
||||
init_i2c |= IOP13XX_INIT_I2C_1;
|
||||
init_i2c |= IOP13XX_INIT_I2C_2;
|
||||
break;
|
||||
/* only enable i2c 1 and 2 */
|
||||
default:
|
||||
init_i2c |= IOP13XX_INIT_I2C_1;
|
||||
init_i2c |= IOP13XX_INIT_I2C_2;
|
||||
}
|
||||
}
|
||||
|
||||
plat_idx = 0;
|
||||
uart_idx = 0;
|
||||
i2c_idx = 0;
|
||||
|
||||
/* uart 1 (if enabled) is ttyS0 */
|
||||
if (init_uart & IOP13XX_INIT_UART_1) {
|
||||
PRINTK("Adding uart1 to platform device list\n");
|
||||
iop13xx_uart1.id = uart_idx++;
|
||||
iop13xx_devices[plat_idx++] = &iop13xx_uart1;
|
||||
}
|
||||
if (init_uart & IOP13XX_INIT_UART_0) {
|
||||
PRINTK("Adding uart0 to platform device list\n");
|
||||
iop13xx_uart0.id = uart_idx++;
|
||||
iop13xx_devices[plat_idx++] = &iop13xx_uart0;
|
||||
}
|
||||
|
||||
for(i = 0; i < IQ81340_NUM_I2C; i++) {
|
||||
if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
|
||||
printk("Adding i2c%d to platform device list\n", i);
|
||||
switch(init_i2c & (1 << i)) {
|
||||
case IOP13XX_INIT_I2C_0:
|
||||
iop13xx_i2c_0_controller.id = i2c_idx++;
|
||||
iop13xx_devices[plat_idx++] =
|
||||
&iop13xx_i2c_0_controller;
|
||||
break;
|
||||
case IOP13XX_INIT_I2C_1:
|
||||
iop13xx_i2c_1_controller.id = i2c_idx++;
|
||||
iop13xx_devices[plat_idx++] =
|
||||
&iop13xx_i2c_1_controller;
|
||||
break;
|
||||
case IOP13XX_INIT_I2C_2:
|
||||
iop13xx_i2c_2_controller.id = i2c_idx++;
|
||||
iop13xx_devices[plat_idx++] =
|
||||
&iop13xx_i2c_2_controller;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MTD_PHYSMAP
|
||||
iq8134x_flash_resource.end = iq8134x_flash_resource.start +
|
||||
iq8134x_probe_flash_size();
|
||||
if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
|
||||
iop13xx_devices[plat_idx++] = &iq8134x_flash;
|
||||
else
|
||||
printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
|
||||
#endif
|
||||
|
||||
platform_add_devices(iop13xx_devices, plat_idx);
|
||||
}
|
||||
|
||||
static int __init iop13xx_init_uart_setup(char *str)
|
||||
{
|
||||
if (str) {
|
||||
while (*str != '\0') {
|
||||
switch(*str) {
|
||||
case '0':
|
||||
init_uart |= IOP13XX_INIT_UART_0;
|
||||
break;
|
||||
case '1':
|
||||
init_uart |= IOP13XX_INIT_UART_1;
|
||||
break;
|
||||
case ',':
|
||||
case '=':
|
||||
break;
|
||||
default:
|
||||
PRINTK("\"iop13xx_init_uart\" malformed"
|
||||
" at character: \'%c\'", *str);
|
||||
*(str + 1) = '\0';
|
||||
init_uart = IOP13XX_INIT_UART_DEFAULT;
|
||||
}
|
||||
str++;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int __init iop13xx_init_i2c_setup(char *str)
|
||||
{
|
||||
if (str) {
|
||||
while (*str != '\0') {
|
||||
switch(*str) {
|
||||
case '0':
|
||||
init_i2c |= IOP13XX_INIT_I2C_0;
|
||||
break;
|
||||
case '1':
|
||||
init_i2c |= IOP13XX_INIT_I2C_1;
|
||||
break;
|
||||
case '2':
|
||||
init_i2c |= IOP13XX_INIT_I2C_2;
|
||||
break;
|
||||
case ',':
|
||||
case '=':
|
||||
break;
|
||||
default:
|
||||
PRINTK("\"iop13xx_init_i2c\" malformed"
|
||||
" at character: \'%c\'", *str);
|
||||
*(str + 1) = '\0';
|
||||
init_i2c = IOP13XX_INIT_I2C_DEFAULT;
|
||||
}
|
||||
str++;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
|
||||
__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
|
||||
102
arch/arm/mach-iop13xx/time.c
Normal file
102
arch/arm/mach-iop13xx/time.c
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* arch/arm/mach-iop13xx/time.c
|
||||
*
|
||||
* Timer code for IOP13xx (copied from IOP32x/IOP33x implementation)
|
||||
*
|
||||
* Author: Deepak Saxena <dsaxena@mvista.com>
|
||||
*
|
||||
* Copyright 2002-2003 MontaVista Software Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/timex.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
static unsigned long ticks_per_jiffy;
|
||||
static unsigned long ticks_per_usec;
|
||||
static unsigned long next_jiffy_time;
|
||||
|
||||
static inline u32 read_tcr1(void)
|
||||
{
|
||||
u32 val;
|
||||
asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
|
||||
return val;
|
||||
}
|
||||
|
||||
unsigned long iop13xx_gettimeoffset(void)
|
||||
{
|
||||
unsigned long offset;
|
||||
u32 cp_flags;
|
||||
|
||||
cp_flags = iop13xx_cp6_save();
|
||||
offset = next_jiffy_time - read_tcr1();
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
|
||||
return offset / ticks_per_usec;
|
||||
}
|
||||
|
||||
static irqreturn_t
|
||||
iop13xx_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
u32 cp_flags = iop13xx_cp6_save();
|
||||
|
||||
write_seqlock(&xtime_lock);
|
||||
|
||||
asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
|
||||
|
||||
while ((signed long)(next_jiffy_time - read_tcr1())
|
||||
>= ticks_per_jiffy) {
|
||||
timer_tick();
|
||||
next_jiffy_time -= ticks_per_jiffy;
|
||||
}
|
||||
|
||||
write_sequnlock(&xtime_lock);
|
||||
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction iop13xx_timer_irq = {
|
||||
.name = "IOP13XX Timer Tick",
|
||||
.handler = iop13xx_timer_interrupt,
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER,
|
||||
};
|
||||
|
||||
void __init iop13xx_init_time(unsigned long tick_rate)
|
||||
{
|
||||
u32 timer_ctl;
|
||||
u32 cp_flags;
|
||||
|
||||
ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
|
||||
ticks_per_usec = tick_rate / 1000000;
|
||||
next_jiffy_time = 0xffffffff;
|
||||
|
||||
timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED |
|
||||
IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1;
|
||||
|
||||
/*
|
||||
* We use timer 0 for our timer interrupt, and timer 1 as
|
||||
* monotonic counter for tracking missed jiffies.
|
||||
*/
|
||||
cp_flags = iop13xx_cp6_save();
|
||||
asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
|
||||
asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
|
||||
asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
|
||||
asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
|
||||
iop13xx_cp6_restore(cp_flags);
|
||||
|
||||
setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
|
||||
}
|
||||
|
|
@ -333,7 +333,7 @@ config CPU_XSCALE
|
|||
# XScale Core Version 3
|
||||
config CPU_XSC3
|
||||
bool
|
||||
depends on ARCH_IXP23XX
|
||||
depends on ARCH_IXP23XX || ARCH_IOP13XX
|
||||
default y
|
||||
select CPU_32v5
|
||||
select CPU_ABRT_EV5T
|
||||
|
|
|
|||
Loading…
Reference in a new issue