From 7a315b1690b1cb2bf21ff14d16fed2a0537a0922 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 4 Aug 2020 00:33:08 +0530 Subject: [PATCH 1/2] bindings: cpufreq-hw: Add binding support for performance lock Add the new optional binding to support perf-lock for CPU. Change-Id: Ibbd9aac72666bfe635c9965066cb332d4ecd1ab1 --- bindings/cpufreq/cpufreq-qcom-hw.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/cpufreq/cpufreq-qcom-hw.txt b/bindings/cpufreq/cpufreq-qcom-hw.txt index 5a3f126df530..251ea7dcca40 100644 --- a/bindings/cpufreq/cpufreq-qcom-hw.txt +++ b/bindings/cpufreq/cpufreq-qcom-hw.txt @@ -42,6 +42,14 @@ Properties: Definition: Indicate to check for Enable of FW before registering with cpufreq. +- qcom,perf-lock-support + Usage: Optional + Value type: bool + Definition: Indicate to check for performance lock support in FW. + In case this property is present, the reg & reg-names + should have the "pdmem-domainX" to indicate the + corresponding bases. + * Property qcom,freq-domain Devices supporting freq-domain must set their "qcom,freq-domain" property with phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. From 820ee3381cbc11679c7895b96ba0f2246d9b6154 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 4 Aug 2020 00:35:36 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Add support for performance lock on HOLI The cpufreq-hw requires the performance lock registers to be updated in the cases where the SW DCVS is requested. Change-Id: I6ac45a577904171a051c84b983363d9a2ea1164d --- qcom/holi.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index d40ab330e2a6..c8c55e498567 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1227,13 +1227,16 @@ cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw-epss"; - reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>; - reg-names = "freq-domain0", "freq-domain1"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>, + <0x0fd04504 0x4>, <0x0fd04508 0x4>; + reg-names = "freq-domain0", "freq-domain1", + "pdmem-domain0", "pdmem-domain1"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; qcom,lut-row-size = <4>; qcom,max-lut-entries = <12>; qcom,skip-enable-check; + qcom,perf-lock-support; interrupts = , ; interrupt-names = "dcvsh0_int", "dcvsh1_int";