diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 602164ef74e9..0decb1041d54 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -1877,4 +1877,12 @@ void adreno_get_bus_counters(struct adreno_device *adreno_dev);
  * power up the gpu
  */
 void adreno_clear_dcvs_counters(struct adreno_device *adreno_dev);
+
+/**
+ * gmu_fault_snapshot - Set gmu fault and trigger snapshot
+ * @device: Pointer to the kgsl device
+ *
+ * Set the gmu fault and take snapshot when we hit a gmu fault
+ */
+void gmu_fault_snapshot(struct kgsl_device *device);
 #endif /*__ADRENO_H */
diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c
index 18a245d5ea62..ec0220e6ecd2 100644
--- a/drivers/gpu/msm/adreno_a6xx.c
+++ b/drivers/gpu/msm/adreno_a6xx.c
@@ -2654,7 +2654,7 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
 	.reg_offsets = a6xx_register_offsets,
 	.probe = a6xx_gmu_device_probe,
 	.start = a6xx_start,
-	.snapshot = a6xx_snapshot,
+	.snapshot = a6xx_gmu_snapshot,
 	.init = a6xx_init,
 	.irq_handler = a6xx_irq_handler,
 	.rb_start = a6xx_rb_start,
@@ -2689,7 +2689,7 @@ struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
 	.reg_offsets = a6xx_register_offsets,
 	.probe = a6xx_rgmu_device_probe,
 	.start = a6xx_start,
-	.snapshot = a6xx_snapshot,
+	.snapshot = a6xx_rgmu_snapshot,
 	.init = a6xx_init,
 	.irq_handler = a6xx_irq_handler,
 	.rb_start = a6xx_rb_start,
@@ -2724,7 +2724,7 @@ struct adreno_gpudev adreno_a630_gpudev = {
 	.reg_offsets = a6xx_register_offsets,
 	.probe = a6xx_gmu_device_probe,
 	.start = a6xx_start,
-	.snapshot = a6xx_snapshot,
+	.snapshot = a6xx_gmu_snapshot,
 	.init = a6xx_init,
 	.irq_handler = a6xx_irq_handler,
 	.rb_start = a6xx_rb_start,
diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c
index 1c75f673af23..5b770f8a9422 100644
--- a/drivers/gpu/msm/adreno_a6xx_gmu.c
+++ b/drivers/gpu/msm/adreno_a6xx_gmu.c
@@ -102,6 +102,12 @@ static struct gmu_iommu_context a6xx_gmu_ctx[] = {
 	[GMU_CONTEXT_KERNEL] = { .name = "gmu_kernel" }
 };
 
+void gmu_fault_snapshot(struct kgsl_device *device)
+{
+	device->gmu_fault = true;
+	kgsl_device_snapshot(device, NULL, true);
+}
+
 struct a6xx_gmu_device *to_a6xx_gmu(struct adreno_device *adreno_dev)
 {
 	struct a6xx_device *a6xx_dev = container_of(adreno_dev,
@@ -443,8 +449,7 @@ static int a6xx_gmu_device_start(struct adreno_device *adreno_dev)
 		gmu_core_regread(device,
 			A6XX_GMU_CM3_DTCM_START + (0x3fdc >> 2), &val);
 		dev_err(&gmu->pdev->dev, "GMU doesn't boot: 0x%x\n", val);
-
-		a6xx_gmu_snapshot(device);
+		gmu_fault_snapshot(device);
 		return -ETIMEDOUT;
 	}
 
@@ -468,7 +473,7 @@ static int a6xx_gmu_hfi_start(struct adreno_device *adreno_dev)
 			GMU_START_TIMEOUT,
 			BIT(0))) {
 		dev_err(&gmu->pdev->dev, "GMU HFI init failed\n");
-		a6xx_gmu_snapshot(device);
+		gmu_fault_snapshot(device);
 		return -ETIMEDOUT;
 	}
 
@@ -744,8 +749,8 @@ static int a6xx_gmu_oob_set(struct kgsl_device *device,
 
 	if (timed_poll_check(device, A6XX_GMU_GMU2HOST_INTR_INFO, check,
 		GPU_START_TIMEOUT, check)) {
+		gmu_fault_snapshot(device);
 		ret = -ETIMEDOUT;
-		a6xx_gmu_snapshot(device);
 		WARN(1, "OOB request %s timed out\n", oob_to_str(req));
 	}
 
@@ -914,7 +919,7 @@ int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev)
 			SPTPRAC_CTRL_TIMEOUT,
 			SPTPRAC_POWERON_STATUS_MASK)) {
 		dev_err(&gmu->pdev->dev, "power on SPTPRAC fail\n");
-		a6xx_gmu_snapshot(device);
+		gmu_fault_snapshot(device);
 		return -ETIMEDOUT;
 	}
 
@@ -1112,6 +1117,7 @@ static int a6xx_gmu_wait_for_lowest_idle(struct adreno_device *adreno_dev)
 	}
 
 	WARN_ON(1);
+	gmu_fault_snapshot(device);
 	return -ETIMEDOUT;
 }
 
@@ -1133,6 +1139,7 @@ static int a6xx_gmu_wait_for_idle(struct adreno_device *adreno_dev)
 				"GMU not idling: status2=0x%x %llx %llx\n",
 				status2, ts1,
 				a6xx_read_alwayson(ADRENO_DEVICE(device)));
+		gmu_fault_snapshot(device);
 		return -ETIMEDOUT;
 	}
 
@@ -1936,14 +1943,13 @@ static irqreturn_t a6xx_gmu_irq_handler(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-
-void a6xx_gmu_snapshot(struct kgsl_device *device)
+static void a6xx_gmu_nmi(struct adreno_device *adreno_dev)
 {
-	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);
 
-	/* Abstain from sending another nmi or over-writing snapshot */
-	if (device->gmu_fault)
+	/* No need to nmi if it was a gpu fault */
+	if (!device->gmu_fault)
 		return;
 
 	/* make sure we're reading the latest cm3_fault */
@@ -1960,16 +1966,24 @@ void a6xx_gmu_snapshot(struct kgsl_device *device)
 		/* Wait for the NMI to be handled */
 		udelay(100);
 	}
+}
 
-	kgsl_device_snapshot(device, NULL, true);
+void a6xx_gmu_snapshot(struct adreno_device *adreno_dev,
+	struct kgsl_snapshot *snapshot)
+{
+	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+
+	a6xx_gmu_nmi(adreno_dev);
+
+	a6xx_gmu_device_snapshot(device, snapshot);
+
+	a6xx_snapshot(adreno_dev, snapshot);
 
 	gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR,
 		0xffffffff);
 	gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK,
 		HFI_IRQ_MASK);
 
-	device->gmu_fault = true;
-
 }
 
 static int a6xx_gmu_aop_send_acd_state(struct mbox_chan *channel, bool flag)
@@ -2245,14 +2259,9 @@ static struct gmu_dev_ops a6xx_gmudev = {
 	.gx_is_on = a6xx_gmu_gx_is_on,
 	.ifpc_store = a6xx_gmu_ifpc_store,
 	.ifpc_show = a6xx_gmu_ifpc_show,
-	.snapshot = a6xx_gmu_device_snapshot,
 	.cooperative_reset = a6xx_gmu_cooperative_reset,
 	.wait_for_active_transition = a6xx_gmu_wait_for_active_transition,
 	.scales_bandwidth = a6xx_gmu_scales_bandwidth,
-};
-
-static struct gmu_core_ops a6xx_gmu_ops = {
-	.snapshot = a6xx_gmu_snapshot,
 	.acd_set = a6xx_gmu_acd_set,
 };
 
@@ -2592,7 +2601,6 @@ static int a6xx_gmu_probe(struct kgsl_device *device,
 
 	set_bit(GMU_ENABLED, &device->gmu_core.flags);
 
-	device->gmu_core.core_ops = &a6xx_gmu_ops;
 	device->gmu_core.dev_ops = &a6xx_gmudev;
 
 	/* Initialize HFI and GMU interrupts */
diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.h b/drivers/gpu/msm/adreno_a6xx_gmu.h
index 2ec6cc30ff08..9a3341c06b75 100644
--- a/drivers/gpu/msm/adreno_a6xx_gmu.h
+++ b/drivers/gpu/msm/adreno_a6xx_gmu.h
@@ -286,9 +286,13 @@ void a6xx_enable_gpu_irq(struct adreno_device *adreno_dev);
 void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev);
 
 /**
- * a6xx_gmu_snapshot - Send nmi to gmu and take snapshot
- * @device: Pointer to the kgsl device
+ * a6xx_gmu_snapshot- Take snapshot for gmu targets
+ * @adreno_dev: Pointer to the adreno device
+ * @snapshot: Pointer to the snapshot structure
  *
+ * Send an NMI to gmu if we hit a gmu fault. Then take gmu
+ * snapshot and carry on with rest of the a6xx snapshot
  */
-void a6xx_gmu_snapshot(struct kgsl_device *device);
+void a6xx_gmu_snapshot(struct adreno_device *adreno_dev,
+	struct kgsl_snapshot *snapshot);
 #endif
diff --git a/drivers/gpu/msm/adreno_a6xx_hfi.c b/drivers/gpu/msm/adreno_a6xx_hfi.c
index 4c18c7004516..06bbe3561e04 100644
--- a/drivers/gpu/msm/adreno_a6xx_hfi.c
+++ b/drivers/gpu/msm/adreno_a6xx_hfi.c
@@ -245,6 +245,7 @@ static int receive_ack_cmd(struct a6xx_gmu_device *gmu, void *rcvd,
 	struct pending_cmd *ret_cmd)
 {
 	struct adreno_device *adreno_dev = a6xx_gmu_to_adreno(gmu);
+	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	uint32_t *ack = rcvd;
 	uint32_t hdr = ack[0];
 	uint32_t req_hdr = ack[1];
@@ -266,7 +267,7 @@ static int receive_ack_cmd(struct a6xx_gmu_device *gmu, void *rcvd,
 		"HFI ACK: Cannot find sender for 0x%8.8x Waiter: 0x%8.8x\n",
 		req_hdr, ret_cmd->sent_hdr);
 
-	a6xx_gmu_snapshot(KGSL_DEVICE(adreno_dev));
+	gmu_fault_snapshot(device);
 
 	return -ENODEV;
 }
@@ -310,6 +311,7 @@ static int a6xx_hfi_send_cmd(struct adreno_device *adreno_dev,
 	uint32_t queue_idx, void *data, struct pending_cmd *ret_cmd)
 {
 	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);
+	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	int rc;
 	uint32_t *cmd = data;
 	struct a6xx_hfi *hfi = &gmu->hfi;
@@ -329,7 +331,7 @@ static int a6xx_hfi_send_cmd(struct adreno_device *adreno_dev,
 		HFI_IRQ_MSGQ_MASK, HFI_IRQ_MSGQ_MASK, HFI_RSP_TIMEOUT);
 
 	if (rc) {
-		a6xx_gmu_snapshot(KGSL_DEVICE(adreno_dev));
+		gmu_fault_snapshot(device);
 		dev_err(&gmu->pdev->dev,
 		"Timed out waiting on ack for 0x%8.8x (id %d, sequence %d)\n",
 		cmd[0], MSG_HDR_GET_ID(*cmd), MSG_HDR_GET_SEQNUM(*cmd));
@@ -337,7 +339,7 @@ static int a6xx_hfi_send_cmd(struct adreno_device *adreno_dev,
 	}
 
 	/* Clear the interrupt */
-	gmu_core_regwrite(KGSL_DEVICE(adreno_dev), A6XX_GMU_GMU2HOST_INTR_CLR,
+	gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR,
 		HFI_IRQ_MSGQ_MASK);
 
 	rc = a6xx_hfi_process_queue(gmu, HFI_MSG_ID, ret_cmd);
@@ -359,8 +361,9 @@ static int a6xx_hfi_send_generic_req(struct adreno_device *adreno_dev,
 
 	if (!rc && ret_cmd.results[2] == HFI_ACK_ERROR) {
 		struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);
+		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 
-		a6xx_gmu_snapshot(KGSL_DEVICE(adreno_dev));
+		gmu_fault_snapshot(device);
 		dev_err(&gmu->pdev->dev, "HFI ACK failure: Req 0x%8.8X\n",
 						ret_cmd.results[1]);
 		return -EINVAL;
diff --git a/drivers/gpu/msm/adreno_a6xx_preempt.c b/drivers/gpu/msm/adreno_a6xx_preempt.c
index d83c095ab1c9..da8851edb4a2 100644
--- a/drivers/gpu/msm/adreno_a6xx_preempt.c
+++ b/drivers/gpu/msm/adreno_a6xx_preempt.c
@@ -375,7 +375,7 @@ void a6xx_preemption_trigger(struct adreno_device *adreno_dev)
 err:
 	/* If fenced write fails, take inline snapshot and trigger recovery */
 	if (!in_interrupt()) {
-		gmu_core_snapshot(device);
+		gmu_fault_snapshot(device);
 		adreno_set_gpu_fault(adreno_dev,
 			ADRENO_GMU_FAULT_SKIP_SNAPSHOT);
 	} else {
diff --git a/drivers/gpu/msm/adreno_a6xx_rgmu.c b/drivers/gpu/msm/adreno_a6xx_rgmu.c
index 6ba17af3df98..7623de43be59 100644
--- a/drivers/gpu/msm/adreno_a6xx_rgmu.c
+++ b/drivers/gpu/msm/adreno_a6xx_rgmu.c
@@ -42,8 +42,6 @@ static const unsigned int a6xx_rgmu_registers[] = {
 	0x26000, 0x26002,
 };
 
-static void a6xx_rgmu_snapshot(struct kgsl_device *device);
-
 static struct a6xx_rgmu_device *to_a6xx_rgmu(struct adreno_device *adreno_dev)
 {
 	struct a6xx_device *a6xx_dev = container_of(adreno_dev,
@@ -167,7 +165,7 @@ static int a6xx_rgmu_oob_set(struct kgsl_device *device,
 		dev_err(&rgmu->pdev->dev,
 				"Timed out while setting OOB req:%s status:0x%x\n",
 				oob_to_str(req), status);
-		a6xx_rgmu_snapshot(device);
+		gmu_fault_snapshot(device);
 		return ret;
 	}
 
@@ -368,7 +366,7 @@ static int a6xx_rgmu_wait_for_lowest_idle(struct adreno_device *adreno_dev)
 			reg[7], reg[8], reg[9]);
 
 	WARN_ON(1);
-	a6xx_rgmu_snapshot(device);
+	gmu_fault_snapshot(device);
 	return -ETIMEDOUT;
 }
 
@@ -452,7 +450,7 @@ static int a6xx_rgmu_fw_start(struct adreno_device *adreno_dev,
 		gmu_core_regread(device, A6XX_RGMU_CX_PCC_DEBUG, &status);
 		dev_err(&rgmu->pdev->dev,
 				"rgmu boot Failed. status:%08x\n", status);
-		a6xx_rgmu_snapshot(device);
+		gmu_fault_snapshot(device);
 		return -ETIMEDOUT;
 	}
 
@@ -522,35 +520,29 @@ static int a6xx_rgmu_disable_gdsc(struct adreno_device *adreno_dev)
 
 static void a6xx_rgmu_halt_execution(struct kgsl_device *device);
 
-static void a6xx_rgmu_snapshot(struct kgsl_device *device)
+void a6xx_rgmu_snapshot(struct adreno_device *adreno_dev,
+	struct kgsl_snapshot *snapshot)
 {
-	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	struct a6xx_rgmu_device *rgmu = to_a6xx_rgmu(adreno_dev);
 
-	if (device->gmu_fault)
-		return;
-
-	/* Mask so there's no interrupt caused by NMI */
-	gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK, 0xFFFFFFFF);
-
-	/* Make sure the interrupt is masked */
-	wmb();
-
 	/*
 	 * Halt RGMU execution so that GX will not
 	 * be collapsed while dumping snapshot.
 	 */
 	a6xx_rgmu_halt_execution(device);
 
-	kgsl_device_snapshot(device, NULL, true);
+	adreno_snapshot_registers(device, snapshot, a6xx_rgmu_registers,
+			ARRAY_SIZE(a6xx_rgmu_registers) / 2);
+
+	a6xx_snapshot(adreno_dev, snapshot);
 
 	gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, 0xffffffff);
 	gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK,
 		RGMU_OOB_IRQ_MASK);
 
-	rgmu->fault_count++;
-
-	device->gmu_fault = true;
+	if (device->gmu_fault)
+		rgmu->fault_count++;
 }
 
 static void a6xx_rgmu_suspend(struct adreno_device *adreno_dev)
@@ -644,6 +636,15 @@ static void a6xx_rgmu_halt_execution(struct kgsl_device *device)
 	struct a6xx_rgmu_device *rgmu = to_a6xx_rgmu(ADRENO_DEVICE(device));
 	unsigned int index, status, fence;
 
+	if (!device->gmu_fault)
+		return;
+
+	/* Mask so there's no interrupt caused by NMI */
+	gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK, 0xFFFFFFFF);
+
+	/* Make sure the interrupt is masked */
+	wmb();
+
 	gmu_core_regread(device, A6XX_RGMU_CX_PCC_DEBUG, &index);
 	gmu_core_regread(device, A6XX_RGMU_CX_PCC_STATUS, &status);
 	gmu_core_regread(device, A6XX_GMU_AO_AHB_FENCE_CTRL, &fence);
@@ -666,22 +667,6 @@ static void a6xx_rgmu_halt_execution(struct kgsl_device *device)
 
 }
 
-/*
- * a6xx_rgmu_snapshot() - A6XX GMU snapshot function
- * @adreno_dev: Device being snapshotted
- * @snapshot: Pointer to the snapshot instance
- *
- * This is where all of the A6XX GMU specific bits and pieces are grabbed
- * into the snapshot memory
- */
-static void a6xx_rgmu_device_snapshot(struct kgsl_device *device,
-		struct kgsl_snapshot *snapshot)
-{
-
-	adreno_snapshot_registers(device, snapshot, a6xx_rgmu_registers,
-					ARRAY_SIZE(a6xx_rgmu_registers) / 2);
-}
-
 static void halt_gbif_arb(struct adreno_device *adreno_dev)
 {
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -1174,11 +1159,6 @@ static struct gmu_dev_ops a6xx_rgmudev = {
 	.gx_is_on = a6xx_rgmu_gx_is_on,
 	.ifpc_store = a6xx_rgmu_ifpc_store,
 	.ifpc_show = a6xx_rgmu_ifpc_show,
-	.snapshot = a6xx_rgmu_device_snapshot,
-};
-
-static struct gmu_core_ops a6xx_rgmu_ops = {
-	.snapshot = a6xx_rgmu_snapshot,
 };
 
 static int a6xx_rgmu_irq_probe(struct kgsl_device *device)
@@ -1345,7 +1325,6 @@ static int a6xx_rgmu_probe(struct kgsl_device *device,
 		rgmu->idle_level = GPU_HW_ACTIVE;
 
 	set_bit(GMU_ENABLED, &device->gmu_core.flags);
-	device->gmu_core.core_ops = &a6xx_rgmu_ops;
 	device->gmu_core.dev_ops = &a6xx_rgmudev;
 
 	return 0;
diff --git a/drivers/gpu/msm/adreno_a6xx_rgmu.h b/drivers/gpu/msm/adreno_a6xx_rgmu.h
index 017e487cd9b3..6defcbc5ac46 100644
--- a/drivers/gpu/msm/adreno_a6xx_rgmu.h
+++ b/drivers/gpu/msm/adreno_a6xx_rgmu.h
@@ -78,4 +78,15 @@ int a6xx_rgmu_device_probe(struct platform_device *pdev,
  * Return: 0 on success or negative error on failure
  */
 int a6xx_rgmu_restart(struct kgsl_device *device);
+
+/**
+ * a6xx_rgmu_snapshot - Take snapshot for rgmu based targets
+ * @adreno_dev: Pointer to the adreno device
+ * @snapshot: Pointer to the snapshot
+ *
+ * This function halts rgmu execution if we hit a rgmu
+ * fault. And then, it takes rgmu and gpu snapshot.
+ */
+void a6xx_rgmu_snapshot(struct adreno_device *adreno_dev,
+	struct kgsl_snapshot *snapshot);
 #endif
diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c
index 8d7c9cdb8540..7181c6ca574a 100644
--- a/drivers/gpu/msm/adreno_a6xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c
@@ -1784,9 +1784,6 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,
 	unsigned int i, roq_size;
 	u32 hi, lo;
 
-	/* GMU TCM data dumped through AHB */
-	gmu_core_dev_snapshot(device, snapshot);
-
 	/*
 	 * Dump debugbus data here to capture it for both
 	 * GMU and GPU snapshot. Debugbus data can be accessed
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 00857d97adeb..b7d134929625 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -104,7 +104,7 @@ static void adreno_ringbuffer_wptr(struct adreno_device *adreno_dev,
 		 * If WPTR update fails, take inline snapshot and trigger
 		 * recovery.
 		 */
-		gmu_core_snapshot(device);
+		gmu_fault_snapshot(device);
 		adreno_set_gpu_fault(adreno_dev,
 			ADRENO_GMU_FAULT_SKIP_SNAPSHOT);
 		adreno_dispatcher_schedule(device);
diff --git a/drivers/gpu/msm/adreno_sysfs.c b/drivers/gpu/msm/adreno_sysfs.c
index 5aacc1e51ffd..72f314257605 100644
--- a/drivers/gpu/msm/adreno_sysfs.c
+++ b/drivers/gpu/msm/adreno_sysfs.c
@@ -261,7 +261,7 @@ static bool _acd_show(struct adreno_device *adreno_dev)
 
 static int _acd_store(struct adreno_device *adreno_dev, bool val)
 {
-	return gmu_core_acd_set(KGSL_DEVICE(adreno_dev), val);
+	return gmu_core_dev_acd_set(KGSL_DEVICE(adreno_dev), val);
 }
 
 static ssize_t _sysfs_store_u32(struct device *dev,
diff --git a/drivers/gpu/msm/kgsl_gmu_core.c b/drivers/gpu/msm/kgsl_gmu_core.c
index 62b9a311f8a3..4654507ee743 100644
--- a/drivers/gpu/msm/kgsl_gmu_core.c
+++ b/drivers/gpu/msm/kgsl_gmu_core.c
@@ -51,7 +51,7 @@ bool gmu_core_isenabled(struct kgsl_device *device)
 
 bool gmu_core_gpmu_isenabled(struct kgsl_device *device)
 {
-	return (device->gmu_core.core_ops != NULL);
+	return (device->gmu_core.dev_ops != NULL);
 }
 
 bool gmu_core_scales_bandwidth(struct kgsl_device *device)
@@ -64,20 +64,12 @@ bool gmu_core_scales_bandwidth(struct kgsl_device *device)
 	return false;
 }
 
-void gmu_core_snapshot(struct kgsl_device *device)
+int gmu_core_dev_acd_set(struct kgsl_device *device, bool val)
 {
-	struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device);
+	struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
 
-	if (gmu_core_ops && gmu_core_ops->snapshot)
-		gmu_core_ops->snapshot(device);
-}
-
-int gmu_core_acd_set(struct kgsl_device *device, bool val)
-{
-	struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device);
-
-	if (gmu_core_ops && gmu_core_ops->acd_set)
-		return gmu_core_ops->acd_set(device, val);
+	if (ops && ops->acd_set)
+		return ops->acd_set(device, val);
 
 	return -EINVAL;
 }
@@ -182,15 +174,6 @@ void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req)
 		ops->oob_clear(device, req);
 }
 
-void gmu_core_dev_snapshot(struct kgsl_device *device,
-		struct kgsl_snapshot *snapshot)
-{
-	struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);
-
-	if (ops && ops->snapshot)
-		ops->snapshot(device, snapshot);
-}
-
 void gmu_core_dev_cooperative_reset(struct kgsl_device *device)
 {
 
diff --git a/drivers/gpu/msm/kgsl_gmu_core.h b/drivers/gpu/msm/kgsl_gmu_core.h
index 943b7a59909d..07f3c7b79139 100644
--- a/drivers/gpu/msm/kgsl_gmu_core.h
+++ b/drivers/gpu/msm/kgsl_gmu_core.h
@@ -7,7 +7,6 @@
 
 /* GMU_DEVICE - Given an KGSL device return the GMU specific struct */
 #define GMU_DEVICE_OPS(_a) ((_a)->gmu_core.dev_ops)
-#define GMU_CORE_OPS(_a) ((_a)->gmu_core.core_ops)
 
 #define NUM_BW_LEVELS		100
 #define MAX_GX_LEVELS		16
@@ -100,23 +99,17 @@ struct device_node;
 struct kgsl_device;
 struct kgsl_snapshot;
 
-struct gmu_core_ops {
-	void (*snapshot)(struct kgsl_device *device);
-	int (*acd_set)(struct kgsl_device *device, bool val);
-};
-
 struct gmu_dev_ops {
 	int (*oob_set)(struct kgsl_device *device, enum oob_request req);
 	void (*oob_clear)(struct kgsl_device *device, enum oob_request req);
 	bool (*gx_is_on)(struct kgsl_device *device);
 	int (*ifpc_store)(struct kgsl_device *device, unsigned int val);
 	unsigned int (*ifpc_show)(struct kgsl_device *device);
-	void (*snapshot)(struct kgsl_device *device,
-		struct kgsl_snapshot *shapshot);
 	void (*cooperative_reset)(struct kgsl_device *device);
 	void (*halt_execution)(struct kgsl_device *device);
 	int (*wait_for_active_transition)(struct kgsl_device *device);
 	bool (*scales_bandwidth)(struct kgsl_device *device);
+	int (*acd_set)(struct kgsl_device *device, bool val);
 };
 
 /**
@@ -127,7 +120,6 @@ struct gmu_dev_ops {
  *	gmu registers using offset defined in GPU register space.
  * @reg_len: GMU registers length
  * @reg_virt: GMU CSR virtual address
- * @core_ops: Pointer to gmu core operations
  * @dev_ops: Pointer to gmu device operations
  * @flags: GMU flags
  */
@@ -136,7 +128,6 @@ struct gmu_core_device {
 	unsigned int gmu2gpu_offset;
 	unsigned int reg_len;
 	void __iomem *reg_virt;
-	struct gmu_core_ops *core_ops;
 	struct gmu_dev_ops *dev_ops;
 	unsigned long flags;
 };
@@ -149,11 +140,10 @@ extern struct platform_driver a6xx_rgmu_driver;
 void __init gmu_core_register(void);
 void __exit gmu_core_unregister(void);
 
-void gmu_core_snapshot(struct kgsl_device *device);
 bool gmu_core_gpmu_isenabled(struct kgsl_device *device);
 bool gmu_core_scales_bandwidth(struct kgsl_device *device);
 bool gmu_core_isenabled(struct kgsl_device *device);
-int gmu_core_acd_set(struct kgsl_device *device, bool val);
+int gmu_core_dev_acd_set(struct kgsl_device *device, bool val);
 bool gmu_core_is_register_offset(struct kgsl_device *device,
 				unsigned int offsetwords);
 void gmu_core_regread(struct kgsl_device *device, unsigned int offsetwords,
@@ -179,8 +169,6 @@ void gmu_core_regrmw(struct kgsl_device *device, unsigned int offsetwords,
 		unsigned int mask, unsigned int bits);
 int gmu_core_dev_oob_set(struct kgsl_device *device, enum oob_request req);
 void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req);
-void gmu_core_dev_snapshot(struct kgsl_device *device,
-		struct kgsl_snapshot *snapshot);
 bool gmu_core_dev_gx_is_on(struct kgsl_device *device);
 int gmu_core_dev_ifpc_show(struct kgsl_device *device);
 int gmu_core_dev_ifpc_store(struct kgsl_device *device, unsigned int val);