From f637c1dbb8f40579c6fe84b32fc534cf1ec26027 Mon Sep 17 00:00:00 2001 From: Git User Date: Tue, 7 May 2019 01:59:23 -0700 Subject: [PATCH 001/362] Initial empty repository From b69ad72f9f3a085e319208237b70e5576883566b Mon Sep 17 00:00:00 2001 From: Nilaan Gunabalachandran Date: Wed, 12 Jun 2019 10:41:07 -0400 Subject: [PATCH 002/362] disp: Add display specific dt files and binding snapshot Move sde, panel, msm dtsi and bindings files from 4.19 kernel device tree project to display techpack. As of commit: 514cd5003a3e (Merge "ARM: dts: msm: correct the wb linewidth for saipan"). Change-Id: I78bf2b9f0bf5f0ba43a3bfa04eceea244f9b8f69 --- bindings/dpu.txt | 131 +++ bindings/dsi.txt | 247 +++++ bindings/edp.txt | 56 ++ bindings/hdmi.txt | 99 ++ bindings/mdp4.txt | 112 +++ bindings/mdp5.txt | 158 ++++ bindings/mdss-dsi-panel.txt | 810 ++++++++++++++++ bindings/mdss-pll.txt | 108 +++ bindings/sde-dp.txt | 237 +++++ bindings/sde-dsi.txt | 118 +++ bindings/sde-rsc.txt | 97 ++ bindings/sde-wb.txt | 23 + bindings/sde.txt | 888 ++++++++++++++++++ display/dsi-panel-ext-bridge-1080p.dtsi | 46 + ...l-hx83112a-truly-singlemipi-fhd-video.dtsi | 151 +++ display/dsi-panel-hx8394d-720p-video.dtsi | 87 ++ ...dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi | 240 +++++ ...i-panel-nt35597-truly-dsc-wqxga-video.dtsi | 226 +++++ ...anel-nt35597-truly-dualmipi-wqxga-cmd.dtsi | 219 +++++ ...el-nt35597-truly-dualmipi-wqxga-video.dtsi | 206 ++++ display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi | 185 ++++ .../dsi-panel-nt35695b-truly-fhd-video.dtsi | 177 ++++ ...panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi | 80 ++ ...anel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi | 129 +++ display/dsi-panel-sharp-1080p-cmd.dtsi | 79 ++ display/dsi-panel-sharp-dsc-4k-cmd.dtsi | 96 ++ display/dsi-panel-sharp-dsc-4k-video.dtsi | 89 ++ display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi | 86 ++ .../dsi-panel-sharp-dualdsi-wqhd-video.dtsi | 82 ++ .../dsi-panel-sharp-dualmipi-1080p-120hz.dtsi | 626 ++++++++++++ display/dsi-panel-sim-cmd.dtsi | 347 +++++++ display/dsi-panel-sim-dsc-10bit-cmd.dtsi | 474 ++++++++++ display/dsi-panel-sim-dsc375-cmd.dtsi | 280 ++++++ display/dsi-panel-sim-dualmipi-cmd.dtsi | 141 +++ .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 327 +++++++ display/dsi-panel-sim-dualmipi-video.dtsi | 63 ++ display/dsi-panel-sim-sec-hd-cmd.dtsi | 68 ++ display/dsi-panel-sim-video.dtsi | 62 ++ ...panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi | 103 ++ ...dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi | 121 +++ ...i-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 101 ++ display/dsi-panel-td4328-1080p-cmd.dtsi | 169 ++++ display/dsi-panel-td4328-1080p-video.dtsi | 164 ++++ display/kona-sde-display-cdp-lcd.dtsi | 36 + display/kona-sde-display-cdp.dtsi | 152 +++ display/kona-sde-display-mtp.dtsi | 87 ++ display/kona-sde-display-qrd.dtsi | 76 ++ display/kona-sde-display-rumi.dtsi | 1 + display/kona-sde-display.dtsi | 528 +++++++++++ display/kona-sde-pll.dtsi | 82 ++ display/kona-sde.dtsi | 686 ++++++++++++++ 51 files changed, 9956 insertions(+) create mode 100644 bindings/dpu.txt create mode 100644 bindings/dsi.txt create mode 100644 bindings/edp.txt create mode 100644 bindings/hdmi.txt create mode 100644 bindings/mdp4.txt create mode 100644 bindings/mdp5.txt create mode 100644 bindings/mdss-dsi-panel.txt create mode 100644 bindings/mdss-pll.txt create mode 100644 bindings/sde-dp.txt create mode 100644 bindings/sde-dsi.txt create mode 100644 bindings/sde-rsc.txt create mode 100644 bindings/sde-wb.txt create mode 100644 bindings/sde.txt create mode 100644 display/dsi-panel-ext-bridge-1080p.dtsi create mode 100644 display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi create mode 100644 display/dsi-panel-hx8394d-720p-video.dtsi create mode 100644 display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi create mode 100644 display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi create mode 100644 display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi create mode 100644 display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi create mode 100644 display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi create mode 100644 display/dsi-panel-nt35695b-truly-fhd-video.dtsi create mode 100644 display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi create mode 100644 display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi create mode 100644 display/dsi-panel-sharp-1080p-cmd.dtsi create mode 100644 display/dsi-panel-sharp-dsc-4k-cmd.dtsi create mode 100644 display/dsi-panel-sharp-dsc-4k-video.dtsi create mode 100644 display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi create mode 100644 display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi create mode 100644 display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi create mode 100644 display/dsi-panel-sim-cmd.dtsi create mode 100644 display/dsi-panel-sim-dsc-10bit-cmd.dtsi create mode 100644 display/dsi-panel-sim-dsc375-cmd.dtsi create mode 100644 display/dsi-panel-sim-dualmipi-cmd.dtsi create mode 100644 display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi create mode 100644 display/dsi-panel-sim-dualmipi-video.dtsi create mode 100644 display/dsi-panel-sim-sec-hd-cmd.dtsi create mode 100644 display/dsi-panel-sim-video.dtsi create mode 100644 display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi create mode 100644 display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi create mode 100644 display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi create mode 100644 display/dsi-panel-td4328-1080p-cmd.dtsi create mode 100644 display/dsi-panel-td4328-1080p-video.dtsi create mode 100644 display/kona-sde-display-cdp-lcd.dtsi create mode 100644 display/kona-sde-display-cdp.dtsi create mode 100644 display/kona-sde-display-mtp.dtsi create mode 100644 display/kona-sde-display-qrd.dtsi create mode 100644 display/kona-sde-display-rumi.dtsi create mode 100644 display/kona-sde-display.dtsi create mode 100644 display/kona-sde-pll.dtsi create mode 100644 display/kona-sde.dtsi diff --git a/bindings/dpu.txt b/bindings/dpu.txt new file mode 100644 index 000000000000..ad2e8830324e --- /dev/null +++ b/bindings/dpu.txt @@ -0,0 +1,131 @@ +Qualcomm Technologies, Inc. DPU KMS + +Description: + +Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates +sub-blocks like DPU display controller, DSI and DP interfaces etc. +The DPU display controller is found in SDM845 SoC. + +MDSS: +Required properties: +- compatible: "qcom,sdm845-mdss" +- reg: physical base address and length of contoller's registers. +- reg-names: register region names. The following region is required: + * "mdss" +- power-domains: a power domain consumer specifier according to + Documentation/devicetree/bindings/power/power_domain.txt +- clocks: list of clock specifiers for clocks needed by the device. +- clock-names: device clock names, must be in same order as clocks property. + The following clocks are required: + * "iface" + * "bus" + * "core" +- interrupts: interrupt signal from MDSS. +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: specifies the number of cells needed to encode an interrupt + source, should be 1. +- iommus: phandle of iommu device node. +- #address-cells: number of address cells for the MDSS children. Should be 1. +- #size-cells: Should be 1. +- ranges: parent bus address space is the same as the child bus address space. + +Optional properties: +- assigned-clocks: list of clock specifiers for clocks needing rate assignment +- assigned-clock-rates: list of clock frequencies sorted in the same order as + the assigned-clocks property. + +MDP: +Required properties: +- compatible: "qcom,sdm845-dpu" +- reg: physical base address and length of controller's registers. +- reg-names : register region names. The following region is required: + * "mdp" + * "vbif" +- clocks: list of clock specifiers for clocks needed by the device. +- clock-names: device clock names, must be in same order as clocks property. + The following clocks are required. + * "bus" + * "iface" + * "core" + * "vsync" +- interrupts: interrupt line from DPU to MDSS. +- ports: contains the list of output ports from DPU device. These ports connect + to interfaces that are external to the DPU hardware, such as DSI, DP etc. + + Each output port contains an endpoint that describes how it is connected to an + external interface. These are described by the standard properties documented + here: + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + Port 0 -> DPU_INTF1 (DSI1) + Port 1 -> DPU_INTF2 (DSI2) + +Optional properties: +- assigned-clocks: list of clock specifiers for clocks needing rate assignment +- assigned-clock-rates: list of clock frequencies sorted in the same order as + the assigned-clocks property. + +Example: + + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&clock_dispcc 0>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_iommu 0>; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xae00000 0xb2008>; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <0 0 300000000 19200000>; + + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; diff --git a/bindings/dsi.txt b/bindings/dsi.txt new file mode 100644 index 000000000000..577b3cede370 --- /dev/null +++ b/bindings/dsi.txt @@ -0,0 +1,247 @@ +Qualcomm Technologies Inc. adreno/snapdragon DSI output + +DSI Controller: +Required properties: +- compatible: + * "qcom,mdss-dsi-ctrl" +- reg: Physical base address and length of the registers of controller +- reg-names: The names of register regions. The following regions are required: + * "dsi_ctrl" +- interrupts: The interrupt signal from the DSI block. +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: Phandles to device clocks. +- clock-names: the following clocks are required: + * "mdp_core" + * "iface" + * "bus" + * "core_mmss" + * "byte" + * "pixel" + * "core" + For DSIv2, we need an additional clock: + * "src" + For DSI6G v2.0 onwards, we need also need the clock: + * "byte_intf" +- assigned-clocks: Parents of "byte" and "pixel" for the given platform. +- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided + by a DSI PHY block. See [1] for details on clock bindings. +- vdd-supply: phandle to vdd regulator device node +- vddio-supply: phandle to vdd-io regulator device node +- vdda-supply: phandle to vdda regulator device node +- phys: phandle to DSI PHY device node +- phy-names: the name of the corresponding PHY device +- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) +- ports: Contains 2 DSI controller ports as child nodes. Each port contains + an endpoint subnode as defined in [2] and [3]. + +Optional properties: +- panel@0: Node of panel connected to this DSI controller. + See files in [4] for each supported panel. +- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is + driving a panel which needs 2 DSI links. +- qcom,master-dsi: Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel. +- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is + driving a 2-DSI panel whose 2 links need receive command simultaneously. +- pinctrl-names: the pin control state names; should contain "default" +- pinctrl-0: the default pinctrl state (active) +- pinctrl-n: the "sleep" pinctrl state +- ports: contains DSI controller input and output ports as children, each + containing one endpoint subnode. + + DSI Endpoint properties: + - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's + input endpoint. For port@1, set to the MDP interface output. See [2] for + device graph info. + + - data-lanes: this describes how the physical DSI data lanes are mapped + to the logical lanes on the given platform. The value contained in + index n describes what physical lane is mapped to the logical lane n + (DATAn, where n lies between 0 and 3). The clock lane position is fixed + and can't be changed. Hence, they aren't a part of the DT bindings. See + [3] for more info on the data-lanes property. + + For example: + + data-lanes = <3 0 1 2>; + + The above mapping describes that the logical data lane DATA0 is mapped to + the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 + to phys DATA1 and logic DATA3 to phys DATA2. + + There are only a limited number of physical to logical mappings possible: + <0 1 2 3> + <1 2 3 0> + <2 3 0 1> + <3 0 1 2> + <0 3 2 1> + <1 0 3 2> + <2 1 0 3> + <3 2 1 0> + +DSI PHY: +Required properties: +- compatible: Could be the following + * "qcom,dsi-phy-28nm-hpm" + * "qcom,dsi-phy-28nm-lp" + * "qcom,dsi-phy-20nm" + * "qcom,dsi-phy-28nm-8960" + * "qcom,dsi-phy-14nm" + * "qcom,dsi-phy-10nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. +- reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_regulator" + For DSI 14nm and 10nm PHYs: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" +- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: Phandles to device clocks. See [1] for details on clock bindings. +- clock-names: the following clocks are required: + * "iface" + For 28nm HPM/LP, 28nm 8960 PHYs: +- vddio-supply: phandle to vdd-io regulator device node + For 20nm PHY: +- vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node + For 14nm PHY: +- vcca-supply: phandle to vcca regulator device node + For 10nm PHY: +- vdds-supply: phandle to vdds regulator device node + +Optional properties: +- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY + regulator is wanted. +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/graph.txt +[3] Documentation/devicetree/bindings/media/video-interfaces.txt +[4] Documentation/devicetree/bindings/display/panel/ + +Example: + dsi0: dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + qcom,dsi-host-index = <0>; + interrupt-parent = <&mdp>; + interrupts = <4 0>; + reg-names = "dsi_ctrl"; + reg = <0xfd922800 0x200>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "bus", + "byte", + "core", + "core_mmss", + "iface", + "mdp_core", + "pixel"; + clocks = + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>; + + assigned-clocks = + <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = + <&dsi_phy0 0>, + <&dsi_phy0 1>; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + phys = <&dsi_phy0>; + phy-names ="dsi-phy"; + + qcom,dual-dsi-mode; + qcom,master-dsi; + qcom,sync-dual-dsi; + + qcom,mdss-mdp-transfer-time-us = <12000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dsi_active>; + pinctrl-1 = <&dsi_suspend>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + link2 = <&secondary>; + + power-supply = <...>; + backlight = <...>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + dsi_phy0: dsi-phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + qcom,dsi-phy-index = <0>; + reg-names = + "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + clock-names = "iface"; + clocks = <&mmcc MDSS_AHB_CLK>; + #clock-cells = <1>; + vddio-supply = <&pma8084_l12>; + + qcom,dsi-phy-regulator-ldo-mode; + qcom,panel-allow-phy-poweroff; + qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>; + qcom,panel-force-clock-lane-hs; + }; diff --git a/bindings/edp.txt b/bindings/edp.txt new file mode 100644 index 000000000000..186ee231a1a1 --- /dev/null +++ b/bindings/edp.txt @@ -0,0 +1,56 @@ +Qualcomm Technologies Inc. snapdragon eDP output + +Required properties: +- compatible: + * "qcom,mdss-edp" +- reg: Physical base address and length of the registers of controller and PLL +- reg-names: The names of register regions. The following regions are required: + * "edp" + * "pll_base" +- interrupts: The interrupt signal from the eDP block. +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: the following clocks are required: + * "core" + * "iface" + * "mdp_core" + * "pixel" + * "link" +- #clock-cells: The value should be 1. +- vdda-supply: phandle to vdda regulator device node +- lvl-vdd-supply: phandle to regulator device node which is used to supply power + to HPD receiving chip +- panel-en-gpios: GPIO pin to supply power to panel. +- panel-hpd-gpios: GPIO pin used for eDP hpd. + + +Example: + mdss_edp: qcom,mdss_edp@fd923400 { + compatible = "qcom,mdss-edp"; + reg-names = + "edp", + "pll_base"; + reg = <0xfd923400 0x700>, + <0xfd923a00 0xd4>; + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "core", + "pixel", + "iface", + "link", + "mdp_core"; + clocks = + <&mmcc MDSS_EDPAUX_CLK>, + <&mmcc MDSS_EDPPIXEL_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_EDPLINK_CLK>, + <&mmcc MDSS_MDP_CLK>; + #clock-cells = <1>; + vdda-supply = <&pma8084_l12>; + lvl-vdd-supply = <&lvl_vreg>; + panel-en-gpios = <&tlmm 137 0>; + panel-hpd-gpios = <&tlmm 103 0>; + }; diff --git a/bindings/hdmi.txt b/bindings/hdmi.txt new file mode 100644 index 000000000000..66a123b221b8 --- /dev/null +++ b/bindings/hdmi.txt @@ -0,0 +1,99 @@ +Qualcomm Technologies, Inc. adreno/snapdragon hdmi output + +Required properties: +- compatible: one of the following + * "qcom,hdmi-tx-8996" + * "qcom,hdmi-tx-8994" + * "qcom,hdmi-tx-8084" + * "qcom,hdmi-tx-8974" + * "qcom,hdmi-tx-8660" + * "qcom,hdmi-tx-8960" +- reg: Physical base address and length of the controller's registers +- reg-names: "core_physical" +- interrupts: The interrupt signal from the hdmi block. +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See ../clocks/clock-bindings.txt for details. +- core-vdda-supply: phandle to supply regulator +- hdmi-mux-supply: phandle to mux regulator +- phys: the phandle for the HDMI PHY device +- phy-names: the name of the corresponding PHY device + +Optional properties: +- hpd-gpios: hpd pin +- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin +- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin +- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin +- power-domains: reference to the power domain(s), if available. +- pinctrl-names: the pin control state names; should contain "default" +- pinctrl-0: the default pinctrl state (active) +- pinctrl-1: the "sleep" pinctrl state + +HDMI PHY: +Required properties: +- compatible: Could be the following + * "qcom,hdmi-phy-8660" + * "qcom,hdmi-phy-8960" + * "qcom,hdmi-phy-8974" + * "qcom,hdmi-phy-8084" + * "qcom,hdmi-phy-8996" +- #phy-cells: Number of cells in a PHY specifier; Should be 0. +- reg: Physical base address and length of the registers of the PHY sub blocks. +- reg-names: The names of register regions. The following regions are required: + * "hdmi_phy" + * "hdmi_pll" + For HDMI PHY on msm8996, these additional register regions are required: + * "hdmi_tx_l0" + * "hdmi_tx_l1" + * "hdmi_tx_l3" + * "hdmi_tx_l4" +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- core-vdda-supply: phandle to vdda regulator device node + +Example: + +/ { + ... + + hdmi: hdmi@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg-names = "core_physical"; + reg = <0x04a00000 0x2f0>; + interrupts = ; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "core", + "master_iface", + "slave_iface"; + clocks = + <&mmcc HDMI_APP_CLK>, + <&mmcc HDMI_M_AHB_CLK>, + <&mmcc HDMI_S_AHB_CLK>; + qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hpd_active &ddc_active &cec_active>; + pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; + + phys = <&hdmi_phy>; + phy-names = "hdmi_phy"; + }; + + hdmi_phy: phy@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg-names = "hdmi_phy", + "hdmi_pll"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + #phy-cells = <0>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = "slave_iface"; + clocks = <&mmcc HDMI_S_AHB_CLK>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + }; +}; diff --git a/bindings/mdp4.txt b/bindings/mdp4.txt new file mode 100644 index 000000000000..1d9cf3579dc6 --- /dev/null +++ b/bindings/mdp4.txt @@ -0,0 +1,112 @@ +Qualcomm Technologies, Inc. adreno/snapdragon MDP4 display controller + +Description: + +This is the bindings documentation for the MDP4 display controller found in +SoCs like MSM8960, APQ8064 and MSM8660. + +Required properties: +- compatible: + * "qcom,mdp4" - mdp4 +- reg: Physical base address and length of the controller's registers. +- interrupts: The interrupt signal from the display controller. +- clocks: device clocks + See ../clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required. + * "core_clk" + * "iface_clk" + * "bus_clk" + * "lut_clk" + * "hdmi_clk" + * "tv_clk" +- ports: contains the list of output ports from MDP. These connect to interfaces + that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a + special case since it is a part of the MDP block itself). + + Each output port contains an endpoint that describes how it is connected to an + external interface. These are described by the standard properties documented + here: + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + The output port mappings are: + Port 0 -> LCDC/LVDS + Port 1 -> DSI1 Cmd/Video + Port 2 -> DSI2 Cmd/Video + Port 3 -> DTV + +Optional properties: +- clock-names: the following clocks are optional: + * "lut_clk" + +Example: + +/ { + ... + + hdmi: hdmi@4a00000 { + ... + ports { + ... + port@0 { + reg = <0>; + hdmi_in: endpoint { + remote-endpoint = <&mdp_dtv_out>; + }; + }; + ... + }; + ... + }; + + ... + + mdp: mdp@5100000 { + compatible = "qcom,mdp4"; + reg = <0x05100000 0xf0000>; + interrupts = ; + clock-names = + "core_clk", + "iface_clk", + "lut_clk", + "hdmi_clk", + "tv_clk"; + clocks = + <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_AXI_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp_lvds_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + mdp_dsi1_out: endpoint { + }; + }; + + port@2 { + reg = <2>; + mdp_dsi2_out: endpoint { + }; + }; + + port@3 { + reg = <3>; + mdp_dtv_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; +}; diff --git a/bindings/mdp5.txt b/bindings/mdp5.txt new file mode 100644 index 000000000000..fcad35c3a26e --- /dev/null +++ b/bindings/mdp5.txt @@ -0,0 +1,158 @@ +Qualcomm Technologies, Inc. adreno/snapdragon MDP5 display controller + +Description: + +This is the bindings documentation for the Mobile Display Subsytem(MDSS) that +encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display +controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. + +MDSS: +Required properties: +- compatible: + * "qcom,mdss" - MDSS +- reg: Physical base address and length of the controller's registers. +- reg-names: The names of register regions. The following regions are required: + * "mdss_phys" + * "vbif_phys" +- interrupts: The interrupt signal from MDSS. +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: specifies the number of cells needed to encode an interrupt + source, should be 1. +- power-domains: a power domain consumer specifier according to + Documentation/devicetree/bindings/power/power_domain.txt +- clocks: device clocks. See ../clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required. + * "iface" + * "bus" + * "vsync" +- #address-cells: number of address cells for the MDSS children. Should be 1. +- #size-cells: Should be 1. +- ranges: parent bus address space is the same as the child bus address space. + +Optional properties: +- clock-names: the following clocks are optional: + * "lut" + +MDP5: +Required properties: +- compatible: + * "qcom,mdp5" - MDP5 +- reg: Physical base address and length of the controller's registers. +- reg-names: The names of register regions. The following regions are required: + * "mdp_phys" +- interrupts: Interrupt line from MDP5 to MDSS interrupt controller. +- clocks: device clocks. See ../clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required. +- * "bus" +- * "iface" +- * "core" +- * "vsync" +- ports: contains the list of output ports from MDP. These connect to interfaces + that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a + special case since it is a part of the MDP block itself). + + Each output port contains an endpoint that describes how it is connected to an + external interface. These are described by the standard properties documented + here: + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + The availability of output ports can vary across SoC revisions: + + For MSM8974 and APQ8084: + Port 0 -> MDP_INTF0 (eDP) + Port 1 -> MDP_INTF1 (DSI1) + Port 2 -> MDP_INTF2 (DSI2) + Port 3 -> MDP_INTF3 (HDMI) + + For MSM8916: + Port 0 -> MDP_INTF1 (DSI1) + + For MSM8994 and MSM8996: + Port 0 -> MDP_INTF1 (DSI1) + Port 1 -> MDP_INTF2 (DSI2) + Port 2 -> MDP_INTF3 (HDMI) + +Optional properties: +- clock-names: the following clocks are optional: + * "lut" + +Example: + +/ { + ... + + mdss: mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, + <0x1ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync" + + interrupts = <0 72 0>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: mdp@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x1a01000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0 0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: dsi@1a98000 { + ... + ports { + ... + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + ... + }; + ... + }; + + dsi_phy0: dsi-phy@1a98300 { + ... + }; + }; +}; diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt new file mode 100644 index 000000000000..338ea8d8dc9e --- /dev/null +++ b/bindings/mdss-dsi-panel.txt @@ -0,0 +1,810 @@ +QTI mdss-dsi-panel + +mdss-dsi-panel is a dsi panel device which supports panels that +are compatible with MIPI display serial interface specification. + +Required properties: +- compatible: This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + This property specifies the version + for DSI HW that this panel will work with + "qcom,dsi-panel-v2" = DSI V2.0 +- status: This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + A string that has to be set to "okay/ok" + to enable the panel driver. By default this property + will be set to "disable". Will be set to "ok/okay" + status for specific platforms. +- qcom,mdss-dsi-panel-controller: Specifies the phandle for the DSI controller that + this panel will be mapped to. +- qcom,mdss-dsi-panel-width: Specifies panel width in pixels. +- qcom,mdss-dsi-panel-height: Specifies panel height in pixels. +- qcom,mdss-dsi-bpp: Specifies the panel bits per pixel. + 3 = for rgb111 + 8 = for rgb332 + 12 = for rgb444 + 16 = for rgb565 + 18 = for rgb666 + 24 = for rgb888 +- qcom,mdss-dsi-panel-destination: A string that specifies the destination display for the panel. + "display_1" = DISPLAY_1 + "display_2" = DISPLAY_2 +- qcom,mdss-dsi-panel-timings: An array of length 12 that specifies the PHY + timing settings for the panel. +- qcom,mdss-dsi-panel-timings-8996: An array of length 40 char that specifies the 8996 PHY lane + timing settings for the panel. +- qcom,mdss-dsi-on-command: A byte stream formed by multiple dcs packets base on + qcom dsi controller protocol. + byte 0: dcs data type + byte 1: set to indicate this is an individual packet + (no chain) + byte 2: virtual channel number + byte 3: expect ack from client (dcs read command) + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload +- qcom,mdss-dsi-off-command: A byte stream formed by multiple dcs packets base on + qcom dsi controller protocol. + byte 0: dcs data type + byte 1: set to indicate this is an individual packet + (no chain) + byte 2: virtual channel number + byte 3: expect ack from client (dcs read command) + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload +- qcom,mdss-dsi-post-panel-on-command: same as "qcom,mdss-dsi-on-command" except commands are + sent after displaying an image. + +Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in +qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit, +then 3 options can be tried. + 1. Send the packet as a long packet instead + Byte 0: dcs data type = 05 (DCS short Packet) + Byte 0: dcs data type = 29 (DCS long Packet) + 2. Send the packet in one burst by prepending with the next packet in packet stream + Byte 1 = 01 (indicates this is an individual packet) + Byte 1 = 00 (indicates this will be appended to the next + individual packet in the packet stream) + 3. Prepend a NULL packet to the short packet and send both in one burst instead of + combining multiple short packets and sending them in one burst. + +Optional properties: +- qcom,mdss-dsi-panel-name: A string used as a descriptive name of the panel +- qcom,mdss-dsi-panel-phy-timings: An array of length 'n' char that specifies the DSI PHY lane + timing settings for the panel. This is specific to SDE DRM driver. + The value of 'n' depends on the DSI PHY h/w revision and parsing this + property properly will be taken care in the DSI PHY DRM driver. +- qcom,cmd-sync-wait-broadcast: Boolean used to broadcast dcs command to panels. +- qcom,mdss-dsi-fbc-enable: Boolean used to enable frame buffer compression mode. +- qcom,mdss-dsi-panel-mode-switch: Boolean used to enable panel operating mode switch. +- qcom,mdss-dsi-fbc-slice-height: Slice height(in lines) of compressed block. + Expressed as power of 2. To set as 128 lines, + this should be set to 7. +- qcom,mdss-dsi-fbc-2d-pred-mode: Boolean to enable 2D map prediction. +- qcom,mdss-dsi-fbc-ver2-mode: Boolean to enable FBC 2.0 that supports 1/3 + compression. +- qcom,mdss-dsi-fbc-bpp: Compressed bpp supported by the panel. + Specified color order is used as default value. +- qcom,mdss-dsi-fbc-packing: Component packing. + 0 = default value. +- qcom,mdss-dsi-fbc-quant-error: Boolean used to enable quantization error calculation. +- qcom,mdss-dsi-fbc-bias: Bias for CD. + 0 = default value. +- qcom,mdss-dsi-fbc-pat-mode: Boolean used to enable PAT mode. +- qcom,mdss-dsi-fbc-vlc-mode: Boolean used to enable VLC mode. +- qcom,mdss-dsi-fbc-bflc-mode: Boolean used to enable BFLC mode. +- qcom,mdss-dsi-fbc-h-line-budget: Per line extra budget. + 0 = default value. +- qcom,mdss-dsi-fbc-budget-ctrl: Extra budget level. + 0 = default value. +- qcom,mdss-dsi-fbc-block-budget: Per block budget. + 0 = default value. +- qcom,mdss-dsi-fbc-lossless-threshold: Lossless mode threshold. + 0 = default value. +- qcom,mdss-dsi-fbc-lossy-threshold: Lossy mode threshold. + 0 = default value. +- qcom,mdss-dsi-fbc-rgb-threshold: Lossy RGB threshold. + 0 = default value. +- qcom,mdss-dsi-fbc-lossy-mode-idx: Lossy mode index value. + 0 = default value. +- qcom,mdss-dsi-fbc-max-pred-err: Max quantization prediction error. + 0 = default value +- qcom,mdss-dsi-h-back-porch: Horizontal back porch value in pixel. + 6 = default value. +- qcom,mdss-dsi-h-front-porch: Horizontal front porch value in pixel. + 6 = default value. +- qcom,mdss-dsi-h-pulse-width: Horizontal pulse width. + 2 = default value. +- qcom,mdss-dsi-h-sync-skew: Horizontal sync skew value. + 0 = default value. +- qcom,mdss-dsi-v-back-porch: Vertical back porch value in pixel. + 6 = default value. +- qcom,mdss-dsi-v-front-porch: Vertical front porch value in pixel. + 6 = default value. +- qcom,mdss-dsi-v-pulse-width: Vertical pulse width. + 2 = default value. +- qcom,mdss-dsi-h-left-border: Horizontal left border in pixel. + 0 = default value +- qcom,mdss-dsi-h-right-border: Horizontal right border in pixel. + 0 = default value +- qcom,mdss-dsi-v-top-border: Vertical top border in pixel. + 0 = default value +- qcom,mdss-dsi-v-bottom-border: Vertical bottom border in pixel. + 0 = default value +- qcom,mdss-dsi-underflow-color: Specifies the controller settings for the + panel under flow color. + 0xff = default value. +- qcom,mdss-dsi-border-color: Defines the border color value if border is present. + 0 = default value. +- qcom,mdss-dsi-panel-jitter: Panel jitter value is expressed in terms of numerator + and denominator. It contains two u32 values - numerator + followed by denominator. The jitter configurition causes + the early wakeup if panel needs to adjust before vsync. + Default jitter value is 2.0%. Max allowed value is 10%. +- qcom,mdss-dsi-panel-prefill-lines: An integer value defines the panel prefill lines required to + calculate the backoff time of rsc. + Default value is 16 lines. Max allowed value is vtotal. +- qcom,mdss-dsi-pan-enable-dynamic-fps: Boolean used to enable change in frame rate dynamically. +- qcom,mdss-dsi-pan-fps-update: A string that specifies when to change the frame rate. + "dfps_suspend_resume_mode"= FPS change request is + implemented during suspend/resume. + "dfps_immediate_clk_mode" = FPS change request is + implemented immediately using DSI clocks. + "dfps_immediate_porch_mode_hfp" = FPS change request is + implemented immediately by changing panel horizontal + front porch values. + "dfps_immediate_porch_mode_vfp" = FPS change request is + implemented immediately by changing panel vertical + front porch values. +- qcom,min-refresh-rate: Minimum refresh rate supported by the panel. +- qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh + rate is not specified, then the frame rate of the panel in + qcom,mdss-dsi-panel-framerate is used. +- qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight + control for this panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) +- qcom,mdss-dsi-sec-bl-pmic-control-type: A string that specifies the implementation of backlight + control for secondary panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) +- qcom,mdss-dsi-bl-pwm-pmi: Boolean to indicate that PWM control is through second pmic chip. +- qcom,mdss-dsi-bl-pmic-bank-select: LPG channel for backlight. + Required if backlight pmic control type is PWM +- qcom,mdss-dsi-bl-pmic-pwm-frequency: PWM period in microseconds. + Required if backlight pmic control type is PWM +- qcom,mdss-dsi-pwm-gpio: PMIC gpio binding to backlight. + Required if backlight pmic control type is PWM +- qcom,mdss-dsi-bl-min-level: Specifies the min backlight level supported by the panel. + 0 = default value. +- qcom,mdss-dsi-bl-max-level: Specifies the max backlight level supported by the panel. + 255 = default value. +- qcom,mdss-brightness-max-level: Specifies the max brightness level supported. + 255 = default value. +- qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. + "delay_until_first_frame" = Delay backlight update of the panel + until the first frame is received from the HW. +- qcom,mdss-dsi-interleave-mode: Specifies interleave mode. + 0 = default value. +- qcom,mdss-dsi-panel-type: Specifies the panel operating mode. + "dsi_video_mode" = enable video mode (default). + "dsi_cmd_mode" = enable command mode. +- qcom,5v-boost-gpio: Specifies the panel gpio for display 5v boost. +- qcom,mdss-dsi-te-check-enable: Boolean to enable Tear Check configuration. +- qcom,mdss-dsi-te-using-wd: Boolean entry enables the watchdog timer support to generate the vsync signal + for command mode panel. By default, panel TE will be used to generate the vsync. +- qcom,mdss-dsi-te-using-te-pin: Boolean to specify whether using hardware vsync. +- qcom,mdss-dsi-qsync-min-refresh-rate: A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature. +- qcom,mdss-dsi-qsync-on-commands: String that specifies the commands to enable qsync feature. +- qcom,mdss-dsi-qsync-on-commands-state: String that specifies the ctrl state for sending qsync on commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-qsync-off-commands: String that specifies the commands to disable qsync feature. +- qcom,mdss-dsi-qsync-off-commands-state: String that specifies the ctrl state for sending qsync off commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-te-pin-select: Specifies TE operating mode. + 0 = TE through embedded dcs command + 1 = TE through TE gpio pin. (default) +- qcom,mdss-dsi-te-dcs-command: Inserts the dcs command. + 1 = default value. +- qcom,mdss-dsi-wr-mem-start: DCS command for write_memory_start. + 0x2c = default value. +- qcom,mdss-dsi-wr-mem-continue: DCS command for write_memory_continue. + 0x3c = default value. +- qcom,mdss-dsi-h-sync-pulse: Specifies the pulse mode option for the panel. + 0 = Don't send hsa/he following vs/ve packet(default) + 1 = Send hsa/he following vs/ve packet +- qcom,mdss-dsi-hfp-power-mode: Boolean to determine DSI lane state during + horizontal front porch (HFP) blanking period. +- qcom,mdss-dsi-hbp-power-mode: Boolean to determine DSI lane state during + horizontal back porch (HBP) blanking period. +- qcom,mdss-dsi-hsa-power-mode: Boolean to determine DSI lane state during + horizontal sync active (HSA) mode. +- qcom,mdss-dsi-last-line-interleave Boolean to determine if last line + interleave flag needs to be enabled. +- qcom,mdss-dsi-bllp-eof-power-mode: Boolean to determine DSI lane state during + blanking low power period (BLLP) EOF mode. +- qcom,mdss-dsi-bllp-power-mode: Boolean to determine DSI lane state during + blanking low power period (BLLP) mode. +- qcom,mdss-dsi-traffic-mode: Specifies the panel traffic mode. + "non_burst_sync_pulse" = non burst with sync pulses (default). + "non_burst_sync_event" = non burst with sync start event. + "burst_mode" = burst mode. +- qcom,mdss-dsi-pixel-packing: Specifies if pixel packing is used (in case of RGB666). + "tight" = Tight packing (default value). + "loose" = Loose packing. +- qcom,mdss-dsi-virtual-channel-id: Specifies the virtual channel identefier. + 0 = default value. +- qcom,mdss-dsi-color-order: Specifies the R, G and B channel ordering. + "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value) + "rgb_swap_rbg" = DSI_RGB_SWAP_RBG + "rgb_swap_brg" = DSI_RGB_SWAP_BRG + "rgb_swap_grb" = DSI_RGB_SWAP_GRB + "rgb_swap_gbr" = DSI_RGB_SWAP_GBR +- qcom,mdss-dsi-lane-0-state: Boolean that specifies whether data lane 0 is enabled. +- qcom,mdss-dsi-lane-1-state: Boolean that specifies whether data lane 1 is enabled. +- qcom,mdss-dsi-lane-2-state: Boolean that specifies whether data lane 2 is enabled. +- qcom,mdss-dsi-lane-3-state: Boolean that specifies whether data lane 3 is enabled. +- qcom,mdss-dsi-t-clk-post: Specifies the byte clock cycles after mode switch. + 0x00 = default value. +- qcom,mdss-dsi-t-clk-pre: Specifies the byte clock cycles before mode switch. + 0x00 = default value. +- qcom,mdss-dsi-stream: Specifies the packet stream to be used. + 0 = stream 0 (default) + 1 = stream 1 +- qcom,mdss-dsi-mdp-trigger: Specifies the trigger mechanism to be used for MDP path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_te" = Software trigger and TE +- qcom,mdss-dsi-dma-trigger: Specifies the trigger mechanism to be used for DMA path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_seof" = Software trigger and start/end of frame trigger. + "trigger_sw_te" = Software trigger and TE +- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel. + 60 = 60 frames per second (default) +- qcom,mdss-dsi-panel-clockrate: A 64 bit value specifies the panel clock speed in Hz. + 0 = default value. +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + 14000 = default value. +- qcom,mdss-dsi-on-command-state: String that specifies the ctrl state for sending ON commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-off-command-state: String that specifies the ctrl state for sending OFF commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-post-mode-switch-on-command-state: String that specifies the ctrl state for sending ON commands post mode switch. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-pan-physical-width-dimension: Specifies panel physical width in mm which corresponds + to the physical width in the framebuffer information. +- qcom,mdss-pan-physical-height-dimension: Specifies panel physical height in mm which corresponds + to the physical height in the framebuffer information. +- qcom,mdss-dsi-mode-sel-gpio-state: String that specifies the lcd mode for panel + (such as single-port/dual-port), if qcom,panel-mode-gpio + binding is defined in dsi controller. + "dual_port" = Set GPIO to LOW + "single_port" = Set GPIO to HIGH + "high" = Set GPIO to HIGH + "low" = Set GPIO to LOW + The default value is "dual_port". +- qcom,mdss-tear-check-disable: Boolean to disable mdp tear check. Tear check is enabled by default to avoid + tearing. Other tear-check properties are ignored if this property is present. + The below tear check configuration properties can be individually tuned if + tear check is enabled. +- qcom,mdss-tear-check-sync-cfg-height: Specifies the vertical total number of lines. + The default value is 0xfff0. +- qcom,mdss-tear-check-sync-init-val: Specifies the init value at which the read pointer gets loaded + at vsync edge. The reader pointer refers to the line number of + panel buffer that is currently being updated. + The default value is panel height. +- qcom,mdss-tear-check-sync-threshold-start: + Allows the first ROI line write to an panel when read pointer is + between the range of ROI start line and ROI start line plus this + setting. + The default value is 4. +- qcom,mdss-tear-check-sync-threshold-continue: + The minimum number of lines the write pointer needs to be + above the read pointer so that it is safe to write to the panel. + (This check is not done for the first ROI line write of an update) + The default value is 4. +- qcom,mdss-tear-check-start-pos: Specify the y position from which the start_threshold value is + added and write is kicked off if the read pointer falls within that + region. + The default value is panel height. +- qcom,mdss-tear-check-rd-ptr-trigger-intr: + Specify the read pointer value at which an interrupt has to be + generated. + The default value is panel height + 1. +- qcom,mdss-tear-check-frame-rate: Specify the value to be a real frame rate(fps) x 100 factor to tune the + timing of TE simulation with more precision. + The default value is 6000 with 60 fps. +- qcom,mdss-dsi-reset-sequence: An array that lists the + sequence of reset gpio values and sleeps + Each command will have the format defined + as below: + --> Reset GPIO value + --> Sleep value (in ms) +- qcom,partial-update-enabled: String used to enable partial + panel update for command mode panels. + "none": partial update is disabled + "single_roi": default enable mode, only single roi is sent to panel + "dual_roi": two rois are merged into one big roi. Panel ddic should be able + to process two roi's along with the DCS command to send two rois. + disabled if property is not specified. This property is specified + per timing node to support resolution restrictions. +- qcom,mdss-dsi-horizontal-line-idle: List of width ranges (EC - SC) in pixels indicating + additional idle time in dsi clock cycles that is needed + to compensate for smaller line width. +- qcom,partial-update-roi-merge: Boolean indicates roi combination is need + and function has been provided for dcs + 2A/2B command. This property is specified per timing node to support + resolution restrictions. +- qcom,dcs-cmd-by-left: Boolean to indicate that dcs command are sent + through the left DSI controller only in a dual-dsi configuration +- qcom,mdss-dsi-panel-hdr-enabled: Boolean to indicate HDR support in panel. +- qcom,mdss-dsi-panel-hdr-color-primaries: + Array of 8 unsigned integers denoting chromaticity of panel.These + values are specified in nits units. The value range is 0 through 50000. + To obtain real chromacity, these values should be divided by factor of + 50000. The structure of array is defined in below order + value 1: x value of white chromaticity of display panel + value 2: y value of white chromaticity of display panel + value 3: x value of red chromaticity of display panel + value 4: y value of red chromaticity of display panel + value 5: x value of green chromaticity of display panel + value 6: y value of green chromaticity of display panel + value 7: x value of blue chromaticity of display panel + value 8: y value of blue chromaticity of display panel +- qcom,mdss-dsi-panel-peak-brightness: Maximum brightness supported by panel.In absence of maximum value + typical value becomes peak brightness. Value is specified in nits units. + To obtain real peak brightness, this value should be divided by factor of + 10000. +- qcom,mdss-dsi-panel-blackness-level: Blackness level supported by panel. Blackness level is defined as + ratio of peak brightness to contrast. Value is specified in nits units. + To obtain real blackness level, this value should be divided by factor of + 10000. +- qcom,mdss-dsi-lp11-init: Boolean used to enable the DSI clocks and data lanes (low power 11) + before issuing hardware reset line. +- qcom,mdss-dsi-init-delay-us: Delay in microseconds(us) before performing any DSI activity in lp11 + mode. This master delay (t_init_delay as per DSI spec) should be sum + of DSI internal delay to reach fuctional after power up and minimum + delay required by panel to reach functional. +- qcom,mdss-dsi-rx-eot-ignore: Boolean used to enable ignoring end of transmission packets. +- qcom,mdss-dsi-tx-eot-append: Boolean used to enable appending end of transmission packets. +- qcom,ulps-enabled: Boolean to enable support for Ultra Low Power State (ULPS) mode. +- qcom,suspend-ulps-enabled: Boolean to enable support for ULPS mode for panels during suspend state. +- qcom,panel-roi-alignment: Specifies the panel ROI alignment restrictions on its + left, top, width, height alignments and minimum width and + height values. This property is specified per timing node to support + resolution's alignment restrictions. +- qcom,esd-check-enabled: Boolean used to enable ESD recovery feature. +- qcom,mdss-dsi-panel-status-command: A byte stream formed by multiple dcs packets based on + qcom dsi controller protocol, to read the panel status. + This value is used to kick in the ESD recovery. + byte 0: dcs data type + byte 1: set to indicate this is an individual packet + (no chain) + byte 2: virtual channel number + byte 3: expect ack from client (dcs read command) + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload +- qcom,mdss-dsi-panel-status-command-mode: + String that specifies the ctrl state for reading the panel status. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-lp1-command: An optional byte stream to request low + power mode on a panel +- qcom,mdss-dsi-lp1-command-mode: String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-lp2-command: An optional byte stream to request ultra + low power mode on a panel +- qcom,mdss-dsi-lp2-command-mode: String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-nolp-command: An optional byte stream to disable low + power and ultra low power panel modes +- qcom,mdss-dsi-nolp-command-mode: String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-panel-status-check-mode:Specifies the panel status check method for ESD recovery. + "bta_check" = Uses BTA to check the panel status + "reg_read" = Reads panel status register to check the panel status + "reg_read_nt35596" = Reads panel status register to check the panel + status for NT35596 panel. + "te_signal_check" = Uses TE signal behaviour to check the panel status +- qcom,mdss-dsi-panel-status-read-length: Integer array that specify the expected read-back length of values + for each of panel registers. Each length is corresponding to number of + returned parameters of register introduced in specification. +- qcom,mdss-dsi-panel-status-valid-params: Integer array that specify the valid returned values which need to check + for each of register. + Some panel need only check the first few values returned from panel. + So: if this property is the same to qcom,mdss-dsi-panel-status-read-length, + then just ignore this one. +- qcom,mdss-dsi-panel-status-value: Multiple integer arrays, each specifies the values of the panel status register + which is used to check the panel status. The size of each array is the sum of + length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal. + This can cover that Some panel may return several alternative values. +- qcom,mdss-dsi-panel-max-error-count: Integer value that specifies the maximum number of errors from register + read that can be ignored before treating that the panel has gone bad. +- qcom,dynamic-mode-switch-enabled: Boolean used to mention whether panel supports + dynamic switching from video mode to command mode + and vice versa. +- qcom,dynamic-mode-switch-type: A string specifies how to perform dynamic mode switch. + If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is + dynamic-switch-suspend-resume. + "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will + go blank during transition. + "dynamic-switch-immediate"= Switch on next frame update. Panel will + not go blank for this transition. + "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will + not go blank for this transition. +- qcom,mdss-dsi-post-mode-switch-on-command: Multiple dcs packets used for turning on DSI panel + after panel has switch modes. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,video-to-cmd-mode-switch-commands: List of commands that need to be sent + to panel in order to switch from video mode to command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,cmd-to-video-mode-switch-commands: List of commands that need to be sent + to panel in order to switch from command mode to video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,send-pps-before-switch: Boolean propety to indicate when PPS commands should be sent, + either before or after switch commands during dynamic resolution + switch in DSC panels. If the property is not present, the default + behavior is to send PPS commands after the switch commands. +- qcom,mdss-dsi-panel-orientation: String used to indicate orientation of panel + "180" = panel is flipped in both horizontal and vertical directions + "hflip" = panel is flipped in horizontal direction + "vflip" = panel is flipped in vertical direction +- qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel + for any commands that we send. +- qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. + +- qcom,compression-mode: Select compression mode for panel. + "fbc" - frame buffer compression + "dsc" - display stream compression. + If "dsc" compression is used then config subnodes needs to be defined. +- qcom,panel-supply-entries: A node that lists the elements of the supply used to + power the DSI panel. There can be more than one instance + of this binding, in which case the entry would be appended + with the supply entry index. For a detailed description of + fields in the supply entry, refer to the qcom,ctrl-supply-entries + binding above. +- qcom,mdss-dsc-version: An 8 bit value indicates the DSC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only DSC rev 1(Major).1(Minor) + right now. +- qcom,mdss-dsc-scr-version: Each DSC version can have multiple SCR. This 8 bit value indicates + current SCR revision information supported by panel. +- qcom,mdss-dsc-encoders: An integer value indicating how many DSC encoders should be used + to drive data stream to DSI. + Default value is 1 and max value is 2. + 2 encoder should be used only if qcom,mdss-lm-split or + qcom,split-mode with pingpong-split is used. +- qcom,mdss-dsc-slice-height: An integer value indicates the dsc slice height. +- qcom,mdss-dsc-slice-width: An integer value indicates the dsc slice width. + Multiple of slice width should be equal to panel-width. + Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders + are used then minimum slice width is equal to panel-width/4. +- qcom,mdss-dsc-slice-per-pkt: An integer value indicates the slice per dsi packet. +- qcom,mdss-dsc-bit-per-component: An integer value indicates the bits per component before compression. +- qcom,mdss-dsc-bit-per-pixel: An integer value indicates the bits per pixel after compression. +- qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder. +- qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps + instead of standard dcs type 0x0A. +- qcom,display-topology: Array of u32 values which specifies the list of topologies available + for the display. A display topology is defined by a + set of 3 values in the order: + - number of mixers + - number of compression encoders + - number of interfaces + Therefore, the array should always contain a tuple of 3 elements. +- qcom,default-topology-index: An u32 value which indexes the topology set + specified by the node "qcom,display-topology" + to identify the default topology for the + display. The first set is indexed by the + value 0. +- qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. +- qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active + region, at which command DMA needs to be triggered. + +Required properties for sub-nodes: None +Optional properties: +- qcom,dba-panel: Indicates whether the current panel is used as a display bridge + to a non-DSI interface. +- qcom,bridge-name: A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name + is required if qcom,dba-panel is defined for the panel. +- qcom,adjust-timer-wakeup-ms: An integer value to indicate the timer delay(in ms) to accommodate + s/w delay while configuring the event timer wakeup logic. + +- qcom,mdss-dsi-display-timings: Parent node that lists the different resolutions that the panel supports. + Each child represents timings settings for a specific resolution. +- qcom,mdss-dsi-post-init-delay: Specifies required number of frames to wait so that panel can be functional + to show proper display. +- qcom,mdss-dsi-video-mode: A boolean to indicates current timing can only work in video mode. +- qcom,mdss-dsi-cmd-mode: A boolean to indicates current timing can only work in command mode. + +Additional properties added to the second level nodes that represent timings properties: +- qcom,mdss-dsi-timing-default: Property that specifies the current child as the default + timing configuration that will be used. +- qcom,mdss-dsi-timing-switch-command: List of commands that need to be sent + to panel when the resolution/timing switch happens dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,mdss-dsi-timing-switch-command-state: String that specifies the ctrl state for sending resolution switch + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + +Note, if a given optional qcom,* binding is not present, then the driver will configure +the default values specified. + +Example: +&mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "simulator video mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-pixel-packing = <0>; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-fbc-enable; + qcom,mdss-dsi-panel-mode-switch; + qcom,mdss-dsi-fbc-slice-height = <5>; + qcom,mdss-dsi-fbc-2d-pred-mode; + qcom,mdss-dsi-fbc-ver2-mode; + qcom,mdss-dsi-fbc-bpp = <0>; + qcom,mdss-dsi-fbc-packing = <0>; + qcom,mdss-dsi-fbc-quant-error; + qcom,mdss-dsi-fbc-bias = <0>; + qcom,mdss-dsi-fbc-pat-mode; + qcom,mdss-dsi-fbc-vlc-mode; + qcom,mdss-dsi-fbc-bflc-mode; + qcom,mdss-dsi-fbc-h-line-budget = <0>; + qcom,mdss-dsi-fbc-budget-ctrl = <0>; + qcom,mdss-dsi-fbc-block-budget = <0>; + qcom,mdss-dsi-fbc-lossless-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-threshold = <0>; + qcom,mdss-dsi-fbc-rgb-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-mode-idx = <0>; + qcom,mdss-dsi-fbc-max-pred-err = <2>; + qcom,mdss-dsi-h-front-porch = <140>; + qcom,mdss-dsi-h-back-porch = <164>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <1>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = < 15>; + qcom,mdss-brightness-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-interleave-mode = <0>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-qsync-min-refresh-rate = <30>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-hfp-power-mode; + qcom,mdss-dsi-hbp-power-mode; + qcom,mdss-dsi-hsa-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-last-line-interleave; + qcom,mdss-dsi-traffic-mode = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-color-order = <0>; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x20>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-mdp-trigger = <0>; + qcom,mdss-dsi-dma-trigger = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 2e 06 08 05 03 04 a0]; + qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 FF 99]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; + qcom,min-refresh-rate = <30>; + qcom,max-refresh-rate = <60>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; + qcom,5v-boost-gpio = <&pm8994_gpios 14 0>; + qcom,mdss-pan-physical-width-dimension = <60>; + qcom,mdss-pan-physical-height-dimension = <140>; + qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode"; + qcom,mdss-tear-check-sync-cfg-height = <0xfff0>; + qcom,mdss-tear-check-sync-init-val = <1280>; + qcom,mdss-tear-check-sync-threshold-start = <4>; + qcom,mdss-tear-check-sync-threshold-continue = <4>; + qcom,mdss-tear-check-start-pos = <1280>; + qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>; + qcom,mdss-tear-check-frame-rate = <6000>; + qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-init-delay-us = <100>; + mdss-dsi-rx-eot-ignore; + mdss-dsi-tx-eot-append; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-read-length = <8>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; + qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 B0 03]; + qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B + 15 01 00 00 00 00 02 C2 08]; + qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03]; + qcom,send-pps-before-switch; + qcom,panel-ack-disabled; + qcom,mdss-dsi-horizontal-line-idle = <0 40 256>, + <40 120 128>, + <128 240 64>; + qcom,mdss-dsi-panel-orientation = "180" + qcom,mdss-dsi-panel-jitter = <0x8 0x10>; + qcom,mdss-dsi-panel-prefill-lines = <0x10>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,compression-mode = "dsc"; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-display-timings { + wqhd { + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <728>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <424000000>; + qcom,mdss-mdp-transfer-time-us = <12500>; + qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2a>; + qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 00 00 00 00 00 02 B0 04 + 29 00 00 00 00 00 02 F1 00]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; + + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <4 4 2 2 20 20>; + }; + }; + qcom,panel-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <2800000>; + qcom,supply-max-voltage = <2800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + qcom,dba-panel; + qcom,bridge-name = "adv7533"; + qcom,mdss-dsc-version = <0x11>; + qcom,mdss-dsc-scr-version = <0x1>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-dma-schedule-line = <5>; + }; +}; diff --git a/bindings/mdss-pll.txt b/bindings/mdss-pll.txt new file mode 100644 index 000000000000..a93529717d1c --- /dev/null +++ b/bindings/mdss-pll.txt @@ -0,0 +1,108 @@ +Qualcomm Technologies, Inc. MDSS pll for DSI/EDP/HDMI + +mdss-pll is a pll controller device which supports pll devices that +are compatible with MIPI display serial interface specification, +HDMI and edp. + +Required properties: +- compatible: Compatible name used in the driver. Should be one of: + "qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939", + "qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994", + "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909", + "qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994", + "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992", + "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996", + "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", + "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", + "qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8", + "qcom,mdss_dsi_pll_10nm", "qcom,mdss_dp_pll_8998", + "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm", + "qcom,mdss_dsi_pll_7nm", "qcom,mdss_dp_pll_7nm", + "qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm", + "qcom,mdss_dp_pll_14nm", "qcom,mdss_dsi_pll_7nm_v2", + "qcom,mdss_hdmi_pll_28lpm","qcom,mdss_dsi_pll_7nm_v4_1", + "qcom,mdss_dp_pll_7nm_v2" +- cell-index: Specifies the controller used +- reg: offset and length of the register set for the device. +- reg-names : names to refer to register sets related to this device +- gdsc-supply: Phandle for gdsc regulator device node. +- vddio-supply: Phandle for vddio regulator device node. +- clocks: List of Phandles for clock device nodes + needed by the device. +- clock-names: List of clock names needed by the device. +- clock-rate: List of clock rates in Hz. + +Optional properties: +- label: A string used to describe the driver used. +- vcca-supply: Phandle for vcca regulator device node. + + +- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. +- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" + or "center-spread". Default is "down-spread" if it is not specified. +- qcom,ssc-frequency-hz: Integer property to specify the spread frequency + to be programmed for the SSC. +- qcom,ssc-ppm: Integer property to specify the Parts per Million + value of SSC. + +- qcom,platform-supply-entries: A node that lists the elements of the supply. There + can be more than one instance of this binding, + in which case the entry would be appended with + the supply entry index. + e.g. qcom,platform-supply-entry@0 + - reg: offset and length of the register set for the device. + -- qcom,supply-name: name of the supply (vdd/vdda/vddio) + -- qcom,supply-min-voltage: minimum voltage level (uV) + -- qcom,supply-max-voltage: maximum voltage level (uV) + -- qcom,supply-enable-load: load drawn (uA) from enabled supply + -- qcom,supply-disable-load: load drawn (uA) from disabled supply + -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on + -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on + -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off + -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off + +Example: + mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 { + compatible = "qcom,mdss_dsi_pll_8974"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + + reg = <0xfd922A00 0xD4>, + <0xfd922900 0x64>, + <0xfd8c2300 0x8>; + reg-names = "pll_base", "dynamic_pll_base", "gdsc_base"; + gdsc-supply = <&gdsc_mdss>; + vddio-supply = <&pm8941_l12>; + vcca-supply = <&pm8941_l28>; + + clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, + <&clock_gcc clk_gcc_mdss_ahb_clk>, + <&clock_gcc clk_gcc_mdss_axi_clk>; + clock-names = "mdp_core_clk", "iface_clk", "bus_clk"; + clock-rate = <0>, <0>, <0>; + + qcom,dsi-pll-slave; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,ssc-frequency-hz = <30000>; + qcom,ssc-ppm = <5000>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <20>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + }; + diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt new file mode 100644 index 000000000000..78812304b887 --- /dev/null +++ b/bindings/sde-dp.txt @@ -0,0 +1,237 @@ +Qualcomm Technologies, Inc. +sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. +DP Controller: Required properties: +- compatible: Should be "qcom,dp-display". +- reg: Base address and length of DP hardware's memory mapped regions. +- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. + "dp_phy" - DP PHY memory region. + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. + "dp_mmss_cc" - Display Clock Control memory region. + "qfprom_physical" - QFPROM Phys memory region. + "dp_pll" - USB3 DP combo PLL memory region. + "usb3_dp_com" - USB3 DP PHY combo memory region. + "hdcp_physical" - DP HDCP memory region. +- cell-index: Specifies the controller instance. +- clocks: Clocks required for Display Port operation. +- clock-names: Names of the clocks corresponding to handles. Following clocks are required: + "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", + "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", + "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". +- gdsc-supply: phandle to gdsc regulator node. +- vdda-1p2-supply: phandle to vdda 1.2V regulator node. +- vdda-0p9-supply: phandle to vdda 0.9V regulator node. +- interrupt-parent phandle to the interrupt parent device node. +- interrupts: The interrupt signal from the DSI block. +- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. +- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. +- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. +- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port. +- qcom,mst-enable: MST feature enable control node. +- qcom,dsc-feature-enable: DSC feature enable control node. +- qcom,fec-feature-enable: FEC feature enable control node. +- qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port. +- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block. +- qcom,dp-usbpd-detection: Phandle for the PMI regulator node for USB PHY PD detection. +- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. +- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. +- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. +- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + -- qcom,supply-name: name of the supply (vdd/vdda/vddio) + -- qcom,supply-min-voltage: minimum voltage level (uV) + -- qcom,supply-max-voltage: maximum voltage level (uV) + -- qcom,supply-enable-load: load drawn (uA) from enabled supply + -- qcom,supply-disable-load: load drawn (uA) from disabled supply + -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on + -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on + -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off + -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off + +msm_ext_disp is a device which manages the interaction between external +display interfaces, e.g. Display Port, and the audio subsystem. + +Optional properties: +- qcom,ext-disp: phandle for msm-ext-display module +- compatible: Must be "qcom,msm-ext-disp" +- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node +- qcom,phy-version: Phy version +- qcom,pn-swap-lane-map: P/N swap configuration of each lane +- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node + Refer to pinctrl-bindings.txt +- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin + controller. These pin configurations are installed in the pinctrl + device node. Refer to pinctrl-bindings.txt +- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. +- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one + +[Optional child nodes]: These nodes are for devices which are +dependent on msm_ext_disp. If msm_ext_disp is disabled then +these devices will be disabled as well. Ex. Audio Codec device. + +- ext_disp_audio_codec: Node for Audio Codec. +- compatible : "qcom,msm-ext-disp-audio-codec-rx"; + +Example: + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + sde_dp: qcom,dp_display@0{ + cell-index = <0>; + compatible = "qcom,dp-display"; + + gdsc-supply = <&mdss_core_gdsc>; + vdda-1p2-supply = <&pm8998_l26>; + vdda-0p9-supply = <&pm8998_l1>; + + reg = <0xae90000 0xa84>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x780000 0x621c>, + <0x88ea030 0x10>, + <0x88e8000 0x621c>, + <0x0aee1000 0x034>; + reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "qfprom_physical", "dp_pll", + "usb3_dp_com", "hdcp_physical"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_ref_clk", "core_usb_cfg_ahb_clk", + "core_usb_pipe_clk", "ctrl_link_clk", + "ctrl_link_iface_clk", "ctrl_crypto_clk", + "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent"; + + qcom,dp-usbpd-detection = <&pm8150b_pdphy>; + qcom,ext-disp = <&ext_disp>; + qcom,phy-version = <0x420>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,aux-cfg0-settings = [1c 00]; + qcom,aux-cfg1-settings = [20 13 23 1d]; + qcom,aux-cfg2-settings = [24 00]; + qcom,aux-cfg3-settings = [28 00]; + qcom,aux-cfg4-settings = [2c 0a]; + qcom,aux-cfg5-settings = [30 26]; + qcom,aux-cfg6-settings = [34 0a]; + qcom,aux-cfg7-settings = [38 03]; + qcom,aux-cfg8-settings = [3c bb]; + qcom,aux-cfg9-settings = [40 03]; + qcom,max-pclk-frequency-khz = <593470>; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-input-width-pixs = <2048>; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; + pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; + qcom,aux-en-gpio = <&tlmm 43 0>; + qcom,aux-sel-gpio = <&tlmm 51 0>; + qcom,usbplug-cc-gpio = <&tlmm 38 0>; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <4>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <32>; + }; + }; + }; +}; diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt new file mode 100644 index 000000000000..e09261d55b31 --- /dev/null +++ b/bindings/sde-dsi.txt @@ -0,0 +1,118 @@ +Qualcomm Technologies, Inc. + +mdss-dsi is the master DSI device which supports multiple DSI host controllers +that are compatible with MIPI display serial interface specification. + +DSI Controller: +Required properties: +- compatible: Should be "qcom,dsi-ctrl-hw-v". Supported + versions include 1.4, 2.0 and 2.2. + eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0, + qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, + qcom,dsi-ctrl-hw-v2.4 + And for dsi phy driver: + qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm, + qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, + qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1 +- reg: Base address and length of DSI controller's memory + mapped regions. +- reg-names: A list of strings that name the list of regs. + "dsi_ctrl" - DSI controller memory region. + "mmss_misc" - MMSS misc memory region. +- cell-index: Specifies the controller instance. +- clocks: Clocks required for DSI controller operation. +- clock-names: Names of the clocks corresponding to handles. Following + clocks are required: + "mdp_core_clk" + "iface_clk" + "core_mmss_clk" + "bus_clk" + "byte_clk" + "pixel_clk" + "core_clk" + "byte_clk_rcg" + "pixel_clk_rcg" +- gdsc-supply: phandle to gdsc regulator node. +- vdda-supply: phandle to vdda regulator node. +- vcca-supply: phandle to vcca regulator node. +- interrupt-parent phandle to the interrupt parent device node. +- interrupts: The interrupt signal from the DSI block. +- qcom,dsi-default-panel: Specifies the default panel. +- qcom,mdp: Specifies the mdp node which can find panel node from this. + +Bus Scaling Data: +- qcom,msm-bus,name: String property describing MDSS client. +- qcom,msm-bus,num-cases: This is the number of bus scaling use cases + defined in the vectors property. This must be + set to <2> for MDSS DSI driver where use-case 0 + is used to remove BW votes from the system. Use + case 1 is used to generate bandwidth requestes + when sending command packets. +- qcom,msm-bus,num-paths: This represents number of paths in each bus + scaling usecase. This value depends on number of + AXI master ports dedicated to MDSS for + particular chipset. +- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format + of (src, dst, ab, ib) which is defined at + Documentation/devicetree/bindings/arm/msm/msm_bus.txt. + DSI driver should always set average bandwidth + (ab) to 0 and always use instantaneous + bandwidth(ib) values. + +Optional properties: +- label: String to describe controller. +- qcom,platform-te-gpio: Specifies the gpio used for TE. +- qcom,panel-te-source: Specifies the source pin for Vsync from panel or WD Timer. +- qcom,dsi-ctrl: handle to dsi controller device +- qcom,dsi-phy: handle to dsi phy device +- qcom,dsi-ctrl-num: Specifies the DSI controllers to use for primary panel +- qcom,dsi-sec-ctrl-num: Specifies the DSI controllers to use for secondary panel +- qcom,dsi-phy-num: Specifies the DSI PHYs to use for primary panel +- qcom,dsi-sec-phy-num: Specifies the DSI PHYs to use for secondary panel +- qcom,dsi-select-clocks: Specifies the required clocks to use for primary panel +- qcom,dsi-select-sec-clocks: Specifies the required clocks to use for secondary panel +- qcom,dsi-display-list: Specifies the list of supported displays. +- qcom,dsi-manager: Specifies dsi manager is present +- qcom,dsi-display: Specifies dsi display is present +- qcom,hdmi-display: Specifies hdmi is present +- qcom,dp-display: Specified dp is present +- qcom,-supply-entries: A node that lists the elements of the supply used by the + a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + -- qcom,supply-name: name of the supply (vdd/vdda/vddio) + -- qcom,supply-min-voltage: minimum voltage level (uV) + -- qcom,supply-max-voltage: maximum voltage level (uV) + -- qcom,supply-enable-load: load drawn (uA) from enabled supply + -- qcom,supply-disable-load: load drawn (uA) from disabled supply + -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on + -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on + -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off + -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. +- qcom,dsi-phy-isolation-enabled: A boolean property enables the phy isolation from dsi + controller. This must be enabled for debugging purpose + only with simulator panel. It should not be enabled for + normal DSI panels. +- - qcom,null-insertion-enabled: A boolean to enable NULL packet insertion feature for DSI controller. +- ports: This video port is used when external bridge is present. + The connection is modeled using the OF graph bindings + specified in Documentation/devicetree/bindings/graph.txt. + Video port 0 reg 0 is for the bridge output. The remote + endpoint phandle should be mipi_dsi_device device node. diff --git a/bindings/sde-rsc.txt b/bindings/sde-rsc.txt new file mode 100644 index 000000000000..3af5629ca467 --- /dev/null +++ b/bindings/sde-rsc.txt @@ -0,0 +1,97 @@ +Qualcomm Technologies, Inc. SDE RSC + +Snapdragon Display Engine implements display rsc to driver +display core to different modes for power saving + +Required properties +- compatible: "qcom,sde-rsc" + "qcom,sde-rsc-rpmh" +- reg: Offset and length of the register set for + the device. +- reg-names: Names to refer to register sets related + to this device + +Optional properties: +- clocks: List of phandles for clock device nodes + needed by the device. +- clock-names: List of clock names needed by the device. +- vdd-supply: phandle for vdd regulator device node. +- qcom,sde-rsc-version: U32 property represents the rsc version. It helps to + select correct sequence for sde rsc based on version. +- qcom,sde-dram-channels: U32 property represents the number of channels in the + Bus memory controller. +- qcom,sde-num-nrt-paths: U32 property represents the number of non-realtime + paths in each Bus Scaling Usecase. This value depends on + number of AXI ports that are dedicated to non-realtime VBIF + for particular chipset. + These paths must be defined after rt-paths in + "qcom,msm-bus,vectors-KBps" vector request. + +Bus Scaling Subnodes: +- qcom,sde-data-bus: Property to provide Bus scaling for data bus access for + sde blocks. +- qcom,sde-llcc-bus: Property to provide Bus scaling for data bus access for + mnoc to llcc. +- qcom,sde-ebi-bus: Property to provide Bus scaling for data bus access for + llcc to ebi. + +Bus Scaling Data: +- qcom,msm-bus,name: String property describing client name. +- qcom,msm-bus,active-only: Boolean context flag for requests in active or + dual (active & sleep) contex +- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases + defined in the vectors property. +- qcom,msm-bus,num-paths: This represents the number of paths in each + Bus Scaling Usecase. +- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format + of (src, dst, ab, ib) which is defined at + Documentation/devicetree/bindings/arm/msm/msm_bus.txt + * Current values of src & dst are defined at + include/linux/msm-bus-board.h +Example: + sde_rscc { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x1c44>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + clocks = <&clock_mmss clk_mdss_ahb_clk>, + <&clock_mmss clk_mdss_axi_clk>; + clock-names = "iface_clk", "bus_clk"; + vdd-supply = <&gdsc_mdss>; + + qcom,sde-rsc-version = <1>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <1>; + + qcom,sde-data-bus { + qcom,msm-bus,name = "sde_rsc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + }; + qcom,sde-llcc-bus { + qcom,msm-bus,name = "sde_rsc_llcc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20001 20513 0 0>, + <20001 20513 0 6400000>, + <20001 20513 0 6400000>; + }; + qcom,sde-ebi-bus { + qcom,msm-bus,name = "sde_rsc_ebi"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20000 20512 0 0>, + <20000 20512 0 6400000>, + <20000 20512 0 6400000>; + }; + }; diff --git a/bindings/sde-wb.txt b/bindings/sde-wb.txt new file mode 100644 index 000000000000..90093e41a917 --- /dev/null +++ b/bindings/sde-wb.txt @@ -0,0 +1,23 @@ +Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display + +Required properties: +- compatible: "qcom,wb-display" + +Optional properties: +- cell-index: Index of writeback device instance. + Default to 0 if not specified. +- label: String to describe this writeback display. + Default to "unknown" if not specified. + +Example: + +/ { + ... + + sde_wb: qcom,wb-display { + compatible = "qcom,wb-display"; + cell-index = <2>; + label = "wb_display"; + }; + +}; diff --git a/bindings/sde.txt b/bindings/sde.txt new file mode 100644 index 000000000000..c4c6698514e8 --- /dev/null +++ b/bindings/sde.txt @@ -0,0 +1,888 @@ +Qualcomm Technologies, Inc. SDE KMS + +Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user +interface to different panel interfaces. SDE driver is the core of +display subsystem which manage all data paths to different panel interfaces. + +Required properties +- compatible: Must be "qcom,sde-kms" +- compatible: "msm-hdmi-audio-codec-rx"; +- reg: Offset and length of the register set for the device. +- reg-names : Names to refer to register sets related to this device +- clocks: List of Phandles for clock device nodes + needed by the device. +- clock-names: List of clock names needed by the device. +- mmagic-supply: Phandle for mmagic mdss supply regulator device node. +- vdd-supply: Phandle for vdd regulator device node. +- interrupt-parent: Must be core interrupt controller. +- interrupts: Interrupt associated with MDSS. +- interrupt-controller: Mark the device node as an interrupt controller. +- #interrupt-cells: Should be one. The first cell is interrupt number. +- iommus: Specifies the SID's used by this context bank. +- qcom,sde-sspp-type: Array of strings for SDE source surface pipes type information. + A source pipe can be "vig", "rgb", "dma" or "cursor" type. + Number of xin ids defined should match the number of offsets + defined in property: qcom,sde-sspp-off. +- qcom,sde-sspp-off: Array of offset for SDE source surface pipes. The offsets + are calculated from register "mdp_phys" defined in + reg property + "sde-off". The number of offsets defined here should + reflect the amount of pipes that can be active in SDE for + this configuration. +- qcom,sde-sspp-xin-id: Array of VBIF clients ids (xins) corresponding + to the respective source pipes. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-sspp-off. +- qcom,sde-ctl-off: Array of offset addresses for the available ctl + hw blocks within SDE, these offsets are + calculated from register "mdp_phys" defined in + reg property. The number of ctl offsets defined + here should reflect the number of control paths + that can be configured concurrently on SDE for + this configuration. +- qcom,sde-wb-off: Array of offset addresses for the programmable + writeback blocks within SDE. +- qcom,sde-wb-xin-id: Array of VBIF clients ids (xins) corresponding + to the respective writeback. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-wb-off. +- qcom,sde-mixer-off: Array of offset addresses for the available + mixer blocks that can drive data to panel + interfaces. These offsets are be calculated from + register "mdp_phys" defined in reg property. + The number of offsets defined should reflect the + amount of mixers that can drive data to a panel + interface. +- qcom,sde-dspp-top-off: Offset address for the dspp top block. + The offset is calculated from register "mdp_phys" + defined in reg property. +- qcom,sde-dspp-off: Array of offset addresses for the available dspp + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. +- qcom,sde-pp-off: Array of offset addresses for the available + pingpong blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. +- qcom,sde-pp-slave: Array of flags indicating whether each ping pong + block may be configured as a pp slave. +- qcom,sde-pp-merge-3d-id: Array of index ID values for the merge 3d block + connected to each pingpong, starting at 0. +- qcom,sde-merge-3d-off: Array of offset addresses for the available + merge 3d blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. +- qcom,sde-intf-off: Array of offset addresses for the available SDE + interface blocks that can drive data to a + panel controller. The offsets are calculated + from "mdp_phys" defined in reg property. The number + of offsets defined should reflect the number of + programmable interface blocks available in hardware. +- qcom,sde-mixer-blend-op-off Array of offset addresses for the available + blending stages. The offsets are relative to + qcom,sde-mixer-off. +- qcom,sde-mixer-pair-mask Array of mixer numbers that can be paired with + mixer number corresponding to the array index. + +Optional properties: +- clock-rate: List of clock rates in Hz. +- clock-max-rate: List of maximum clock rate in Hz that this device supports. +- qcom,platform-supply-entries: A node that lists the elements of the supply. There + can be more than one instance of this binding, + in which case the entry would be appended with + the supply entry index. + e.g. qcom,platform-supply-entry@0 + -- reg: offset and length of the register set for the device. + -- qcom,supply-name: name of the supply (vdd/vdda/vddio) + -- qcom,supply-min-voltage: minimum voltage level (uV) + -- qcom,supply-max-voltage: maximum voltage level (uV) + -- qcom,supply-enable-load: load drawn (uA) from enabled supply + -- qcom,supply-disable-load: load drawn (uA) from disabled supply + -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on + -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on + -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off + -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off +- qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. +- qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. +- qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. +- qcom,sde-dspp-size: A u32 value indicates the address range for each dspp. +- qcom,sde-intf-size: A u32 value indicates the address range for each intf. +- qcom,sde-dsc-size: A u32 value indicates the address range for each dsc. +- qcom,sde-cdm-size: A u32 value indicates the address range for each cdm. +- qcom,sde-pp-size: A u32 value indicates the address range for each pingpong. +- qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d. +- qcom,sde-wb-size: A u32 value indicates the address range for each writeback. +- qcom,sde-len: A u32 entry for SDE address range. +- qcom,sde-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on + each interface. +- qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width. +- qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. +- qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. +- qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. +- qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for + alpha blending. +- qcom,sde-qseed-type: A string entry indiates qseed support on sspp and wb. + It supports "qssedv3" and "qseedv2" entries for qseed + type. By default "qseedv2" is used if this optional property + is not defined. +- qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. + It supports "csc" and "csc-10bit" entries for csc + type. +- qcom,sde-highest-bank-bit: A u32 property to indicate GPU/Camera/Video highest memory + bank bit used for tile format buffers. +- qcom,sde-ubwc-version: Property to specify the UBWC feature version. +- qcom,sde-ubwc-static: Property to specify the default UBWC static + configuration value. +- qcom,sde-ubwc-bw-calc-version: A u32 property to specify version of UBWC bandwidth + calculation algorithm +- qcom,sde-ubwc-swizzle: Property to specify the default UBWC swizzle + configuration value. +- qcom,sde-smart-panel-align-mode: A u32 property to specify the align mode for + split display on smart panel. Possible values: + 0x0 - no alignment + 0xc - align at start of frame + 0xd - align at start of line +- qcom,sde-panic-per-pipe: Boolean property to indicate if panic signal + control feature is available on each source pipe. +- qcom,sde-has-src-split: Boolean property to indicate if source split + feature is available or not. +- qcom,sde-has-dim-layer: Boolean property to indicate if mixer has dim layer + feature is available or not. +- qcom,sde-has-idle-pc: Boolean property to indicate if target has idle + power collapse feature available or not. +- qcom,fullsize-va-map: Boolean property to indicate smmu mapping range + for mdp should be full range (4GB). +- qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction + feature available or not. +- qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler + feature is available or not. +- qcom,sde-max-dest-scaler-input-linewidth: A u32 value indicates the + maximum input line width to destination scaler. +- qcom,sde-max-dest-scaler-output-linewidth: A u32 value indicates the + maximum output line width of destination scaler. +- qcom,sde-dest-scaler-top-off: A u32 value provides the + offset from mdp base to destination scaler block. +- qcom,sde-dest-scaler-top-size: A u32 value indicates the address range for ds top +- qcom,sde-dest-scaler-off: Array of u32 offsets indicate the qseed3 scaler blocks + offset from destination scaler top offset. +- qcom,sde-dest-scaler-size: A u32 value indicates the address range for each scaler block +- qcom,sde-sspp-clk-ctrl: Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off +- qcom,sde-sspp-clk-status: Array of offsets describing clk status + offsets for dynamic clock gating. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off. +- qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle + support on each sspp. +- qcom,sde-sspp-smart-dma-priority: Array of u32 values indicating hw pipe + priority of secondary rectangles when smart dma + is supported. Number of priority values should + match the number of offsets defined in + qcom,sde-sspp-off node. Zero indicates no support + for smart dma for the sspp. +- qcom,sde-smart-dma-rev: A string entry indicating the smart dma version + supported on the device. Supported entries are + "smart_dma_v1" and "smart_dma_v2". +- qcom,sde-intf-type: Array of string provides the interface type information. + Possible string values + "dsi" - dsi display interface + "dp" - Display Port interface + "hdmi" - HDMI display interface + An interface is considered as "none" if interface type + is not defined. +- qcom,sde-off: SDE offset from "mdp_phys" defined in reg property. +- qcom,sde-cdm-off: Array of offset addresses for the available + cdm blocks. These offsets will be calculated from + register "mdp_phys" defined in reg property. +- qcom,sde-vbif-off: Array of offset addresses for the available + vbif blocks. These offsets will be calculated from + register "vbif_phys" defined in reg property. +- qcom,sde-vbif-size: A u32 value indicates the vbif block address range. +- qcom,sde-uidle-off: A u32 value with the offset for the uidle + block, from the "mdp_phys". +- qcom,sde-uidle-size: A u32 value indicates the uidle block address range. +- qcom,sde-te-off: A u32 offset indicates the te block offset on pingpong. + This offset is 0x0 by default. +- qcom,sde-te2-off: A u32 offset indicates the te2 block offset on pingpong. +- qcom,sde-te-size: A u32 value indicates the te block address range. +- qcom,sde-te2-size: A u32 value indicates the te2 block address range. +- qcom,sde-dsc-off: A u32 offset indicates the dsc block offset on pingpong. +- qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. +- qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. +- qcom,sde-dither-version: A u32 value indicates the dither block version. +- qcom,sde-dither-size: A u32 value indicates the dither block address range. +- qcom,sde-sspp-vig-blocks: A node that lists the blocks inside the VIG hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the SSPP VIG contains that feature hardware. + e.g. qcom,sde-sspp-vig-blocks + -- qcom,sde-vig-csc-off: offset of CSC hardware + -- qcom,sde-vig-qseed-off: offset of QSEED hardware + -- qcom,sde-vig-qseed-size: A u32 address range for qseed scaler. + -- qcom,sde-vig-pcc: offset and version of PCC hardware + -- qcom,sde-vig-hsic: offset and version of global PA adjustment + -- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware + -- qcom,sde-vig-gamut: offset and version of 3D LUT Gamut hardware + -- qcom,sde-vig-igc: offset and version of 1D LUT IGC hardware + -- qcom,sde-vig-inverse-pma: Boolean property to indicate if + inverse PMA feature is available on VIG pipe +- qcom,sde-sspp-dma-blocks: A node that lists the blocks inside the DMA hardware. There + can be more than one instance of this binding, in which case the + entry would be appended with dgm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP DMA contains + that feature hardware. + e.g. qcom,sde-sspp-dma-blocks + -- dgm@0 + -- qcom,sde-dma-igc: offset and version of DMA IGC + -- qcom,sde-dma-gc: offset and version of DMA GC + -- qcom,sde-dma-inverse-pma: Boolean property to indicate if + inverse PMA feature is available on DMA pipe + -- qcom,sde-dma-csc-off: offset of CSC hardware +- qcom,sde-sspp-rgb-blocks: A node that lists the blocks inside the RGB hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the SSPP RGB contains that feature hardware. + e.g. qcom,sde-sspp-rgb-blocks + -- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware + -- qcom,sde-rgb-scaler-size: A u32 address range for scaler. + -- qcom,sde-rgb-pcc: offset and version of PCC hardware +- qcom,sde-dspp-blocks: A node that lists the blocks inside the DSPP hardware. The + block entries will contain the offset and version of each + feature block. The presence of a block entry indicates that + the DSPP contains that feature hardware. + e.g. qcom,sde-dspp-blocks + -- qcom,sde-dspp-pcc: offset and version of PCC hardware + -- qcom,sde-dspp-gc: offset and version of GC hardware + -- qcom,sde-dspp-igc: offset and version of IGC hardware + -- qcom,sde-dspp-hsic: offset and version of global PA adjustment + -- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware + -- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware + -- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware + -- qcom,sde-dspp-dither: offset and version of dither hardware + -- qcom,sde-dspp-hist: offset and version of histogram hardware + -- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware +- qcom,sde-mixer-blocks: A node that lists the blocks inside the layer mixer hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the layer mixer contains that feature hardware. + e.g. qcom,sde-mixer-blocks + -- qcom,sde-mixer-gc: offset and version of mixer GC hardware +- qcom,sde-dspp-ad-off: Array of u32 offsets indicate the ad block offset from the + DSPP offset. Since AD hardware is represented as part of + DSPP block, the AD offsets must be offset from the + corresponding DSPP base. +- qcom,sde-dspp-ad-version A u32 value indicating the version of the AD hardware +- qcom,sde-dspp-ltm-version A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits) + version of the LTM hardware +- qcom,sde-dspp-ltm-off: Array of u32 offsets indicate the LTM block offsets from the + DSPP offsets. Since LTM hardware is represented as part of + DSPP block, the LTM offsets are calculated based on the + corresponding DSPP base. +- qcom,sde-vbif-id: Array of vbif ids corresponding to the + offsets defined in property: qcom,sde-vbif-off. +- qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit +- qcom,sde-vbif-default-ot-wr-limit: A u32 value indicates the default write OT limit +- qcom,sde-vbif-dynamic-ot-rd-limit: A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the read limit to apply if the given + pps is not exceeded. +- qcom,sde-vbif-dynamic-ot-wr-limit: A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the write limit to apply if the given + pps is not exceeded. +- qcom,sde-vbif-memtype-0: Array of u32 vbif memory type settings, group 0 +- qcom,sde-vbif-memtype-1: Array of u32 vbif memory type settings, group 1 +- qcom,sde-wb-id: Array of writeback ids corresponding to the + offsets defined in property: qcom,sde-wb-off. +- qcom,sde-wb-clk-ctrl: Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off +- qcom,sde-reg-dma-off: Offset of the register dma hardware block from + "regdma_phys" defined in reg property. +- qcom,sde-reg-dma-version: Version of the reg dma hardware block. +- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys" + defined in reg property. +- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast + functionality in the register dma hardware block should be used. +- qcom,sde-reg-dma-xin-id: VBIF clients id (xin) corresponding + to the LUTDMA block. +- qcom,sde-reg-dma-clk-ctrl: Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. +- qcom,sde-dram-channels: This represents the number of channels in the + Bus memory controller. +- qcom,sde-num-nrt-paths: Integer property represents the number of non-realtime + paths in each Bus Scaling Usecase. This value depends on + number of AXI ports that are dedicated to non-realtime VBIF + for particular chipset. + These paths must be defined after rt-paths in + "qcom,msm-bus,vectors-KBps" vector request. +- qcom,sde-max-bw-low-kbps: This value indicates the max bandwidth in Kbps + that can be supported without underflow. + This is a low bandwidth threshold which should + be applied in most scenarios to be safe from + underflows when unable to satisfy bandwidth + requirements. +- qcom,sde-max-bw-high-kbps: This value indicates the max bandwidth in Kbps + that can be supported without underflow in the + event where there is no VFE. + This is a high bandwidth threshold which can be + applied in scenarios where panel interface can + be more tolerant to memory latency such as + command mode panels. +- qcom,sde-core-ib-ff: A string entry indicating the fudge factor for + core ib calculation. +- qcom,sde-core-clk-ff: A string entry indicating the fudge factor for + core clock calculation. +- qcom,sde-min-core-ib-kbps: This u32 value indicates the minimum mnoc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. +- qcom,sde-min-llcc-ib-kbps: This u32 value indicates the minimum llcc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. +- qcom,sde-min-dram-ib-kbps: This u32 value indicates the minimum dram ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. +- qcom,sde-comp-ratio-rt: A string entry indicating the compression ratio + for each supported compressed format on realtime interface. + The string is composed of one or more of + /// + separated with spaces. +- qcom,sde-comp-ratio-nrt: A string entry indicating the compression ratio + for each supported compressed format on non-realtime interface. + The string is composed of one or more of + /// + separated with spaces. +- qcom,sde-undersized-prefill-lines: A u32 value indicates the size of undersized prefill in lines. +- qcom,sde-xtra-prefill-lines: A u32 value indicates the extra prefill in lines. +- qcom,sde-dest-scale-prefill-lines: A u32 value indicates the latency of destination scaler in lines. +- qcom,sde-macrotile-prefill-lines: A u32 value indicates the latency of macrotile in lines. +- qcom,sde-yuv-nv12-prefill-lines: A u32 value indicates the latency of yuv/nv12 in lines. +- qcom,sde-linear-prefill-lines: A u32 value indicates the latency of linear in lines. +- qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines. +- qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps. +- qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines. +- qcom,sde-vbif-qos-rt-remap: This array is used to program vbif qos remapper register + priority for realtime clients. +- qcom,sde-vbif-qos-nrt-remap: This array is used to program vbif qos remapper register + priority for non-realtime clients. +- qcom,sde-vbif-qos-cwb-remap: This array is used to program vbif qos remapper register + priority for concurrent writeback clients. +- qcom,sde-vbif-qos-lutdma-remap: This array is used to program vbif qos remapper register + priority for lutdma client. +- qcom,sde-danger-lut: Array of 5 cell property, with a format of + , + indicating the danger luts on sspp. +- qcom,sde-safe-lut-linear: Array of 2 cell property, with a format of + in ascending fill level + indicating the safe luts for linear format on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-safe-lut-macrotile: Array of 2 cell property, with a format of + in ascending fill level + indicating the safe luts for macrotile format on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-safe-lut-macrotile-qseed: Array of 2 cell property, with a format of + in ascending fill level + indicating the safe luts for macrotile format + with qseed3 on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-safe-lut-nrt: Array of 2 cell property, with a format of + in ascending fill level + indicating the safe luts for nrt (e.g wfd) on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-safe-lut-cwb: Array of 2 cell property, with a format of + in ascending fill level + indicating the safe luts for cwb on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-qos-lut-linear: Array of 3 cell property, with a format of + in ascending fill level + indicating the qos luts for linear format on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-qos-lut-macrotile: Array of 3 cell property, with a format of + in ascending fill level + indicating the qos luts for macrotile format on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-qos-lut-macrotile-qseed: Array of 3 cell property, with a format of + in ascending fill level + indicating the qos luts for macrotile format + with qseed3 enabled on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-qos-lut-nrt: Array of 3 cell property, with a format of + in ascending fill level + indicating the qos luts for nrt (e.g wfd) on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-qos-lut-cwb: Array of 3 cell property, with a format of + in ascending fill level + indicating the qos luts for cwb on sspp. + Zero fill level on the last entry identifies the default lut. +- qcom,sde-cdp-setting: Array of 2 cell property, with a format of + for cdp use cases in + order of , and . +- qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask. +- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. +- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline + rotation. +- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, + namely sspp or wb. Number of entries should match + the number of xin-ids defined in + property: qcom,sde-inline-rot-xin +- qcom,sde-inline-rot-clk-ctrl: Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of xin-ids defined in + property: qcom,sde-inline-rot-xin +- qcom,sde-secure-sid-mask: Array of secure SID masks used during + secure-camera/secure-display usecases. +- #power-domain-cells: Number of cells in a power-domain specifier and should contain 0. +- #list-cells: Number of mdp cells, must be 1. +- qcom,sde-mixer-display-pref: A string array indicating the preferred display type + for the mixer block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display +- qcom,sde-mixer-cwb-pref: A string array indicating the preferred mixer block. + for CWB. Possible values: + "cwb" - preferred for cwb + "none" - no preference on display +- qcom,sde-ctl-display-pref: A string array indicating the preferred display type + for the ctl block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display +- qcom,sde-pipe-order-version: A u32 property to indicate version of pipe + ordering block + 0: lower priority pipe has to be on the left for a given pair of pipes. + 1: priority have to be explicitly configured for a given pair of pipes. + +Bus Scaling Subnodes: +- qcom,sde-reg-bus: Property to provide Bus scaling for register access for + mdss blocks. +- qcom,sde-data-bus: Property to provide Bus scaling for data bus access for + mdss blocks. +- qcom,sde-llcc-bus: Property to provide Bus scaling for data bus access for + mnoc to llcc. +- qcom,sde-ebi-bus: Property to provide Bus scaling for data bus access for + llcc to ebi. + +- qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle, + instance id), of inline rotator device. + +Bus Scaling Data: +- qcom,msm-bus,name: String property describing client name. +- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases + defined in the vectors property. +- qcom,msm-bus,num-paths: This represents the number of paths in each + Bus Scaling Usecase. +- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format + of (src, dst, ab, ib) which is defined at + Documentation/devicetree/bindings/arm/msm/msm_bus.txt + * Current values of src & dst are defined at + include/linux/msm-bus-board.h + +SMMU Subnodes: +- smmu_sde_****: Child nodes representing sde smmu virtual + devices + +Subnode properties: +- compatible: Compatible names used for smmu devices. + names should be: + "qcom,smmu_sde_unsec": smmu context bank device + for unsecure sde real time domain. + "qcom,smmu_sde_sec": smmu context bank device + for secure sde real time domain. + "qcom,smmu_sde_nrt_unsec": smmu context bank device + for unsecure sde non-real time domain. + "qcom,smmu_sde_nrt_sec": smmu context bank device + for secure sde non-real time domain. + + +Please refer to ../../interrupt-controller/interrupts.txt for a general +description of interrupt bindings. + +Example: + mdss_mdp: qcom,mdss_mdp@900000 { + compatible = "qcom,sde-kms"; + reg = <0x00900000 0x90000>, + <0x009b0000 0x1040>, + <0x009b8000 0x1040>, + <0x0aeac000 0x00f0>; + reg-names = "mdp_phys", + "vbif_phys", + "vbif_nrt_phys", + "regdma_phys"; + clocks = <&clock_mmss clk_mdss_ahb_clk>, + <&clock_mmss clk_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>, + <&clock_mmss clk_mdss_mdp_vote_clk>, + <&clock_mmss clk_smmu_mdp_axi_clk>, + <&clock_mmss clk_mmagic_mdss_axi_clk>, + <&clock_mmss clk_mdss_vsync_clk>; + clock-names = "iface_clk", + "bus_clk", + "core_clk_src", + "core_clk", + "iommu_clk", + "mmagic_clk", + "vsync_clk"; + clock-rate = <0>, <0>, <0>; + clock-max-rate= <0 320000000 0>; + mmagic-supply = <&gdsc_mmagic_mdss>; + vdd-supply = <&gdsc_mdss>; + interrupt-parent = <&intc>; + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&mdp_smmu 0>; + #power-domain-cells = <0>; + + qcom,sde-off = <0x1000>; + qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 + 0x00002600 0x00002800>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + qcom,sde-mixer-off = <0x00045000 0x00046000 + 0x00047000 0x0004a000>; + qcom,sde-mixer-display-pref = "primary", "none", + "none", "none"; + qcom,sde-mixer-cwb-pref = "none", "none", + "cwb", "none"; + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-off = <0x00055000 0x00057000>; + qcom,sde-dspp-ad-off = <0x24000 0x22800>; + qcom,sde-dspp-ad-version = <0x00030000>; + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-wb-off = <0x00066000>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-intf-off = <0x0006b000 0x0006b800 + 0x0006c000 0x0006c800>; + qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; + qcom,sde-pp-off = <0x00071000 0x00071800 + 0x00072000 0x00072800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; + qcom,sde-cdm-off = <0x0007a200>; + qcom,sde-dsc-off = <0x00081000 0x00081400>; + qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; + + qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-qdss-off = <0x81a00>; + + qcom,sde-sspp-type = "vig", "vig", "vig", + "vig", "rgb", "rgb", + "rgb", "rgb", "dma", + "dma", "cursor", "cursor"; + + qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000 + 0x0000b000 0x00015000 0x00017000 + 0x00019000 0x0001b000 0x00025000 + 0x00027000 0x00035000 0x00037000>; + + qcom,sde-sspp-xin-id = <0 4 8 + 12 1 5 + 9 13 2 + 10 7 7>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2560>; + qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-highest-bank-bit = <0x2>; + qcom,sde-ubwc-version = <0x100>; + qcom,sde-ubwc-static = <0x100>; + qcom,sde-ubwc-swizzle = <0>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-smart-panel-align-mode = <0xd>; + qcom,sde-panic-per-pipe; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-sspp-src-size = <0x100>; + qcom,sde-mixer-size = <0x100>; + qcom,sde-ctl-size = <0x100>; + qcom,sde-dspp-top-size = <0xc>; + qcom,sde-dspp-size = <0x100>; + qcom,sde-intf-size = <0x100>; + qcom,sde-dsc-size = <0x100>; + qcom,sde-cdm-size = <0x100>; + qcom,sde-pp-size = <0x100>; + qcom,sde-wb-size = <0x100>; + qcom,sde-dest-scaler-top-size = <0xc>; + qcom,sde-dest-scaler-size = <0x800>; + qcom,sde-len = <0x100>; + qcom,sde-wb-linewidth = <2560>; + qcom,sde-sspp-scale-size = <0x100>; + qcom,sde-mixer-blendstages = <0x8>; + qcom,sde-qseed-type = "qseedv2"; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-highest-bank-bit = <15>; + qcom,sde-has-mixer-gc; + qcom,sde-has-idle-pc; + qcom,fullsize-va-map; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-sspp-max-rects = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-smart-dma-priority = <0 0 0 0 + 0 0 0 0 + 0 0 + 1 2>; + qcom,sde-smart-dma-rev = "smart_dma_v2"; + qcom,sde-te-off = <0x100>; + qcom,sde-te2-off = <0x100>; + qcom,sde-te-size = <0xffff>; + qcom,sde-te2-size = <0xffff>; + + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + + qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff>; + qcom,sde-safe-lut-linear = <0 0xfff8>; + qcom,sde-safe-lut-macrotile = <0 0xf000>; + qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0xffff>; + + qcom,sde-qos-lut-linear = + <4 0x00000000 0x00000357>, + <5 0x00000000 0x00003357>, + <6 0x00000000 0x00023357>, + <7 0x00000000 0x00223357>, + <8 0x00000000 0x02223357>, + <9 0x00000000 0x22223357>, + <10 0x00000002 0x22223357>, + <11 0x00000022 0x22223357>, + <12 0x00000222 0x22223357>, + <13 0x00002222 0x22223357>, + <14 0x00012222 0x22223357>, + <0 0x00112222 0x22223357>; + qcom,sde-qos-lut-macrotile = + <10 0x00000003 0x44556677>, + <11 0x00000033 0x44556677>, + <12 0x00000233 0x44556677>, + <13 0x00002233 0x44556677>, + <14 0x00012233 0x44556677>, + <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = + <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = + <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = + <0 0x75300000 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-vbif-off = <0 0>; + qcom,sde-vbif-id = <0 1>; + qcom,sde-vbif-default-ot-rd-limit = <32>; + qcom,sde-vbif-default-ot-wr-limit = <16>; + qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <1>; + + qcom,sde-max-bw-high-kbps = <9000000>; + qcom,sde-max-bw-low-kbps = <9000000>; + + qcom,sde-core-ib-ff = "1.1"; + qcom,sde-core-clk-ff = "1.0"; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-undersized-prefill-lines = <4>; + qcom,sde-xtra-prefill-lines = <5>; + qcom,sde-dest-scale-prefill-lines = <6>; + qcom,sde-macrotile-prefill-lines = <7>; + qcom,sde-yuv-nv12-prefill-lines = <8>; + qcom,sde-linear-prefill-lines = <9>; + qcom,sde-downscaling-prefill-lines = <10>; + qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000 + 2400000 2400000 2400000 2400000>; + qcom,sde-amortizable-threshold = <11>; + qcom,sde-secure-sid-mask = <0x200801 0x200c01>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-broadcast-disabled = <0>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x320>; + qcom,sde-vig-qseed-off = <0x200>; + qcom,sde-vig-qseed-size = <0x74>; + /* Offset from vig top, version of HSIC */ + qcom,sde-vig-hsic = <0x200 0x00010000>; + qcom,sde-vig-memcolor = <0x200 0x00010000>; + qcom,sde-vig-pcc = <0x1780 0x00010000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + } + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + } + }; + + qcom,sde-sspp-rgb-blocks { + qcom,sde-rgb-scaler-off = <0x200>; + qcom,sde-rgb-scaler-size = <0x74>; + qcom,sde-rgb-pcc = <0x380 0x00010000>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00010000>; + qcom,sde-dspp-pcc = <0x1700 0x00010000>; + qcom,sde-dspp-gc = <0x17c0 0x00010000>; + qcom,sde-dspp-hsic = <0x0 0x00010000>; + qcom,sde-dspp-memcolor = <0x0 0x00010000>; + qcom,sde-dspp-sixzone = <0x0 0x00010000>; + qcom,sde-dspp-gamut = <0x1600 0x00010000>; + qcom,sde-dspp-dither = <0x0 0x00010000>; + qcom,sde-dspp-hist = <0x0 0x00010000>; + qcom,sde-dspp-vlut = <0x0 0x00010000>; + }; + + qcom,sde-mixer-blocks { + qcom,sde-mixer-gc = <0x3c0 0x00010000>; + }; + + qcom,msm-hdmi-audio-rx { + compatible = "qcom,msm-hdmi-audio-codec-rx"; + }; + + qcom,sde-inline-rotator = <&mdss_rotator 0>; + qcom,sde-inline-rot-xin = <10 11>; + qcom,sde-inline-rot-xin-type = "sspp", "wb"; + qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, <25 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <25 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>, + <25 512 0 6400000>; + }; + qcom,sde-llcc-bus { + qcom,msm-bus,name = "mdss_sde_llcc"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <132 770 0 0>, + <132 770 0 6400000>, + <132 770 0 6400000>; + }; + qcom,sde-ebi-bus { + qcom,msm-bus,name = "mdss_sde_ebi"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <129 512 0 0>, + <129 512 0 6400000>, + <129 512 0 6400000>; + }; + + qcom,sde-reg-bus { + /* Reg Bus Scale Settings */ + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 160000>, + <1 590 0 320000>; + }; + + smmu_kms_unsec: qcom,smmu_kms_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&mmss_smmu 0>; + }; + + smmu_kms_sec: qcom,smmu_kms_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&mmss_smmu 1>; + }; + }; diff --git a/display/dsi-panel-ext-bridge-1080p.dtsi b/display/dsi-panel-ext-bridge-1080p.dtsi new file mode 100644 index 000000000000..07d398e9e16c --- /dev/null +++ b/display/dsi-panel-ext-bridge-1080p.dtsi @@ -0,0 +1,46 @@ +&mdss_mdp { + dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p { + qcom,mdss-dsi-panel-name = "ext video mode dsi bridge"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x24>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,mdss-dsi-ext-bridge-mode; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <1080>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <148>; + qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <36>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <5>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; + }; +}; diff --git a/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi b/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi new file mode 100644 index 000000000000..9dc1a26207f3 --- /dev/null +++ b/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi @@ -0,0 +1,151 @@ +&mdss_mdp { + dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video { + qcom,mdss-dsi-panel-name = + "hx83112a video mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <65>; + qcom,mdss-pan-physical-height-dimension = <129>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <42>; + qcom,mdss-dsi-h-back-porch = <42>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <15>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <3>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 B9 83 11 2A + 39 01 00 00 00 00 09 B1 08 29 29 00 00 4F 54 + 33 + 39 01 00 00 00 00 11 B2 00 02 00 80 70 00 08 + 26 FC 01 00 03 15 A3 87 09 + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 03 D2 2C 2C + 39 01 00 00 00 00 1C B4 01 CE 01 CE 01 CE 0A + CE 0A CE 0A CE 00 FF 00 FF 00 00 22 23 00 + 28 0A 13 14 00 8A + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 0A B4 00 92 12 22 88 12 12 + 00 53 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 04 B6 82 82 E3 + 39 01 00 00 00 00 02 CC 08 + 39 01 00 00 00 00 2B D3 40 00 00 00 00 01 01 + 0A 0A 07 07 00 08 09 09 09 09 32 10 09 00 + 09 32 21 0A 00 0A 32 10 08 00 00 00 00 00 + 00 00 00 00 0B 08 82 + 39 01 00 00 00 00 02 BD 01 + 39 01 00 00 00 00 09 D3 00 00 19 00 00 0A 00 + 81 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18 + 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0 + 18 40 40 01 00 07 06 05 04 03 02 21 20 18 + 18 19 19 18 18 03 03 18 18 18 18 18 18 + 39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18 + 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0 + 18 40 40 02 03 04 05 06 07 00 01 20 21 18 + 18 18 18 19 19 20 20 18 18 18 18 18 18 + 39 01 00 00 00 00 19 D8 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 + 39 01 00 00 00 00 02 BD 01 + 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA + AA AA AA AA AA AA AA AA AA AA AA AA AA AA + AA AA AA + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 0D D8 AF FF FA AA BA AA AA + FF FA AA BA AA + 39 01 00 00 00 00 02 BD 03 + 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA + AA AA AA AA AA AA AA AA AA AA AA AA AA AA + AA AA AA + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 18 E7 0E 0E 1E 6A 1D 6A 00 + 32 02 02 00 00 02 02 02 05 14 14 32 B9 23 + B9 08 + 39 01 00 00 00 00 02 BD 01 + 39 01 00 00 00 00 0A E7 02 00 98 01 9A 0D A8 + 0E 01 + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 04 00 00 00 00 02 00 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 02 C1 01 + 39 01 00 00 00 00 02 BD 01 + 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 + C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 + 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 + 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 + C6 B8 9C 37 43 3D E5 00 + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 + C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 + 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 + 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 + C6 B8 9C 37 43 3D E5 00 + 39 01 00 00 00 00 02 BD 03 + 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 + C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 + 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 + 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 + C6 B8 9C 37 43 3D E5 00 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 02 E9 C3 + 39 01 00 00 00 00 03 CB 92 01 + 39 01 00 00 00 00 02 E9 3F + 39 01 00 00 00 00 07 C7 70 00 04 E0 33 00 + 39 01 00 00 00 00 03 51 0F FF + 39 01 00 00 00 00 02 53 24 + 39 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 96 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-hx8394d-720p-video.dtsi b/display/dsi-panel-hx8394d-720p-video.dtsi new file mode 100644 index 000000000000..6de6c6c4c859 --- /dev/null +++ b/display/dsi-panel-hx8394d-720p-video.dtsi @@ -0,0 +1,87 @@ +&mdss_mdp { + dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video { + qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <52>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <24>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 b9 ff 83 94 + 39 01 00 00 00 00 03 ba 33 83 + 39 01 00 00 00 00 10 b1 6c 12 12 + 37 04 11 f1 80 ec 94 23 80 c0 + d2 18 + 39 01 00 00 00 00 0c b2 00 64 0e + 0d 32 23 08 08 1c 4d 00 + 39 01 00 00 00 00 0d b4 00 ff 03 + 50 03 50 03 50 01 6a 01 6a + 39 01 00 00 00 00 02 bc 07 + 39 01 00 00 00 00 04 bf 41 0e 01 + 39 01 00 00 00 00 1f d3 00 07 00 + 00 00 10 00 32 10 05 00 00 32 + 10 00 00 00 32 10 00 00 00 36 + 03 09 09 37 00 00 37 + 39 01 00 00 00 00 2d d5 02 03 00 + 01 06 07 04 05 20 21 22 23 18 + 18 18 18 18 18 18 18 18 18 18 + 18 18 18 18 18 18 18 18 18 18 + 18 18 18 18 18 24 25 18 18 19 + 19 + 39 01 00 00 00 00 2d d6 05 04 07 + 06 01 00 03 02 23 22 21 20 18 + 18 18 18 18 18 58 58 18 18 18 + 18 18 18 18 18 18 18 18 18 18 + 18 18 18 18 18 25 24 19 19 18 + 18 + 39 01 00 00 00 00 02 cc 09 + 39 01 00 00 00 00 03 c0 30 14 + 39 01 00 00 00 00 05 c7 00 c0 40 c0 + 39 01 00 00 00 00 03 b6 43 43 + 05 01 00 00 c8 00 02 11 00 + 05 01 00 00 0a 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [ + 79 1a 12 00 3e 42 + 16 1e 15 03 04 00 + ]; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>; + qcom,mdss-pan-physical-width-dimension = <59>; + qcom,mdss-pan-physical-height-dimension = <104>; + + }; +}; diff --git a/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi b/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi new file mode 100644 index 000000000000..8a05258d0e43 --- /dev/null +++ b/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi @@ -0,0 +1,240 @@ +&mdss_mdp { + dsi_nt35597_truly_dsc_cmd: qcom,mdss_dsi_nt35597_dsc_cmd_truly { + qcom,mdss-dsi-panel-name = + "nt35597 cmd mode dsi truly panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x1 0x1>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f ae + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6D + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c D8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 C0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi new file mode 100644 index 000000000000..2d888cbce876 --- /dev/null +++ b/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi @@ -0,0 +1,226 @@ +&mdss_mdp { + dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_video_truly { + qcom,mdss-dsi-panel-name = + "nt35597 video mode dsi truly panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + qcom,mdss-dsi-dma-schedule-line = <5>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x00(2 Port SDC); + * 0x01(1 PortA FBC); + * 0x02(MTK); 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 39 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 03 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi new file mode 100644 index 000000000000..cddf9165ff1f --- /dev/null +++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi @@ -0,0 +1,219 @@ +&mdss_mdp { + dsi_dual_nt35597_truly_cmd: qcom,mdss_dsi_nt35597_truly_wqxga_cmd { + qcom,mdss-dsi-panel-name = + "Dual nt35597 cmd mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-jitter = <0x1 0x1>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi new file mode 100644 index 000000000000..aff695014114 --- /dev/null +++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi @@ -0,0 +1,206 @@ +&mdss_mdp { + dsi_dual_nt35597_truly_video: qcom,mdss_dsi_nt35597_wqxga_video_truly { + qcom,mdss-dsi-panel-name = + "Dual nt35597 video mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-underflow-color = <0x3ff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-bpp = <24>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 FF 24 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 FF 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 03 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi b/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi new file mode 100644 index 000000000000..ffefa6a671d6 --- /dev/null +++ b/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi @@ -0,0 +1,185 @@ +&mdss_mdp { + dsi_nt35695b_truly_fhd_cmd: qcom,mdss_dsi_nt35695b_truly_fhd_cmd { + qcom,mdss-dsi-panel-name = + "nt35695b truly fhd command mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [15 01 00 00 10 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 03 55 + 15 01 00 00 00 00 02 05 50 + 15 01 00 00 00 00 02 06 a8 + 15 01 00 00 00 00 02 07 ad + 15 01 00 00 00 00 02 08 0c + 15 01 00 00 00 00 02 0b aa + 15 01 00 00 00 00 02 0c aa + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f b3 + 15 01 00 00 00 00 02 11 28 + 15 01 00 00 00 00 02 12 10 + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 4a + 15 01 00 00 00 00 02 15 12 + 15 01 00 00 00 00 02 16 12 + 15 01 00 00 00 00 02 30 01 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 58 82 + 15 01 00 00 00 00 02 59 00 + 15 01 00 00 00 00 02 5a 02 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5c 82 + 15 01 00 00 00 00 02 5d 80 + 15 01 00 00 00 00 02 5e 02 + 15 01 00 00 00 00 02 5f 00 + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 89 + 15 01 00 00 00 00 02 04 8a + 15 01 00 00 00 00 02 05 0f + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 1c + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 00 + 15 01 00 00 00 00 02 0c 00 + 15 01 00 00 00 00 02 0d 13 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 01 + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 89 + 15 01 00 00 00 00 02 14 8a + 15 01 00 00 00 00 02 15 0f + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 1c + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 00 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 13 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 17 + 15 01 00 00 00 00 02 20 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 55 25 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 93 06 + 15 01 00 00 00 00 02 94 06 + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b 0f + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + 15 01 00 00 00 00 02 b6 21 + 15 01 00 00 00 00 02 b7 22 + 15 01 00 00 00 00 02 b8 07 + 15 01 00 00 00 00 02 b9 07 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bd 20 + 15 01 00 00 00 00 02 be 07 + 15 01 00 00 00 00 02 bf 07 + 15 01 00 00 00 00 02 c1 6d + 15 01 00 00 00 00 02 c4 24 + 15 01 00 00 00 00 02 e3 00 + 15 01 00 00 00 00 02 ec 00 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 + 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt35695b-truly-fhd-video.dtsi b/display/dsi-panel-nt35695b-truly-fhd-video.dtsi new file mode 100644 index 000000000000..fe84525de197 --- /dev/null +++ b/display/dsi-panel-nt35695b-truly-fhd-video.dtsi @@ -0,0 +1,177 @@ +&mdss_mdp { + dsi_nt35695b_truly_fhd_video: qcom,mdss_dsi_nt35695b_truly_fhd_video { + qcom,mdss-dsi-panel-name = + "nt35695b truly fhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = + [15 01 00 00 10 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 03 55 + 15 01 00 00 00 00 02 05 50 + 15 01 00 00 00 00 02 06 a8 + 15 01 00 00 00 00 02 07 ad + 15 01 00 00 00 00 02 08 0c + 15 01 00 00 00 00 02 0b aa + 15 01 00 00 00 00 02 0c aa + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f b3 + 15 01 00 00 00 00 02 11 28 + 15 01 00 00 00 00 02 12 10 + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 4a + 15 01 00 00 00 00 02 15 12 + 15 01 00 00 00 00 02 16 12 + 15 01 00 00 00 00 02 30 01 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 58 82 + 15 01 00 00 00 00 02 59 00 + 15 01 00 00 00 00 02 5a 02 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5c 82 + 15 01 00 00 00 00 02 5d 80 + 15 01 00 00 00 00 02 5e 02 + 15 01 00 00 00 00 02 5f 00 + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 89 + 15 01 00 00 00 00 02 04 8a + 15 01 00 00 00 00 02 05 0f + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 1c + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 00 + 15 01 00 00 00 00 02 0c 00 + 15 01 00 00 00 00 02 0d 13 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 01 + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 89 + 15 01 00 00 00 00 02 14 8a + 15 01 00 00 00 00 02 15 0f + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 1c + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 00 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 13 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 17 + 15 01 00 00 00 00 02 20 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 55 25 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 93 06 + 15 01 00 00 00 00 02 94 06 + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b 0f + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + 15 01 00 00 00 00 02 b6 21 + 15 01 00 00 00 00 02 b7 22 + 15 01 00 00 00 00 02 b8 07 + 15 01 00 00 00 00 02 b9 07 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bd 20 + 15 01 00 00 00 00 02 be 07 + 15 01 00 00 00 00 02 bf 07 + 15 01 00 00 00 00 02 c1 6d + 15 01 00 00 00 00 02 c4 24 + 15 01 00 00 00 00 02 e3 00 + 15 01 00 00 00 00 02 ec 00 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bb 03 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 + 14 00 02 28 00 05 01 00 00 78 00 + 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi b/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi new file mode 100644 index 000000000000..d066925a86f2 --- /dev/null +++ b/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi @@ -0,0 +1,80 @@ +&mdss_mdp { + dsi_dual_nt36850_truly_cmd: qcom,mdss_dsi_nt36850_truly_wqhd_cmd { + qcom,mdss-dsi-panel-name = + "Dual nt36850 cmd mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 50>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <140>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 03 e8 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 2c + 15 01 00 00 00 00 02 55 01 + 05 01 00 00 0a 00 02 20 00 + 15 01 00 00 00 00 02 bb 10 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi b/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi new file mode 100644 index 000000000000..11eb3a30d232 --- /dev/null +++ b/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi @@ -0,0 +1,129 @@ +&mdss_mdp { + dsi_dual_s6e3ha3_amoled_cmd: qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd { + qcom,mdss-dsi-panel-name = + "Dual s6e3ha3 amoled cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <31>; + qcom,mdss-dsi-v-front-porch = <30>; + qcom,mdss-dsi-v-pulse-width = <8>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00 + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 09 ff + 39 01 00 00 00 00 03 f0 5a 5a + 39 01 00 00 00 00 02 b0 10 + 39 01 00 00 00 00 02 b5 a0 + 39 01 00 00 00 00 02 c4 03 + 39 01 00 00 00 00 0a + f6 42 57 37 00 aa cc d0 00 00 + 39 01 00 00 00 00 02 f9 03 + 39 01 00 00 00 00 14 + c2 00 00 d8 d8 00 80 2b 05 08 + 0e 07 0b 05 0d 0a 15 13 20 1e + 39 01 00 00 78 00 03 f0 a5 a5 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 02 51 60 + 05 01 00 00 05 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00 + 05 01 00 00 b4 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a + 39 00 00 00 05 00 03 f1 5a 5a + 39 00 00 00 05 00 03 fc 5a 5a + 39 00 00 00 05 00 02 b0 17 + 39 00 00 00 05 00 02 cb 10 + 39 00 00 00 05 00 02 b0 2d + 39 00 00 00 05 00 02 cb cd + 39 00 00 00 05 00 02 b0 0e + 39 00 00 00 05 00 02 cb 02 + 39 00 00 00 05 00 02 b0 0f + 39 00 00 00 05 00 02 cb 09 + 39 00 00 00 05 00 02 b0 02 + 39 00 00 00 05 00 02 f2 c9 + 39 00 00 00 05 00 02 b0 03 + 39 00 00 00 05 00 02 f2 c0 + 39 00 00 00 05 00 02 b0 03 + 39 00 00 00 05 00 02 f4 aa + 39 00 00 00 05 00 02 b0 08 + 39 00 00 00 05 00 02 b1 30 + 39 00 00 00 05 00 02 b0 09 + 39 00 00 00 05 00 02 b1 0a + 39 00 00 00 05 00 02 b0 0d + 39 00 00 00 05 00 02 b1 10 + 39 00 00 00 05 00 02 b0 00 + 39 00 00 00 05 00 02 f7 03 + 39 00 00 00 05 00 02 fe 30 + 39 01 00 00 05 00 02 fe b0]; + qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a + 39 00 00 00 05 00 03 f1 5a 5a + 39 00 00 00 05 00 03 fc 5a 5a + 39 00 00 00 05 00 02 b0 2d + 39 00 00 00 05 00 02 cb 4d + 39 00 00 00 05 00 02 b0 17 + 39 00 00 00 05 00 02 cb 04 + 39 00 00 00 05 00 02 b0 0e + 39 00 00 00 05 00 02 cb 06 + 39 00 00 00 05 00 02 b0 0f + 39 00 00 00 05 00 02 cb 05 + 39 00 00 00 05 00 02 b0 02 + 39 00 00 00 05 00 02 f2 b8 + 39 00 00 00 05 00 02 b0 03 + 39 00 00 00 05 00 02 f2 80 + 39 00 00 00 05 00 02 b0 03 + 39 00 00 00 05 00 02 f4 8a + 39 00 00 00 05 00 02 b0 08 + 39 00 00 00 05 00 02 b1 10 + 39 00 00 00 05 00 02 b0 09 + 39 00 00 00 05 00 02 b1 0a + 39 00 00 00 05 00 02 b0 0d + 39 00 00 00 05 00 02 b1 80 + 39 00 00 00 05 00 02 b0 00 + 39 00 00 00 05 00 02 f7 03 + 39 00 00 00 05 00 02 fe 30 + 39 01 00 00 05 00 02 fe b0]; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <122>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + }; +}; diff --git a/display/dsi-panel-sharp-1080p-cmd.dtsi b/display/dsi-panel-sharp-1080p-cmd.dtsi new file mode 100644 index 000000000000..8ffa0eb7749d --- /dev/null +++ b/display/dsi-panel-sharp-1080p-cmd.dtsi @@ -0,0 +1,79 @@ +&mdss_mdp { + dsi_sharp_1080_cmd: qcom,mdss_dsi_sharp_1080p_cmd { + qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,mdss-dsi-panel-clockrate = <850000000>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <64>; + qcom,mdss-pan-physical-height-dimension = <117>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi new file mode 100644 index 000000000000..89df5ffd4029 --- /dev/null +++ b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi @@ -0,0 +1,96 @@ +&mdss_mdp { + dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <129>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-dsc-4k-video.dtsi b/display/dsi-panel-sharp-dsc-4k-video.dtsi new file mode 100644 index 000000000000..feb55406288c --- /dev/null +++ b/display/dsi-panel-sharp-dsc-4k-video.dtsi @@ -0,0 +1,89 @@ +&mdss_mdp { + dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <129>; + qcom,mdss-dsi-tx-eot-append; + + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 10 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi b/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi new file mode 100644 index 000000000000..c909864db377 --- /dev/null +++ b/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi @@ -0,0 +1,86 @@ +&mdss_mdp { + dsi_dual_sharp_wqhd_cmd: qcom,mdss_dsi_sharp_wqhd_cmd { + qcom,mdss-dsi-panel-name = + "Dual Sharp WQHD cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <121>; + + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 + 20 00 20 02 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 15 01 00 00 00 00 02 90 01 + 15 01 00 00 00 00 02 03 00 + 15 01 00 00 00 00 02 58 01 + 15 01 00 00 00 00 02 c9 00 + 15 01 00 00 00 00 02 c0 15 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi b/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi new file mode 100644 index 000000000000..37330078b1ff --- /dev/null +++ b/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi @@ -0,0 +1,82 @@ +&mdss_mdp { + dsi_dual_sharp_wqhd_video: qcom,mdss_dsi_sharp_wqhd_video { + qcom,mdss-dsi-panel-name = + "Dual Sharp wqhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <121>; + + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 + 20 00 20 02 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 10 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 15 01 00 00 00 00 02 90 01 + 15 01 00 00 00 00 02 03 00 + 15 01 00 00 00 00 02 58 01 + 15 01 00 00 00 00 02 c9 00 + 15 01 00 00 00 00 02 c0 15 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + }; + }; + }; +}; + diff --git a/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi b/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi new file mode 100644 index 000000000000..06a95cadbd58 --- /dev/null +++ b/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi @@ -0,0 +1,626 @@ +&mdss_mdp { + dsi_dual_sharp_1080_120hz_cmd: qcom,mdss_dual_sharp_1080p_120hz_cmd { + qcom,mdss-dsi-panel-name = + "sharp 1080p 120hz dual dsi cmd mode panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 10>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,cmd-sync-wait-trigger; + qcom,mdss-tear-check-frame-rate = <12000>; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <28>; + qcom,mdss-dsi-h-back-porch = <4>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = + [15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 ba 07 + 15 01 00 00 00 00 02 c0 00 + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 d9 00 + 15 01 00 00 00 00 02 ef 70 + 15 01 00 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00 02 c8 c4 + 15 01 00 00 00 00 02 c9 02 + 15 01 00 00 00 00 02 ca 0d + 15 01 00 00 00 00 02 cb 02 + 15 01 00 00 00 00 02 cc 4a + 15 01 00 00 00 00 02 cd 02 + 15 01 00 00 00 00 02 ce 4c + 15 01 00 00 00 00 02 cf 02 + 15 01 00 00 00 00 02 d0 85 + 15 01 00 00 00 00 02 d1 02 + 15 01 00 00 00 00 02 d2 c3 + 15 01 00 00 00 00 02 d3 02 + 15 01 00 00 00 00 02 d4 e9 + 15 01 00 00 00 00 02 d5 03 + 15 01 00 00 00 00 02 d6 16 + 15 01 00 00 00 00 02 d7 03 + 15 01 00 00 00 00 02 d8 34 + 15 01 00 00 00 00 02 d9 03 + 15 01 00 00 00 00 02 da 56 + 15 01 00 00 00 00 02 db 03 + 15 01 00 00 00 00 02 dc 62 + 15 01 00 00 00 00 02 dd 03 + 15 01 00 00 00 00 02 de 6c + 15 01 00 00 00 00 02 df 03 + 15 01 00 00 00 00 02 e0 74 + 15 01 00 00 00 00 02 e1 03 + 15 01 00 00 00 00 02 e2 80 + 15 01 00 00 00 00 02 e3 03 + 15 01 00 00 00 00 02 e4 89 + 15 01 00 00 00 00 02 e5 03 + 15 01 00 00 00 00 02 e6 8b + 15 01 00 00 00 00 02 e7 03 + 15 01 00 00 00 00 02 e8 8d + 15 01 00 00 00 00 02 e9 03 + 15 01 00 00 00 00 02 ea 8e + 15 01 00 00 00 00 02 FF 10 + 05 01 00 00 00 00 01 29]; + qcom,mdss-dsi-off-command = + [15 01 00 00 00 00 02 ff 10 + 05 01 00 00 10 00 01 28 + 15 01 00 00 00 00 02 b0 00 + 05 01 00 00 40 00 01 10 + 15 01 00 00 00 00 02 4f 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-cmd.dtsi b/display/dsi-panel-sim-cmd.dtsi new file mode 100644 index 000000000000..f62ce3b9d7b5 --- /dev/null +++ b/display/dsi-panel-sim-cmd.dtsi @@ -0,0 +1,347 @@ +&mdss_mdp { + dsi_sim_cmd: qcom,mdss_dsi_sim_cmd { + qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-mode-switch; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,cmd-to-video-mode-switch-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + 15 01 00 00 00 00 02 3d 10 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 55 0c + ]; + qcom,cmd-to-video-mode-switch-commands-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,video-to-cmd-mode-switch-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + 15 01 00 00 00 00 02 3d 11 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 55 0b + ]; + qcom,video-to-cmd-mode-switch-commands-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <740>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <840>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <1380>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi new file mode 100644 index 000000000000..310ce40cd902 --- /dev/null +++ b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi @@ -0,0 +1,474 @@ +&mdss_mdp { + dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-panel-name = + "Simulator cmd mode DSC3:1 10bit dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dsc375-cmd.dtsi b/display/dsi-panel-sim-dsc375-cmd.dtsi new file mode 100644 index 000000000000..ef40a2e7b3e6 --- /dev/null +++ b/display/dsi-panel-sim-dsc375-cmd.dtsi @@ -0,0 +1,280 @@ +&mdss_mdp { + dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = + "Simulator cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dualmipi-cmd.dtsi b/display/dsi-panel-sim-dualmipi-cmd.dtsi new file mode 100644 index 000000000000..5f4be88fb88f --- /dev/null +++ b/display/dsi-panel-sim-dualmipi-cmd.dtsi @@ -0,0 +1,141 @@ +&mdss_mdp { + dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd { + qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0 40 256>, + <40 120 128>, + <120 240 64>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + qcom,mdss-dsi-qsync-min-refresh-rate = <45>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <28>; + qcom,mdss-dsi-h-back-porch = <4>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = + [/* exit sleep mode, wait 0ms */ + 05 01 00 00 00 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [/* exit sleep mode, wait 0ms */ + 05 01 00 00 00 00 01 29]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-on-command = + [/* exit sleep mode, wait 0ms */ + 05 01 00 00 00 00 01 29]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi new file mode 100644 index 000000000000..87b4a76a3a96 --- /dev/null +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -0,0 +1,327 @@ +&mdss_mdp { + dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = + "Sim dual cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0 40 256>, + <40 120 128>, + <120 240 64>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <2520>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <1080>; + qcom,mdss-dsc-slice-width = <1260>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dualmipi-video.dtsi b/display/dsi-panel-sim-dualmipi-video.dtsi new file mode 100644 index 000000000000..3bee9f6f104d --- /dev/null +++ b/display/dsi-panel-sim-dualmipi-video.dtsi @@ -0,0 +1,63 @@ +&mdss_mdp { + dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video { + qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-panel-broadcast-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>; + qcom,panel-ack-disabled; + qcom,mdss-dsi-qsync-min-refresh-rate = <45>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-sec-hd-cmd.dtsi b/display/dsi-panel-sim-sec-hd-cmd.dtsi new file mode 100644 index 000000000000..e9d31359ed5b --- /dev/null +++ b/display/dsi-panel-sim-sec-hd-cmd.dtsi @@ -0,0 +1,68 @@ +&mdss_mdp { + dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-panel-name = + "sim hd command mode secondary dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,panel-ack-disabled; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-video.dtsi b/display/dsi-panel-sim-video.dtsi new file mode 100644 index 000000000000..5a2ac01716d3 --- /dev/null +++ b/display/dsi-panel-sim-video.dtsi @@ -0,0 +1,62 @@ +&mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <640>; + qcom,mdss-dsi-panel-height = <480>; + qcom,mdss-dsi-h-front-porch = <8>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 00 00 00 00 00 00 00 00 00 00 00]; + qcom,mdss-dsi-on-command = + [32 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-off-command = + [22 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi new file mode 100644 index 000000000000..6195f8c82a53 --- /dev/null +++ b/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi @@ -0,0 +1,103 @@ +&mdss_mdp { + dsi_sw43404_amoled_fhd_plus_cmd: qcom,mdss_dsi_sw43404_fhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "sw43404 amoled boe fhd+ panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <138>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <160>; + qcom,mdss-dsi-h-back-porch = <72>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 0a 01 00 00 00 00 80 11 00 00 89 30 80 + 08 70 04 38 02 1c 02 1c 02 1c 02 00 + 02 0e 00 20 34 29 00 07 00 0C 00 2e + 00 31 18 00 10 F0 03 0C 20 00 06 0B + 0B 33 0E 1C 2A 38 46 54 62 69 70 77 + 79 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 + 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 39 01 00 00 00 00 03 b0 a5 00 + 15 01 00 00 00 00 02 5e 10 + 39 01 00 00 00 00 06 b9 bf 11 40 00 30 + 39 01 00 00 00 00 09 F8 00 08 10 08 2D + 00 00 2D + 15 01 00 00 00 00 02 55 08 + 05 01 00 00 1e 00 02 11 00 + 15 01 00 00 78 00 02 3d 01 + 39 01 00 00 00 00 03 b0 a5 00 + 05 01 00 00 78 00 02 35 00 + 05 01 00 00 3c 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <270>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi new file mode 100644 index 000000000000..032fc39b91bf --- /dev/null +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi @@ -0,0 +1,121 @@ +&mdss_mdp { + dsi_sw43404_amoled_cmd: qcom,mdss_dsi_sw43404_amoled_wqhd_cmd { + qcom,mdss-dsi-panel-name = + "sw43404 amoled cmd mode dsi boe panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-qsync-min-refresh-rate = <55>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2880>; + qcom,mdss-dsi-h-front-porch = <60>; + qcom,mdss-dsi-h-back-porch = <30>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 03 5c 42 00 + 07 01 00 00 00 00 02 01 00 + 0a 01 00 00 00 00 80 11 00 00 89 30 80 + 0B 40 05 A0 05 A0 02 D0 02 D0 02 00 + 02 68 00 20 9A DB 00 0A 00 0C 00 12 + 00 0E 18 00 10 F0 03 0C 20 00 06 0B + 0B 33 0E 1C 2A 38 46 54 62 69 70 77 + 79 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 + 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 09 F8 00 08 10 08 2D + 00 00 2D + 15 01 00 00 00 00 02 55 08 + 05 01 00 00 1e 00 02 11 00 + 39 01 00 00 00 00 03 b0 a5 00 + 15 01 00 00 00 00 02 e0 18 + 39 01 00 00 00 00 0c c0 00 53 6f 51 50 + 51 34 4f 5a 33 19 + 05 01 00 00 78 00 02 35 00 + 05 01 00 00 3c 00 02 29 00 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 5a 01]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 5a 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-lp1-command = [ + 05 01 00 00 00 00 02 39 00 + ]; + qcom,mdss-dsi-lp1-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 00 00 02 38 00 + ]; + qcom,mdss-dsi-nolp-command-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <180>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi new file mode 100644 index 000000000000..37c0dfcd7d75 --- /dev/null +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi @@ -0,0 +1,101 @@ +&mdss_mdp { + dsi_sw43404_amoled_video: qcom,mdss_dsi_sw43404_amoled_wqhd_video { + qcom,mdss-dsi-panel-name = + "sw43404 amoled video mode dsi boe panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2880>; + qcom,mdss-dsi-h-front-porch = <10>; + qcom,mdss-dsi-h-back-porch = <10>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + 15 01 00 00 00 00 02 3d 10 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 55 08 + 39 01 00 00 00 00 09 f8 00 08 10 08 2d + 00 00 2d + 39 01 00 00 3c 00 03 51 00 00 + 05 01 00 00 50 00 02 11 00 + 39 01 00 00 00 00 03 b0 34 04 + 39 01 00 00 00 00 05 c1 00 00 00 46 + 39 01 00 00 00 00 03 b0 a5 00 + 0a 01 00 00 00 00 80 11 00 00 89 30 80 + 0B 40 05 A0 02 d0 02 D0 02 D0 02 00 + 02 68 00 20 4e a8 00 0A 00 0C 00 23 + 00 1c 18 00 10 F0 03 0C 20 00 06 0B + 0B 33 0E 1C 2A 38 46 54 62 69 70 77 + 79 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 + 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 39 01 00 00 00 00 03 b0 a5 00 + 15 01 00 00 00 00 02 e0 18 + 39 01 00 00 00 00 0c c0 00 53 6f 51 50 + 51 34 4f 5a 33 19 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-lp1-command = [ + 05 01 00 00 00 00 02 39 00 + ]; + qcom,mdss-dsi-lp1-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 00 00 02 38 00 + ]; + qcom,mdss-dsi-nolp-command-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <180>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-td4328-1080p-cmd.dtsi b/display/dsi-panel-td4328-1080p-cmd.dtsi new file mode 100644 index 000000000000..476c34c01d34 --- /dev/null +++ b/display/dsi-panel-td4328-1080p-cmd.dtsi @@ -0,0 +1,169 @@ +&mdss_mdp { + dsi_td4328_truly_cmd: qcom,mdss_dsi_td4328_truly_cmd { + qcom,mdss-dsi-panel-name = + "td4328 cmd mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <70>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <5>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 04 B3 00 00 06 + 29 01 00 00 00 00 02 B4 00 + 29 01 00 00 00 00 06 B6 33 DB 80 12 00 + 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A + 50 50 + 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14 + C8 C8 + 29 01 00 00 00 00 08 BA B5 33 41 64 23 + A0 A0 + 29 01 00 00 00 00 03 BB 14 14 + 29 01 00 00 00 00 03 BC 37 32 + 29 01 00 00 00 00 03 BD 64 32 + 29 01 00 00 00 00 02 BE 04 + 29 01 00 00 00 00 02 C0 00 + 29 01 00 00 00 00 2E C1 04 48 00 00 26 + 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C + 6B 93 4D 22 18 8B 2A 41 00 00 00 00 + 00 00 00 00 00 40 02 22 1B 06 03 00 + 07 FF 00 01 + 29 01 00 00 00 00 18 C2 01 F8 70 08 68 + 08 0C 10 00 08 30 00 00 00 00 00 00 + 20 02 43 00 00 00 + 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0 + 00 00 00 00 00 00 04 3A 00 00 00 04 + 44 00 00 01 01 03 28 00 01 00 01 00 + 00 19 00 0C 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 32 00 19 00 5A + 02 32 00 19 00 5A 02 40 00 + 29 01 00 00 00 00 15 C4 70 00 00 00 11 + 11 00 00 00 02 02 31 01 00 00 00 02 + 01 01 01 + 29 01 00 00 00 00 08 C5 08 00 00 00 00 + 70 00 + 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54 + 07 54 01 02 01 02 07 07 00 00 07 07 + 0F 11 07 5B 00 5B 5B C2 C2 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F + 5A 71 80 8B 95 45 4F 5C 71 7B 88 98 + A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95 + 45 4F 5C 71 7B 88 98 A6 BE + 29 01 00 00 00 00 38 C8 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 14 C9 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 2C CA 1C FC FC FC 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 1C CB FF FF FF FF 0F + 00 08 00 01 00 31 F0 40 08 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 CC 02 + 29 01 00 00 00 00 27 CD 10 80 37 C0 1A + 00 5C 02 19 90 11 88 D8 6C D8 6C 01 + 00 00 00 32 00 32 00 5D 02 32 32 01 + 33 00 33 00 5E 02 32 32 AF + 29 01 00 00 00 00 1A CE 5D 40 49 53 59 + 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF + 04 00 04 04 42 00 69 5A + 29 01 00 00 00 00 03 CF 4A 1D + 29 01 00 00 00 00 12 D0 33 57 D4 31 01 + 10 10 10 19 19 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 D1 00 + 29 01 00 00 00 00 20 D2 10 00 00 10 75 + 0F 03 25 20 00 00 00 00 00 00 00 00 + 04 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 17 D3 1B 3B BB 77 77 + 77 BB B3 33 00 00 6D 6E C7 C7 33 BB + F2 FD C6 0B 07 + 29 01 00 00 00 00 08 D4 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 08 D5 03 00 00 02 2B + 02 2B + 29 01 00 00 00 00 02 D6 01 + 29 01 00 00 00 00 22 D7 F6 FF 03 05 41 + 24 80 1F C7 1F 1B 00 0C 07 20 00 00 + 00 00 00 0C 00 1F 00 FC 00 00 AA 67 + 7E 5D 06 00 + 29 01 00 00 00 00 03 D9 20 14 + 29 01 00 00 00 00 05 DD 30 06 23 65 + 29 01 00 00 00 00 05 DE 00 3F FF 50 + 29 01 00 00 00 00 06 E7 00 00 00 46 61 + 29 01 00 00 00 00 02 EA 1F + 29 01 00 00 00 00 04 EE 41 51 00 + 29 01 00 00 00 00 03 F1 00 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 08 6F + 39 01 00 00 00 00 01 2C + 29 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 96 00 01 11 + 05 01 00 00 32 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-td4328-1080p-video.dtsi b/display/dsi-panel-td4328-1080p-video.dtsi new file mode 100644 index 000000000000..e9b7bac34504 --- /dev/null +++ b/display/dsi-panel-td4328-1080p-video.dtsi @@ -0,0 +1,164 @@ +&mdss_mdp { + dsi_td4328_truly_video: qcom,mdss_dsi_td4328_truly_video { + qcom,mdss-dsi-panel-name = + "td4328 video mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <70>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <5>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 04 B3 31 00 06 + 29 01 00 00 00 00 02 B4 00 + 29 01 00 00 00 00 06 B6 33 DB 80 12 00 + 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A + 50 50 + 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14 + C8 C8 + 29 01 00 00 00 00 08 BA B5 33 41 64 23 + A0 A0 + 29 01 00 00 00 00 03 BB 14 14 + 29 01 00 00 00 00 03 BC 37 32 + 29 01 00 00 00 00 03 BD 64 32 + 29 01 00 00 00 00 02 BE 04 + 29 01 00 00 00 00 02 C0 00 + 29 01 00 00 00 00 2E C1 04 48 00 00 26 + 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C + 6B 93 4D 22 18 8B 2A 41 00 00 00 00 + 00 00 00 00 00 40 02 22 1B 06 03 00 + 07 FF 00 01 + 29 01 00 00 00 00 18 C2 01 F8 70 08 68 + 08 0C 10 00 08 30 00 00 00 00 00 00 + 20 02 43 00 00 00 + 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0 + 00 00 00 00 00 00 04 3A 00 00 00 04 + 44 00 00 01 01 03 28 00 01 00 01 00 + 00 19 00 0C 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 32 00 19 00 5A + 02 32 00 19 00 5A 02 40 00 + 29 01 00 00 00 00 15 C4 70 00 00 00 11 + 11 00 00 00 02 02 31 01 00 00 00 02 + 01 01 01 + 29 01 00 00 00 00 08 C5 08 00 00 00 00 + 70 00 + 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54 + 07 54 01 02 01 02 07 07 00 00 07 07 + 0F 11 07 5B 00 5B 5B C2 C2 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F + 5A 71 80 8B 95 45 4F 5C 71 7B 88 98 + A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95 + 45 4F 5C 71 7B 88 98 A6 BE + 29 01 00 00 00 00 38 C8 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 14 C9 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 2C CA 1C FC FC FC 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 1C CB FF FF FF FF 0F + 00 08 00 01 00 31 F0 40 08 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 CC 02 + 29 01 00 00 00 00 27 CD 10 80 37 C0 1A + 00 5C 02 19 90 11 88 D8 6C D8 6C 01 + 00 00 00 32 00 32 00 5D 02 32 32 01 + 33 00 33 00 5E 02 32 32 AF + 29 01 00 00 00 00 1A CE 5D 40 49 53 59 + 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF + 04 00 04 04 42 00 69 5A + 29 01 00 00 00 00 03 CF 4A 1D + 29 01 00 00 00 00 12 D0 33 57 D4 31 01 + 10 10 10 19 19 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 D1 00 + 29 01 00 00 00 00 20 D2 10 00 00 10 75 + 0F 03 25 20 00 00 00 00 00 00 00 00 + 04 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 17 D3 1B 3B BB 77 77 + 77 BB B3 33 00 00 6D 6E DB DB 33 BB + F2 FD C6 0B 07 + 29 01 00 00 00 00 08 D4 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 08 D5 03 00 00 02 40 + 02 40 + 29 01 00 00 00 00 02 D6 01 + 29 01 00 00 00 00 22 D7 F6 FF 03 05 41 + 24 80 1F C7 1F 1B 00 0C 07 20 00 00 + 00 00 00 0C 00 1F 00 FC 00 00 AA 67 + 7E 5D 06 00 + 29 01 00 00 00 00 03 D9 20 14 + 29 01 00 00 00 00 05 DD 30 06 23 65 + 29 01 00 00 00 00 05 DE 00 3F FF 90 + 29 01 00 00 00 00 06 E7 00 00 00 46 61 + 29 01 00 00 00 00 02 EA 1F + 29 01 00 00 00 00 04 EE 41 51 00 + 29 01 00 00 00 00 03 F1 00 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 08 6F + 39 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 05 01 00 00 96 00 01 11 + 05 01 00 00 32 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/kona-sde-display-cdp-lcd.dtsi b/display/kona-sde-display-cdp-lcd.dtsi new file mode 100644 index 000000000000..a7d85dfd9194 --- /dev/null +++ b/display/kona-sde-display-cdp-lcd.dtsi @@ -0,0 +1,36 @@ +&dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sharp_1080_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&sde_dsi { + /delete-property/ avdd-supply; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>; +}; diff --git a/display/kona-sde-display-cdp.dtsi b/display/kona-sde-display-cdp.dtsi new file mode 100644 index 000000000000..fadbce641428 --- /dev/null +++ b/display/kona-sde-display-cdp.dtsi @@ -0,0 +1,152 @@ +#include "kona-sde-display.dtsi" + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-en-gpio = <&tlmm 60 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-en-gpio = <&tlmm 60 0>; +}; + +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-sec-reset-gpio = <&tlmm 128 0>; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-sec-reset-gpio = <&tlmm 128 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; +}; diff --git a/display/kona-sde-display-mtp.dtsi b/display/kona-sde-display-mtp.dtsi new file mode 100644 index 000000000000..b81aad8801d0 --- /dev/null +++ b/display/kona-sde-display-mtp.dtsi @@ -0,0 +1,87 @@ +#include "kona-sde-display.dtsi" + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-sec-reset-gpio = <&tlmm 128 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; +}; diff --git a/display/kona-sde-display-qrd.dtsi b/display/kona-sde-display-qrd.dtsi new file mode 100644 index 000000000000..1f6e32ac60f8 --- /dev/null +++ b/display/kona-sde-display-qrd.dtsi @@ -0,0 +1,76 @@ +#include "kona-sde-display.dtsi" + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; +}; diff --git a/display/kona-sde-display-rumi.dtsi b/display/kona-sde-display-rumi.dtsi new file mode 100644 index 000000000000..3eb83e40a9c0 --- /dev/null +++ b/display/kona-sde-display-rumi.dtsi @@ -0,0 +1 @@ +#include "kona-sde-display.dtsi" diff --git a/display/kona-sde-display.dtsi b/display/kona-sde-display.dtsi new file mode 100644 index 000000000000..6257b55c4e1d --- /dev/null +++ b/display/kona-sde-display.dtsi @@ -0,0 +1,528 @@ +#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-1080p-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include + +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3300000>; + qcom,supply-max-voltage = <3300000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + }; + + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + + display_panel_avdd: display_gpio_regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 61 0>; + enable-active-high; + regulator-boot-on; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "src_byte_clk0", "src_pixel_clk0", + "src_byte_clk1", "src_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&pm8150_l14>; + vdd-supply = <&pm8150a_l11>; + avdd-supply = <&display_panel_avdd>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "src_byte_clk0", "src_pixel_clk0", + "src_byte_clk1", "src_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 67 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&pm8150_l14>; + vdd-supply = <&pm8150a_l11>; + avdd-supply = <&display_panel_avdd>; + + qcom,mdp = <&mdss_mdp>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dp { + qcom,dp-usbpd-detection = <&pm8150b_pdphy>; + qcom,ext-disp = <&ext_disp>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,usbplug-cc-gpio = <&tlmm 65 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&sde_dp_usbplug_cc_active>; + pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; +}; + +&mdss_mdp { + connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; +}; + +/* PHY TIMINGS REVISION W */ +&dsi_sw43404_amoled_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 + 05 03 02 04 00 12 15]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; + }; +}; + +&dsi_sw43404_amoled_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 57 55>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; + qcom,mdss-dsi-min-refresh-rate = <55>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 + 05 03 02 04 00 12 15]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 + 05 02 03 04 00 11 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 270 270 270 1080 270>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_1080_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-panel-clockrate = <900000000>; + }; + }; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-min-refresh-rate = <53>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 1080 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 + 09 06 02 04 00 18 17]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 46 13 14 33 30 12 + 14 0e 02 04 00 37 22]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; diff --git a/display/kona-sde-pll.dtsi b/display/kona-sde-pll.dtsi new file mode 100644 index 000000000000..e6bda66f50ac --- /dev/null +++ b/display/kona-sde-pll.dtsi @@ -0,0 +1,82 @@ +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 { + compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94900 0x260>, + <0xae94400 0x800>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 { + compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96900 0x260>, + <0xae96400 0x800>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@c011000 { + compatible = "qcom,mdss_dp_pll_7nm"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x088ea000 0x200>, + <0x088eaa00 0x200>, + <0x088ea200 0x200>, + <0x088ea600 0x200>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "ln_tx0_base", + "ln_tx1_base", "gdsc_base"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "iface_clk", "ref_clk_src", + "gcc_iface", "pipe_clk"; + clock-rate = <0>; + }; +}; diff --git a/display/kona-sde.dtsi b/display/kona-sde.dtsi new file mode 100644 index 000000000000..a91ef2219900 --- /dev/null +++ b/display/kona-sde.dtsi @@ -0,0 +1,686 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84208>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x214>, + <0x0ae8f000 0x02c>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000 + 460000000>; + + mmcx-supply = <&VDD_MMCX_LEVEL>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800 0x2a00>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "cwb", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000 0x72800 0x73000 0x73800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; + + qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 4 8 12 + 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4400000 4400000 + 4400000 4400000 + 4400000 4400000 + 4400000 4400000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5300000 5300000 + 5300000 5300000 + 5300000 5300000 + 5300000 5300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x3>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-has-idle-pc; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <13700000>; + qcom,sde-max-bw-high-kbps = <16600000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x000000ff 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + qcom,sde-safe-lut-macrotile = <0 0xff00>; + /* same as safe-lut-macrotile */ + qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0x3ff>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x4000821>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040001>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 150000>, + <1 590 0 300000>; + }; + }; + + sde_dp: qcom,dp_display@ae90000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + vdda-1p2-supply = <&pm8150_l9>; + vdda-0p9-supply = <&pm8150_l18>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x780000 0x621c>, + <0x88ea040 0x10>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>; + /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "qfprom_physical", "dp_pll", + "usb3_dp_com", "hdcp_physical", "dp_p1"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "pixel1_parent", + "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,phy-version = <0x420>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,mst-enable; + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-input-width-pixs = <2048>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <33000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <126000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x3c50>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <3>; + + qcom,sde-dram-channels = <2>; + + vdd-supply = <&mdss_core_gdsc>; + clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "disp_rsc_mnoc_llcc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <20003 20513 0 0>, <20004 20513 0 0>, + <20003 20513 0 6400000>, <20004 20513 0 6400000>, + <20003 20513 0 6400000>, <20004 20513 0 6400000>; + }; + + qcom,sde-ebi-bus { + qcom,msm-bus,name = "disp_rsc_ebi"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20000 20512 0 0>, + <20000 20512 0 6400000>, + <20000 20512 0 6400000>; + }; + }; + + mdss_rotator: qcom,mdss_rotator@aea8800 { + compatible = "qcom,sde_rotator"; + reg = <0x0ae00000 0xac000>, + <0x0aeb8000 0x3000>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + status = "disabled"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x3>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <25 512 0 0>, + <25 512 0 6400000>, + <25 512 0 6400000>; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-vbif-memtype = <3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x215C 0x0400>; + qcom,iommu-dma = "disabled"; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&pm8150_l9>; + refgen-supply = <&refgen>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <26700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + vdda-1p2-supply = <&pm8150_l9>; + refgen-supply = <&refgen>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <26700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { + compatible = "qcom,dsi-phy-v4.1"; + label = "dsi-phy-0"; + cell-index = <0>; + reg = <0xae94400 0x760>; + reg-names = "dsi_phy"; + vdda-0p9-supply = <&pm8150_l5>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <46000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 { + compatible = "qcom,dsi-phy-v4.1"; + label = "dsi-phy-1"; + cell-index = <1>; + reg = <0xae96400 0x760>; + reg-names = "dsi_phy"; + vdda-0p9-supply = <&pm8150_l5>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <46000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + +}; From 231b07b46b02a8e2b6fb57c225923e7289936728 Mon Sep 17 00:00:00 2001 From: Ping Li Date: Mon, 3 Jun 2019 17:33:01 -0700 Subject: [PATCH 003/362] ARM: dts: msm: add support for sw fuse on Kona Add sw fuse range to dts file for Kona. Change-Id: I23b64e5569f6c4c931e6b2816ebf35877454fa08 --- display/kona-sde.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/display/kona-sde.dtsi b/display/kona-sde.dtsi index a91ef2219900..d6a849eb4925 100644 --- a/display/kona-sde.dtsi +++ b/display/kona-sde.dtsi @@ -6,11 +6,13 @@ reg = <0x0ae00000 0x84208>, <0x0aeb0000 0x2008>, <0x0aeac000 0x214>, - <0x0ae8f000 0x02c>; + <0x0ae8f000 0x02c>, + <0x0af50000 0x038>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "sid_phys"; + "sid_phys", + "swfuse_phys"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, From 1ae72cca202c191edecb4cf587ffcd0249cf1925 Mon Sep 17 00:00:00 2001 From: Nilaan Gunabalachandran Date: Tue, 26 Nov 2019 11:14:13 -0500 Subject: [PATCH 004/362] ARM: dts: msm: Add display specific dt files and binding snapshot Move sde, panel, msm dtsi and binding files from 4.19 kernel device tree project to display techpack. As of commit 5054306 (Merge "ARM: dts: qcom: Include camera sensor related dtsi overlays"). Change-Id: I120f98f4a914633ba2177baddaa8b510ee7f509d --- bindings/dsi.txt | 11 +- bindings/hdmi.txt | 2 +- bindings/mdp4.txt | 2 +- bindings/mdp5.txt | 2 +- bindings/mdss-dsi-panel.txt | 7 + bindings/sde.txt | 41 +- ...anel-nt35597-truly-dualmipi-wqxga-cmd.dtsi | 1 - ...el-nt35597-truly-dualmipi-wqxga-video.dtsi | 1 - display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi | 2 - .../dsi-panel-nt35695b-truly-fhd-video.dtsi | 4 +- ...panel-rm69299-visionox-fhd-plus-video.dtsi | 64 + display/dsi-panel-sharp-1080p-cmd.dtsi | 1 - display/dsi-panel-sharp-dsc-4k-cmd.dtsi | 1 - display/dsi-panel-sharp-dsc-4k-video.dtsi | 1 - display/dsi-panel-sharp-qsync-fhd-cmd.dtsi | 361 ++++++ display/dsi-panel-sharp-qsync-fhd-video.dtsi | 118 ++ display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi | 921 ++++++++++++++ display/dsi-panel-sharp-qsync-wqhd-video.dtsi | 120 ++ display/dsi-panel-sim-cmd.dtsi | 1 - display/dsi-panel-sim-dsc-10bit-cmd.dtsi | 1 - display/dsi-panel-sim-dsc375-cmd.dtsi | 1 - display/dsi-panel-sim-dualmipi-cmd.dtsi | 1 - .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 1123 ++++++++++++++++- display/dsi-panel-sim-dualmipi-video.dtsi | 1 - display/dsi-panel-sim-sec-hd-cmd.dtsi | 1 - display/dsi-panel-sim-video.dtsi | 1 - ...panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi | 3 +- ...dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi | 194 ++- ...i-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 3 +- ...el-td4330-truly-v2-singlemipi-fhd-cmd.dtsi | 296 +++++ ...el-td4330-truly-v2-singlemipi-fhd-vid.dtsi | 295 +++++ display/kona-sde-display-cdp-lcd.dtsi | 119 ++ display/kona-sde-display-cdp.dtsi | 22 + display/kona-sde-display-mtp.dtsi | 3 + display/kona-sde-display-qrd.dtsi | 3 + display/kona-sde-display.dtsi | 352 +++++- display/kona-sde-pll.dtsi | 25 +- display/kona-sde.dtsi | 36 +- 38 files changed, 4076 insertions(+), 65 deletions(-) create mode 100644 display/dsi-panel-rm69299-visionox-fhd-plus-video.dtsi create mode 100644 display/dsi-panel-sharp-qsync-fhd-cmd.dtsi create mode 100644 display/dsi-panel-sharp-qsync-fhd-video.dtsi create mode 100644 display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi create mode 100644 display/dsi-panel-sharp-qsync-wqhd-video.dtsi create mode 100644 display/dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi create mode 100644 display/dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi diff --git a/bindings/dsi.txt b/bindings/dsi.txt index 577b3cede370..1d421b23af6a 100644 --- a/bindings/dsi.txt +++ b/bindings/dsi.txt @@ -1,4 +1,4 @@ -Qualcomm Technologies Inc. adreno/snapdragon DSI output +Qualcomm Technologies Inc. snapdragon DSI output DSI Controller: Required properties: @@ -134,6 +134,14 @@ Optional properties: than two times the dsi link rate time. If the property is not specified, then the default value is 14000 us. +- frame-threshold-time-us: For command mode panels, this specifies the idle + time for dsi controller where no active data is + send to the panel, as controller is done sending + active pixels. If there is no desired DSI clocks + specified, then clocks will be derived from this + threshold time, which has a default value in chipset + based on the CPU processing power. + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/graph.txt [3] Documentation/devicetree/bindings/media/video-interfaces.txt @@ -184,6 +192,7 @@ Example: qcom,sync-dual-dsi; qcom,mdss-mdp-transfer-time-us = <12000>; + frame-threshold-time-us = <800>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&dsi_active>; diff --git a/bindings/hdmi.txt b/bindings/hdmi.txt index 66a123b221b8..e108fb6c86d0 100644 --- a/bindings/hdmi.txt +++ b/bindings/hdmi.txt @@ -1,4 +1,4 @@ -Qualcomm Technologies, Inc. adreno/snapdragon hdmi output +Qualcomm Technologies, Inc. snapdragon hdmi output Required properties: - compatible: one of the following diff --git a/bindings/mdp4.txt b/bindings/mdp4.txt index 1d9cf3579dc6..a87f9a58bc83 100644 --- a/bindings/mdp4.txt +++ b/bindings/mdp4.txt @@ -1,4 +1,4 @@ -Qualcomm Technologies, Inc. adreno/snapdragon MDP4 display controller +Qualcomm Technologies, Inc. snapdragon MDP4 display controller Description: diff --git a/bindings/mdp5.txt b/bindings/mdp5.txt index fcad35c3a26e..aeb21663a910 100644 --- a/bindings/mdp5.txt +++ b/bindings/mdp5.txt @@ -1,4 +1,4 @@ -Qualcomm Technologies, Inc. adreno/snapdragon MDP5 display controller +Qualcomm Technologies, Inc. snapdragon MDP5 display controller Description: diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 338ea8d8dc9e..b6a2ac6f79e5 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -79,6 +79,10 @@ then 3 options can be tried. Optional properties: - qcom,mdss-dsi-panel-name: A string used as a descriptive name of the panel +- qcom,mdss-dsi-physical-type: A string used as a decriptive type of the panel. + "oled" : That indicate it's an OLED panel. + "lcd" : That indicate it's an LCD panel. + If it is not set, consider it is a LCD panel as default. - qcom,mdss-dsi-panel-phy-timings: An array of length 'n' char that specifies the DSI PHY lane timing settings for the panel. This is specific to SDE DRM driver. The value of 'n' depends on the DSI PHY h/w revision and parsing this @@ -310,6 +314,7 @@ Optional properties: to the physical width in the framebuffer information. - qcom,mdss-pan-physical-height-dimension: Specifies panel physical height in mm which corresponds to the physical height in the framebuffer information. +- qcom,mdss-dsi-panel-test-pin: Specifies the panel test gpio. - qcom,mdss-dsi-mode-sel-gpio-state: String that specifies the lcd mode for panel (such as single-port/dual-port), if qcom,panel-mode-gpio binding is defined in dsi controller. @@ -528,6 +533,8 @@ Optional properties: - qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder. - qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps instead of standard dcs type 0x0A. +- qcom,mdss-pps-delay-ms: An u32 value that indicates post PPS command + delay in milliseconds. If no value is specified, it chooses zero by default. - qcom,display-topology: Array of u32 values which specifies the list of topologies available for the display. A display topology is defined by a set of 3 values in the order: diff --git a/bindings/sde.txt b/bindings/sde.txt index c4c6698514e8..a09486452287 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -112,6 +112,7 @@ Optional properties: - qcom,sde-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on each interface. - qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width. +- qcom,sde-vig-sspp-linewidth: A u32 value indicates the max vig sspp line width. - qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. - qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. - qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. @@ -146,8 +147,6 @@ Optional properties: feature is available or not. - qcom,sde-has-idle-pc: Boolean property to indicate if target has idle power collapse feature available or not. -- qcom,fullsize-va-map: Boolean property to indicate smmu mapping range - for mdp should be full range (4GB). - qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction feature available or not. - qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler @@ -467,6 +466,15 @@ Optional properties: ordering block 0: lower priority pipe has to be on the left for a given pair of pipes. 1: priority have to be explicitly configured for a given pair of pipes. +- qcom,sde-limits: A node that lists the limits for different properties. This node + can have multiple child nodes. Each child node represents a + specific usecase limit. The usecase can be defined for properties like + sspp linewidth, bw limit etc. + e.g. qcom,sde-limits + -- qcom,sde-limit-name: name of the usecase + -- qcom,sde-limit-cases: different usecases to be considered + -- qcom,sde-limit-ids: respective ids for the above usecases + -- qcom,sde-limit-values: usecase and value for different combinations Bus Scaling Subnodes: - qcom,sde-reg-bus: Property to provide Bus scaling for register access for @@ -803,6 +811,35 @@ Example: qcom,sde-dspp-vlut = <0x0 0x00010000>; }; + qcom,sde-limits { + qcom,sde-linewidth-limits{ + qcom,sde-limit-cases = "vig", "dma", "scaling", "inline_rot"; + qcom,sde-limit-ids= <0x1 0x2 0x4 0x8>; + /* the qcom,sde-limit-values property consist of two values: + one for the usecase and the other for the value. The usecase can be + any combination of the values mentioned in qcom,sde-limit-ids. + For eg: <0x5 2560> means usecase is 0x5 and value is 2560. + 0x5 = (0x1 | 0x4) = vig + scaling. Thus the linewidth for usecase + vig + scaling = 2560 */ + qcom,sde-limit-values = <0x1 4096>, + <0x5 2560>, + <0xd 1088>, + <0x2 4096>; + }; + qcom,sde-bw-limits{ + qcom,sde-limit-cases = "per_pipe", "total_bw", "vfe_on", "cwb_on"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2600000>, + <0x9 2600000>, + <0x5 2600000>, + <0xd 2600000>, + <0x2 5800000>, + <0xa 5500000>, + <0x6 4400000>, + <0xe 3900000>; + }; + }; + qcom,sde-mixer-blocks { qcom,sde-mixer-gc = <0x3c0 0x00010000>; }; diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi index cddf9165ff1f..8b3aedf2c52d 100644 --- a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi +++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi @@ -6,7 +6,6 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi index aff695014114..090c75f8b90d 100644 --- a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi +++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi @@ -6,7 +6,6 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi b/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi index ffefa6a671d6..698c466b2ffd 100644 --- a/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi +++ b/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi @@ -6,11 +6,9 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,dsi-sec-ctrl-num = <1>; qcom,dsi-sec-phy-num = <1>; - qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-nt35695b-truly-fhd-video.dtsi b/display/dsi-panel-nt35695b-truly-fhd-video.dtsi index fe84525de197..78ae48b0ff86 100644 --- a/display/dsi-panel-nt35695b-truly-fhd-video.dtsi +++ b/display/dsi-panel-nt35695b-truly-fhd-video.dtsi @@ -6,7 +6,9 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-rm69299-visionox-fhd-plus-video.dtsi b/display/dsi-panel-rm69299-visionox-fhd-plus-video.dtsi new file mode 100644 index 000000000000..4687a3bcea9a --- /dev/null +++ b/display/dsi-panel-rm69299-visionox-fhd-plus-video.dtsi @@ -0,0 +1,64 @@ +&mdss_mdp { + dsi_rm69299_visionox_amoled_video: + qcom,mdss_dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-panel-name = + "rm69299 amoled fhd+ video mode dsi visionox panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2248>; + qcom,mdss-dsi-h-front-porch = <26>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <56>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 02 C2 08 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 51 FF + 05 01 00 00 96 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-1080p-cmd.dtsi b/display/dsi-panel-sharp-1080p-cmd.dtsi index 8ffa0eb7749d..c78aa1c268ff 100644 --- a/display/dsi-panel-sharp-1080p-cmd.dtsi +++ b/display/dsi-panel-sharp-1080p-cmd.dtsi @@ -6,7 +6,6 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-panel-destination = "display_1"; qcom,mdss-dsi-panel-clockrate = <850000000>; diff --git a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi index 89df5ffd4029..08c6a928b60a 100644 --- a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi +++ b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi @@ -5,7 +5,6 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sharp-dsc-4k-video.dtsi b/display/dsi-panel-sharp-dsc-4k-video.dtsi index feb55406288c..54894686a0fa 100644 --- a/display/dsi-panel-sharp-dsc-4k-video.dtsi +++ b/display/dsi-panel-sharp-dsc-4k-video.dtsi @@ -5,7 +5,6 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sharp-qsync-fhd-cmd.dtsi b/display/dsi-panel-sharp-qsync-fhd-cmd.dtsi new file mode 100644 index 000000000000..fae031cdfaa1 --- /dev/null +++ b/display/dsi-panel-sharp-qsync-fhd-cmd.dtsi @@ -0,0 +1,361 @@ +&mdss_mdp { + dsi_sharp_qsync_fhd_cmd: qcom,mdss_dsi_sharp_qsync_fhd_cmd { + qcom,mdss-dsi-panel-name = "Sharp fhd cmd mode qsync dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-panel-mode-switch; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <134>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 00 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 00 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 03 + 39 01 00 00 00 00 02 17 70 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 02 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 03 + 39 01 00 00 00 00 02 17 70 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-qsync-fhd-video.dtsi b/display/dsi-panel-sharp-qsync-fhd-video.dtsi new file mode 100644 index 000000000000..61f6078c69cd --- /dev/null +++ b/display/dsi-panel-sharp-qsync-fhd-video.dtsi @@ -0,0 +1,118 @@ +&mdss_mdp { + dsi_sharp_qsync_fhd_video: qcom,mdss_dsi_sharp_qsync_fhd_video { + qcom,mdss-dsi-panel-name = + "Sharp fhd video mode qsync dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <134>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <124>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <1968>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 05 be 00 10 00 10 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi new file mode 100644 index 000000000000..215b3ab46dde --- /dev/null +++ b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi @@ -0,0 +1,921 @@ +&mdss_mdp { + dsi_sharp_qsync_wqhd_cmd: qcom,mdss_dsi_sharp_qsync_wqhd_cmd { + qcom,mdss-dsi-panel-name = "Sharp 2k cmd mode qsync dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-panel-mode-switch; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <134>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 15 01 00 00 00 00 02 ff 10 + 05 01 00 00 00 00 01 28 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,cmd-to-video-mode-post-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 bb 13 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 06 + ]; + qcom,video-to-cmd-mode-post-switch-commands-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <80>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <2608>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 05 be 00 10 00 10 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,video-to-cmd-mode-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 bb 10 + ]; + qcom,video-to-cmd-mode-post-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 bb 10 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 00 + ]; + qcom,video-to-cmd-mode-switch-commands-state = + "dsi_lp_mode"; + qcom,video-to-cmd-mode-post-switch-commands-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 15 01 00 00 00 00 02 ff 10 + 05 01 00 00 00 00 01 28 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 03 + 39 01 00 00 00 00 02 17 70 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 02 + 15 01 00 00 00 00 02 ff 10 + 05 01 00 00 00 00 01 28 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 03 + 39 01 00 00 00 00 02 17 70 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 03 + 15 01 00 00 00 00 02 ff 10 + 05 01 00 00 00 00 01 28 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,cmd-to-video-mode-post-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 bb 13 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 06 + ]; + qcom,video-to-cmd-mode-post-switch-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@5 { + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 05 be 00 10 00 10 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,video-to-cmd-mode-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 bb 10 + ]; + qcom,video-to-cmd-mode-post-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 bb 10 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 00 + ]; + qcom,video-to-cmd-mode-switch-commands-state = + "dsi_lp_mode"; + qcom,video-to-cmd-mode-post-switch-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@6 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 00 + 15 01 00 00 00 00 02 ff 10 + 05 01 00 00 00 00 01 28 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 00 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@7 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <80>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 16 03 + 39 01 00 00 00 00 02 17 70 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 02 + 15 01 00 00 00 00 02 ff 10 + 05 01 00 00 00 00 01 28 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 03 + 39 01 00 00 00 00 02 17 70 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-qsync-wqhd-video.dtsi b/display/dsi-panel-sharp-qsync-wqhd-video.dtsi new file mode 100644 index 000000000000..0268ded1a74c --- /dev/null +++ b/display/dsi-panel-sharp-qsync-wqhd-video.dtsi @@ -0,0 +1,120 @@ +&mdss_mdp { + dsi_sharp_qsync_wqhd_video: qcom,mdss_dsi_sharp_qsync_wqhd_video { + qcom,mdss-dsi-panel-name = + "Sharp 2k video mode qsync dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <134>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <80>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <2608>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 03 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 83 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 68 00 d5 00 0a 0d b7 09 89 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 05 be 00 10 00 10 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + }; + }; +}; diff --git a/display/dsi-panel-sim-cmd.dtsi b/display/dsi-panel-sim-cmd.dtsi index f62ce3b9d7b5..b0748f8d04a1 100644 --- a/display/dsi-panel-sim-cmd.dtsi +++ b/display/dsi-panel-sim-cmd.dtsi @@ -5,7 +5,6 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi index 310ce40cd902..edb09ed0db4e 100644 --- a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi @@ -6,7 +6,6 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sim-dsc375-cmd.dtsi b/display/dsi-panel-sim-dsc375-cmd.dtsi index ef40a2e7b3e6..4600fc312572 100644 --- a/display/dsi-panel-sim-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dsc375-cmd.dtsi @@ -6,7 +6,6 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sim-dualmipi-cmd.dtsi b/display/dsi-panel-sim-dualmipi-cmd.dtsi index 5f4be88fb88f..6407ef2d75b2 100644 --- a/display/dsi-panel-sim-dualmipi-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-cmd.dtsi @@ -5,7 +5,6 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index 87b4a76a3a96..118d1e935460 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -6,7 +6,6 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; @@ -40,6 +39,58 @@ qcom,mdss-dsi-display-timings { timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <3840>; qcom,mdss-dsi-h-front-porch = <30>; @@ -91,7 +142,499 @@ qcom,mdss-dsc-block-prediction-enable; }; - timing@1 { + timing@2 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@5 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@6 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@7 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@8 { + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@9 { qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-panel-width = <720>; qcom,mdss-dsi-panel-height = <2560>; @@ -271,7 +814,367 @@ qcom,mdss-dsc-block-prediction-enable; }; - timing@2 { + timing@10 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@11 { + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@12 { qcom,mdss-dsi-panel-width = <2520>; qcom,mdss-dsi-panel-height = <2160>; qcom,mdss-dsi-h-front-porch = <30>; @@ -282,6 +1185,214 @@ qcom,mdss-dsi-v-front-porch = <8>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <1080>; + qcom,mdss-dsc-slice-width = <1260>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@13 { + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@14 { + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@15 { + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@16 { + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-on-command = [ @@ -315,9 +1426,9 @@ qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <1080>; - qcom,mdss-dsc-slice-width = <1260>; - qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; qcom,mdss-dsc-bit-per-component = <10>; qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; diff --git a/display/dsi-panel-sim-dualmipi-video.dtsi b/display/dsi-panel-sim-dualmipi-video.dtsi index 3bee9f6f104d..9121f2cb8750 100644 --- a/display/dsi-panel-sim-dualmipi-video.dtsi +++ b/display/dsi-panel-sim-dualmipi-video.dtsi @@ -5,7 +5,6 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sim-sec-hd-cmd.dtsi b/display/dsi-panel-sim-sec-hd-cmd.dtsi index e9d31359ed5b..973dc517711c 100644 --- a/display/dsi-panel-sim-sec-hd-cmd.dtsi +++ b/display/dsi-panel-sim-sec-hd-cmd.dtsi @@ -6,7 +6,6 @@ qcom,dsi-sec-ctrl-num = <1>; qcom,dsi-sec-phy-num = <1>; - qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sim-video.dtsi b/display/dsi-panel-sim-video.dtsi index 5a2ac01716d3..f5a522b0748e 100644 --- a/display/dsi-panel-sim-video.dtsi +++ b/display/dsi-panel-sim-video.dtsi @@ -5,7 +5,6 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi index 6195f8c82a53..4d77525decb6 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi @@ -3,10 +3,9 @@ qcom,mdss-dsi-panel-name = "sw43404 amoled boe fhd+ panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - + qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi index 032fc39b91bf..1c08e1931f81 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi @@ -3,6 +3,7 @@ qcom,mdss-dsi-panel-name = "sw43404 amoled cmd mode dsi boe panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; qcom,mdss-dsi-bpp = <24>; @@ -12,7 +13,6 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; qcom,mdss-dsi-lane-map = "lane_map_0123"; @@ -54,7 +54,15 @@ qcom,mdss-dsi-h-right-border = <0>; qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-jitter = <0x6 0x1>; + qcom,mdss-mdp-transfer-time-us = <15300>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 0c b1 a0 9f 42 4f 63 0e 0a 10 0e 0a 10 + 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 + ]; + qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 03 b0 a5 00 39 01 00 00 00 00 03 5c 42 00 @@ -116,6 +124,188 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <50>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2880>; + qcom,mdss-dsi-h-front-porch = <60>; + qcom,mdss-dsi-h-back-porch = <30>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 + 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 03 5c 42 00 + 07 01 00 00 00 00 02 01 00 + 0a 01 00 00 00 00 80 11 00 00 89 30 80 + 0B 40 05 A0 05 A0 02 D0 02 D0 02 00 + 02 68 00 20 9A DB 00 0A 00 0C 00 12 + 00 0E 18 00 10 F0 03 0C 20 00 06 0B + 0B 33 0E 1C 2A 38 46 54 62 69 70 77 + 79 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 + 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 09 F8 00 08 10 08 2D + 00 00 2D + 15 01 00 00 00 00 02 55 00 + 05 01 00 00 1e 00 02 11 00 + 39 01 00 00 00 00 03 b0 a5 00 + 15 01 00 00 00 00 02 e0 18 + 39 01 00 00 00 00 0c c0 00 53 6f 51 50 + 51 34 4f 5a 33 19 + 05 01 00 00 78 00 02 35 00 + 05 01 00 00 3c 00 02 29 00 + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 + 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 + 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 5a 01]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 5a 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-lp1-command = [ + 05 01 00 00 00 00 02 39 00 + ]; + qcom,mdss-dsi-lp1-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 00 00 02 38 00 + ]; + qcom,mdss-dsi-nolp-command-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <180>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2880>; + qcom,mdss-dsi-h-front-porch = <60>; + qcom,mdss-dsi-h-back-porch = <30>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 0c b1 a0 9f 63 4f 63 0e 0a 10 0e 0a 10 + 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 03 5c 42 00 + 07 01 00 00 00 00 02 01 00 + 0a 01 00 00 00 00 80 11 00 00 89 30 80 + 0B 40 05 A0 05 A0 02 D0 02 D0 02 00 + 02 68 00 20 9A DB 00 0A 00 0C 00 12 + 00 0E 18 00 10 F0 03 0C 20 00 06 0B + 0B 33 0E 1C 2A 38 46 54 62 69 70 77 + 79 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 + 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 09 F8 00 08 10 08 2D + 00 00 2D + 15 01 00 00 00 00 02 55 00 + 05 01 00 00 1e 00 02 11 00 + 39 01 00 00 00 00 03 b0 a5 00 + 15 01 00 00 00 00 02 e0 18 + 39 01 00 00 00 00 0c c0 00 53 6f 51 50 + 51 34 4f 5a 33 19 + 05 01 00 00 78 00 02 35 00 + 05 01 00 00 3c 00 02 29 00 + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 + 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 0c b1 a0 9f 63 4f 63 0e 0a 10 0e 0a 10 + 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 5a 01]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 5a 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-lp1-command = [ + 05 01 00 00 00 00 02 39 00 + ]; + qcom,mdss-dsi-lp1-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 00 00 02 38 00 + ]; + qcom,mdss-dsi-nolp-command-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <180>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi index 37c0dfcd7d75..ecac0d4bfc65 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi @@ -3,10 +3,9 @@ qcom,mdss-dsi-panel-name = "sw43404 amoled video mode dsi boe panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_video_mode"; - + qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; diff --git a/display/dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi b/display/dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi new file mode 100644 index 000000000000..0c37fa4a425d --- /dev/null +++ b/display/dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi @@ -0,0 +1,296 @@ +&mdss_mdp { + dsi_td4330_truly_v2_cmd: qcom,mdss_dsi_td4330_truly_v2_cmd { + qcom,mdss-dsi-panel-name = + "td4330 v2 cmd mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + qcom,mdss-dsi-h-front-porch = <80>; + qcom,mdss-dsi-h-back-porch = <80>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <13>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 + B0 00 + 29 01 00 00 00 00 0D + B6 30 6B 00 06 03 0A 13 1A 6C + 18 19 02 + 29 01 00 00 00 00 05 + B7 40 00 00 00 + 29 01 00 00 00 00 08 + B8 57 3D 19 BE 1E 0A 0A + 29 01 00 00 00 00 08 + B9 6F 3D 28 BE 3C 14 0A + 29 01 00 00 00 00 08 + BA B5 33 41 BE 64 23 0A + 29 01 00 00 00 00 0C + BB 44 26 C3 1F 19 06 03 C0 00 + 00 10 + 29 01 00 00 00 00 0C + BC 32 4C C3 52 32 1F 03 F2 00 + 00 13 + 29 01 00 00 00 00 0C + BD 24 68 C3 AA 3F 32 03 FF 00 + 00 25 + 29 01 00 00 00 00 0D + BE 00 00 00 00 00 00 00 00 00 + 00 00 00 + 29 01 00 00 00 00 0D + C0 00 DC 00 DC 04 08 E8 00 04 + 00 03 78 + 29 01 00 00 00 00 24 + C1 30 00 00 11 11 00 00 00 22 + 00 05 20 FA 00 08 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 + 29 01 00 00 00 00 79 + C2 06 E0 6E 01 03 00 02 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 11 00 00 00 00 04 A0 C9 + 00 00 00 00 00 00 48 EB 00 00 + 01 00 00 00 11 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 11 00 00 00 00 + 00 00 DC 00 00 00 00 04 00 08 + EF 00 00 00 00 00 11 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 + 29 01 00 00 00 00 6D + C3 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 AA AA AA 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 62 + C4 00 4C 00 3F 00 83 00 00 87 + 86 85 84 00 00 00 00 00 61 5D + 5F 00 5E 60 62 00 00 00 02 00 + 83 00 00 87 86 85 84 00 00 00 + 00 00 61 5D 5F 00 5E 60 62 FF + FF FF FF FF FF 00 0F 0E 00 0F + 0E 00 00 00 00 00 00 00 0F EE + 00 0F EE 00 00 E0 00 00 E0 0E + 00 00 00 0E 00 00 00 00 00 FF + 57 00 00 00 00 00 00 00 + 29 01 00 00 00 00 06 + C5 08 00 00 00 00 + 29 01 00 00 00 00 3A + C6 02 0A 08 FC FF FF FF 00 00 + 13 01 F0 0C 06 01 43 43 43 00 + 00 00 01 77 09 28 28 06 01 43 + 43 43 00 00 00 01 61 00 00 00 + 1C 01 00 00 00 00 00 00 00 00 + 00 00 00 00 20 20 00 00 + 29 01 00 00 00 00 4D + C7 00 00 00 E0 01 E9 02 7E 02 + 05 02 90 02 F6 02 40 02 5C 02 + 77 02 C8 02 1B 02 5B 02 BD 02 + 27 02 C3 03 54 03 D8 03 FF 00 + 00 00 E0 01 E9 02 7E 02 05 02 + 90 02 F6 02 40 02 5C 02 77 02 + C8 02 1B 02 5B 02 BD 02 27 02 + C3 03 54 03 D8 03 FF + 29 01 00 00 00 00 42 + C8 41 00 FF FA 00 FF 00 00 FE + F6 FE E9 00 00 FF F7 FB E1 00 + 00 00 00 00 FF 00 00 FF FA 00 + FF 00 FE F6 FE E9 00 FF F7 FB + E1 00 00 00 00 FF 00 FF FA 00 + FF 00 FE F6 FE E9 00 FF F7 FB + E1 00 00 00 00 FF + 29 01 00 00 00 00 19 + C9 00 FF FA 00 FF 00 00 FE F6 + FE E9 00 00 FF F7 FB E1 00 00 + 00 00 00 FF 00 + 29 01 00 00 00 00 42 + CA 1C FC FC FC 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 + 29 01 00 00 00 00 0B + CC 00 00 4D 8B 55 4D 8B AA 4D + 8B + 29 01 00 00 00 00 02 + CD 00 + 29 01 00 00 00 00 24 + CE 5D 40 49 53 59 5E 63 68 6E + 74 7E 8A 98 A8 BB D0 E7 FF 04 + 00 04 04 42 04 69 5A 40 11 F4 + 00 00 84 FA 00 00 + 29 01 00 00 00 00 07 + CF 00 00 80 46 61 00 + 29 01 00 00 00 00 12 + D0 F6 95 11 B1 55 CF 00 F6 D3 + 11 F0 01 12 CF 02 20 11 + 29 01 00 00 00 00 23 + D1 D3 D3 33 33 07 03 3B 33 77 + 37 77 37 35 77 07 77 F7 33 73 + 07 33 33 03 33 1B 03 32 3D 0A + 30 13 13 20 00 + 29 01 00 00 00 00 05 + D2 00 00 07 00 + 29 01 00 00 00 00 9A + D3 03 00 00 00 00 00 00 0F 00 + 57 00 00 32 00 00 1A 70 01 19 + 80 01 01 F0 02 00 E0 06 FF F7 + FF FF F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF FF F7 + FF FF F7 FF + 29 01 00 00 00 00 05 + E5 03 00 00 00 + 29 01 00 00 00 00 09 + D5 02 42 02 42 02 DC 02 DC + 29 01 00 00 00 00 02 + D6 C0 + 29 01 00 00 00 00 32 + D7 21 10 52 52 00 B6 04 FD 00 + B6 04 FD 00 82 80 83 84 85 83 + 80 84 45 85 85 85 87 04 06 02 + 04 04 07 10 0C 0B 0A 0A 07 06 + 00 08 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 05 + DD 30 06 23 65 + 29 01 00 00 00 00 0D + DE 00 00 00 0F FF 00 00 00 00 + 00 00 10 + 29 01 00 00 00 00 02 + E3 FF + 29 01 00 00 00 00 07 + E6 00 00 00 00 00 00 + 29 01 00 00 00 00 0B + E7 50 04 00 00 00 00 00 00 00 + 00 + 29 01 00 00 00 00 05 + E8 00 01 23 00 + 29 01 00 00 00 00 1E + EA 01 02 47 80 47 00 00 00 05 + 00 13 60 02 47 80 47 00 00 00 + 00 13 60 00 11 00 30 10 21 02 + 29 01 00 00 00 00 08 + EB 00 00 00 00 01 00 11 + 29 01 00 00 00 00 04 + EC 00 00 00 + 29 01 00 00 00 00 21 + ED 01 01 02 02 02 02 00 00 00 + 00 00 00 0A 00 00 00 00 10 00 + 18 00 18 00 B0 00 00 00 00 00 + DA 10 00 + 29 01 00 00 00 00 61 + EE 03 0F 00 00 00 00 40 1F 00 + 00 0F F2 3F 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 10 + 01 00 09 01 8C D8 EF 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 50 1F 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 + 29 01 00 00 00 00 8C + EF 00 70 4A 08 D0 00 00 00 00 + 3C 3C 3C 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 70 + 4A 08 D0 00 00 00 00 3C 3C 3C + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 08 EC 50 10 00 10 + 00 0A 0A 00 00 00 00 10 0F 00 + 03 51 00 50 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 03 08 EC + 29 01 00 00 00 00 02 + B0 03 + 29 01 00 00 00 00 02 + B0 04 + 29 01 00 00 00 00 02 + D6 00 + 39 01 00 00 00 00 03 + 51 FF F0 + 39 01 00 00 00 00 02 + 53 0C + 39 01 00 00 00 00 02 + 55 00 + 39 01 00 00 00 00 02 + 35 00 + 39 01 00 00 00 00 05 + 2A 00 00 04 37 + 39 01 00 00 00 00 05 + 2B 00 00 08 E7 + 05 01 00 00 FF 00 02 + 29 00 + 05 01 00 00 FF 00 02 + 11 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi b/display/dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi new file mode 100644 index 000000000000..8092c2c286fa --- /dev/null +++ b/display/dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi @@ -0,0 +1,295 @@ +&mdss_mdp { + dsi_td4330_truly_v2_video: qcom,mdss_dsi_td4330_truly_v2_video { + qcom,mdss-dsi-panel-name = + "td4330 v2 video mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <65>; + qcom,mdss-pan-physical-height-dimension = <129>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + qcom,mdss-dsi-h-front-porch = <40>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <16>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 + B0 00 + 29 01 00 00 00 00 0D + B6 30 6B 00 06 03 0A 13 1A 6C + 18 19 02 + 29 01 00 00 00 00 05 + B7 51 00 00 00 + 29 01 00 00 00 00 08 + B8 57 3D 19 BE 1E 0A 0A + 29 01 00 00 00 00 08 + B9 6F 3D 28 BE 3C 14 0A + 29 01 00 00 00 00 08 + BA B5 33 41 BE 64 23 0A + 29 01 00 00 00 00 0C + BB 44 26 C3 1F 19 06 03 C0 00 + 00 10 + 29 01 00 00 00 00 0C + BC 32 4C C3 52 32 1F 03 F2 00 + 00 13 + 29 01 00 00 00 00 0C + BD 24 68 C3 AA 3F 32 03 FF 00 + 00 25 + 29 01 00 00 00 00 0D + BE 00 00 00 00 00 00 00 00 00 + 00 00 00 + 29 01 00 00 00 00 0D + C0 00 DC 00 DC 04 08 E8 00 04 + 00 03 78 + 29 01 00 00 00 00 24 + C1 30 00 00 11 11 00 00 00 22 + 00 05 20 FA 00 08 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 + 29 01 00 00 00 00 79 + C2 06 E0 6E 01 03 00 02 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 11 00 00 00 00 04 A0 C9 + 00 00 00 00 00 00 48 EB 00 00 + 01 00 00 00 11 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 11 00 00 00 00 + 00 00 DC 00 00 00 00 04 00 08 + EF 00 00 00 00 00 11 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 + 29 01 00 00 00 00 6D + C3 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 AA AA AA 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 62 + C4 00 4C 00 3F 00 83 00 00 87 + 86 85 84 00 00 00 00 00 61 5D + 5F 00 5E 60 62 00 00 00 02 00 + 83 00 00 87 86 85 84 00 00 00 + 00 00 61 5D 5F 00 5E 60 62 FF + FF FF FF FF FF 00 0F 0E 00 0F + 0E 00 00 00 00 00 00 00 0F EE + 00 0F EE 00 00 E0 00 00 E0 0E + 00 00 00 0E 00 00 00 00 00 FF + 57 00 00 00 00 00 00 00 + 29 01 00 00 00 00 06 + C5 08 00 00 00 00 + 29 01 00 00 00 00 3A + C6 02 0A 08 FC FF FF FF 00 00 + 13 01 F0 0C 06 01 43 43 43 00 + 00 00 01 77 09 28 28 06 01 43 + 43 43 00 00 00 01 61 00 00 00 + 1C 01 00 00 00 00 00 00 00 00 + 00 00 00 00 20 20 00 00 + 29 01 00 00 00 00 4D + C7 00 00 00 E0 01 E9 02 7E 02 + 05 02 90 02 F6 02 40 02 5C 02 + 77 02 C8 02 1B 02 5B 02 BD 02 + 27 02 C3 03 54 03 D8 03 FF 00 + 00 00 E0 01 E9 02 7E 02 05 02 + 90 02 F6 02 40 02 5C 02 77 02 + C8 02 1B 02 5B 02 BD 02 27 02 + C3 03 54 03 D8 03 FF + 29 01 00 00 00 00 42 + C8 41 00 FF FA 00 FF 00 00 FE + F6 FE E9 00 00 FF F7 FB E1 00 + 00 00 00 00 FF 00 00 FF FA 00 + FF 00 FE F6 FE E9 00 FF F7 FB + E1 00 00 00 00 FF 00 FF FA 00 + FF 00 FE F6 FE E9 00 FF F7 FB + E1 00 00 00 00 FF + 29 01 00 00 00 00 19 + C9 00 FF FA 00 FF 00 00 FE F6 + FE E9 00 00 FF F7 FB E1 00 00 + 00 00 00 FF 00 + 29 01 00 00 00 00 42 + CA 1C FC FC FC 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 + 29 01 00 00 00 00 0B + CC 00 00 4D 8B 55 4D 8B AA 4D + 8B + 29 01 00 00 00 00 02 + CD 00 + 29 01 00 00 00 00 24 + CE 5D 40 49 53 59 5E 63 68 6E + 74 7E 8A 98 A8 BB D0 E7 FF 04 + 00 04 04 42 04 69 5A 40 11 F4 + 00 00 84 FA 00 00 + 29 01 00 00 00 00 07 + CF 00 00 80 46 61 00 + 29 01 00 00 00 00 12 + D0 F6 95 11 B1 55 CF 00 F6 D3 + 11 F0 01 12 CF 02 20 11 + 29 01 00 00 00 00 23 + D1 D3 D3 33 33 07 03 3B 33 77 + 37 77 37 35 77 07 77 F7 33 73 + 07 33 33 03 33 1B 03 32 3D 0A + 30 13 13 20 00 + 29 01 00 00 00 00 05 + D2 00 00 07 00 + 29 01 00 00 00 00 9A + D3 03 00 00 00 00 00 00 0F 00 + 57 00 00 32 00 00 1A 70 01 19 + 80 01 01 F0 02 00 E0 06 FF F7 + FF FF F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF FF F7 + FF FF F7 FF + 29 01 00 00 00 00 05 + E5 03 00 00 00 + 29 01 00 00 00 00 09 + D5 02 42 02 42 02 DC 02 DC + 29 01 00 00 00 00 02 + D6 C0 + 29 01 00 00 00 00 32 + D7 21 10 52 52 00 B6 04 FD 00 + B6 04 FD 00 82 80 83 84 85 83 + 80 84 45 85 85 85 87 04 06 02 + 04 04 07 10 0C 0B 0A 0A 07 06 + 00 08 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 05 + DD 30 06 23 65 + 29 01 00 00 00 00 0D + DE 00 00 00 0F FF 00 00 00 00 + 00 00 10 + 29 01 00 00 00 00 02 + E3 FF + 29 01 00 00 00 00 07 + E6 00 00 00 00 00 00 + 29 01 00 00 00 00 0B + E7 50 04 00 00 00 00 00 00 00 + 00 + 29 01 00 00 00 00 05 + E8 00 01 23 00 + 29 01 00 00 00 00 1E + EA 01 02 47 80 47 00 00 00 05 + 00 13 60 02 47 80 47 00 00 00 + 00 13 60 00 11 00 30 10 21 02 + 29 01 00 00 00 00 08 + EB 00 00 00 00 01 00 11 + 29 01 00 00 00 00 04 + EC 00 00 00 + 29 01 00 00 00 00 21 + ED 01 01 02 02 02 02 00 00 00 + 00 00 00 0A 00 00 00 00 10 00 + 18 00 18 00 B0 00 00 00 00 00 + DA 10 00 + 29 01 00 00 00 00 61 + EE 03 0F 00 00 00 00 40 1F 00 + 00 0F F2 3F 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 10 + 01 00 09 01 8C D8 EF 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 50 1F 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 + 29 01 00 00 00 00 8C + EF 00 70 4A 08 D0 00 00 00 00 + 3C 3C 3C 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 70 + 4A 08 D0 00 00 00 00 3C 3C 3C + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 08 EC 50 10 00 10 + 00 0A 0A 00 00 00 00 10 0F 00 + 03 51 00 50 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 03 08 EC + 29 01 00 00 00 00 02 + B0 03 + 29 01 00 00 00 00 02 + B0 04 + 29 01 00 00 00 00 02 + D6 00 + 39 01 00 00 00 00 03 + 51 FF F0 + 39 01 00 00 00 00 02 + 53 0C + 39 01 00 00 00 00 02 + 55 00 + 39 01 00 00 00 00 02 + 35 00 + 39 01 00 00 00 00 05 + 2A 00 00 04 37 + 39 01 00 00 00 00 05 + 2B 00 00 08 E7 + 05 01 00 00 FF 00 02 + 29 00 + 05 01 00 00 FF 00 02 + 11 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/kona-sde-display-cdp-lcd.dtsi b/display/kona-sde-display-cdp-lcd.dtsi index a7d85dfd9194..6360807c9608 100644 --- a/display/kona-sde-display-cdp-lcd.dtsi +++ b/display/kona-sde-display-cdp-lcd.dtsi @@ -1,36 +1,155 @@ &dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; /delete-property/ qcom,platform-en-gpio; }; &dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-qsync-min-refresh-rate = <55>; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; /delete-property/ qcom,platform-en-gpio; }; &dsi_sharp_1080_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; }; &dsi_dual_nt35597_truly_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; }; &dsi_dual_nt35597_truly_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; }; &dsi_nt35695b_truly_fhd_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; }; &dsi_nt35695b_truly_fhd_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; }; +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; +}; + &sde_dsi { /delete-property/ avdd-supply; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>; }; + +&sde_dsi1 { + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; +}; diff --git a/display/kona-sde-display-cdp.dtsi b/display/kona-sde-display-cdp.dtsi index fadbce641428..c432cb7b2965 100644 --- a/display/kona-sde-display-cdp.dtsi +++ b/display/kona-sde-display-cdp.dtsi @@ -8,6 +8,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 66 0>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sw43404_amoled_video { @@ -17,6 +18,7 @@ qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sw43404_amoled_fhd_plus_cmd { @@ -27,6 +29,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 66 0>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sharp_4k_dsc_cmd { @@ -48,6 +51,25 @@ qcom,platform-en-gpio = <&tlmm 60 0>; }; +&dsi_sharp_qsync_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-en-gpio = <&tlmm 60 0>; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-en-gpio = <&tlmm 60 0>; +}; + &dsi_sharp_1080_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/kona-sde-display-mtp.dtsi b/display/kona-sde-display-mtp.dtsi index b81aad8801d0..ad378d6b0ddf 100644 --- a/display/kona-sde-display-mtp.dtsi +++ b/display/kona-sde-display-mtp.dtsi @@ -8,6 +8,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 66 0>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sw43404_amoled_video { @@ -17,6 +18,7 @@ qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sw43404_amoled_fhd_plus_cmd { @@ -27,6 +29,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 66 0>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sim_cmd { diff --git a/display/kona-sde-display-qrd.dtsi b/display/kona-sde-display-qrd.dtsi index 1f6e32ac60f8..2c8a7bc52ec0 100644 --- a/display/kona-sde-display-qrd.dtsi +++ b/display/kona-sde-display-qrd.dtsi @@ -8,6 +8,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 66 0>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sw43404_amoled_video { @@ -17,6 +18,7 @@ qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sw43404_amoled_fhd_plus_cmd { @@ -27,6 +29,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 66 0>; qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; }; &dsi_sim_cmd { diff --git a/display/kona-sde-display.dtsi b/display/kona-sde-display.dtsi index 6257b55c4e1d..a477f44fffc0 100644 --- a/display/kona-sde-display.dtsi +++ b/display/kona-sde-display.dtsi @@ -3,11 +3,14 @@ #include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" +#include "dsi-panel-sharp-qsync-wqhd-video.dtsi" #include "dsi-panel-sharp-1080p-cmd.dtsi" #include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" #include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-sim-dsc375-cmd.dtsi" @@ -66,6 +69,59 @@ qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <0>; }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_lab_ibb: dsi_panel_pwr_supply_lab_ibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; }; dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { @@ -114,10 +170,23 @@ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + <&mdss_dsi1_pll PCLK_MUX_1_CLK>, + <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, + <&mdss_dsi1_pll PCLK_SRC_1_CLK>, + <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; + + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -129,6 +198,8 @@ vddio-supply = <&pm8150_l14>; vdd-supply = <&pm8150a_l11>; avdd-supply = <&display_panel_avdd>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; @@ -145,8 +216,8 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; @@ -186,6 +257,18 @@ }; /* PHY TIMINGS REVISION W */ +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; @@ -194,6 +277,14 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <552424501 549895420 547366339>; + + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 @@ -203,6 +294,24 @@ qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 180 180 180 1440 180>; }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1e 05 + 05 03 02 04 00 12 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 1e 1e 04 + 04 02 02 04 00 10 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; }; }; @@ -218,6 +327,15 @@ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; qcom,mdss-dsi-min-refresh-rate = <55>; qcom,mdss-dsi-max-refresh-rate = <60>; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <534712320 532484352 530256384>; + + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 @@ -236,6 +354,7 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 @@ -244,12 +363,14 @@ qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 270 270 270 1080 270>; + qcom,mdss-dsi-panel-clockrate = <400000000>; }; }; }; &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 @@ -261,6 +382,7 @@ }; &dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 @@ -271,8 +393,94 @@ }; }; +&dsi_sharp_qsync_wqhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03 + 03 01 02 04 00 0c 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@1 { /* WQHD 60FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 + 06 03 02 04 00 13 15]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* FHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02 + 02 00 02 04 00 0a 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + + timing@3 { /* WQHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 1e 1e 04 + 04 02 02 04 00 0f 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@4 { /* WQHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05 + 05 03 02 04 00 12 14]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@5 { /* WQHD 120FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 + 06 03 02 04 00 13 15]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 04 02 02 04 00 0e 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + + timing@7 { /* FHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 + 02 01 02 04 00 0c 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + }; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 + 06 03 02 04 00 13 15]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_1080_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 @@ -286,6 +494,7 @@ &dsi_dual_nt35597_truly_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 @@ -298,6 +507,7 @@ }; &dsi_dual_nt35597_truly_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-min-refresh-rate = <53>; qcom,mdss-dsi-max-refresh-rate = <60>; qcom,mdss-dsi-pan-enable-dynamic-fps; @@ -315,6 +525,8 @@ &dsi_nt35695b_truly_fhd_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 @@ -326,6 +538,8 @@ }; &dsi_nt35695b_truly_fhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 @@ -338,6 +552,7 @@ &dsi_sim_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 @@ -345,6 +560,8 @@ qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; }; timing@1 { @@ -353,6 +570,8 @@ qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; }; timing@2 { @@ -388,6 +607,7 @@ }; &dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 @@ -401,6 +621,7 @@ &dsi_sim_dsc_375_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* 1080p */ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 @@ -422,6 +643,7 @@ &dsi_sim_dsc_10b_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* QHD 60fps */ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 @@ -450,6 +672,7 @@ &dsi_dual_sim_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 @@ -476,6 +699,7 @@ }; &dsi_dual_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 @@ -489,24 +713,123 @@ &dsi_dual_sim_dsc_375_cmd { qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { - timing@0 { /* qhd */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 04 02 02 04 00 0e 13]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; - timing@1 { /* 4k */ - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 + 06 04 02 04 00 15 16]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; - timing@2 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 46 13 14 33 30 12 - 14 0e 02 04 00 37 22]; + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 09 + 09 06 02 04 00 1c 19]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4k 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 29 27 0c + 0c 08 02 04 00 24 1b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 01 02 04 00 0a 11]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 + 02 01 02 04 00 0c 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 03 02 02 04 00 0e 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1e 1e 04 + 04 02 02 04 00 10 14]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 + 02 01 02 04 00 0b 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 1e 1d 04 + 04 02 02 04 00 0f 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05 + 05 03 02 04 00 12 15]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07 + 06 04 02 04 00 15 16]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07 + 07 04 02 04 00 16 16]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1a 1a 01 + 01 00 02 04 00 08 11]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 01 02 04 00 0a 11]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 + 02 01 02 04 00 0b 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 + 03 01 02 04 00 0c 12]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; @@ -515,6 +838,7 @@ &dsi_sim_sec_hd_cmd { qcom,ulps-enabled; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 diff --git a/display/kona-sde-pll.dtsi b/display/kona-sde-pll.dtsi index e6bda66f50ac..8c9a152fed57 100644 --- a/display/kona-sde-pll.dtsi +++ b/display/kona-sde-pll.dtsi @@ -6,12 +6,14 @@ #clock-cells = <1>; reg = <0xae94900 0x260>, <0xae94400 0x800>, - <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", "gdsc_base"; + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "pll_base", "phy_base", "gdsc_base", + "dynamic_pll_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; - gdsc-supply = <&mdss_core_gdsc>; + memory-region = <&dfps_data_memory>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; qcom,platform-supply-entries { @@ -35,12 +37,13 @@ #clock-cells = <1>; reg = <0xae96900 0x260>, <0xae96400 0x800>, - <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", "gdsc_base"; + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "pll_base", "phy_base", "gdsc_base", + "dynamic_pll_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; - gdsc-supply = <&mdss_core_gdsc>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; qcom,platform-supply-entries { @@ -66,10 +69,16 @@ reg = <0x088ea000 0x200>, <0x088eaa00 0x200>, <0x088ea200 0x200>, + <0x088ea2b8 0x8>, + <0x088ea2e8 0x4>, <0x088ea600 0x200>, + <0x088ea6b8 0x8>, + <0x088ea6e8 0x4>, <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", "ln_tx0_base", - "ln_tx1_base", "gdsc_base"; + reg-names = "pll_base", "phy_base", + "ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base", + "ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base", + "gdsc_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_rpmh RPMH_CXO_CLK>, diff --git a/display/kona-sde.dtsi b/display/kona-sde.dtsi index d6a849eb4925..7c332fb5b40e 100644 --- a/display/kona-sde.dtsi +++ b/display/kona-sde.dtsi @@ -95,6 +95,7 @@ qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1 4 3>; qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x30e0 0x30e0>; @@ -160,8 +161,8 @@ qcom,sde-max-dest-scaler-output-linewidth = <2560>; qcom,sde-max-bw-low-kbps = <13700000>; qcom,sde-max-bw-high-kbps = <16600000>; - qcom,sde-min-core-ib-kbps = <2400000>; - qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-core-ib-kbps = <4800000>; + qcom,sde-min-llcc-ib-kbps = <0>; qcom,sde-min-dram-ib-kbps = <800000>; qcom,sde-dram-channels = <2>; qcom,sde-num-nrt-paths = <0>; @@ -247,7 +248,7 @@ qcom,sde-dspp-hist = <0x800 0x00010007>; qcom,sde-dspp-sixzone= <0x900 0x00010007>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040001>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; qcom,sde-dspp-pcc = <0x1700 0x00040000>; qcom,sde-dspp-gc = <0x17c0 0x00010008>; qcom,sde-dspp-dither = <0x82c 0x00010007>; @@ -321,7 +322,6 @@ <0x88ea200 0x200>, <0x88ea600 0x200>, <0xaf02000 0x1a0>, - <0x780000 0x621c>, <0x88ea040 0x10>, <0x88e8000 0x20>, <0x0aee1000 0x034>, @@ -329,7 +329,7 @@ /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "qfprom_physical", "dp_pll", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1"; interrupt-parent = <&mdss_mdp>; @@ -454,6 +454,17 @@ <20000 20512 0 6400000>, <20000 20512 0 6400000>; }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "disp_rsc_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 150000>, + <1 590 0 300000>; + }; }; mdss_rotator: qcom,mdss_rotator@aea8800 { @@ -520,7 +531,8 @@ smmu_rot_unsec: qcom,smmu_rot_unsec_cb { compatible = "qcom,smmu_sde_rot_unsec"; iommus = <&apps_smmu 0x215C 0x0400>; - qcom,iommu-dma = "disabled"; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; }; }; @@ -528,6 +540,7 @@ compatible = "qcom,dsi-ctrl-hw-v2.4"; label = "dsi-ctrl-0"; cell-index = <0>; + frame-threshold-time-us = <800>; reg = <0xae94000 0x400>, <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; @@ -577,6 +590,7 @@ compatible = "qcom,dsi-ctrl-hw-v2.4"; label = "dsi-ctrl-1"; cell-index = <1>; + frame-threshold-time-us = <800>; reg = <0xae96000 0x400>, <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; @@ -625,8 +639,9 @@ compatible = "qcom,dsi-phy-v4.1"; label = "dsi-phy-0"; cell-index = <0>; - reg = <0xae94400 0x760>; - reg-names = "dsi_phy"; + reg = <0xae94400 0x7c0>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "dyn_refresh_base"; vdda-0p9-supply = <&pm8150_l5>; qcom,platform-strength-ctrl = [55 03 55 03 @@ -657,8 +672,9 @@ compatible = "qcom,dsi-phy-v4.1"; label = "dsi-phy-1"; cell-index = <1>; - reg = <0xae96400 0x760>; - reg-names = "dsi_phy"; + reg = <0xae96400 0x7c0>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "dyn_refresh_base"; vdda-0p9-supply = <&pm8150_l5>; qcom,platform-strength-ctrl = [55 03 55 03 From 50c6b08a4f42bc0708e880afd048fc15e011cd53 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Tue, 26 Nov 2019 14:24:19 -0800 Subject: [PATCH 005/362] ARM: dts: msm: snapshot change for lahaina target This snapshot change brings all the device tree entries for lahaina display driver. Change-Id: I3677b0227c3330d2d4bfe09172ffae519883fac2 --- display/lahaina-sde-display-cdp-lcd.dtsi | 155 +++++ display/lahaina-sde-display-cdp.dtsi | 174 +++++ display/lahaina-sde-display-mtp.dtsi | 90 +++ display/lahaina-sde-display-qrd.dtsi | 79 +++ display/lahaina-sde-display-rumi.dtsi | 1 + display/lahaina-sde-display.dtsi | 852 +++++++++++++++++++++++ display/lahaina-sde-pll.dtsi | 91 +++ display/lahaina-sde.dtsi | 704 +++++++++++++++++++ 8 files changed, 2146 insertions(+) create mode 100644 display/lahaina-sde-display-cdp-lcd.dtsi create mode 100644 display/lahaina-sde-display-cdp.dtsi create mode 100644 display/lahaina-sde-display-mtp.dtsi create mode 100644 display/lahaina-sde-display-qrd.dtsi create mode 100644 display/lahaina-sde-display-rumi.dtsi create mode 100644 display/lahaina-sde-display.dtsi create mode 100644 display/lahaina-sde-pll.dtsi create mode 100644 display/lahaina-sde.dtsi diff --git a/display/lahaina-sde-display-cdp-lcd.dtsi b/display/lahaina-sde-display-cdp-lcd.dtsi new file mode 100644 index 000000000000..6360807c9608 --- /dev/null +++ b/display/lahaina-sde-display-cdp-lcd.dtsi @@ -0,0 +1,155 @@ +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-qsync-min-refresh-rate = <55>; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sharp_1080_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_dual_nt35597_truly_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; +}; + +&sde_dsi { + /delete-property/ avdd-supply; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>; +}; + +&sde_dsi1 { + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; +}; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi new file mode 100644 index 000000000000..c432cb7b2965 --- /dev/null +++ b/display/lahaina-sde-display-cdp.dtsi @@ -0,0 +1,174 @@ +#include "kona-sde-display.dtsi" + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-en-gpio = <&tlmm 60 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-en-gpio = <&tlmm 60 0>; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-en-gpio = <&tlmm 60 0>; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-en-gpio = <&tlmm 60 0>; +}; + +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-sec-reset-gpio = <&tlmm 128 0>; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-sec-reset-gpio = <&tlmm 128 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; +}; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi new file mode 100644 index 000000000000..ad378d6b0ddf --- /dev/null +++ b/display/lahaina-sde-display-mtp.dtsi @@ -0,0 +1,90 @@ +#include "kona-sde-display.dtsi" + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-sec-reset-gpio = <&tlmm 128 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; +}; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi new file mode 100644 index 000000000000..2c8a7bc52ec0 --- /dev/null +++ b/display/lahaina-sde-display-qrd.dtsi @@ -0,0 +1,79 @@ +#include "kona-sde-display.dtsi" + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; +}; diff --git a/display/lahaina-sde-display-rumi.dtsi b/display/lahaina-sde-display-rumi.dtsi new file mode 100644 index 000000000000..3eb83e40a9c0 --- /dev/null +++ b/display/lahaina-sde-display-rumi.dtsi @@ -0,0 +1 @@ +#include "kona-sde-display.dtsi" diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi new file mode 100644 index 000000000000..a477f44fffc0 --- /dev/null +++ b/display/lahaina-sde-display.dtsi @@ -0,0 +1,852 @@ +#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" +#include "dsi-panel-sharp-qsync-wqhd-video.dtsi" +#include "dsi-panel-sharp-1080p-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include + +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3300000>; + qcom,supply-max-voltage = <3300000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_lab_ibb: dsi_panel_pwr_supply_lab_ibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + + display_panel_avdd: display_gpio_regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 61 0>; + enable-active-high; + regulator-boot-on; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>, + <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, + <&mdss_dsi1_pll PCLK_SRC_1_CLK>, + <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; + + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&pm8150_l14>; + vdd-supply = <&pm8150a_l11>; + avdd-supply = <&display_panel_avdd>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 67 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&pm8150_l14>; + vdd-supply = <&pm8150a_l11>; + avdd-supply = <&display_panel_avdd>; + + qcom,mdp = <&mdss_mdp>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dp { + qcom,dp-usbpd-detection = <&pm8150b_pdphy>; + qcom,ext-disp = <&ext_disp>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,usbplug-cc-gpio = <&tlmm 65 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&sde_dp_usbplug_cc_active>; + pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; +}; + +&mdss_mdp { + connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; +}; + +/* PHY TIMINGS REVISION W */ +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <552424501 549895420 547366339>; + + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 + 05 03 02 04 00 12 15]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1e 05 + 05 03 02 04 00 12 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 1e 1e 04 + 04 02 02 04 00 10 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; + }; +}; + +&dsi_sw43404_amoled_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 57 55>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; + qcom,mdss-dsi-min-refresh-rate = <55>; + qcom,mdss-dsi-max-refresh-rate = <60>; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <534712320 532484352 530256384>; + + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 + 05 03 02 04 00 12 15]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 + 05 02 03 04 00 11 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 270 270 270 1080 270>; + qcom,mdss-dsi-panel-clockrate = <400000000>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03 + 03 01 02 04 00 0c 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@1 { /* WQHD 60FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 + 06 03 02 04 00 13 15]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* FHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02 + 02 00 02 04 00 0a 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + + timing@3 { /* WQHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 1e 1e 04 + 04 02 02 04 00 0f 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@4 { /* WQHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05 + 05 03 02 04 00 12 14]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@5 { /* WQHD 120FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 + 06 03 02 04 00 13 15]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 04 02 02 04 00 0e 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + + timing@7 { /* FHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 + 02 01 02 04 00 0c 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + }; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 + 06 03 02 04 00 13 15]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_1080_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-panel-clockrate = <900000000>; + }; + }; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-min-refresh-rate = <53>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 1080 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 + 09 06 02 04 00 18 17]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 04 02 02 04 00 0e 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 + 06 04 02 04 00 15 16]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 09 + 09 06 02 04 00 1c 19]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4k 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 29 27 0c + 0c 08 02 04 00 24 1b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 01 02 04 00 0a 11]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 + 02 01 02 04 00 0c 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 03 02 02 04 00 0e 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1e 1e 04 + 04 02 02 04 00 10 14]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 + 02 01 02 04 00 0b 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 1e 1d 04 + 04 02 02 04 00 0f 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05 + 05 03 02 04 00 12 15]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07 + 06 04 02 04 00 15 16]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07 + 07 04 02 04 00 16 16]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1a 1a 01 + 01 00 02 04 00 08 11]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 01 02 04 00 0a 11]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 + 02 01 02 04 00 0b 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 + 03 01 02 04 00 0c 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; diff --git a/display/lahaina-sde-pll.dtsi b/display/lahaina-sde-pll.dtsi new file mode 100644 index 000000000000..8c9a152fed57 --- /dev/null +++ b/display/lahaina-sde-pll.dtsi @@ -0,0 +1,91 @@ +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 { + compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94900 0x260>, + <0xae94400 0x800>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "pll_base", "phy_base", "gdsc_base", + "dynamic_pll_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + memory-region = <&dfps_data_memory>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 { + compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96900 0x260>, + <0xae96400 0x800>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "pll_base", "phy_base", "gdsc_base", + "dynamic_pll_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@c011000 { + compatible = "qcom,mdss_dp_pll_7nm"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x088ea000 0x200>, + <0x088eaa00 0x200>, + <0x088ea200 0x200>, + <0x088ea2b8 0x8>, + <0x088ea2e8 0x4>, + <0x088ea600 0x200>, + <0x088ea6b8 0x8>, + <0x088ea6e8 0x4>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", + "ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base", + "ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base", + "gdsc_base"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "iface_clk", "ref_clk_src", + "gcc_iface", "pipe_clk"; + clock-rate = <0>; + }; +}; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi new file mode 100644 index 000000000000..7c332fb5b40e --- /dev/null +++ b/display/lahaina-sde.dtsi @@ -0,0 +1,704 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84208>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x214>, + <0x0ae8f000 0x02c>, + <0x0af50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys", + "swfuse_phys"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000 + 460000000>; + + mmcx-supply = <&VDD_MMCX_LEVEL>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800 0x2a00>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "cwb", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000 0x72800 0x73000 0x73800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; + + qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1 4 3>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 4 8 12 + 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4400000 4400000 + 4400000 4400000 + 4400000 4400000 + 4400000 4400000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5300000 5300000 + 5300000 5300000 + 5300000 5300000 + 5300000 5300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x3>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-has-idle-pc; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <13700000>; + qcom,sde-max-bw-high-kbps = <16600000>; + qcom,sde-min-core-ib-kbps = <4800000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x000000ff 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + qcom,sde-safe-lut-macrotile = <0 0xff00>; + /* same as safe-lut-macrotile */ + qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0x3ff>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x4000821>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 150000>, + <1 590 0 300000>; + }; + }; + + sde_dp: qcom,dp_display@ae90000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + vdda-1p2-supply = <&pm8150_l9>; + vdda-0p9-supply = <&pm8150_l18>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x88ea040 0x10>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>; + /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", + "usb3_dp_com", "hdcp_physical", "dp_p1"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "pixel1_parent", + "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,phy-version = <0x420>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,mst-enable; + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-input-width-pixs = <2048>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <33000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <126000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x3c50>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <3>; + + qcom,sde-dram-channels = <2>; + + vdd-supply = <&mdss_core_gdsc>; + clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "disp_rsc_mnoc_llcc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <20003 20513 0 0>, <20004 20513 0 0>, + <20003 20513 0 6400000>, <20004 20513 0 6400000>, + <20003 20513 0 6400000>, <20004 20513 0 6400000>; + }; + + qcom,sde-ebi-bus { + qcom,msm-bus,name = "disp_rsc_ebi"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20000 20512 0 0>, + <20000 20512 0 6400000>, + <20000 20512 0 6400000>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "disp_rsc_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 150000>, + <1 590 0 300000>; + }; + }; + + mdss_rotator: qcom,mdss_rotator@aea8800 { + compatible = "qcom,sde_rotator"; + reg = <0x0ae00000 0xac000>, + <0x0aeb8000 0x3000>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + status = "disabled"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x3>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <25 512 0 0>, + <25 512 0 6400000>, + <25 512 0 6400000>; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-vbif-memtype = <3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x215C 0x0400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&pm8150_l9>; + refgen-supply = <&refgen>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <26700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + vdda-1p2-supply = <&pm8150_l9>; + refgen-supply = <&refgen>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <26700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { + compatible = "qcom,dsi-phy-v4.1"; + label = "dsi-phy-0"; + cell-index = <0>; + reg = <0xae94400 0x7c0>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "dyn_refresh_base"; + vdda-0p9-supply = <&pm8150_l5>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <46000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 { + compatible = "qcom,dsi-phy-v4.1"; + label = "dsi-phy-1"; + cell-index = <1>; + reg = <0xae96400 0x7c0>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "dyn_refresh_base"; + vdda-0p9-supply = <&pm8150_l5>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <46000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + +}; From a439d30fc9e968a0a5b143052bbc36ef7aca313a Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Thu, 5 Dec 2019 19:11:43 -0800 Subject: [PATCH 006/362] ARM: dts: msm: add lahaina offsets This change adds lahaina display HW sub-block offsets. Change-Id: I39510040d2adbcbd9d216f7f5abe1fe675214bf5 --- display/lahaina-sde-display-mtp.dtsi | 2 +- display/lahaina-sde-display-qrd.dtsi | 2 +- display/lahaina-sde.dtsi | 35 ++++++++++++++-------------- 3 files changed, 20 insertions(+), 19 deletions(-) diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index ad378d6b0ddf..5b09d3bd35ad 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -1,4 +1,4 @@ -#include "kona-sde-display.dtsi" +#include "lahaina-sde-display.dtsi" &dsi_sw43404_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 2c8a7bc52ec0..7ed5ce310868 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -1,4 +1,4 @@ -#include "kona-sde-display.dtsi" +#include "lahaina-sde-display.dtsi" &dsi_sw43404_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 7c332fb5b40e..095154242c23 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -3,7 +3,7 @@ &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; - reg = <0x0ae00000 0x84208>, + reg = <0x0ae00000 0x84000>, <0x0aeb0000 0x2008>, <0x0aeac000 0x214>, <0x0ae8f000 0x02c>, @@ -43,9 +43,9 @@ qcom,sde-off = <0x1000>; qcom,sde-len = <0x494>; - qcom,sde-ctl-off = <0x2000 0x2200 0x2400 - 0x2600 0x2800 0x2a00>; - qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000 0x1a000>; + qcom,sde-ctl-size = <0x1e8>; qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none"; @@ -74,21 +74,20 @@ qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-intf-off = <0x6b000 0x6b800 - 0x6c000 0x6c800>; - qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-off = <0x35000 0x36000 + 0x37000 0x38000>; + qcom,sde-intf-size = <0x2c0>; qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; - qcom,sde-pp-off = <0x71000 0x71800 - 0x72000 0x72800 0x73000 0x73800>; + qcom,sde-pp-off = <0x6a000 0x6b000 + 0x6c000 0x6d000 0x6e000 0x6f000>; qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; qcom,sde-pp-size = <0xd4>; qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; - qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>; - qcom,sde-merge-3d-size = <0x100>; - - qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>; + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>; + qcom,sde-merge-3d-size = <0x10>; qcom,sde-cdm-off = <0x7a200>; qcom,sde-cdm-size = <0x224>; @@ -97,8 +96,8 @@ qcom,sde-dsc-size = <0x140>; qcom,sde-dsc-pair-mask = <2 1 4 3>; - qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 - 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-off = <0xe0 0xe0 0xe0 + 0xe0 0xe0 0xe0>; qcom,sde-dither-version = <0x00010000>; qcom,sde-dither-size = <0x20>; @@ -168,7 +167,7 @@ qcom,sde-num-nrt-paths = <0>; qcom,sde-dspp-ltm-version = <0x00010000>; /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; + qcom,sde-dspp-ltm-off = <0x15300 0x14300>; qcom,sde-uidle-off = <0x80000>; qcom,sde-uidle-size = <0x70>; @@ -314,6 +313,7 @@ vdda-1p2-supply = <&pm8150_l9>; vdda-0p9-supply = <&pm8150_l18>; + reg = <0xae90000 0x0dc>, <0xae90200 0x0c0>, <0xae90400 0x508>, @@ -427,6 +427,7 @@ qcom,sde-dram-channels = <2>; vdd-supply = <&mdss_core_gdsc>; + clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; @@ -467,7 +468,7 @@ }; }; - mdss_rotator: qcom,mdss_rotator@aea8800 { + mdss_rotator: qcom,mdss_rotator@aea9000 { compatible = "qcom,sde_rotator"; reg = <0x0ae00000 0xac000>, <0x0aeb8000 0x3000>; From 0f113bdb93b7cf2276e85037b138523338ff476b Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Thu, 5 Dec 2019 19:16:47 -0800 Subject: [PATCH 007/362] ARM: dts: msm: fix device tree for validating wb on lahaina This change adds gdsc voting from mdss_mdp until display rscc is enabled and also removes interface clocks until the dsi interface validation is completed. Change-Id: Ia2841b147fc9b71c2c20d6266b48f7f5ca5d4667 --- display/lahaina-sde-display-rumi.dtsi | 2 +- display/lahaina-sde-display.dtsi | 43 +-------------------------- display/lahaina-sde.dtsi | 36 +++++++++++----------- 3 files changed, 20 insertions(+), 61 deletions(-) diff --git a/display/lahaina-sde-display-rumi.dtsi b/display/lahaina-sde-display-rumi.dtsi index 3eb83e40a9c0..01d0c4119d6c 100644 --- a/display/lahaina-sde-display-rumi.dtsi +++ b/display/lahaina-sde-display-rumi.dtsi @@ -1 +1 @@ -#include "kona-sde-display.dtsi" +#include "lahaina-sde-display.dtsi" diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index a477f44fffc0..b2111479ca12 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -168,38 +168,12 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, - <&mdss_dsi0_pll PCLK_SRC_0_CLK>, - <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>, - <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>, - <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, - <&mdss_dsi1_pll PCLK_SRC_1_CLK>, - <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; - - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; qcom,platform-te-gpio = <&tlmm 66 0>; qcom,panel-te-source = <0>; - vddio-supply = <&pm8150_l14>; - vdd-supply = <&pm8150a_l11>; avdd-supply = <&display_panel_avdd>; - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; @@ -212,22 +186,11 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; qcom,platform-te-gpio = <&tlmm 67 0>; qcom,panel-te-source = <1>; - vddio-supply = <&pm8150_l14>; - vdd-supply = <&pm8150a_l11>; avdd-supply = <&display_panel_avdd>; qcom,mdp = <&mdss_mdp>; @@ -241,19 +204,15 @@ }; &sde_dp { - qcom,dp-usbpd-detection = <&pm8150b_pdphy>; qcom,ext-disp = <&ext_disp>; - qcom,dp-aux-switch = <&fsa4480>; qcom,usbplug-cc-gpio = <&tlmm 65 0>; pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; - pinctrl-0 = <&sde_dp_usbplug_cc_active>; - pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; }; &mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; + connectors = <&sde_wb>; }; /* PHY TIMINGS REVISION W */ diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 095154242c23..064acfdf25bd 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -31,14 +31,13 @@ 460000000>; mmcx-supply = <&VDD_MMCX_LEVEL>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; /* interrupt config */ interrupts = ; interrupt-controller; #interrupt-cells = <1>; - #power-domain-cells = <0>; - /* hw blocks */ qcom,sde-off = <0x1000>; qcom,sde-len = <0x494>; @@ -265,6 +264,15 @@ qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; + + qcom,platform-supply-entry@1 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; }; smmu_sde_unsec: qcom,smmu_sde_unsec_cb { @@ -309,10 +317,7 @@ sde_dp: qcom,dp_display@ae90000 { cell-index = <0>; compatible = "qcom,dp-display"; - - vdda-1p2-supply = <&pm8150_l9>; - vdda-0p9-supply = <&pm8150_l18>; - + status = "disabled"; reg = <0xae90000 0x0dc>, <0xae90200 0x0c0>, @@ -341,15 +346,12 @@ <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_iface_clk", - "pixel_clk_rcg", "pixel_parent", - "pixel1_clk_rcg", "pixel1_parent", + "pixel_clk_rcg", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,phy-version = <0x420>; @@ -419,6 +421,7 @@ sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; + status = "disabled"; reg = <0xaf20000 0x3c50>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; @@ -426,7 +429,7 @@ qcom,sde-dram-channels = <2>; - vdd-supply = <&mdss_core_gdsc>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, @@ -490,7 +493,6 @@ <25 512 0 6400000>, <25 512 0 6400000>; - rot-vdd-supply = <&mdss_core_gdsc>; qcom,supply-names = "rot-vdd"; clocks = @@ -546,9 +548,8 @@ <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; + status = "disabled"; interrupts = <4 0>; - vdda-1p2-supply = <&pm8150_l9>; - refgen-supply = <&refgen>; clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -596,9 +597,8 @@ <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; + status = "disabled"; interrupts = <5 0>; - vdda-1p2-supply = <&pm8150_l9>; - refgen-supply = <&refgen>; clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, @@ -643,7 +643,7 @@ reg = <0xae94400 0x7c0>, <0xae94200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; - vdda-0p9-supply = <&pm8150_l5>; + status = "disabled"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 @@ -676,7 +676,7 @@ reg = <0xae96400 0x7c0>, <0xae96200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; - vdda-0p9-supply = <&pm8150_l5>; + status = "disabled"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 From c1b3d005b930fbc3ee667dd0f21b0f569a86b2c3 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 15 Nov 2019 10:49:23 +0800 Subject: [PATCH 008/362] ARM: dts: msm: set ICB bus node for mdss Enable bus scaling for SDE and rotator. Add the new DT nodes according to the ICB bus framework. Change-Id: Id9180ae991201963dd3bf6edd5a4fc783624e1c3 --- display/lahaina-sde.dtsi | 84 ++++++++++------------------------------ 1 file changed, 20 insertions(+), 64 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 064acfdf25bd..a15358489303 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -214,6 +214,15 @@ qcom,sde-secure-sid-mask = <0x4000821>; + /* data and reg bus scale settings */ + interconnects = + <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; @@ -291,27 +300,6 @@ qcom,iommu-vmid = <0xa>; }; - /* data and reg bus scale settings */ - qcom,sde-data-bus { - qcom,msm-bus,name = "mdss_sde"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>; - }; - - qcom,sde-reg-bus { - qcom,msm-bus,name = "mdss_reg"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 150000>, - <1 590 0 300000>; - }; }; sde_dp: qcom,dp_display@ae90000 { @@ -435,40 +423,10 @@ <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; - - /* data and reg bus scale settings */ - qcom,sde-data-bus { - qcom,msm-bus,name = "disp_rsc_mnoc_llcc"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <20003 20513 0 0>, <20004 20513 0 0>, - <20003 20513 0 6400000>, <20004 20513 0 6400000>, - <20003 20513 0 6400000>, <20004 20513 0 6400000>; - }; - - qcom,sde-ebi-bus { - qcom,msm-bus,name = "disp_rsc_ebi"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <20000 20512 0 0>, - <20000 20512 0 6400000>, - <20000 20512 0 6400000>; - }; - - qcom,sde-reg-bus { - qcom,msm-bus,name = "disp_rsc_reg"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 150000>, - <1 590 0 300000>; - }; + interconnects = + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-reg-bus"; }; mdss_rotator: qcom,mdss_rotator@aea9000 { @@ -483,15 +441,13 @@ qcom,mdss-rot-mode = <1>; qcom,mdss-highest-bank-bit = <0x3>; - - /* Bus Scale Settings */ - qcom,msm-bus,name = "mdss_rotator"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <25 512 0 0>, - <25 512 0 6400000>, - <25 512 0 6400000>; + interconnects = + <&mmss_noc MASTER_ROTATOR &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,rot-data-bus0", + "qcom,sde-reg-bus"; + qcom,msm-bus,active-only; qcom,supply-names = "rot-vdd"; From 7dac15bb951768af3769c15ed4688fedc32485f2 Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Tue, 26 Nov 2019 16:24:14 -0800 Subject: [PATCH 009/362] disp: add binding documentation for sde-intf-tear-irq-off Add documentation for the new SDE device tree node which gives the INTF TE IRQ offsets. This is required for TE support on all targets with refactored interrupt support (kernel 5.4+). Change-Id: I8bae73b1407e39c9dcf2ee95a2e0d7aed1e50fd2 Signed-off-by: Steve Cohen --- bindings/sde.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index a09486452287..e741494a2735 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -193,6 +193,10 @@ Optional properties: "hdmi" - HDMI display interface An interface is considered as "none" if interface type is not defined. +- qcom,sde-intf-tear-irq-off Array of offset addresses for the available + tear effect (TE) IRQ blocks from "mdp_phys". + There should be one entry per INTF instance with + a zero value for INTFs without TE IRQ block. - qcom,sde-off: SDE offset from "mdp_phys" defined in reg property. - qcom,sde-cdm-off: Array of offset addresses for the available cdm blocks. These offsets will be calculated from @@ -579,6 +583,7 @@ Example: qcom,sde-intf-off = <0x0006b000 0x0006b800 0x0006c000 0x0006c800>; qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; qcom,sde-pp-off = <0x00071000 0x00071800 0x00072000 0x00072800>; qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; From f8497c2209c5246cb4ad1b0c2c3deb5a18b8ecd6 Mon Sep 17 00:00:00 2001 From: Shashank Babu Chinta Venkata Date: Thu, 19 Dec 2019 16:02:12 -0800 Subject: [PATCH 010/362] ARM: dts: msm: enable DSI for Lahaina target Enable DSI probe by adding panel and regulators for Lahaina target. Change-Id: I5e4c4ef2084944eb6fb4fb787b6400fb4d7c1ed6 --- display/lahaina-sde-display-cdp.dtsi | 170 +----- display/lahaina-sde-display-mtp.dtsi | 83 +-- display/lahaina-sde-display-rumi.dtsi | 10 + display/lahaina-sde-display.dtsi | 764 +------------------------- display/lahaina-sde-pll.dtsi | 91 --- display/lahaina-sde.dtsi | 52 +- 6 files changed, 64 insertions(+), 1106 deletions(-) delete mode 100644 display/lahaina-sde-pll.dtsi diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index c432cb7b2965..0876d9f6200b 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -1,174 +1,12 @@ -#include "kona-sde-display.dtsi" - -&dsi_sw43404_amoled_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; -}; - -&dsi_sw43404_amoled_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; -}; - -&dsi_sw43404_amoled_fhd_plus_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; -}; - -&dsi_sharp_4k_dsc_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-en-gpio = <&tlmm 60 0>; -}; - -&dsi_sharp_4k_dsc_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-en-gpio = <&tlmm 60 0>; -}; - -&dsi_sharp_qsync_wqhd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-en-gpio = <&tlmm 60 0>; -}; - -&dsi_sharp_qsync_wqhd_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-en-gpio = <&tlmm 60 0>; -}; - -&dsi_sharp_1080_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_nt35597_truly_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_nt35695b_truly_fhd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-sec-reset-gpio = <&tlmm 128 0>; -}; - -&dsi_nt35695b_truly_fhd_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; +#include "lahaina-sde-display.dtsi" &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_sec_hd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-sec-reset-gpio = <&tlmm 128 0>; + qcom,platform-reset-gpio = <&tlmm 25 0>; }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_dual_sim_vid>; }; + diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 5b09d3bd35ad..df5b48fbbdea 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -1,90 +1,11 @@ #include "lahaina-sde-display.dtsi" -&dsi_sw43404_amoled_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; -}; - -&dsi_sw43404_amoled_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; -}; - -&dsi_sw43404_amoled_fhd_plus_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; -}; - -&dsi_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_sec_hd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-sec-reset-gpio = <&tlmm 128 0>; + qcom,platform-reset-gpio = <&tlmm 25 0>; }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_dual_sim_vid>; }; diff --git a/display/lahaina-sde-display-rumi.dtsi b/display/lahaina-sde-display-rumi.dtsi index 01d0c4119d6c..df5b48fbbdea 100644 --- a/display/lahaina-sde-display-rumi.dtsi +++ b/display/lahaina-sde-display-rumi.dtsi @@ -1 +1,11 @@ #include "lahaina-sde-display.dtsi" + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 25 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_dual_sim_vid>; +}; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index b2111479ca12..35751222ebda 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -19,23 +19,7 @@ #include "dsi-panel-sim-dualmipi-video.dtsi" #include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" #include "dsi-panel-sim-sec-hd-cmd.dtsi" -#include - -&tlmm { - display_panel_avdd_default: display_panel_avdd_default { - mux { - pins = "gpio61"; - function = "gpio"; - }; - - config { - pins = "gpio61"; - drive-strength = <8>; - bias-disable = <0>; - output-high; - }; - }; -}; +#include &soc { ext_disp: qcom,msm-ext-disp { @@ -46,121 +30,6 @@ }; }; - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <62000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <3300000>; - qcom,supply-max-voltage = <3300000>; - qcom,supply-enable-load = <857000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - }; - - qcom,panel-supply-entry@3 { - reg = <3>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - dsi_panel_pwr_supply_lab_ibb: dsi_panel_pwr_supply_lab_ibb { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <62000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <62000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "avdd"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - }; - }; - - display_panel_avdd: display_gpio_regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "display_panel_avdd"; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 61 0>; - enable-active-high; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&display_panel_avdd_default>; - }; - sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; @@ -168,32 +37,22 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - pinctrl-names = "panel_active", "panel_suspend"; + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; - qcom,platform-te-gpio = <&tlmm 66 0>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 82 0>; qcom,panel-te-source = <0>; - avdd-supply = <&display_panel_avdd>; - - qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; - }; - - sde_dsi1: qcom,dsi-display-secondary { - compatible = "qcom,dsi-display"; - label = "secondary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - pinctrl-names = "panel_active", "panel_suspend"; - - qcom,platform-te-gpio = <&tlmm 67 0>; - qcom,panel-te-source = <1>; - - avdd-supply = <&display_panel_avdd>; - qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_dual_sim_vid>; }; sde_wb: qcom,wb-display@0 { @@ -203,609 +62,20 @@ }; }; -&sde_dp { - qcom,ext-disp = <&ext_disp>; - - qcom,usbplug-cc-gpio = <&tlmm 65 0>; - - pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; -}; - &mdss_mdp { - connectors = <&sde_wb>; -}; - -/* PHY TIMINGS REVISION W */ -&dsi_ext_bridge_1080p { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sw43404_amoled_cmd { - qcom,ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-list = <552424501 549895420 547366339>; - - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 - 05 03 02 04 00 12 15]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 180 180 180 1440 180>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1e 05 - 05 03 02 04 00 12 14]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 180 180 180 1440 180>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 1e 1e 04 - 04 02 02 04 00 10 14]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 180 180 180 1440 180>; - }; - }; -}; - -&dsi_sw43404_amoled_video { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-supported-dfps-list = <60 57 55>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; - qcom,mdss-dsi-min-refresh-rate = <55>; - qcom,mdss-dsi-max-refresh-rate = <60>; - - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-list = - <534712320 532484352 530256384>; - - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 - 05 03 02 04 00 12 15]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sw43404_amoled_fhd_plus_cmd { - qcom,ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 - 05 02 03 04 00 11 14]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 270 270 270 1080 270>; - qcom,mdss-dsi-panel-clockrate = <400000000>; - }; - }; -}; - -&dsi_sharp_4k_dsc_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_4k_dsc_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qsync_wqhd_cmd { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* WQHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03 - 03 01 02 04 00 0c 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 8 8 8 1440 8>; - }; - - timing@1 { /* WQHD 60FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 - 06 03 02 04 00 13 15]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* FHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02 - 02 00 02 04 00 0a 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 8 8 8 1080 8>; - }; - - timing@3 { /* WQHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 1e 1e 04 - 04 02 02 04 00 0f 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 8 8 8 1440 8>; - }; - - timing@4 { /* WQHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05 - 05 03 02 04 00 12 14]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 8 8 8 1440 8>; - }; - - timing@5 { /* WQHD 120FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 - 06 03 02 04 00 13 15]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@6 { /* FHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 - 04 02 02 04 00 0e 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 8 8 8 1080 8>; - }; - - timing@7 { /* FHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 02 01 02 04 00 0c 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 8 8 8 1080 8>; - }; - }; -}; - -&dsi_sharp_qsync_wqhd_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06 - 06 03 02 04 00 13 15]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_1080_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - qcom,mdss-dsi-panel-clockrate = <900000000>; - }; - }; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_dual_nt35597_truly_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-min-refresh-rate = <53>; - qcom,mdss-dsi-max-refresh-rate = <60>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_nt35695b_truly_fhd_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 - 08 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_nt35695b_truly_fhd_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 - 08 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - - timing@3 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - qcom,panel-roi-alignment = <540 40 540 40 540 40>; - qcom,partial-update-enabled = "single_roi"; - }; - - timing@4 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - qcom,panel-roi-alignment = <360 40 360 40 360 40>; - qcom,partial-update-enabled = "single_roi"; - }; - }; -}; - -&dsi_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 0 1>, - <2 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_dsc_375_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* 1080p */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* qhd */ - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <1 1 1>, - <2 2 1>, /* dsc merge */ - <2 1 1>; /* 3d mux */ - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* QHD 60fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 1080 60fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <1 1 1>, - <2 2 1>, /* dsc merge */ - <2 1 1>; /* 3d mux */ - qcom,default-topology-index = <0>; - }; - - timing@2 { /* QHD 90fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_dual_sim_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 - 09 06 02 04 00 18 17]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - }; + connectors = <&sde_wb &sde_dsi>; }; +/* PHY TIMINGS REVISION YB */ &dsi_dual_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; + qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 + 07 07 04 02 00 14 0b]; qcom,display-topology = <2 0 2>, <1 0 2>; qcom,default-topology-index = <0>; }; }; }; - -&dsi_dual_sim_dsc_375_cmd { - qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* 4k 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 - 04 02 02 04 00 0e 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 4k 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 - 06 04 02 04 00 15 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* 4k 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 09 - 09 06 02 04 00 1c 19]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4k 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 29 27 0c - 0c 08 02 04 00 24 1b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@4 { /* 1080 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 - 01 01 02 04 00 0a 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@5 { /* 1080 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 02 01 02 04 00 0c 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@6 { /* 1080 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 - 03 02 02 04 00 0e 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@7 { /* 1080 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1e 1e 04 - 04 02 02 04 00 10 14]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@8 { /* qhd 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 - 02 01 02 04 00 0b 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@9 { /* qhd 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 1e 1d 04 - 04 02 02 04 00 0f 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@10 { /* qhd 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05 - 05 03 02 04 00 12 15]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@11 { /* qhd 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07 - 06 04 02 04 00 15 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@12 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07 - 07 04 02 04 00 16 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@13 { /* 720p 30 FPS */ - qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1a 1a 01 - 01 00 02 04 00 08 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@14 { /* 720p 60 FPS */ - qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 - 01 01 02 04 00 0a 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@15 { /* 720p 90 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 - 02 01 02 04 00 0b 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@16 { /* 720 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 03 01 02 04 00 0c 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_sec_hd_cmd { - qcom,ulps-enabled; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 - 08 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - }; -}; diff --git a/display/lahaina-sde-pll.dtsi b/display/lahaina-sde-pll.dtsi deleted file mode 100644 index 8c9a152fed57..000000000000 --- a/display/lahaina-sde-pll.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -&soc { - mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 { - compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; - label = "MDSS DSI 0 PLL"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94900 0x260>, - <0xae94400 0x800>, - <0xaf03000 0x8>, - <0xae94200 0x100>; - reg-names = "pll_base", "phy_base", "gdsc_base", - "dynamic_pll_base"; - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface_clk"; - clock-rate = <0>; - memory-region = <&dfps_data_memory>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 { - compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; - label = "MDSS DSI 1 PLL"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96900 0x260>, - <0xae96400 0x800>, - <0xaf03000 0x8>, - <0xae96200 0x100>; - reg-names = "pll_base", "phy_base", "gdsc_base", - "dynamic_pll_base"; - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface_clk"; - clock-rate = <0>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dp_pll: qcom,mdss_dp_pll@c011000 { - compatible = "qcom,mdss_dp_pll_7nm"; - label = "MDSS DP PLL"; - cell-index = <0>; - #clock-cells = <1>; - - reg = <0x088ea000 0x200>, - <0x088eaa00 0x200>, - <0x088ea200 0x200>, - <0x088ea2b8 0x8>, - <0x088ea2e8 0x4>, - <0x088ea600 0x200>, - <0x088ea6b8 0x8>, - <0x088ea6e8 0x4>, - <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", - "ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base", - "ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base", - "gdsc_base"; - - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_DISP_AHB_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "iface_clk", "ref_clk_src", - "gcc_iface", "pipe_clk"; - clock-rate = <0>; - }; -}; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index a15358489303..9ba15be5d614 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -1,4 +1,4 @@ -#include +#include &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { @@ -496,7 +496,7 @@ }; mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; + compatible = "qcom,dsi-ctrl-hw-v2.5"; label = "dsi-ctrl-0"; cell-index = <0>; frame-threshold-time-us = <800>; @@ -504,8 +504,9 @@ <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; - status = "disabled"; interrupts = <4 0>; + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -524,7 +525,7 @@ qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <26700>; + qcom,supply-enable-load = <1000>; qcom,supply-disable-load = <0>; }; }; @@ -545,7 +546,7 @@ }; mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; + compatible = "qcom,dsi-ctrl-hw-v2.5"; label = "dsi-ctrl-1"; cell-index = <1>; frame-threshold-time-us = <800>; @@ -553,8 +554,9 @@ <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; - status = "disabled"; interrupts = <5 0>; + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, @@ -572,7 +574,7 @@ qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <26700>; + qcom,supply-enable-load = <1000>; qcom,supply-disable-load = <0>; }; }; @@ -592,14 +594,18 @@ }; }; - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { - compatible = "qcom,dsi-phy-v4.1"; + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; label = "dsi-phy-0"; cell-index = <0>; - reg = <0xae94400 0x7c0>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "dyn_refresh_base"; - status = "disabled"; + #clock-cells = <1>; + reg = <0xae94900 0x77c>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0x0ae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + vdda-0p9-supply = <&L5B>; qcom,platform-strength-ctrl = [55 03 55 03 55 03 @@ -619,20 +625,24 @@ qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <46000>; + qcom,supply-enable-load = <1000>; qcom,supply-disable-load = <0>; }; }; }; - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 { - compatible = "qcom,dsi-phy-v4.1"; + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; label = "dsi-phy-1"; cell-index = <1>; - reg = <0xae96400 0x7c0>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "dyn_refresh_base"; - status = "disabled"; + #clock-cells = <1>; + reg = <0xae96900 0x77c>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0x0ae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + vdda-0p9-supply = <&L5B>; qcom,platform-strength-ctrl = [55 03 55 03 55 03 @@ -652,7 +662,7 @@ qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <46000>; + qcom,supply-enable-load = <1000>; qcom,supply-disable-load = <0>; }; }; From e956e50fef5acb71020c467ec16c14c0b63cdc19 Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Wed, 22 Jan 2020 18:49:52 -0800 Subject: [PATCH 011/362] Documentation: devicetree: add documentation for dsc hw block Add the documentation for configuring the DSC hw blocks present in the DPU. Change-Id: If2e6ab6215b17e2d5828e9384c9530884e623e47 --- bindings/sde.txt | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index e741494a2735..65dcc6b0da86 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -213,7 +213,20 @@ Optional properties: - qcom,sde-te2-off: A u32 offset indicates the te2 block offset on pingpong. - qcom,sde-te-size: A u32 value indicates the te block address range. - qcom,sde-te2-size: A u32 value indicates the te2 block address range. -- qcom,sde-dsc-off: A u32 offset indicates the dsc block offset on pingpong. +- qcom,sde-dsc-off: Array of offset addresses for the available dsc + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. +- qcom,sde-dsc-hw-rev: A string value indicates the dsc hw block + version. +- qcom,sde-dsc-enc: Array of offset addresses for the available dsc + encoder blocks. These offsets are calculated from + the corresponding DSC base. +- qcom,sde-dsc-ctl: Array of offset addresses for the available dsc + ctl blocks. These offsets are calculated from + the corresponding DSC base. +- qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc + block can support native 422 and native 420 + encoding. - qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. - qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. - qcom,sde-dither-version: A u32 value indicates the dither block version. From fa8952baab1e2bf0afa8e79246291931a2bf66bd Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Tue, 3 Dec 2019 12:38:57 -0800 Subject: [PATCH 012/362] ARM: dts: msm: add dsc 1.2 offsets on lahaina target This change adds register offsets and capabilities of different dsc hw sub-blocks in dpu for lahaina target. Change-Id: Ib0e0a5754544ad6236a56edf41c2a6ef4c10678a --- display/lahaina-sde.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 9ba15be5d614..ca8691bf457e 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -91,9 +91,13 @@ qcom,sde-cdm-off = <0x7a200>; qcom,sde-cdm-size = <0x224>; - qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; + qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>; qcom,sde-dsc-size = <0x140>; qcom,sde-dsc-pair-mask = <2 1 4 3>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>; + qcom,sde-dsc-native422-supp = <0 0 1 1>; qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; From a3d86c5a16f2378f10dd3458d216676f08bcd7a1 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 13 Jan 2020 16:57:13 -0800 Subject: [PATCH 013/362] bindings: Documentation: add documentation for VDC-m panels Add the documentation necessary for VDC-m panels to work with MSM chipsets. Change-Id: Ic2bb776fe1fbe6ff9503cb35fd1747e0316f6008 --- bindings/mdss-dsi-panel.txt | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index b6a2ac6f79e5..fbf167c62e9a 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -504,7 +504,8 @@ Optional properties: - qcom,compression-mode: Select compression mode for panel. "fbc" - frame buffer compression "dsc" - display stream compression. - If "dsc" compression is used then config subnodes needs to be defined. + "vdc" - VESA display compression. + If "dsc" or "vdc" compression is used then config subnodes needs to be defined. - qcom,panel-supply-entries: A node that lists the elements of the supply used to power the DSI panel. There can be more than one instance of this binding, in which case the entry would be appended @@ -533,6 +534,26 @@ Optional properties: - qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder. - qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps instead of standard dcs type 0x0A. +- qcom,vdc-version: An 8 bit value indicates the VDC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only VDC rev 1(Major).1(Minor) + right now. +- qcom,vdc-version-release: An 8 bit value indicated VDC version release. This has to be set to 0. +- qcom,vdc-slice-height: An u32 value which indicates slice height. This should be atleast 16 lines. +- qcom,vdc-slice-width: An u32 value which indicates slice width. This should be atleast 64 pixels and + should also be a multiple of 8 +- qcom,vdc-slice-per-pkt: An u32 value indicates the slice per dsi packet. +- qcom,vdc-bit-per-component: An u32 value indicates the bits per component before compression. +- qcom,vdc-bit-per-pixel: An u32 value indicates the bits per pixel after compression. +- qcom,src-color-space: An u32 value indicating the source color space. It can either be RGB or YUV. + Default value is assumed to be RGB + 0 - RGB + 1 - YUV +- qcom,src-chroma-format: An u32 value indicating the source color space. It can either be 444, 420 or 422. + Default value is assumed to be 444 + 0 - 444 + 1 - 422 + 2 - 420 - qcom,mdss-pps-delay-ms: An u32 value that indicates post PPS command delay in milliseconds. If no value is specified, it chooses zero by default. - qcom,display-topology: Array of u32 values which specifies the list of topologies available @@ -812,6 +833,15 @@ Example: qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <0>; + qcom,vdc-version = <0x11>; + qcom,vdc-version-release = <0>; + qcom,vdc-slice-height = <256>; + qcom,vdc-slice-width = <720>; + qcom,vdc-slice-per-pkt = <2>; + qcom,vdc-bit-per-component = <8>; + qcom,vdc-bit-per-pixel = <6>; + qcom,src-color-space = <0>; + qcom,src-chroma-format = <0>; qcom,mdss-dsi-dma-schedule-line = <5>; }; }; From 941f9c610d66539071349fb64da651ee1bfa9a08 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 21 Jan 2020 18:34:32 -0800 Subject: [PATCH 014/362] ARM: dts: msm: add panel power supply for Lahaina This change adds Panel power supply node for Lahaina target. Change-Id: Ia84ddc6340703509de578e6a01c1fbc9ba6ad579 --- display/lahaina-sde-display.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 35751222ebda..cf060c143a75 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -30,6 +30,9 @@ }; }; + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; From 2cd856ee00abf4be5332b4474e4c29aab800a673 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Mon, 13 Jan 2020 17:04:39 -0800 Subject: [PATCH 015/362] bindings: Documentation: add documentation for VDC-m hw block Add the documentation for configuring the VDC-m hw block present in the DPU. Change-Id: I5671d5a1f66517a636396637686de614181b4556 --- bindings/sde.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 65dcc6b0da86..4fc7209c9fc1 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -104,6 +104,7 @@ Optional properties: - qcom,sde-dspp-size: A u32 value indicates the address range for each dspp. - qcom,sde-intf-size: A u32 value indicates the address range for each intf. - qcom,sde-dsc-size: A u32 value indicates the address range for each dsc. +- qcom,sde-vdc-size: A u32 value indicates the address range for each vdc. - qcom,sde-cdm-size: A u32 value indicates the address range for each cdm. - qcom,sde-pp-size: A u32 value indicates the address range for each pingpong. - qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d. @@ -186,6 +187,7 @@ Optional properties: - qcom,sde-smart-dma-rev: A string entry indicating the smart dma version supported on the device. Supported entries are "smart_dma_v1" and "smart_dma_v2". +- qcom,sde-vdc-hw-rev: A string indicating the hw version of vdc. - qcom,sde-intf-type: Array of string provides the interface type information. Possible string values "dsi" - dsi display interface @@ -227,6 +229,13 @@ Optional properties: - qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc block can support native 422 and native 420 encoding. +- qcom,sde-vdc-off: A u32 offset address for the available vdc blocks. + This offset is calculated from register "mdp_phys" + defined in reg property. +- qcom,sde-vdc-enc: A u32 offset address for the vdc encoder block. This offset is + calculated from qcom,sde-vdc-off. +- qcom,sde-vdc-ctl: A u32 offset address for the vdc ctl block. This offset is + calculated from qcom,sde-vdc-off. - qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. - qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. - qcom,sde-dither-version: A u32 value indicates the dither block version. @@ -602,6 +611,11 @@ Example: qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; qcom,sde-cdm-off = <0x0007a200>; qcom,sde-dsc-off = <0x00081000 0x00081400>; + qcom,sde-vdc-off = <0x7C000>; + qcom,sde-vdc-size = <0xf10>; + qcom,sde-vdc-hw-rev = "vdc_1_1"; + qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-ctl = <0xf00>; qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; From b358e477566c31a4a622cfbccfa9514c5d2ab70f Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Fri, 17 Jan 2020 15:07:55 -0800 Subject: [PATCH 016/362] ARM: dts: msm: add VDC video mode simulator dsi panel Add VDC video mode simulator DSI panel Change-Id: I8f6b1d1be38dce8d2fc6ebe01990e0aa501537bd --- display/dsi-panel-sim-vdc-vid.dtsi | 230 +++++++++++++++++++++++++++++ 1 file changed, 230 insertions(+) create mode 100644 display/dsi-panel-sim-vdc-vid.dtsi diff --git a/display/dsi-panel-sim-vdc-vid.dtsi b/display/dsi-panel-sim-vdc-vid.dtsi new file mode 100644 index 000000000000..2162e72cef4c --- /dev/null +++ b/display/dsi-panel-sim-vdc-vid.dtsi @@ -0,0 +1,230 @@ +&mdss_mdp { + dsi_sim_vdc_vid: qcom,mdss_dsi_sim_vdc_vid { + qcom,mdss-dsi-panel-name = + "Simulator video mode VDC dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <300>; + qcom,mdss-dsi-h-back-porch = <48>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "vdc"; + qcom,vdc-version = <0x11>; + qcom,vdc-version-release = <0>; + qcom,vdc-slice-height = <256>; + qcom,vdc-slice-width = <720>; + qcom,vdc-slice-per-pkt = <2>; + qcom,vdc-bit-per-component = <8>; + qcom,vdc-bit-per-pixel = <6>; + qcom,src-chroma-format = <0>; + qcom,src-color-space = <0>; + }; + }; + }; +}; From 7fb91cdbbd0e36f024e016198f02928df0e94c49 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Fri, 17 Jan 2020 15:13:58 -0800 Subject: [PATCH 017/362] ARM: dts: msm: add VDC command mode simulator dsi panel Add VDC command mode simulator DSI panel Change-Id: I11de7203cd3c319c88b2901105afb39787b85790 --- display/dsi-panel-sim-vdc-cmd.dtsi | 237 +++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) create mode 100644 display/dsi-panel-sim-vdc-cmd.dtsi diff --git a/display/dsi-panel-sim-vdc-cmd.dtsi b/display/dsi-panel-sim-vdc-cmd.dtsi new file mode 100644 index 000000000000..61a47f94dcb9 --- /dev/null +++ b/display/dsi-panel-sim-vdc-cmd.dtsi @@ -0,0 +1,237 @@ +&mdss_mdp { + dsi_sim_vdc_cmd: qcom,mdss_dsi_sim_vdc_cmd { + qcom,mdss-dsi-panel-name = + "Simulator cmd mode VDC dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "vdc"; + qcom,vdc-version = <0x11>; + qcom,vdc-version-release = <0>; + qcom,vdc-slice-height = <256>; + qcom,vdc-slice-width = <720>; + qcom,vdc-slice-per-pkt = <2>; + qcom,vdc-bit-per-component = <8>; + qcom,vdc-bit-per-pixel = <6>; + qcom,src-color-space = <0>; + qcom,src-chroma-format = <0>; + }; + }; + }; +}; From b5a4930c2e71d3bfecf90b659b3a597491f5b2cb Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Fri, 17 Jan 2020 18:57:53 -0800 Subject: [PATCH 018/362] ARM: dts: msm: add support for VDC-m on lahaina Add support for VDC-m on lahaina chipset Change-Id: I7a0f998919a0ed3e11a8e5d4a1653feb6de9cfc7 --- display/lahaina-sde.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index ca8691bf457e..3289c2cf2ad3 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -104,6 +104,12 @@ qcom,sde-dither-version = <0x00010000>; qcom,sde-dither-size = <0x20>; + qcom,sde-vdc-off = <0x7C000>; + qcom,sde-vdc-size = <0xf10>; + qcom,sde-vdc-hw-rev = "vdc_1_1"; + qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-ctl = <0xf00>; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma"; From ad03ed03482d57e978c0d36f8669028e81ca4bf4 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Tue, 21 Jan 2020 12:53:57 -0800 Subject: [PATCH 019/362] ARM: dts: msm: include VDC panel files in lahaina display dtsi Include the VDC panel DTSI files in the lahaina display dtsi file. Change-Id: Iee5994d1d325dd8b367e3542ef8a2920d0684afa --- display/lahaina-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index cf060c143a75..c0da7964ee10 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -20,6 +20,8 @@ #include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" #include "dsi-panel-sim-sec-hd-cmd.dtsi" #include +#include "dsi-panel-sim-vdc-vid.dtsi" +#include "dsi-panel-sim-vdc-cmd.dtsi" &soc { ext_disp: qcom,msm-ext-disp { From e3bade4605e7dbb63fcd1d21548fb0b49ec77eb0 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Tue, 17 Dec 2019 14:18:16 -0500 Subject: [PATCH 020/362] ARM: dts: msm: add support for rounded corner on Lahaina target Adding dtsi entries for rounded corner hardware block and associated binding documentation for Lahaina target. Change-Id: I7f945bb5c0e9ec97cd7f9b339dc927fb8cd7a820 --- bindings/sde.txt | 11 +++++++++++ display/lahaina-sde.dtsi | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 4fc7209c9fc1..19432d600a2e 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -308,6 +308,13 @@ Optional properties: DSPP offsets. Since LTM hardware is represented as part of DSPP block, the LTM offsets are calculated based on the corresponding DSPP base. +- qcom,sde-dspp-rc-version: A u32 value indicating the version of the RC hardware. +- qcom,sde-dspp-rc-off: Array of u32 offsets indicate the RC block offsets from the + DSPP offsets. Since RC hardware is represented as part of + DSPP block, the RC offsets are calculated based on the + corresponding DSPP base. +- qcom,sde-dspp-rc-size: A u32 value indicating the RC block address range. +- qcom,sde-dspp-rc-mem-size: A u32 value indicating the RC block shared memory size. - qcom,sde-vbif-id: Array of vbif ids corresponding to the offsets defined in property: qcom,sde-vbif-off. - qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit @@ -598,6 +605,10 @@ Example: qcom,sde-dspp-off = <0x00055000 0x00057000>; qcom,sde-dspp-ad-off = <0x24000 0x22800>; qcom,sde-dspp-ad-version = <0x00030000>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800 0x14c00>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; qcom,sde-dest-scaler-top-off = <0x00061000>; qcom,sde-dest-scaler-off = <0x800 0x1000>; qcom,sde-wb-off = <0x00066000>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 3289c2cf2ad3..810807a6d693 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -62,6 +62,11 @@ qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; qcom,sde-dspp-size = <0x1800>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800 0x14c00>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dest-scaler-top-off = <0x00061000>; qcom,sde-dest-scaler-top-size = <0x1c>; qcom,sde-dest-scaler-off = <0x800 0x1000>; From 6bbc9102bfb8eec3fb66768d4a257e7c044d3d8a Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 27 Jan 2020 21:35:23 -0800 Subject: [PATCH 021/362] ARM: dts: msm: update peak current for DSI supplies This change updates the peak current of DSI controller and PHY supplies. Change-Id: Ic897b55efd6578fb24206844dabd291801b026bc --- display/lahaina-sde.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 810807a6d693..40d27558cc8b 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -540,7 +540,7 @@ qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <1000>; + qcom,supply-enable-load = <8350>; qcom,supply-disable-load = <0>; }; }; @@ -589,7 +589,7 @@ qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <1000>; + qcom,supply-enable-load = <8350>; qcom,supply-disable-load = <0>; }; }; @@ -640,7 +640,7 @@ qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <1000>; + qcom,supply-enable-load = <37550>; qcom,supply-disable-load = <0>; }; }; @@ -677,7 +677,7 @@ qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <1000>; + qcom,supply-enable-load = <37550>; qcom,supply-disable-load = <0>; }; }; From 6bbe4313d1a01031abd0d186f96920e6b86c708f Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Wed, 29 Jan 2020 22:44:51 -0800 Subject: [PATCH 022/362] ARM: dts: msm: fix DSI PHY register base for Lahaina Change fixes the base address and size for DSI PHY register for lahaina target. Change-Id: I58962d7b82c814d960231be8323235b134319179 --- display/lahaina-sde.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 40d27558cc8b..7687860bd570 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -614,10 +614,10 @@ label = "dsi-phy-0"; cell-index = <0>; #clock-cells = <1>; - reg = <0xae94900 0x77c>, + reg = <0xae94400 0x800>, <0xae94900 0x27c>, <0xaf03000 0x8>, - <0x0ae94200 0x100>; + <0xae94200 0x100>; reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; pll-label = "dsi_pll_5nm"; vdda-0p9-supply = <&L5B>; @@ -651,10 +651,10 @@ label = "dsi-phy-1"; cell-index = <1>; #clock-cells = <1>; - reg = <0xae96900 0x77c>, + reg = <0xae96400 0x800>, <0xae96900 0x27c>, <0xaf03000 0x8>, - <0x0ae96200 0x100>; + <0xae96200 0x100>; reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; pll-label = "dsi_pll_5nm"; vdda-0p9-supply = <&L5B>; From e6d0946f1b116dc16a038b03422d59ae18793553 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 28 Jan 2020 18:04:26 -0800 Subject: [PATCH 023/362] ARM: dts: msm: add BOE panels for lahaina target Change adds BOE Amoled WQHD DSC command mode and video mode panel and the required power supply entries for Lahaina CDP and MTP target. Change-Id: I85840d55aed8d5a533724f42622d738b7bf3d714 --- ...dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi | 182 ------------------ display/lahaina-sde-display-cdp.dtsi | 23 ++- display/lahaina-sde-display-mtp.dtsi | 23 ++- display/lahaina-sde-display.dtsi | 53 ++++- 4 files changed, 94 insertions(+), 187 deletions(-) diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi index 1c08e1931f81..a46f4e80548b 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi @@ -124,188 +124,6 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; - - timing@1 { - qcom,mdss-dsi-panel-framerate = <50>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2880>; - qcom,mdss-dsi-h-front-porch = <60>; - qcom,mdss-dsi-h-back-porch = <30>; - qcom,mdss-dsi-h-pulse-width = <12>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <10>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 - 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 03 5c 42 00 - 07 01 00 00 00 00 02 01 00 - 0a 01 00 00 00 00 80 11 00 00 89 30 80 - 0B 40 05 A0 05 A0 02 D0 02 D0 02 00 - 02 68 00 20 9A DB 00 0A 00 0C 00 12 - 00 0E 18 00 10 F0 03 0C 20 00 06 0B - 0B 33 0E 1C 2A 38 46 54 62 69 70 77 - 79 7B 7D 7E 01 02 01 00 09 40 09 BE - 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 - 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 09 F8 00 08 10 08 2D - 00 00 2D - 15 01 00 00 00 00 02 55 00 - 05 01 00 00 1e 00 02 11 00 - 39 01 00 00 00 00 03 b0 a5 00 - 15 01 00 00 00 00 02 e0 18 - 39 01 00 00 00 00 0c c0 00 53 6f 51 50 - 51 34 4f 5a 33 19 - 05 01 00 00 78 00 02 35 00 - 05 01 00 00 3c 00 02 29 00 - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 - 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 - 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 - ]; - - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 5a 01]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_lp_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 5a 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_lp_mode"; - qcom,mdss-dsi-lp1-command = [ - 05 01 00 00 00 00 02 39 00 - ]; - qcom,mdss-dsi-lp1-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-nolp-command = [ - 05 01 00 00 00 00 02 38 00 - ]; - qcom,mdss-dsi-nolp-command-state = - "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <180>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-framerate = <40>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2880>; - qcom,mdss-dsi-h-front-porch = <60>; - qcom,mdss-dsi-h-back-porch = <30>; - qcom,mdss-dsi-h-pulse-width = <12>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <12>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 0c b1 a0 9f 63 4f 63 0e 0a 10 0e 0a 10 - 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 03 5c 42 00 - 07 01 00 00 00 00 02 01 00 - 0a 01 00 00 00 00 80 11 00 00 89 30 80 - 0B 40 05 A0 05 A0 02 D0 02 D0 02 00 - 02 68 00 20 9A DB 00 0A 00 0C 00 12 - 00 0E 18 00 10 F0 03 0C 20 00 06 0B - 0B 33 0E 1C 2A 38 46 54 62 69 70 77 - 79 7B 7D 7E 01 02 01 00 09 40 09 BE - 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 - 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 09 F8 00 08 10 08 2D - 00 00 2D - 15 01 00 00 00 00 02 55 00 - 05 01 00 00 1e 00 02 11 00 - 39 01 00 00 00 00 03 b0 a5 00 - 15 01 00 00 00 00 02 e0 18 - 39 01 00 00 00 00 0c c0 00 53 6f 51 50 - 51 34 4f 5a 33 19 - 05 01 00 00 78 00 02 35 00 - 05 01 00 00 3c 00 02 29 00 - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10 - 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 0c b1 a0 9f 63 4f 63 0e 0a 10 0e 0a 10 - 39 01 00 00 00 00 07 e4 30 06 00 40 34 03 - ]; - - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 5a 01]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_lp_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 5a 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_lp_mode"; - qcom,mdss-dsi-lp1-command = [ - 05 01 00 00 00 00 02 39 00 - ]; - qcom,mdss-dsi-lp1-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-nolp-command = [ - 05 01 00 00 00 00 02 38 00 - ]; - qcom,mdss-dsi-nolp-command-state = - "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <180>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; }; }; }; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 0876d9f6200b..806cea26659a 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -1,12 +1,31 @@ #include "lahaina-sde-display.dtsi" +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 25 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_dual_sim_vid>; + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index df5b48fbbdea..efa951de57d4 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -1,11 +1,30 @@ #include "lahaina-sde-display.dtsi" +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 25 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_dual_sim_vid>; + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index c0da7964ee10..41402d4a60aa 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -33,6 +33,28 @@ }; dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; }; sde_dsi: qcom,dsi-display-primary { @@ -56,8 +78,11 @@ qcom,platform-te-gpio = <&tlmm 82 0>; qcom,panel-te-source = <0>; + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_dual_sim_vid>; + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; sde_wb: qcom,wb-display@0 { @@ -72,6 +97,32 @@ }; /* PHY TIMINGS REVISION YB */ +&dsi_sw43404_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 + 05 03 02 04 00 0f 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 + 05 03 02 04 00 0f 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_dual_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { From e504276f1b4d36f34466e28275d81ad6ba3550e1 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Tue, 7 Jan 2020 11:30:52 +0800 Subject: [PATCH 024/362] ARM: dts: msm: Add r66451 panel for QRD Lahaina Add QRD Lahaina panel dt files. Change-Id: I8b1495f41ed2b0882c3149d459ba87e35ff4b4e0 --- display/dsi-panel-r66451-dsc-qhd-cmd.dtsi | 91 +++++++++++++++++++++ display/dsi-panel-r66451-dsc-qhd-video.dtsi | 78 ++++++++++++++++++ display/lahaina-sde-display-qrd.dtsi | 43 ++++------ display/lahaina-sde-display.dtsi | 26 ++++++ 4 files changed, 210 insertions(+), 28 deletions(-) create mode 100644 display/dsi-panel-r66451-dsc-qhd-cmd.dtsi create mode 100644 display/dsi-panel-r66451-dsc-qhd-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi new file mode 100644 index 000000000000..e1c7c4d40434 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi @@ -0,0 +1,91 @@ +&mdss_mdp { + dsi_r66451_amoled_cmd: qcom,mdss_dsi_r66451_qhd_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionx panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-qhd-video.dtsi b/display/dsi-panel-r66451-dsc-qhd-video.dtsi new file mode 100644 index 000000000000..44229ba0208f --- /dev/null +++ b/display/dsi-panel-r66451-dsc-qhd-video.dtsi @@ -0,0 +1,78 @@ +&mdss_mdp { + dsi_r66451_amoled_video: qcom,mdss_dsi_r66451_qhd_video { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionx panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 7ed5ce310868..50a41f2753b0 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -1,79 +1,66 @@ #include "lahaina-sde-display.dtsi" -&dsi_sw43404_amoled_cmd { +&dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; -&dsi_sw43404_amoled_video { +&dsi_r66451_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; -}; - -&dsi_sw43404_amoled_fhd_plus_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &dsi_sim_dsc_375_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &dsi_sim_dsc_10b_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &dsi_dual_sim_dsc_375_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 41402d4a60aa..e966ae27af3c 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -10,6 +10,8 @@ #include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-r66451-dsc-qhd-cmd.dtsi" +#include "dsi-panel-r66451-dsc-qhd-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" @@ -123,6 +125,30 @@ }; }; +&dsi_r66451_amoled_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 + 06 04 02 04 00 12 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 + 06 04 02 04 00 12 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_dual_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { From 51850f1252808d9373d51c7b1e77a6cbf04c308f Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Fri, 24 Jan 2020 12:12:00 -0800 Subject: [PATCH 025/362] ARM: dts: msm: remove rotator node on lahaina target This change removes rotator node and adds CTL_5 base offset for lahaina sde target. Change-Id: I5f629f3093ee18b80337d490e4869c90599954ca --- display/lahaina-sde.dtsi | 71 ++-------------------------------------- 1 file changed, 2 insertions(+), 69 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 7687860bd570..f47bc7f99e72 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -43,10 +43,10 @@ qcom,sde-len = <0x494>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 - 0x19000 0x1a000>; + 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1e8>; qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none"; + "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000>; @@ -433,7 +433,6 @@ qcom,sde-dram-channels = <2>; vdd-supply = <&disp_cc_mdss_core_gdsc>; - clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; @@ -444,72 +443,6 @@ interconnect-names = "qcom,sde-reg-bus"; }; - mdss_rotator: qcom,mdss_rotator@aea9000 { - compatible = "qcom,sde_rotator"; - reg = <0x0ae00000 0xac000>, - <0x0aeb8000 0x3000>; - reg-names = "mdp_phys", - "rot_vbif_phys"; - status = "disabled"; - - #list-cells = <1>; - - qcom,mdss-rot-mode = <1>; - qcom,mdss-highest-bank-bit = <0x3>; - interconnects = - <&mmss_noc MASTER_ROTATOR &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,rot-data-bus0", - "qcom,sde-reg-bus"; - qcom,msm-bus,active-only; - - qcom,supply-names = "rot-vdd"; - - clocks = - <&clock_gcc GCC_DISP_AHB_CLK>, - <&clock_gcc GCC_DISP_SF_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", - "iface_clk", "rot_clk"; - - interrupt-parent = <&mdss_mdp>; - interrupts = <2 0>; - - power-domains = <&mdss_mdp>; - - /* Offline rotator QoS setting */ - qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; - qcom,mdss-rot-vbif-memtype = <3 3>; - qcom,mdss-rot-cdp-setting = <1 1>; - qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; - qcom,mdss-rot-danger-lut = <0x0 0x0>; - qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; - - qcom,mdss-default-ot-rd-limit = <32>; - qcom,mdss-default-ot-wr-limit = <32>; - - qcom,mdss-sbuf-headroom = <20>; - - /* reg bus scale settings */ - rot_reg: qcom,rot-reg-bus { - qcom,msm-bus,name = "mdss_rot_reg"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>; - }; - - smmu_rot_unsec: qcom,smmu_rot_unsec_cb { - compatible = "qcom,smmu_sde_rot_unsec"; - iommus = <&apps_smmu 0x215C 0x0400>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - }; - }; - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { compatible = "qcom,dsi-ctrl-hw-v2.5"; label = "dsi-ctrl-0"; From f830d50a783330ba7bbb791e97a21099422cdeb3 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Tue, 21 Jan 2020 17:57:48 -0800 Subject: [PATCH 026/362] ARM: dts: msm: update ping pong dither-version This change brings ping pong dither version 2 to lahaina target. Change-Id: I91499a89d85e6ab45038b7ec1cd46e9ab6f11f8c --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index f47bc7f99e72..6d0e7591826e 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -106,7 +106,7 @@ qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; - qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-version = <0x00020000>; qcom,sde-dither-size = <0x20>; qcom,sde-vdc-off = <0x7C000>; From 5f9530e2f437aa74f771296dfa857a8d3d7e62af Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Wed, 5 Feb 2020 22:34:31 -0800 Subject: [PATCH 027/362] ARM: dts: msm: add 4K cmd and video mode panels for lahaina Change adds Sharp 4K DSC enabled command and video mode panels for lahaina CDP target. Change-Id: I9ee64b6c5f2bd66eb1fc0aef42f8df2711f41a82 --- display/lahaina-sde-display-cdp.dtsi | 19 +++++++ display/lahaina-sde-display.dtsi | 83 ++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 806cea26659a..e1bccea2f0bb 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -19,6 +19,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index e966ae27af3c..a93643afd3f8 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -25,6 +25,22 @@ #include "dsi-panel-sim-vdc-vid.dtsi" #include "dsi-panel-sim-vdc-cmd.dtsi" +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + &soc { ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; @@ -59,6 +75,42 @@ }; }; + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <182000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + + display_panel_avdd: display_gpio_regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 12 0>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; @@ -82,6 +134,7 @@ vddio-supply = <&L12C>; vdd-supply = <&L13C>; + avdd-supply = <&display_panel_avdd>; qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; @@ -149,6 +202,36 @@ }; }; +&dsi_sharp_4k_dsc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 + 05 03 02 04 00 10 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + /* + * Using same clock as Video mode panel as a + * temporary solution for PHY timing issue that causes + * corruption. + */ + qcom,mdss-dsi-panel-clockrate = <685751040>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 + 05 03 02 04 00 10 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_dual_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { From f285a41fe409813e2c31cbb30c2e1909b333d262 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Fri, 7 Feb 2020 17:08:46 -0800 Subject: [PATCH 028/362] ARM: dts: msm: add 2K cmd and video mode panels for lahaina Change adds Truly 2K Dual DSI command and video mode panels for lahaina CDP target. Change-Id: Icfbcf3f611e7b848545364ac32d0b0ac82dec3c1 --- display/lahaina-sde-display-cdp.dtsi | 17 +++++++++++++++ display/lahaina-sde-display.dtsi | 31 ++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index e1bccea2f0bb..725eaef5b2f3 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -38,6 +38,23 @@ qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index a93643afd3f8..e88a4cad9511 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -232,6 +232,37 @@ }; }; +&dsi_dual_nt35597_truly_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + /* + * Using PHY Timings version W as a + * temporary solution for PHY timing issue that causes + * corruption. + */ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06 + 06 04 02 04 00 15 16]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 07 07 0c 0a 07 + 07 05 02 04 00 15 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_dual_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { From 181705205d2986252431ca1ed315e5f3c88fc57f Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 18 Feb 2020 13:20:33 -0800 Subject: [PATCH 029/362] ARM: dts: msm: add 1080p cmd mode panels for lahaina Change adds Sharp 1080 and Truly 1080 command mode panels for lahaina CDP target. Change-Id: I6e43a1d6f71e28964bc493ddd439bc4429ae62a5 --- display/lahaina-sde-display-cdp.dtsi | 18 ++++++++++++++++++ display/lahaina-sde-display.dtsi | 25 +++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 725eaef5b2f3..0b7d7b783013 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -38,6 +38,15 @@ qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_nt35597_truly_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; @@ -55,6 +64,15 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index e88a4cad9511..84796205e90e 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -232,6 +232,19 @@ }; }; +&dsi_sharp_1080_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-panel-clockrate = <900000000>; + }; + }; +}; + &dsi_dual_nt35597_truly_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { @@ -263,6 +276,18 @@ }; }; +&dsi_nt35695b_truly_fhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_dual_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { From 672369c18e27999b6297ace2d99c74e217234f3b Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Mon, 10 Feb 2020 14:58:05 -0500 Subject: [PATCH 030/362] ARM: dts: msm: Add SB LUTDMA support for lahaina target A new LUTDMA instance is added to the DMA hardware in Lahaina. This change updates the corresponding entries, including block size, offsets, and version. This change also updates the DSPP IGC and Gamut version to indicate new HW programming changes using SB LUTDMA. Change-Id: I7a7314b2c80991e3e15990a080774bacf6de0e19 --- bindings/sde.txt | 13 ++++++++----- display/lahaina-sde.dtsi | 13 +++++++------ 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 19432d600a2e..b0665fb4c1d1 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -338,9 +338,11 @@ Optional properties: control register. Number of offsets defined should match the number of offsets defined in property: qcom,sde-wb-off -- qcom,sde-reg-dma-off: Offset of the register dma hardware block from - "regdma_phys" defined in reg property. -- qcom,sde-reg-dma-version: Version of the reg dma hardware block. +- qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks, + relative to "regdma_phys" defined in reg property. +- qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the + offsets declared in property: qcom,sde-reg-dma-off +- qcom,sde-reg-dma-version: Version of the reg dma hardware blocks. - qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys" defined in reg property. - qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast @@ -802,8 +804,9 @@ Example: qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-reg-dma-broadcast-disabled = <0>; qcom,sde-reg-dma-xin-id = <7>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6d0e7591826e..9b37dcb296de 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -5,7 +5,7 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x84000>, <0x0aeb0000 0x2008>, - <0x0aeac000 0x214>, + <0x0aeac000 0x648>, <0x0ae8f000 0x02c>, <0x0af50000 0x038>; reg-names = "mdp_phys", @@ -221,8 +221,9 @@ /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; @@ -242,7 +243,7 @@ qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; qcom,sde-vig-igc = <0x1d00 0x00060000>; qcom,sde-vig-inverse-pma; }; @@ -264,13 +265,13 @@ }; qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-igc = <0x1260 0x00030002>; qcom,sde-dspp-hsic = <0x800 0x00010007>; qcom,sde-dspp-memcolor = <0x880 0x00010007>; qcom,sde-dspp-hist = <0x800 0x00010007>; qcom,sde-dspp-sixzone= <0x900 0x00010007>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; qcom,sde-dspp-pcc = <0x1700 0x00040000>; qcom,sde-dspp-gc = <0x17c0 0x00010008>; qcom,sde-dspp-dither = <0x82c 0x00010007>; From 6ce403bdf733114902068f31b0b0747a9c0fcbe4 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 20 Feb 2020 09:14:58 -0800 Subject: [PATCH 031/362] ARM: dts: msm: remove LCD CDP platform device tree file for Lahaina The change removes LCD CDP display device tree file, as it is not planned on lahaina target. Change-Id: Ide0d2fd5ea2996750ea2d19a8883d4c0d18015f8 --- display/lahaina-sde-display-cdp-lcd.dtsi | 155 ----------------------- 1 file changed, 155 deletions(-) delete mode 100644 display/lahaina-sde-display-cdp-lcd.dtsi diff --git a/display/lahaina-sde-display-cdp-lcd.dtsi b/display/lahaina-sde-display-cdp-lcd.dtsi deleted file mode 100644 index 6360807c9608..000000000000 --- a/display/lahaina-sde-display-cdp-lcd.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -&dsi_sharp_4k_dsc_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x77>; - qcom,mdss-dsi-panel-on-check-value = <0x77>; - qcom,mdss-dsi-panel-status-read-length = <1>; - /delete-property/ qcom,platform-en-gpio; -}; - -&dsi_sharp_4k_dsc_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x77>; - qcom,mdss-dsi-panel-on-check-value = <0x77>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-qsync-min-refresh-rate = <55>; - /delete-property/ qcom,platform-en-gpio; -}; - -&dsi_sharp_qsync_wqhd_cmd { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - /delete-property/ qcom,platform-en-gpio; -}; - -&dsi_sharp_qsync_wqhd_video { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - /delete-property/ qcom,platform-en-gpio; -}; - -&dsi_sharp_1080_cmd { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_dual_nt35597_truly_video { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_nt35695b_truly_fhd_cmd { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_nt35695b_truly_fhd_video { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; -}; - -&dsi_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; -}; - -&dsi_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; -}; - -&dsi_dual_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; -}; - -&dsi_dual_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; -}; - -&dsi_dual_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; -}; - -&dsi_sim_sec_hd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; - qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; -}; - -&sde_dsi { - /delete-property/ avdd-supply; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>; -}; - -&sde_dsi1 { - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; -}; From d2c0fe4e101745bc2eac0b97e7790251d3e1bb08 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 18 Feb 2020 13:45:34 -0800 Subject: [PATCH 032/362] ARM: dts: msm: add Simulation panels for lahaina Change adds all available simulation panel configurations for lahaina target. Change-Id: Ib3570d6509de477e00f58880c678d5691ffaba44 --- display/dsi-panel-sim-dualmipi-cmd.dtsi | 34 ++- display/lahaina-sde-display-cdp.dtsi | 36 ++++ display/lahaina-sde-display-mtp.dtsi | 36 ++++ display/lahaina-sde-display.dtsi | 266 ++++++++++++++++++++++++ 4 files changed, 370 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-sim-dualmipi-cmd.dtsi b/display/dsi-panel-sim-dualmipi-cmd.dtsi index 6407ef2d75b2..a96d81cc8fdb 100644 --- a/display/dsi-panel-sim-dualmipi-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-cmd.dtsi @@ -39,6 +39,36 @@ qcom,mdss-dsi-display-timings { timing@0 { + qcom,mdss-dsi-panel-width = <2520>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [/* exit sleep mode, wait 0ms */ + 05 01 00 00 00 00 01 29]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@1 { qcom,mdss-dsi-panel-width = <540>; qcom,mdss-dsi-panel-height = <1920>; qcom,mdss-dsi-h-front-porch = <28>; @@ -72,7 +102,7 @@ "dsi_hs_mode"; }; - timing@1 { + timing@2 { qcom,mdss-dsi-panel-width = <1280>; qcom,mdss-dsi-panel-height = <1440>; qcom,mdss-dsi-h-front-porch = <120>; @@ -106,7 +136,7 @@ "dsi_hs_mode"; }; - timing@2 { + timing@3 { qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <3840>; qcom,mdss-dsi-h-front-porch = <30>; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 0b7d7b783013..dd3f7661b950 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -73,12 +73,48 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index efa951de57d4..8643ec14d181 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -19,12 +19,48 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 84796205e90e..03c1e6dcf5b2 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -288,6 +288,148 @@ }; }; +&dsi_sim_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 + 06 04 02 04 00 12 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 + 06 04 02 04 00 12 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 + 06 04 02 04 00 12 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 0d 0c 08 + 08 05 02 04 00 17 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@4 { /* HD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 09 10 0e 0a + 0a 07 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 00 04 04 08 07 05 + 05 03 02 04 00 0e 09]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 + 02 01 02 04 00 08 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 1080 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 11 10 1b 17 11 + 11 0c 02 04 00 30 15]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 + 04 02 02 04 00 0c 08]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 03 03 05 05 03 + 03 01 02 04 00 0a 08]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 05 09 08 05 + 05 03 02 04 00 10 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_dual_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { @@ -300,3 +442,127 @@ }; }; }; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 + 05 03 02 04 00 10 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08 + 08 05 02 04 00 16 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4k 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a + 0a 07 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01 + 01 01 02 04 00 05 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 + 02 01 02 04 00 08 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 + 04 02 02 04 00 0c 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02 + 01 00 02 04 00 06 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04 + 04 02 02 04 00 0c 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 + 05 03 02 04 00 0f 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 + 07 04 02 04 00 14 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01 + 01 00 02 04 00 04 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02 + 02 01 02 04 00 07 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03 + 03 01 02 04 00 08 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; From efb26a71ad536ef2ecf9e245a334417a13fdffc9 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Sun, 23 Feb 2020 22:35:46 -0500 Subject: [PATCH 033/362] Revert "ARM: dts: msm: Add SB LUTDMA support for lahaina target" This reverts commit 672369c18e27999b6297ace2d99c74e217234f3b. Intermittent crashes have been seen on Lahaina silicon when SBDMA / LUTBUS is used. Change-Id: I816b0d8914357c73a4f5b3f7781ad176a2061a50 --- bindings/sde.txt | 13 +++++-------- display/lahaina-sde.dtsi | 13 ++++++------- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index b0665fb4c1d1..19432d600a2e 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -338,11 +338,9 @@ Optional properties: control register. Number of offsets defined should match the number of offsets defined in property: qcom,sde-wb-off -- qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks, - relative to "regdma_phys" defined in reg property. -- qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the - offsets declared in property: qcom,sde-reg-dma-off -- qcom,sde-reg-dma-version: Version of the reg dma hardware blocks. +- qcom,sde-reg-dma-off: Offset of the register dma hardware block from + "regdma_phys" defined in reg property. +- qcom,sde-reg-dma-version: Version of the reg dma hardware block. - qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys" defined in reg property. - qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast @@ -804,9 +802,8 @@ Example: qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - qcom,sde-reg-dma-off = <0 0x400>; - qcom,sde-reg-dma-id = <0 1>; - qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010002>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-reg-dma-broadcast-disabled = <0>; qcom,sde-reg-dma-xin-id = <7>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 9b37dcb296de..6d0e7591826e 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -5,7 +5,7 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x84000>, <0x0aeb0000 0x2008>, - <0x0aeac000 0x648>, + <0x0aeac000 0x214>, <0x0ae8f000 0x02c>, <0x0af50000 0x038>; reg-names = "mdp_phys", @@ -221,9 +221,8 @@ /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-reg-dma-off = <0 0x400>; - qcom,sde-reg-dma-id = <0 1>; - qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010002>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; @@ -243,7 +242,7 @@ qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; qcom,sde-vig-igc = <0x1d00 0x00060000>; qcom,sde-vig-inverse-pma; }; @@ -265,13 +264,13 @@ }; qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x1260 0x00030002>; + qcom,sde-dspp-igc = <0x0 0x00030001>; qcom,sde-dspp-hsic = <0x800 0x00010007>; qcom,sde-dspp-memcolor = <0x880 0x00010007>; qcom,sde-dspp-hist = <0x800 0x00010007>; qcom,sde-dspp-sixzone= <0x900 0x00010007>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; qcom,sde-dspp-pcc = <0x1700 0x00040000>; qcom,sde-dspp-gc = <0x17c0 0x00010008>; qcom,sde-dspp-dither = <0x82c 0x00010007>; From 3eec98a21ce07a6425c8bda0d1576843f6b2939c Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 20 Feb 2020 09:24:26 -0800 Subject: [PATCH 034/362] ARM: dts: msm: remove workaround for Sharp 4K CMD panel for Lahaina The change removes the workaround used for Sharp 4K command mode panel for Lahaina target. A higher clock is no longer required for this panel. Change-Id: I661cf2b8c5a1353f3fe45b389476e8208eee282d --- display/lahaina-sde-display.dtsi | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 03c1e6dcf5b2..c57bcfd01687 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -206,16 +206,10 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 - 05 03 02 04 00 10 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 10 05 04 08 07 05 + 05 03 02 04 00 0f 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; - /* - * Using same clock as Video mode panel as a - * temporary solution for PHY timing issue that causes - * corruption. - */ - qcom,mdss-dsi-panel-clockrate = <685751040>; }; }; }; From c7b6993fe19a9ce79c18230b6438cd65a41267aa Mon Sep 17 00:00:00 2001 From: Abhijit kulkarni Date: Wed, 12 Feb 2020 17:34:56 -0800 Subject: [PATCH 035/362] ARM: dts: msm: remove sid node for lahaina This change removes the sid register space from display device tree as for this target driver need not access these registers. Change-Id: If036aeec25136b4686598da76739bb4251890fce --- display/lahaina-sde.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6d0e7591826e..685c388836c2 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -6,12 +6,10 @@ reg = <0x0ae00000 0x84000>, <0x0aeb0000 0x2008>, <0x0aeac000 0x214>, - <0x0ae8f000 0x02c>, <0x0af50000 0x038>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "sid_phys", "swfuse_phys"; clocks = From d0dbb66b556b9e268c0299b92b0be614df4a7a5b Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 24 Feb 2020 19:16:29 -0800 Subject: [PATCH 036/362] ARM: dts: msm: add Sharp WQHD CMD and Video mode panel for lahaina Change adds Sharp Qsync WQHD command and video mode panels for lahaina target. Change-Id: I9e170d6808f62bda8190f22bbf63217066731cfe --- display/lahaina-sde-display-cdp.dtsi | 19 +++++++ display/lahaina-sde-display.dtsi | 85 ++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index dd3f7661b950..0df81a648cb1 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -47,6 +47,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sharp_qsync_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + &dsi_dual_nt35597_truly_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index c57bcfd01687..0311f336758e 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -239,6 +239,91 @@ }; }; +&dsi_sharp_qsync_wqhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 + 06 03 02 04 00 11 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@1 { /* WQHD 60FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 + 06 03 02 04 00 11 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* FHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02 + 02 00 02 04 00 0a 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + + timing@3 { /* WQHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0f 04 04 07 07 04 + 05 02 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@4 { /* WQHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 26 0b 0a 11 0f 0b + 0b 07 02 04 00 1f 0f]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 8 8 8 1440 8>; + }; + + timing@5 { /* WQHD 120FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 + 06 03 02 04 00 11 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 04 02 02 04 00 0e 13]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + + timing@7 { /* FHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 + 02 01 02 04 00 0c 12]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + }; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 + 06 03 02 04 00 11 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_dual_nt35597_truly_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { From da408a0be8c85ce3ef4018b01246e1fed4f860ed Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Thu, 20 Feb 2020 21:20:47 -0800 Subject: [PATCH 037/362] dt-bindings: add binding documentation for MSM HDCP driver This change adds the binding documentation for the MSM HDCP driver on kernel-5.4. Change-Id: I618e6e0254f63bca4769965305157813ca2c9f03 --- bindings/msm_hdcp.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 bindings/msm_hdcp.txt diff --git a/bindings/msm_hdcp.txt b/bindings/msm_hdcp.txt new file mode 100644 index 000000000000..8d5f55d7a8ca --- /dev/null +++ b/bindings/msm_hdcp.txt @@ -0,0 +1,14 @@ +MSM HDCP driver + +Standalone driver managing HDCP related communications +between TZ and HLOS for MSM chipset. + +Required properties: + +compatible = "qcom,msm-hdcp"; + +Example: + +qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; +}; From 5ec0aa1557295ac49e9b298216e2e502fbbd242a Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 2 Mar 2020 20:28:29 -0800 Subject: [PATCH 038/362] ARM: dts: msm: enable ESD for panels on Lahaina This change enables ESD for all DSI panels supported on Lahaina. Change-Id: I9cd99b773e88ce74974ef5fd4f01f3b1f2c55c6d --- display/lahaina-sde-display.dtsi | 67 ++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 0311f336758e..95b2a66cb6a6 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -153,6 +153,12 @@ /* PHY TIMINGS REVISION YB */ &dsi_sw43404_amoled_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { @@ -166,6 +172,12 @@ }; &dsi_sw43404_amoled_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { @@ -203,6 +215,13 @@ }; &dsi_sharp_4k_dsc_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -215,6 +234,14 @@ }; &dsi_sharp_4k_dsc_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -227,6 +254,13 @@ }; &dsi_sharp_1080_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -240,6 +274,12 @@ }; &dsi_sharp_qsync_wqhd_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ @@ -313,6 +353,12 @@ }; &dsi_sharp_qsync_wqhd_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -325,6 +371,13 @@ }; &dsi_dual_nt35597_truly_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -343,6 +396,13 @@ }; &dsi_dual_nt35597_truly_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -356,6 +416,13 @@ }; &dsi_nt35695b_truly_fhd_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { From a46ace96239c5b631afb1ae00fabd17d5061ec93 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 2 Mar 2020 20:31:17 -0800 Subject: [PATCH 039/362] ARM: dts: msm: enable DFPS for Truly 2K video mode panel on lahaina Change enables dynamic refresh rate feature for Truly 2K dual DSI video mode panel on lahaina target. Change-Id: I1d266a993d19a0b1ca49d0cd1fa1b8048b0d0323 --- display/lahaina-sde-display.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 95b2a66cb6a6..4e25afc889f7 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -403,6 +403,11 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 57 55>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <53>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { From 17bb915ad177854b050f9af8cc8b2e57c884e0a7 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 2 Mar 2020 20:34:58 -0800 Subject: [PATCH 040/362] ARM: dts: msm: enable SSC for DSI on Lahaina The change enables Spread Spectrum Clocking for DSI PLL for lahaina target. SSC mode is set to down-spread. Change-Id: I074b22520944bec2394e93f83d03c511a5cb0f8e --- display/lahaina-sde.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 685c388836c2..7ac119544138 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -552,6 +552,8 @@ reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; pll-label = "dsi_pll_5nm"; vdda-0p9-supply = <&L5B>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 @@ -589,6 +591,8 @@ reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; pll-label = "dsi_pll_5nm"; vdda-0p9-supply = <&L5B>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 From 9621e7326ef542c0223cc1078acef7e3b549a5e7 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 2 Mar 2020 20:40:11 -0800 Subject: [PATCH 041/362] ARM: dts: msm: enable ULPS for CMD mode panels on Lahaina This change enables ULPS for all command mode panels on lahaina target. Change-Id: I153f1a041949f62547021f6283cd29099dd7cf0c --- display/lahaina-sde-display.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 4e25afc889f7..7eba4ee35223 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -153,6 +153,7 @@ /* PHY TIMINGS REVISION YB */ &dsi_sw43404_amoled_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -203,6 +204,7 @@ }; &dsi_r66451_amoled_cmd { + qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -215,6 +217,7 @@ }; &dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; @@ -254,6 +257,7 @@ }; &dsi_sharp_1080_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -274,6 +278,7 @@ }; &dsi_sharp_qsync_wqhd_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -371,6 +376,7 @@ }; &dsi_dual_nt35597_truly_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -421,6 +427,7 @@ }; &dsi_nt35695b_truly_fhd_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -440,6 +447,7 @@ }; &dsi_sim_cmd { + qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS cmd mode*/ @@ -498,6 +506,7 @@ }; &dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* 1080p */ @@ -519,6 +528,7 @@ }; &dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* QHD 60fps */ @@ -547,6 +557,7 @@ }; &dsi_dual_sim_cmd { + qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { @@ -595,6 +606,7 @@ }; &dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* 4k 30 FPS*/ From f0c68dac7c7bb43ba2cba005a8ee6285fc69aa00 Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Wed, 5 Feb 2020 10:19:31 -0800 Subject: [PATCH 042/362] ARM: dts: msm: update sde qos and dcvs config for lahaina This change adds 60 and 120 fps creq, safe and danger lut qos configuration for lahaina target. It also updates the min and max bandwidth limit for per pipe and sde device for lahaina target. Change-Id: I2a0140fd2f6a3b7910df9166d98efff9e1a0e10d --- bindings/sde.txt | 120 ++++++++++++++------------------------- display/lahaina-sde.dtsi | 50 ++++++++-------- 2 files changed, 66 insertions(+), 104 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 19432d600a2e..4cf9296109c5 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -416,51 +416,35 @@ Optional properties: priority for concurrent writeback clients. - qcom,sde-vbif-qos-lutdma-remap: This array is used to program vbif qos remapper register priority for lutdma client. -- qcom,sde-danger-lut: Array of 5 cell property, with a format of - , - indicating the danger luts on sspp. -- qcom,sde-safe-lut-linear: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for linear format on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-safe-lut-macrotile: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for macrotile format on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-safe-lut-macrotile-qseed: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for macrotile format - with qseed3 on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-safe-lut-nrt: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for nrt (e.g wfd) on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-safe-lut-cwb: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for cwb on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-linear: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for linear format on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-macrotile: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for macrotile format on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-macrotile-qseed: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for macrotile format - with qseed3 enabled on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-nrt: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for nrt (e.g wfd) on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-cwb: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for cwb on sspp. - Zero fill level on the last entry identifies the default lut. +- qcom,sde-qos-refresh-rates: A u32 array indicates danger, safe and creq luts + qos configuration for different refresh rates. +- qcom,sde-danger-lut: A u32 array of 6 cell property, with a format of + , + indicating the danger luts on sspp and wb. +- qcom,sde-safe-lut: A u32 array of 6 cell property, with a format of + , + indicating the safe luts on sspp and wb. +- qcom,sde-qos-lut-linear: A u64 array of 2 cell property, with a format of + in ascending fill level indicating + the creq luts for linear format on sspp. +- qcom,sde-qos-lut-linear-qseed: A u64 array of 2 cell property, with a format of + in ascending fill level indicating + the creq luts for linear format with qseed usage + (scaling) on sspp. +- qcom,sde-qos-lut-macrotile: A u64 array of 2 cell property, with a format of + in ascending fill level indicating + the creq luts for macrotile format on sspp. +- qcom,sde-qos-lut-macrotile-qseed: A u64 array of 2 cell property, with a format of + in ascending fill level + indicating the creq luts for macrotile format + with qseed enabled (scaling enabled) on sspp. +- qcom,sde-qos-lut-nrt: A u64 array of 2 cell property, with a format of + in ascending fill level + indicating the creq luts for nrt (e.g wfd) on sspp + and wb. +- qcom,sde-qos-lut-cwb: A u64 array of 2 cell property, with a format of + in ascending fill level + indicating the creq luts for cwb on sspp. - qcom,sde-cdp-setting: Array of 2 cell property, with a format of for cdp use cases in order of , and . @@ -718,40 +702,20 @@ Example: qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff>; - qcom,sde-safe-lut-linear = <0 0xfff8>; - qcom,sde-safe-lut-macrotile = <0 0xf000>; - qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; - qcom,sde-safe-lut-nrt = <0 0xffff>; - qcom,sde-safe-lut-cwb = <0 0xffff>; + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - qcom,sde-qos-lut-linear = - <4 0x00000000 0x00000357>, - <5 0x00000000 0x00003357>, - <6 0x00000000 0x00023357>, - <7 0x00000000 0x00223357>, - <8 0x00000000 0x02223357>, - <9 0x00000000 0x22223357>, - <10 0x00000002 0x22223357>, - <11 0x00000022 0x22223357>, - <12 0x00000222 0x22223357>, - <13 0x00002222 0x22223357>, - <14 0x00012222 0x22223357>, - <0 0x00112222 0x22223357>; - qcom,sde-qos-lut-macrotile = - <10 0x00000003 0x44556677>, - <11 0x00000033 0x44556677>, - <12 0x00000233 0x44556677>, - <13 0x00002233 0x44556677>, - <14 0x00012233 0x44556677>, - <0 0x00112233 0x44556677>; - qcom,sde-qos-lut-macrotile-qseed = - <0 0x00112233 0x66777777>; - qcom,sde-qos-lut-nrt = - <0 0x00000000 0x00000000>; - qcom,sde-qos-lut-cwb = - <0 0x75300000 0x00000000>; + qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; qcom,sde-cdp-setting = <1 1>, <1 0>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 685c388836c2..e372bd4aa8ec 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -132,15 +132,15 @@ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; - qcom,sde-max-per-pipe-bw-kbps = <4400000 4400000 - 4400000 4400000 - 4400000 4400000 - 4400000 4400000>; + qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000 + 3900000 3900000 + 3900000 3900000 + 3900000 3900000>; - qcom,sde-max-per-pipe-bw-high-kbps = <5300000 5300000 - 5300000 5300000 - 5300000 5300000 - 5300000 5300000>; + qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000 + 5200000 5200000 + 5200000 5200000 + 5200000 5200000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-sspp-clk-ctrl = @@ -170,9 +170,9 @@ qcom,sde-has-idle-pc; qcom,sde-max-dest-scaler-input-linewidth = <2048>; qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <13700000>; - qcom,sde-max-bw-high-kbps = <16600000>; - qcom,sde-min-core-ib-kbps = <4800000>; + qcom,sde-max-bw-low-kbps = <11800000>; + qcom,sde-max-bw-high-kbps = <15500000>; + qcom,sde-min-core-ib-kbps = <2500000>; qcom,sde-min-llcc-ib-kbps = <0>; qcom,sde-min-dram-ib-kbps = <800000>; qcom,sde-dram-channels = <2>; @@ -193,24 +193,22 @@ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>; - /* macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x000000ff 0x0000ffff - 0x00000000 0x00000000 0x0000ffff>; + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - qcom,sde-safe-lut-linear = <0 0xfff0>; - qcom,sde-safe-lut-macrotile = <0 0xff00>; - /* same as safe-lut-macrotile */ - qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>; - qcom,sde-safe-lut-nrt = <0 0xffff>; - qcom,sde-safe-lut-cwb = <0 0x3ff>; + qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; - qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; - qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; - qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; - qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; - qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>; + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; qcom,sde-cdp-setting = <1 1>, <1 0>; From e5aa8b65b8b89fcf357efe2d20c3734cb017e231 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Mon, 24 Feb 2020 23:16:38 +0800 Subject: [PATCH 043/362] ARM: dts: msm: add other fps support for lahaina qrd Add 60hz and 120hz cmd mode support and dynamic fps switch commands. Change-Id: I9b09fa2e99844a0ed34b9366b6b822acb2505af2 --- display/dsi-panel-r66451-dsc-qhd-cmd.dtsi | 183 +++++++++++++++++++- display/dsi-panel-r66451-dsc-qhd-video.dtsi | 9 +- display/lahaina-sde-display.dtsi | 28 ++- 3 files changed, 208 insertions(+), 12 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi index e1c7c4d40434..1d9d3e26f7cf 100644 --- a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi @@ -1,5 +1,5 @@ &mdss_mdp { - dsi_r66451_amoled_cmd: qcom,mdss_dsi_r66451_qhd_cmd { + dsi_r66451_amoled_cmd: qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd { qcom,mdss-dsi-panel-name = "r66451 amoled cmd mode dsi visionx panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; @@ -34,12 +34,12 @@ qcom,mdss-dsi-te-using-te-pin; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-front-porch = <95>; qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-pulse-width = <1>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <4>; qcom,mdss-dsi-v-front-porch = <25>; @@ -49,6 +49,111 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 00 00 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 02 e6 00 @@ -71,12 +176,80 @@ 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; - qcom,mdss-dsi-off-command = [ 05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-qhd-video.dtsi b/display/dsi-panel-r66451-dsc-qhd-video.dtsi index 44229ba0208f..9b86cfa0323c 100644 --- a/display/dsi-panel-r66451-dsc-qhd-video.dtsi +++ b/display/dsi-panel-r66451-dsc-qhd-video.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { - dsi_r66451_amoled_video: qcom,mdss_dsi_r66451_qhd_video { + dsi_r66451_amoled_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_video { qcom,mdss-dsi-panel-name = - "r66451 amoled cmd mode dsi visionx panel with DSC"; + "r66451 amoled video mode dsi visionx panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; @@ -26,9 +26,9 @@ timing@0 { qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-front-porch = <95>; qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-pulse-width = <1>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <4>; qcom,mdss-dsi-v-front-porch = <25>; @@ -52,7 +52,6 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 7eba4ee35223..007cfb84b90f 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -194,6 +194,13 @@ &dsi_r66451_amoled_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { + /* + * CDP could not display using the old HFP(96) and HSYNC(32). + * Modified HFP to 95 and HSYNC to 1, but using the new porch + * to caculator the PHY timing based on version YB, 90hz could + * not display, need to keep the PHY timing(which based on + * HFP=96, HSYNC=32). + */ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 06 04 02 04 00 12 0b]; @@ -208,8 +215,25 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 - 06 04 02 04 00 12 0b]; + qcom,mdss-dsi-panel-phy-timings = [00 19 08 07 0c 0b 07 + 07 05 02 04 00 16 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 1f 06 + 06 03 02 04 00 11 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + /* + * Using PHY Timings version YB 60hz could not display, + * refer to version W, changed T_HS_ZERO from 0x06 to 0x1e. + */ + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 0d 04 04 07 1e 04 + 04 02 02 04 00 0c 09]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From 1ee393a1aa212f5457e5f188bd0dbece3a0028e6 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 25 Feb 2020 15:43:28 -0800 Subject: [PATCH 044/362] ARM: dts: msm: enable visionox fhd plus cmd and vid panel for lahaina Change adds Visionox FHD plus command and video mode panels for Lahaina CDP target. Change-Id: I3c07e0a855f0f4a331c32f9efb383cb808fa722c --- display/lahaina-sde-display-cdp.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 0df81a648cb1..b8f8c28266c7 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -19,6 +19,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sharp_4k_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; From c50e652f6e8583bfef1ead3be9aeb6b5b4a0c68c Mon Sep 17 00:00:00 2001 From: Ashwini Muduganti Date: Mon, 10 Feb 2020 17:39:49 -0800 Subject: [PATCH 045/362] ARM: dts: msm: fix iommu smr mask for lahaina This change fixes smr mask for secure iommu device tree entry as per the hw recommendation. Change-Id: Ic6e7262915d359f87d422a51339bd07266561956 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6d0e7591826e..fc6c9f30dc72 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -309,7 +309,7 @@ smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x821 0x400>; + iommus = <&apps_smmu 0x821 0x0>; qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; From d19830a0492ebb5679d27a74531ab11d9baff2b1 Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Mon, 24 Feb 2020 19:19:44 -0800 Subject: [PATCH 046/362] ARM: dts: msm: fix dsc/vdc register range for lahaina DSC and VDC-M sub-block registers are not on contiguous address range. This change allows specifying the individual register ranges for each sub-block. Change-Id: I16a1c4b6ac3570d4f43e2ff99132055949574173 --- bindings/sde.txt | 4 ++++ display/lahaina-sde.dtsi | 8 ++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 4cf9296109c5..fa854afbb2f8 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -223,19 +223,23 @@ Optional properties: - qcom,sde-dsc-enc: Array of offset addresses for the available dsc encoder blocks. These offsets are calculated from the corresponding DSC base. +- qcom,sde-dsc-enc-size A u32 value indicates the enc block offset range. - qcom,sde-dsc-ctl: Array of offset addresses for the available dsc ctl blocks. These offsets are calculated from the corresponding DSC base. +- qcom,sde-dsc-ctl-size A u32 value indicates the ctl block offset range. - qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc block can support native 422 and native 420 encoding. - qcom,sde-vdc-off: A u32 offset address for the available vdc blocks. This offset is calculated from register "mdp_phys" defined in reg property. +- qcom,sde-vdc-enc-size A u32 value indicates the enc block offset range. - qcom,sde-vdc-enc: A u32 offset address for the vdc encoder block. This offset is calculated from qcom,sde-vdc-off. - qcom,sde-vdc-ctl: A u32 offset address for the vdc ctl block. This offset is calculated from qcom,sde-vdc-off. +- qcom,sde-vdc-ctl-size A u32 value indicates the ctl block offset range. - qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. - qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. - qcom,sde-dither-version: A u32 value indicates the dither block version. diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index f2324b788a9a..cb3598053881 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -95,11 +95,13 @@ qcom,sde-cdm-size = <0x224>; qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>; - qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-size = <0x10>; qcom,sde-dsc-pair-mask = <2 1 4 3>; qcom,sde-dsc-hw-rev = "dsc_1_2"; qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>; + qcom,sde-dsc-enc-size = <0x100>; qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>; + qcom,sde-dsc-ctl-size = <0x10>; qcom,sde-dsc-native422-supp = <0 0 1 1>; qcom,sde-dither-off = <0xe0 0xe0 0xe0 @@ -108,10 +110,12 @@ qcom,sde-dither-size = <0x20>; qcom,sde-vdc-off = <0x7C000>; - qcom,sde-vdc-size = <0xf10>; + qcom,sde-vdc-size = <0x10>; qcom,sde-vdc-hw-rev = "vdc_1_1"; qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-enc-size = <0x1C8>; qcom,sde-vdc-ctl = <0xf00>; + qcom,sde-vdc-ctl-size = <0x10>; qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma"; From ee7e5aa052ec67c3cb63b2936507784c177e84e5 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 10 Mar 2020 15:15:37 -0700 Subject: [PATCH 047/362] ARM: dts: msm: enable Qsync feature for BOE video mode panel on lahaina Change enables Qsync feature for BOE video mode panel on lahaina target. Change-Id: I8b82bd0d751b927156b614db37dc882b854aeecd --- display/lahaina-sde-display.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 7eba4ee35223..1b4f311fc88a 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -179,6 +179,7 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-qsync-min-refresh-rate = <55>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { From 5130ab1496026f08121b2e2f63f20ca46e2d8618 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Tue, 11 Feb 2020 17:24:14 -0800 Subject: [PATCH 048/362] bindings: Documentation: add documentation for poms align vsync property This change adds documentation for align vsync property for poms supported panels. Change-Id: I911aca194bdb0395237618861ca299d51f0eff59 --- bindings/mdss-dsi-panel.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index fbf167c62e9a..f9f2634c825f 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -90,6 +90,7 @@ Optional properties: - qcom,cmd-sync-wait-broadcast: Boolean used to broadcast dcs command to panels. - qcom,mdss-dsi-fbc-enable: Boolean used to enable frame buffer compression mode. - qcom,mdss-dsi-panel-mode-switch: Boolean used to enable panel operating mode switch. +- qcom,poms-align-panel-vsync: Boolean used to align panel TE with timing engine vsync in POMS - qcom,mdss-dsi-fbc-slice-height: Slice height(in lines) of compressed block. Expressed as power of 2. To set as 128 lines, this should be set to 7. @@ -615,6 +616,7 @@ Example: qcom,cmd-sync-wait-broadcast; qcom,mdss-dsi-fbc-enable; qcom,mdss-dsi-panel-mode-switch; + qcom,poms-align-panel-vsync; qcom,mdss-dsi-fbc-slice-height = <5>; qcom,mdss-dsi-fbc-2d-pred-mode; qcom,mdss-dsi-fbc-ver2-mode; From 7dc2fc5f452a000719cc0e18f2d57403784f7a35 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Mon, 9 Mar 2020 19:09:57 -0700 Subject: [PATCH 049/362] ARM: dts: msm: add poms align vsync property to sim panel for Lahaina This change adds poms align vsync property to sim panel which supports video mode, command mode switch for Lahaina. Change-Id: I59c886e451a33e0b5d2c47da4d8933699f410024 --- display/lahaina-sde-display.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 7eba4ee35223..8d23ea6e6e66 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -449,6 +449,7 @@ &dsi_sim_cmd { qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,poms-align-panel-vsync; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS cmd mode*/ qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 From be0b0335b22a591b3ef6e678fb2b10a186836217 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 9 Mar 2020 18:25:31 -0700 Subject: [PATCH 050/362] ARM: dts: msm: add Sharp QHD plus cmd panel for lahaina Change adds Sharp QHD plus command mode panel for lahaina target. Change-Id: I429ac35d82dabbe35a88845d2edd4194198ab881 --- display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi | 199 ++++++++++++++++++ display/lahaina-sde-display-cdp.dtsi | 10 + display/lahaina-sde-display.dtsi | 13 ++ 3 files changed, 222 insertions(+) create mode 100644 display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi new file mode 100644 index 000000000000..06c9b92e86d6 --- /dev/null +++ b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi @@ -0,0 +1,199 @@ +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_cmd: qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp qhd cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 0df81a648cb1..dc83cd6c18cb 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -66,6 +66,16 @@ qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + &dsi_dual_nt35597_truly_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 7eba4ee35223..5b487483bb2f 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -3,6 +3,7 @@ #include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" #include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" #include "dsi-panel-sharp-qsync-wqhd-video.dtsi" #include "dsi-panel-sharp-1080p-cmd.dtsi" @@ -375,6 +376,18 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 15 06 + 06 04 02 04 00 14 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_dual_nt35597_truly_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; From 70f6e56dbbf329abc6c6c403e4ee66a1229a7aad Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Thu, 23 Jan 2020 19:11:36 -0800 Subject: [PATCH 051/362] ARM: dts: msm: update settings for DP controller on Lahaina Update the base register offsets, regulator, clock and PLL settings. Change-Id: I9148bb70dc7a8d2266c74f1dec22aca2d80fd4c2 --- display/lahaina-sde-display.dtsi | 10 +----- display/lahaina-sde.dtsi | 57 ++++++++++++++++++++++++-------- 2 files changed, 45 insertions(+), 22 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 33ee668e99c2..0ee619a10862 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -42,14 +42,6 @@ }; &soc { - ext_disp: qcom,msm-ext-disp { - compatible = "qcom,msm-ext-disp"; - - ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - }; - }; - dsi_panel_pwr_supply: dsi_panel_pwr_supply { #address-cells = <1>; #size-cells = <0>; @@ -148,7 +140,7 @@ }; &mdss_mdp { - connectors = <&sde_wb &sde_dsi>; + connectors = <&sde_dp &sde_wb &sde_dsi>; }; /* PHY TIMINGS REVISION YB */ diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index cb3598053881..03eb69b3cf48 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -317,10 +317,22 @@ }; + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + sde_dp: qcom,dp_display@ae90000 { cell-index = <0>; compatible = "qcom,dp-display"; - status = "disabled"; + + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-parent = "altmode_0"; + usb-controller = <&usb0>; reg = <0xae90000 0x0dc>, <0xae90200 0x0c0>, @@ -330,33 +342,36 @@ <0x88ea200 0x200>, <0x88ea600 0x200>, <0xaf02000 0x1a0>, - <0x88ea040 0x10>, + <0x88ea000 0x200>, <0x88e8000 0x20>, <0x0aee1000 0x034>, - <0xae91400 0x094>; - /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + <0xae91400 0x094>, + <0xaf03000 0x8>; reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "dp_pll", - "usb3_dp_com", "hdcp_physical", "dp_p1"; + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; interrupt-parent = <&mdss_mdp>; interrupts = <12 0>; + #clock-cells = <1>; clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_iface_clk", - "pixel_clk_rcg", "pixel1_clk_rcg", + "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + qcom,pll-revision = "5nm-v1"; qcom,phy-version = <0x420>; qcom,aux-cfg0-settings = [20 00]; qcom,aux-cfg1-settings = [24 13]; @@ -371,13 +386,13 @@ qcom,max-pclk-frequency-khz = <675000>; - qcom,mst-enable; - qcom,widebus-enable; - qcom,dsc-feature-enable; - qcom,fec-feature-enable; qcom,max-dp-dsc-blks = <2>; qcom,max-dp-dsc-input-width-pixs = <2048>; + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + qcom,ctrl-supply-entries { #address-cells = <1>; #size-cells = <0>; @@ -387,7 +402,7 @@ qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <33000>; + qcom,supply-enable-load = <21700>; qcom,supply-disable-load = <0>; }; }; @@ -401,7 +416,7 @@ qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <912000>; qcom,supply-max-voltage = <912000>; - qcom,supply-enable-load = <126000>; + qcom,supply-enable-load = <115000>; qcom,supply-disable-load = <0>; }; }; @@ -419,6 +434,22 @@ qcom,supply-disable-load = <0>; }; }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; sde_rscc: qcom,sde_rscc@af20000 { From 25e0512a9dc6774e3a596e8452b7deea06cae589 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinaala Date: Tue, 17 Mar 2020 12:22:23 -0700 Subject: [PATCH 052/362] bindings: Documentation: update documentation for DSI Change updates documentation for SDE DSI by moving PLL properties as a part of DSI PHY and adding new versions for Controller and PHY. Change-Id: I88bd50733e6b830a417cbfd803b59357c6deba63 --- bindings/mdss-pll.txt | 108 ------------------------------------------ bindings/sde-dsi.txt | 16 +++++-- 2 files changed, 13 insertions(+), 111 deletions(-) delete mode 100644 bindings/mdss-pll.txt diff --git a/bindings/mdss-pll.txt b/bindings/mdss-pll.txt deleted file mode 100644 index a93529717d1c..000000000000 --- a/bindings/mdss-pll.txt +++ /dev/null @@ -1,108 +0,0 @@ -Qualcomm Technologies, Inc. MDSS pll for DSI/EDP/HDMI - -mdss-pll is a pll controller device which supports pll devices that -are compatible with MIPI display serial interface specification, -HDMI and edp. - -Required properties: -- compatible: Compatible name used in the driver. Should be one of: - "qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939", - "qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994", - "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909", - "qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994", - "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992", - "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996", - "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", - "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", - "qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8", - "qcom,mdss_dsi_pll_10nm", "qcom,mdss_dp_pll_8998", - "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm", - "qcom,mdss_dsi_pll_7nm", "qcom,mdss_dp_pll_7nm", - "qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm", - "qcom,mdss_dp_pll_14nm", "qcom,mdss_dsi_pll_7nm_v2", - "qcom,mdss_hdmi_pll_28lpm","qcom,mdss_dsi_pll_7nm_v4_1", - "qcom,mdss_dp_pll_7nm_v2" -- cell-index: Specifies the controller used -- reg: offset and length of the register set for the device. -- reg-names : names to refer to register sets related to this device -- gdsc-supply: Phandle for gdsc regulator device node. -- vddio-supply: Phandle for vddio regulator device node. -- clocks: List of Phandles for clock device nodes - needed by the device. -- clock-names: List of clock names needed by the device. -- clock-rate: List of clock rates in Hz. - -Optional properties: -- label: A string used to describe the driver used. -- vcca-supply: Phandle for vcca regulator device node. - - -- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. -- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" - or "center-spread". Default is "down-spread" if it is not specified. -- qcom,ssc-frequency-hz: Integer property to specify the spread frequency - to be programmed for the SSC. -- qcom,ssc-ppm: Integer property to specify the Parts per Million - value of SSC. - -- qcom,platform-supply-entries: A node that lists the elements of the supply. There - can be more than one instance of this binding, - in which case the entry would be appended with - the supply entry index. - e.g. qcom,platform-supply-entry@0 - - reg: offset and length of the register set for the device. - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off - -Example: - mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 { - compatible = "qcom,mdss_dsi_pll_8974"; - label = "MDSS DSI 0 PLL"; - cell-index = <0>; - - reg = <0xfd922A00 0xD4>, - <0xfd922900 0x64>, - <0xfd8c2300 0x8>; - reg-names = "pll_base", "dynamic_pll_base", "gdsc_base"; - gdsc-supply = <&gdsc_mdss>; - vddio-supply = <&pm8941_l12>; - vcca-supply = <&pm8941_l28>; - - clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, - <&clock_gcc clk_gcc_mdss_ahb_clk>, - <&clock_gcc clk_gcc_mdss_axi_clk>; - clock-names = "mdp_core_clk", "iface_clk", "bus_clk"; - clock-rate = <0>, <0>, <0>; - - qcom,dsi-pll-slave; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,ssc-frequency-hz = <30000>; - qcom,ssc-ppm = <5000>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <20>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - }; - }; - diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt index e09261d55b31..8e720f75f1ee 100644 --- a/bindings/sde-dsi.txt +++ b/bindings/sde-dsi.txt @@ -3,17 +3,18 @@ Qualcomm Technologies, Inc. mdss-dsi is the master DSI device which supports multiple DSI host controllers that are compatible with MIPI display serial interface specification. -DSI Controller: +DSI Controller and PHY: Required properties: - compatible: Should be "qcom,dsi-ctrl-hw-v". Supported versions include 1.4, 2.0 and 2.2. eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0, qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, - qcom,dsi-ctrl-hw-v2.4 + qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5 And for dsi phy driver: qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm, qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, - qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1 + qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, + qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2 - reg: Base address and length of DSI controller's memory mapped regions. - reg-names: A list of strings that name the list of regs. @@ -32,6 +33,8 @@ Required properties: "core_clk" "byte_clk_rcg" "pixel_clk_rcg" +- pll-label Supported versions of DSI PLL: + dsi_pll_5nm - gdsc-supply: phandle to gdsc regulator node. - vdda-supply: phandle to vdda regulator node. - vcca-supply: phandle to vcca regulator node. @@ -116,3 +119,10 @@ Optional properties: specified in Documentation/devicetree/bindings/graph.txt. Video port 0 reg 0 is for the bridge output. The remote endpoint phandle should be mipi_dsi_device device node. +- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. +- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" + or "center-spread". Default is "down-spread" if it is not specified. +- qcom,ssc-frequency-hz: Integer property to specify the spread frequency + to be programmed for the SSC. +- qcom,ssc-ppm: Integer property to specify the Parts per Million + value of SSC. From 3c44286a6ea69c48082929d318312683690da294 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Mon, 10 Feb 2020 14:58:05 -0500 Subject: [PATCH 053/362] ARM: dts: msm: Add SB LUTDMA support for lahaina target A new LUTDMA instance is added to the DMA hardware in Lahaina. This change updates the corresponding entries, including block size, offsets, and version. The DSPP IGC and Gamut versions have been updated to indicate new HW programming changes using SB LUTDMA. Change-Id: I44091e99d4a47162faf539eeb2e64f3799dc8855 --- bindings/sde.txt | 13 ++++++++----- display/lahaina-sde.dtsi | 11 ++++++----- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 4cf9296109c5..9d7e7e4fe9d9 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -338,9 +338,11 @@ Optional properties: control register. Number of offsets defined should match the number of offsets defined in property: qcom,sde-wb-off -- qcom,sde-reg-dma-off: Offset of the register dma hardware block from - "regdma_phys" defined in reg property. -- qcom,sde-reg-dma-version: Version of the reg dma hardware block. +- qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks, + relative to "regdma_phys" defined in reg property. +- qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the + offsets declared in property: qcom,sde-reg-dma-off +- qcom,sde-reg-dma-version: Version of the reg dma hardware blocks. - qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys" defined in reg property. - qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast @@ -766,8 +768,9 @@ Example: qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-reg-dma-broadcast-disabled = <0>; qcom,sde-reg-dma-xin-id = <7>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index f2324b788a9a..8ca2bcd45060 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -5,7 +5,7 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x84000>, <0x0aeb0000 0x2008>, - <0x0aeac000 0x214>, + <0x0aeac000 0x800>, <0x0af50000 0x038>; reg-names = "mdp_phys", "vbif_phys", @@ -217,8 +217,9 @@ /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; @@ -260,13 +261,13 @@ }; qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-igc = <0x1260 0x00030002>; qcom,sde-dspp-hsic = <0x800 0x00010007>; qcom,sde-dspp-memcolor = <0x880 0x00010007>; qcom,sde-dspp-hist = <0x800 0x00010007>; qcom,sde-dspp-sixzone= <0x900 0x00010007>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; qcom,sde-dspp-pcc = <0x1700 0x00040000>; qcom,sde-dspp-gc = <0x17c0 0x00010008>; qcom,sde-dspp-dither = <0x82c 0x00010007>; From 908eb2d3476ec1359448b915d24518c8e1c4eb49 Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Thu, 20 Feb 2020 15:55:43 -0800 Subject: [PATCH 054/362] bindings: Documentation: add documentation of spr block entries Add documentation for SPR hardware block device tree entries. Change-Id: Id8a6d22f04002f1a294dec158288593f2da3f1a5 --- bindings/sde.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index fa854afbb2f8..0ba34a6e1d84 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -319,6 +319,10 @@ Optional properties: corresponding DSPP base. - qcom,sde-dspp-rc-size: A u32 value indicating the RC block address range. - qcom,sde-dspp-rc-mem-size: A u32 value indicating the RC block shared memory size. +- qcom,sde-dspp-spr-off: Array of u32 offsets indicate the SPR block offsets from the + corresponding DSPP block offset as base. +- qcom,sde-dspp-spr-size: A u32 value indicating the SPR block register address range +- qcom,sde-dspp-spr-version: A u32 value indicating the version of SPR hardware. - qcom,sde-vbif-id: Array of vbif ids corresponding to the offsets defined in property: qcom,sde-vbif-off. - qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit @@ -596,6 +600,9 @@ Example: qcom,sde-dspp-rc-version = <0x00010000>; qcom,sde-dspp-rc-off = <0x15800 0x14c00>; qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>: qcom,sde-dspp-rc-mem-size = <2720>; qcom,sde-dest-scaler-top-off = <0x00061000>; qcom,sde-dest-scaler-off = <0x800 0x1000>; From 09d73d2f3a722388bf23162cdfe6abaa0ed51e22 Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Mon, 3 Feb 2020 16:53:48 -0800 Subject: [PATCH 055/362] ARM: dts: msm: add support for spr hw block on lahaina This change adds device tree entries for spr hw block on lahaina Change-Id: Ibcbeb75805546e014e1025a8b3c6ab1f3884cba4 --- display/lahaina-sde.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index cb3598053881..8aeb20997a28 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -185,6 +185,10 @@ /* offsets are based off dspp 0 and dspp 1 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300>; + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + qcom,sde-uidle-off = <0x80000>; qcom,sde-uidle-size = <0x70>; From 16605c6c633bf6d2a72455ebf40aedad023f7d0b Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Thu, 20 Feb 2020 17:25:02 -0800 Subject: [PATCH 056/362] bindings: Documentation: add documentation for spr pack type Add documentation for specifying spr pack type of panel and currently supported pack type strings. Change-Id: Id069428c81d1720997a14a53a54a6fba20fdc8cf --- bindings/mdss-dsi-panel.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index f9f2634c825f..45ed1d08ec9b 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -410,6 +410,9 @@ Optional properties: - qcom,mdss-dsi-tx-eot-append: Boolean used to enable appending end of transmission packets. - qcom,ulps-enabled: Boolean to enable support for Ultra Low Power State (ULPS) mode. - qcom,suspend-ulps-enabled: Boolean to enable support for ULPS mode for panels during suspend state. +- qcom,spr-pack-type: String to specify the SPR pack type of panel pixel layout + Expected string for the pack types supported by MDSS are, + "pentile", "rgbw", "yygm", "yygw" - qcom,panel-roi-alignment: Specifies the panel ROI alignment restrictions on its left, top, width, height alignments and minimum width and height values. This property is specified per timing node to support @@ -652,6 +655,7 @@ Example: qcom,mdss-dsi-bl-max-level = < 15>; qcom,mdss-brightness-max-level = <255>; qcom,bl-update-flag = "delay_until_first_frame"; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-interleave-mode = <0>; qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,mdss-dsi-te-check-enable; From 46292b23b44b082afbefeaef0c6d81029f3f30d6 Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Mon, 23 Mar 2020 13:53:16 -0700 Subject: [PATCH 057/362] ARM: dts: msm: define ramdump buffer reservation node This change defines ramdump buffer reservation node for lahaina target. Change-Id: I9bcce869e01e533ecb4b1acc82d5e6f8c70cb197 --- display/lahaina-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 3506dd002a79..d4607746dc98 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -1,6 +1,11 @@ #include &soc { + disp_rdump_memory: disp_rdump_region@e1000000 { + reg = <0x0 0xe1000000 0x0 0x00800000>; + label = "disp_rdump_region"; + }; + mdss_mdp: qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x84000>, From ec906ed412d2cd1f004f76c3701d685553cdb52e Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 31 Mar 2020 10:32:14 -0700 Subject: [PATCH 058/362] ARM: dts: msm: add ibb and lab for AMOLED panels for lahaina Change adds LAB and IBB regulator supply for AMOLED panels for Lahaina target. Change-Id: I7e516cdbbbfc7f8e6dd7fbb61fac88779e0913bc --- display/lahaina-sde-display.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 630ac106a3c2..01a52289f2d6 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -66,6 +66,25 @@ qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <0>; }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <363000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <363000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; }; dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { @@ -128,6 +147,8 @@ vddio-supply = <&L12C>; vdd-supply = <&L13C>; avdd-supply = <&display_panel_avdd>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; From cb73c3f5b97b218d701cfe5e8bc88bc5b327d2ec Mon Sep 17 00:00:00 2001 From: Gopikrishnaiah Anandan Date: Tue, 31 Mar 2020 14:53:52 -0700 Subject: [PATCH 059/362] bindings: Documentation: add documentation for demura block entries Add documentation for demura hardware block device tree entries. Change-Id: Ieb3e8d11d80e8c5318df1a1443ca1e2a7017bc5e --- bindings/sde.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 71c521d2bff1..f61db98acd97 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -323,6 +323,10 @@ Optional properties: corresponding DSPP block offset as base. - qcom,sde-dspp-spr-size: A u32 value indicating the SPR block register address range - qcom,sde-dspp-spr-version: A u32 value indicating the version of SPR hardware. +- qcom,sde-dspp-demura-off: Array of u32 offsets indicate the demura block offsets from the + corresponding DSPP block offset as base. +- qcom,sde-dspp-demura-size: A u32 value indicating the demura block register address range +- qcom,sde-dspp-demura-version: A u32 value indicating the version of demura hardware. - qcom,sde-vbif-id: Array of vbif ids corresponding to the offsets defined in property: qcom,sde-vbif-off. - qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit @@ -605,6 +609,9 @@ Example: qcom,sde-dspp-spr-off = <0x15400 0x14400>; qcom,sde-dspp-spr-size = <0x200>; qcom,sde-dspp-spr-version = <0x00010000>: + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>: qcom,sde-dspp-rc-mem-size = <2720>; qcom,sde-dest-scaler-top-off = <0x00061000>; qcom,sde-dest-scaler-off = <0x800 0x1000>; From a67c24437d1a748aac53ea10cfe2676ce35ee17f Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Wed, 18 Mar 2020 16:47:37 -0700 Subject: [PATCH 060/362] ARM: dts: msm: enable PU on sim panel for Lahaina Change enables Partial Update feature for Simulation command mode panel for Lahaina target. Change-Id: I4ff42e64f5cc81c96c72f7983b279874f14ccff3 --- display/lahaina-sde-display.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 6e4eac5b4223..b950a7755950 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -495,6 +495,8 @@ qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; }; timing@1 { /* WQHD 60FPS vid mode*/ @@ -511,6 +513,8 @@ qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; }; timing@3 { /* FHD 60FPS cmd mode*/ @@ -519,6 +523,8 @@ qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,partial-update-enabled = "single_roi"; }; timing@4 { /* HD 60FPS cmd mode*/ @@ -527,6 +533,8 @@ qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; }; }; }; From 5e2f067715de630249c0c3b06588b3cbbeb0fe4c Mon Sep 17 00:00:00 2001 From: Gopikrishnaiah Anandan Date: Tue, 25 Feb 2020 19:25:45 -0800 Subject: [PATCH 061/362] ARM: dts: qcom: Add support for demura block on lahaina target DPU version supports demura block, change adds offsets of module. Change-Id: I97c79047b2b48a0b059c8a918d35aa09c1034766 --- display/lahaina-sde.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d4607746dc98..152ba738e3b6 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -194,6 +194,10 @@ qcom,sde-dspp-spr-size = <0x200>; qcom,sde-dspp-spr-version = <0x00010000>; + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + qcom,sde-uidle-off = <0x80000>; qcom,sde-uidle-size = <0x70>; From d332a6106d66fd39578fb04398f31f4b57b79c4b Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Thu, 20 Feb 2020 14:34:03 -0800 Subject: [PATCH 062/362] ARM: dts: msm: enable BOE panel partial update for lahaina This change enables partial update by specifying the partial update roi this panel supports. Change-Id: Ifdae12a1980d1e35a0abe36b5c3632520093c64f --- display/lahaina-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index d8e1185e4c0c..ddf30d475092 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -161,6 +161,8 @@ 05 03 02 04 00 0f 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; }; }; }; From c6543f488f2233432f8287476660baecd00777b4 Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Wed, 25 Mar 2020 13:46:47 -0400 Subject: [PATCH 063/362] ARM: dts: msm: add ebi bus for split vote on APPS RSC Split the data bus votes between MNOC and EBI when using the APPS RSC. Change-Id: I93f8e1ad3697039afae292e7561f4e807c77c2ed --- display/lahaina-sde.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 3506dd002a79..5066ab3ff0ca 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -236,12 +236,13 @@ /* data and reg bus scale settings */ interconnects = - <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP0 &gem_noc SLAVE_LLCC>, + <&mmss_noc MASTER_MDP1 &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; + &config_noc SLAVE_DISPLAY_CFG>; interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; From d7ae7e47affe5c24b4c0759041da38c80587b552 Mon Sep 17 00:00:00 2001 From: Steven Cohen Date: Sat, 14 Mar 2020 19:38:40 -0400 Subject: [PATCH 064/362] ARM: dts: msm: enable SDE RSC rev 4 on lahaina Enable the SDE RSC rev4 driver and HW, and update the interconnect bindings. Change-Id: I85336dac6d0c4081350259c636c1159c32c582a5 --- display/lahaina-sde-display.dtsi | 2 +- display/lahaina-sde.dtsi | 35 ++++++++++++-------------------- 2 files changed, 14 insertions(+), 23 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 630ac106a3c2..3b30d34f777b 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -141,7 +141,7 @@ }; &mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi>; + connectors = <&sde_dp &sde_wb &sde_dsi &sde_rscc>; }; /* PHY TIMINGS REVISION YB */ diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 5066ab3ff0ca..31fdba926563 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -29,7 +29,6 @@ 460000000>; mmcx-supply = <&VDD_MMCX_LEVEL>; - vdd-supply = <&disp_cc_mdss_core_gdsc>; /* interrupt config */ interrupts = ; @@ -235,14 +234,12 @@ qcom,sde-secure-sid-mask = <0x4000821>; /* data and reg bus scale settings */ - interconnects = - <&mmss_noc MASTER_MDP0 &gem_noc SLAVE_LLCC>, - <&mmss_noc MASTER_MDP1 &gem_noc SLAVE_LLCC>, - <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + "qcom,sde-reg-bus"; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; @@ -294,15 +291,6 @@ qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; - - qcom,platform-supply-entry@1 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; }; smmu_sde_unsec: qcom,smmu_sde_unsec_cb { @@ -461,11 +449,10 @@ sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; - status = "disabled"; - reg = <0xaf20000 0x3c50>, + reg = <0xaf20000 0x4d68>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; - qcom,sde-rsc-version = <3>; + qcom,sde-rsc-version = <4>; qcom,sde-dram-channels = <2>; @@ -474,10 +461,14 @@ <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + + qcom,msm-bus,active-only; interconnects = - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-reg-bus"; + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mmss_noc MASTER_MDP1_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-ebi-bus"; }; mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { From eb73113b8ccf4d6cba31a176cc439543c0be945e Mon Sep 17 00:00:00 2001 From: Rajkumar Subbiah Date: Fri, 3 Apr 2020 11:47:03 -0400 Subject: [PATCH 065/362] ARM: dts: msm: Enable widebus for DP This change enabled widebus support to DP so that the DP controller processes 2 pixels per clock in uncompressed mode or 6 bytes per clock in compressed mode. Change-Id: Id6b316f818b5424e3684bef99ec8e40d8df83b85 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 3506dd002a79..681d2732a806 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -391,6 +391,7 @@ qcom,max-pclk-frequency-khz = <675000>; + qcom,widebus-enable; qcom,max-dp-dsc-blks = <2>; qcom,max-dp-dsc-input-width-pixs = <2048>; From 8ba01f225dfa31b9f3d88130cc31a05254f4675e Mon Sep 17 00:00:00 2001 From: Divya Sharma Date: Fri, 3 Apr 2020 11:30:46 -0700 Subject: [PATCH 066/362] Revert "ARM: dts: msm: fix iommu smr mask for lahaina" This reverts commit c50e652f6e8583bfef1ead3be9aeb6b5b4a0c68c. Change-Id: I82b7d7b8286313d6d680db337121827663e311ab --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index fc6c9f30dc72..6d0e7591826e 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -309,7 +309,7 @@ smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x821 0x0>; + iommus = <&apps_smmu 0x821 0x400>; qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; From 1dad423801ff7fdb835cd0e44830565b160a8cd3 Mon Sep 17 00:00:00 2001 From: Rajkumar Subbiah Date: Fri, 3 Apr 2020 11:54:34 -0400 Subject: [PATCH 067/362] ARM: dts: msm: Enable DSC and FEC support for DP This change enables DSC compression and Forward Error Correction support for Display Port. Change-Id: Ib883367417e7cd5ea7090ababed1c6abe8f68594 --- display/lahaina-sde.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 681d2732a806..5daba5ffb84f 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -392,6 +392,8 @@ qcom,max-pclk-frequency-khz = <675000>; qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; qcom,max-dp-dsc-blks = <2>; qcom,max-dp-dsc-input-width-pixs = <2048>; From b8d2134cb04e8b5d6b9aaca601eab4a6279e88d7 Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Sat, 4 Apr 2020 01:57:33 -0400 Subject: [PATCH 068/362] ARM: dts: msm: specify reg bus scaling griffins for SDE on Lahaina Provide bus scaling griffins for the SDE AHB path. These values are now moved to the device-tree for scalability. Change-Id: Ic23aa5534ab0ccb1838355d6c0f9d10e9d76489c --- bindings/sde.txt | 91 ++++++++++++---------------------------- display/lahaina-sde.dtsi | 4 ++ 2 files changed, 31 insertions(+), 64 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index f61db98acd97..831e30b476b1 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -507,31 +507,25 @@ Optional properties: -- qcom,sde-limit-ids: respective ids for the above usecases -- qcom,sde-limit-values: usecase and value for different combinations -Bus Scaling Subnodes: -- qcom,sde-reg-bus: Property to provide Bus scaling for register access for - mdss blocks. -- qcom,sde-data-bus: Property to provide Bus scaling for data bus access for - mdss blocks. -- qcom,sde-llcc-bus: Property to provide Bus scaling for data bus access for - mnoc to llcc. -- qcom,sde-ebi-bus: Property to provide Bus scaling for data bus access for - llcc to ebi. - +Bus Scaling: +- interconnects An array of 4 cell properties with the format of + (src-noc master-id dst-noc slave-id) as described in: + Documentation/devicetree/bindings/interconnect/interconnect.txt + One entry for each interconnect path available. + Master/Slave ID bindings can be found at: + include/dt-bindings/interconnect/ +- interconnect-names An array of string properties associated with "interconnects" + each with a unique name used to lookup the respective path. + The following paths are currently supported: qcom,sde-reg-bus, + qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus, + qcom,sde-ebi-bus +- qcom,sde-reg-bus,vectors-KBps:A series of 2 cell properties with a format of + (ab, ib) specified in kilobytes-per-second. + Used when applying reg-bus votes and must be + given whenever "qcom,sde-reg-bus" is used. - qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle, instance id), of inline rotator device. -Bus Scaling Data: -- qcom,msm-bus,name: String property describing client name. -- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases - defined in the vectors property. -- qcom,msm-bus,num-paths: This represents the number of paths in each - Bus Scaling Usecase. -- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt - * Current values of src & dst are defined at - include/linux/msm-bus-board.h - SMMU Subnodes: - smmu_sde_****: Child nodes representing sde smmu virtual devices @@ -898,48 +892,17 @@ Example: }; }; - qcom,sde-data-bus { - qcom,msm-bus,name = "mdss_sde"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <3>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, <25 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <25 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>, - <25 512 0 6400000>; - }; - qcom,sde-llcc-bus { - qcom,msm-bus,name = "mdss_sde_llcc"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <132 770 0 0>, - <132 770 0 6400000>, - <132 770 0 6400000>; - }; - qcom,sde-ebi-bus { - qcom,msm-bus,name = "mdss_sde_ebi"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <129 512 0 0>, - <129 512 0 6400000>, - <129 512 0 6400000>; - }; - - qcom,sde-reg-bus { - /* Reg Bus Scale Settings */ - qcom,msm-bus,name = "mdss_reg"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,active-only; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 160000>, - <1 590 0 320000>; - }; + interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC> + <&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>, + <&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; smmu_kms_unsec: qcom,smmu_kms_unsec_cb { compatible = "qcom,smmu_sde_unsec"; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6675eb604202..45f323e9c4fd 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -249,6 +249,10 @@ &config_noc SLAVE_DISPLAY_CFG>; interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; From a5561be9274b99b17df9b05ce61d0d6341df8dca Mon Sep 17 00:00:00 2001 From: Lakshmi Narayana Kalavala Date: Mon, 6 Apr 2020 21:22:30 -0700 Subject: [PATCH 069/362] ARM: dts: msm: Update the LTM hardware version for Lahaina This change Updates the LTM hardware version for Lahaina target. Change-Id: I5f3ba0f13049d90977772d35a9c3dab9c2b36b13 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6675eb604202..157b77e7783a 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -185,7 +185,7 @@ qcom,sde-min-dram-ib-kbps = <800000>; qcom,sde-dram-channels = <2>; qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-ltm-version = <0x00010000>; + qcom,sde-dspp-ltm-version = <0x00010001>; /* offsets are based off dspp 0 and dspp 1 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300>; From 60f712090ae556214029287115a74bf3220d4299 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Thu, 12 Mar 2020 15:02:02 -0400 Subject: [PATCH 070/362] ARM: dts: msm: Add LUTBUS support for VIG Gamut on Lahaina On Lahaina based targets the DB LUTDMA enGine now supports the new LUTBUS DMA operation. Update VIG Gamut version to indicate the LUTBUS operation is now used for DMA programming. Change-Id: I0979be7aaaec6b8a45fd44d40523bc459dbe948e --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d4607746dc98..b388dc1d7d8d 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -252,7 +252,7 @@ qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; qcom,sde-vig-igc = <0x1d00 0x00060000>; qcom,sde-vig-inverse-pma; }; From e804b4caf00df88138648f46e13d37285a030fab Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 9 Apr 2020 06:26:10 -0700 Subject: [PATCH 071/362] ARM: dts: msm: update Sharp qsync panel DSI phy timings for lahaina Change updates PHY timings of Sharp QSYNC CMD and VID mode panels as per latest HW recommendation. Change-Id: Iaf4b886b04fcc527df3986f70cf47538eea463ab --- display/lahaina-sde-display.dtsi | 36 ++++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 5d64f743a336..23771547699f 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -329,8 +329,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03 + 03 02 02 04 00 0b 07]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -338,15 +338,15 @@ }; timing@1 { /* WQHD 60FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; timing@2 { /* FHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02 - 02 00 02 04 00 0a 12]; + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -354,8 +354,8 @@ }; timing@3 { /* WQHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0f 04 04 07 07 04 - 05 02 02 04 00 0d 09]; + qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04 + 04 03 02 04 00 0e 08]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -363,8 +363,8 @@ }; timing@4 { /* WQHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 26 0b 0a 11 0f 0b - 0b 07 02 04 00 1f 0f]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -372,15 +372,15 @@ }; timing@5 { /* WQHD 120FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; timing@6 { /* FHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 - 04 02 02 04 00 0e 13]; + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 10 03 + 03 02 02 04 00 0c 08]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -388,8 +388,8 @@ }; timing@7 { /* FHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 02 01 02 04 00 0c 12]; + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -408,8 +408,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; From 831f7d54a7172a4e54f20e45d70b9270ba71e83a Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 10 Mar 2020 19:22:41 -0700 Subject: [PATCH 072/362] ARM: dts: msm: enable secondary DSI display for lahaina Change enables secondary DSI display for lahaina target. Change-Id: I77869965a807ef2189ac4c5a822d45288c635bfa --- display/dsi-panel-r66451-dsc-qhd-cmd.dtsi | 3 ++ display/lahaina-sde-display-cdp.dtsi | 19 ++++++++- display/lahaina-sde-display-mtp.dtsi | 11 ++++++ display/lahaina-sde-display.dtsi | 47 ++++++++++++++++++++++- 4 files changed, 78 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi index 1d9d3e26f7cf..f5bb6a05fea2 100644 --- a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi @@ -14,6 +14,9 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; qcom,mdss-dsi-lane-map = "lane_map_0123"; qcom,mdss-dsi-bllp-eof-power-mode; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 5e6288b7d302..909a24d435b7 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -21,12 +21,15 @@ &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_r66451_amoled_video { @@ -114,11 +117,14 @@ &dsi_nt35695b_truly_fhd_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_sim_cmd { @@ -163,7 +169,18 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; +}; + + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; - diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 8643ec14d181..1670754abfd0 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -61,6 +61,17 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 5d64f743a336..8816b03298ea 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -154,6 +154,34 @@ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + avdd-supply = <&display_panel_avdd>; + + qcom,mdp = <&mdss_mdp>; + }; + sde_wb: qcom,wb-display@0 { compatible = "qcom,wb-display"; cell-index = <0>; @@ -162,7 +190,7 @@ }; &mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi &sde_rscc>; + connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; /* PHY TIMINGS REVISION YB */ @@ -230,6 +258,7 @@ &dsi_r66451_amoled_cmd { qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 08 07 0c 0b 07 @@ -489,6 +518,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 @@ -791,3 +821,18 @@ }; }; }; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; From b4abb17f3dbf0541470afaf24219e8419b2ee246 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 1 Apr 2020 14:28:47 +0800 Subject: [PATCH 073/362] ARM: dts: msm: set 60hz cmd mode as default mode for qrd lahaina Set 60hz cmd mode as default display panel mode, and enable ESD check for cmd mode. Changed the PHY timing settings according to the new PHY timing excel version. Change-Id: Ib026bb19595a7f30bc7b2a36ac5eeb02749b043e --- display/dsi-panel-r66451-dsc-qhd-cmd.dtsi | 262 +++++++++++----------- display/lahaina-sde-display-qrd.dtsi | 2 +- display/lahaina-sde-display.dtsi | 34 ++- 3 files changed, 148 insertions(+), 150 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi index f5bb6a05fea2..c1caaf5afd7a 100644 --- a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi @@ -37,6 +37,138 @@ qcom,mdss-dsi-te-using-te-pin; qcom,mdss-dsi-display-timings { timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <2340>; @@ -132,136 +264,6 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; - - timing@1 { - qcom,mdss-dsi-panel-framerate = <90>; - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <95>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <1>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 1a c2 09 24 0c 00 00 - 0c 03 14 00 09 3c 00 00 00 00 00 00 - 00 00 00 00 00 30 00 6c - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 19 cf 64 0b 00 00 00 - 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 02 f7 01 - 39 01 00 00 00 00 03 df 50 40 - 39 01 00 00 00 00 06 f3 50 00 00 00 00 - 39 01 00 00 00 00 02 f2 11 - 39 01 00 00 00 00 06 f3 01 00 00 00 01 - 39 01 00 00 00 00 03 f4 00 02 - 39 01 00 00 00 00 02 f2 19 - 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 2a 00 00 04 37 - 39 01 00 00 00 00 05 2b 00 00 09 23 - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 - ]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <20>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <95>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <1>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 1a c2 09 24 0c 00 00 - 0c 09 3c 00 09 3c 00 00 00 00 00 00 - 00 00 00 00 00 30 00 6c - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 13 d8 00 00 00 00 00 - 00 00 00 00 5b 00 5b 00 5b 00 5b 00 - 5b - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 19 cf 64 0b 00 00 00 - 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 02 f7 01 - 39 01 00 00 00 00 03 df 50 40 - 39 01 00 00 00 00 06 f3 50 00 00 00 00 - 39 01 00 00 00 00 02 f2 11 - 39 01 00 00 00 00 06 f3 01 00 00 00 01 - 39 01 00 00 00 00 03 f4 00 02 - 39 01 00 00 00 00 02 f2 19 - 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 2a 00 00 04 37 - 39 01 00 00 00 00 05 2b 00 00 09 23 - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 - ]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <20>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; }; }; }; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 50a41f2753b0..b28072692f4e 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -62,5 +62,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 7bfc29dc3452..0d0bb48d2298 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -239,16 +239,9 @@ &dsi_r66451_amoled_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { - /* - * CDP could not display using the old HFP(96) and HSYNC(32). - * Modified HFP to 95 and HSYNC to 1, but using the new porch - * to caculator the PHY timing based on version YB, 90hz could - * not display, need to keep the PHY timing(which based on - * HFP=96, HSYNC=32). - */ timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 - 06 04 02 04 00 12 0b]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; @@ -257,29 +250,32 @@ &dsi_r66451_amoled_cmd { qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 19 08 07 0c 0b 07 - 07 05 02 04 00 16 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 1f 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; - /* - * Using PHY Timings version YB 60hz could not display, - * refer to version W, changed T_HS_ZERO from 0x06 to 0x1e. - */ + timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 0d 04 04 07 1e 04 - 04 02 02 04 00 0c 09]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From 0c4d032cb0c95b98ba1f7e7c6acc598f737992e8 Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Wed, 25 Mar 2020 13:46:47 -0400 Subject: [PATCH 074/362] ARM: dts: msm: add ebi bus for split vote on APPS RSC Split the data bus votes between MNOC and EBI when using the APPS RSC. Change-Id: I93f8e1ad3697039afae292e7561f4e807c77c2ed --- display/lahaina-sde.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d4607746dc98..6c4fbc48afa0 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -241,12 +241,13 @@ /* data and reg bus scale settings */ interconnects = - <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP0 &gem_noc SLAVE_LLCC>, + <&mmss_noc MASTER_MDP1 &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; + &config_noc SLAVE_DISPLAY_CFG>; interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; From bbe3d8d7fbec594b45914018a2e613770c073ecd Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Wed, 25 Mar 2020 14:31:22 -0700 Subject: [PATCH 075/362] ARM: dts: msm: enable VDC sim panel on lahaina This change adds missing dtsi entry to enable VDC simulation panel for lahaina target. Change-Id: I4f99fc520831ea6828fd5542972b6155757ae0e0 --- display/lahaina-sde-display-cdp.dtsi | 12 ++++++++++++ display/lahaina-sde-display-mtp.dtsi | 12 ++++++++++++ display/lahaina-sde-display.dtsi | 24 ++++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 909a24d435b7..876780b10608 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -163,6 +163,18 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_vdc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vdc_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_sim_dsc_375_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 1670754abfd0..522e827866b2 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -72,6 +72,18 @@ qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; +&dsi_sim_vdc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vdc_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 0d0bb48d2298..b3b1589841c9 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -593,6 +593,30 @@ }; }; +&dsi_sim_vdc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vdc_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sim_dsc_375_cmd { qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; From 5de689988aec9fb9025bc068dd6fc91358387cce Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 13 Apr 2020 11:52:41 -0700 Subject: [PATCH 076/362] ARM: dts: msm: add supported panels for lahaina MTP and QRD Change adds all the supported DSI panels to the Lahaina MTP and QRD platform devicetree. These panels can be chosen on these platforms to run in simulation mode. Change-Id: Idd73668c09b2f3c12e785aad7fe6f20e7cbdde79 --- display/lahaina-sde-display-mtp.dtsi | 102 +++++++++++++++++++++++++++ display/lahaina-sde-display-qrd.dtsi | 102 +++++++++++++++++++++++++++ 2 files changed, 204 insertions(+) diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 522e827866b2..8594b9d3d0b5 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -19,6 +19,108 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index b28072692f4e..cee3ab009b04 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -19,6 +19,108 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 39a3e84c257bf802a31297644c8f287e27299712 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Mon, 6 Apr 2020 10:19:24 -0700 Subject: [PATCH 077/362] bindings: Documentation: add pm_qos cpu mask for performance This change adds documentation for pm_qos mask for performance use case. Change-Id: I8ca41b578accbe6cc67041a5abb91b0d63fbd07d Signed-off-by: Narendra Muppalla --- bindings/sde.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 831e30b476b1..f5b8e898e45d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -463,6 +463,9 @@ Optional properties: for cdp use cases in order of , and . - qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask. +- qcom,sde-qos-cpu-mask-performance: Each bit represents a CPU mask. For example + 0xf represents 4 cpu cores. These cores can be + silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. @@ -734,6 +737,7 @@ Example: qcom,sde-cdp-setting = <1 1>, <1 0>; qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-vbif-off = <0 0>; From 5db3ba7d723c4d5cd604ff2073d98b4c6cd52dc5 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Fri, 17 Apr 2020 13:12:09 -0700 Subject: [PATCH 078/362] ARM: dts: msm: update DSI PHY timings for panels on Lahaina Change updates PHY timings of DSI panels as per latest HW recommendation for lahaina target. Change-Id: I7c029a11542be4a449212b35afb81a1bc8796d2e --- display/lahaina-sde-display.dtsi | 43 ++++++++++++++++---------------- 1 file changed, 22 insertions(+), 21 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index b3b1589841c9..47efdcc7d8e4 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -193,7 +193,7 @@ connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; -/* PHY TIMINGS REVISION YB */ +/* PHY TIMINGS REVISION YC with reduced margins*/ &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; @@ -206,8 +206,8 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 - 05 03 02 04 00 0f 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05 + 05 06 02 04 00 12 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -228,8 +228,8 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 - 05 03 02 04 00 0f 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 + 05 06 02 04 00 12 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; @@ -294,8 +294,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 05 04 08 07 05 - 05 03 02 04 00 0f 09]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; @@ -314,8 +314,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 - 05 03 02 04 00 10 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06 + 06 07 02 04 00 15 0b]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; @@ -334,8 +334,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 - 08 05 02 04 00 17 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 00 1a 0c]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; qcom,mdss-dsi-panel-clockrate = <900000000>; @@ -445,8 +445,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 15 06 - 06 04 02 04 00 14 0b]; + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0a]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; @@ -466,12 +466,10 @@ qcom,mdss-dsi-display-timings { timing@0 { /* - * Using PHY Timings version W as a - * temporary solution for PHY timing issue that causes - * corruption. + * DPHY regular margins */ qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06 - 06 04 02 04 00 15 16]; + 06 07 02 04 00 17 16 ]; qcom,display-topology = <2 0 2>, <1 0 2>; qcom,default-topology-index = <0>; @@ -495,8 +493,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 19 07 07 0c 0a 07 - 07 05 02 04 00 15 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; qcom,display-topology = <2 0 2>, <1 0 2>; qcom,default-topology-index = <0>; @@ -517,8 +515,11 @@ qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 - 08 05 02 04 00 17 0c]; + /* + * DPHY regular margins + */ + qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07 + 07 07 02 04 00 18 16]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; }; From 822a8638aa6f98876c2d553391ae881f93a7c653 Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Fri, 24 Apr 2020 02:48:26 -0400 Subject: [PATCH 079/362] Revert: "dt-bindings: add documentation for sde-limit" This reverts commit 658f1491b962fceccb622a9ba78e74af3c1fc0f0 from msm-4.19 which was ported as part of the display device tree techpack. Support for sde-limits has been removed from the driver as it's no longer needed. BW limits have moved to per target based XML files in user-space and linewidth limits already have other properties for specifying. Change-Id: Idcbe8e10e94785bc5774a94e2326d2f77ce4b5ac --- bindings/sde.txt | 38 -------------------------------------- 1 file changed, 38 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 831e30b476b1..bf8e09927a86 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -497,15 +497,6 @@ Optional properties: ordering block 0: lower priority pipe has to be on the left for a given pair of pipes. 1: priority have to be explicitly configured for a given pair of pipes. -- qcom,sde-limits: A node that lists the limits for different properties. This node - can have multiple child nodes. Each child node represents a - specific usecase limit. The usecase can be defined for properties like - sspp linewidth, bw limit etc. - e.g. qcom,sde-limits - -- qcom,sde-limit-name: name of the usecase - -- qcom,sde-limit-cases: different usecases to be considered - -- qcom,sde-limit-ids: respective ids for the above usecases - -- qcom,sde-limit-values: usecase and value for different combinations Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -833,35 +824,6 @@ Example: qcom,sde-dspp-vlut = <0x0 0x00010000>; }; - qcom,sde-limits { - qcom,sde-linewidth-limits{ - qcom,sde-limit-cases = "vig", "dma", "scaling", "inline_rot"; - qcom,sde-limit-ids= <0x1 0x2 0x4 0x8>; - /* the qcom,sde-limit-values property consist of two values: - one for the usecase and the other for the value. The usecase can be - any combination of the values mentioned in qcom,sde-limit-ids. - For eg: <0x5 2560> means usecase is 0x5 and value is 2560. - 0x5 = (0x1 | 0x4) = vig + scaling. Thus the linewidth for usecase - vig + scaling = 2560 */ - qcom,sde-limit-values = <0x1 4096>, - <0x5 2560>, - <0xd 1088>, - <0x2 4096>; - }; - qcom,sde-bw-limits{ - qcom,sde-limit-cases = "per_pipe", "total_bw", "vfe_on", "cwb_on"; - qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; - qcom,sde-limit-values = <0x1 2600000>, - <0x9 2600000>, - <0x5 2600000>, - <0xd 2600000>, - <0x2 5800000>, - <0xa 5500000>, - <0x6 4400000>, - <0xe 3900000>; - }; - }; - qcom,sde-mixer-blocks { qcom,sde-mixer-gc = <0x3c0 0x00010000>; }; From 8fcb88994a4234467be2fa982388b9538690de97 Mon Sep 17 00:00:00 2001 From: Steven Cohen Date: Wed, 22 Apr 2020 13:33:04 -0400 Subject: [PATCH 080/362] ARM: dts: msm: add scaling linewidth information Add documentation for scaling linewidth property which defines the maximum linewidth supported for scaling use cases. Change-Id: Ib02ab7cf1281b4e50bcc063ac5f45112caab2576 --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index bf8e09927a86..409cae1bb374 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -114,6 +114,8 @@ Optional properties: each interface. - qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width. - qcom,sde-vig-sspp-linewidth: A u32 value indicates the max vig sspp line width. +- qcom,sde-scaling-linewidth: A u32 value indicates the max vig source pipe line width + for scaling purposes. - qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. - qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. - qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. @@ -648,6 +650,7 @@ Example: <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, <0x3b0 16>; + qcom,sde-scaling-linewidth = <2560>; qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <2560>; qcom,sde-mixer-blendstages = <0x7>; From 8ef89dbf54f7507248d372a3ed40d4150eaf8ac6 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Wed, 15 Apr 2020 20:56:30 -0700 Subject: [PATCH 081/362] bindings: Documentation: update VDC-m revision in bindings Update the VDC-m revision in bindings as per the latest programming guidelines. Change-Id: I5400b8cc5dac2c549a0697e42cedaca4b06d7e79 --- bindings/mdss-dsi-panel.txt | 4 ++-- bindings/sde.txt | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 45ed1d08ec9b..3810bb221e3a 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -540,7 +540,7 @@ Optional properties: instead of standard dcs type 0x0A. - qcom,vdc-version: An 8 bit value indicates the VDC version supported by panel. Bits[0.3] provides information about minor version while Bits[4.7] provides - major version information. It supports only VDC rev 1(Major).1(Minor) + major version information. It supports only VDC rev 1(Major).2(Minor) right now. - qcom,vdc-version-release: An 8 bit value indicated VDC version release. This has to be set to 0. - qcom,vdc-slice-height: An u32 value which indicates slice height. This should be atleast 16 lines. @@ -839,7 +839,7 @@ Example: qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <0>; - qcom,vdc-version = <0x11>; + qcom,vdc-version = <0x12>; qcom,vdc-version-release = <0>; qcom,vdc-slice-height = <256>; qcom,vdc-slice-width = <720>; diff --git a/bindings/sde.txt b/bindings/sde.txt index ffa9d7f8d04e..3b3945ecfacc 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -616,7 +616,7 @@ Example: qcom,sde-dsc-off = <0x00081000 0x00081400>; qcom,sde-vdc-off = <0x7C000>; qcom,sde-vdc-size = <0xf10>; - qcom,sde-vdc-hw-rev = "vdc_1_1"; + qcom,sde-vdc-hw-rev = "vdc_1_2"; qcom,sde-vdc-enc = <0x200>; qcom,sde-vdc-ctl = <0xf00>; qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; From d4e70b9254d42cda408fbac8d2160611a9f0c1de Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Wed, 15 Apr 2020 21:00:03 -0700 Subject: [PATCH 082/362] ARM: dts: msm: update VDC-m revision for display Update the VDC-m revision for the simulation panels and SDE as per latest programming guidelines. Change-Id: If8c1d9646aac96e06b5a3afab97dc8d7469bdcfc --- display/dsi-panel-sim-vdc-cmd.dtsi | 2 +- display/dsi-panel-sim-vdc-vid.dtsi | 2 +- display/lahaina-sde.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/dsi-panel-sim-vdc-cmd.dtsi b/display/dsi-panel-sim-vdc-cmd.dtsi index 61a47f94dcb9..32f4850ac3c6 100644 --- a/display/dsi-panel-sim-vdc-cmd.dtsi +++ b/display/dsi-panel-sim-vdc-cmd.dtsi @@ -222,7 +222,7 @@ qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "vdc"; - qcom,vdc-version = <0x11>; + qcom,vdc-version = <0x12>; qcom,vdc-version-release = <0>; qcom,vdc-slice-height = <256>; qcom,vdc-slice-width = <720>; diff --git a/display/dsi-panel-sim-vdc-vid.dtsi b/display/dsi-panel-sim-vdc-vid.dtsi index 2162e72cef4c..35cc01f1cdc2 100644 --- a/display/dsi-panel-sim-vdc-vid.dtsi +++ b/display/dsi-panel-sim-vdc-vid.dtsi @@ -215,7 +215,7 @@ qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "vdc"; - qcom,vdc-version = <0x11>; + qcom,vdc-version = <0x12>; qcom,vdc-version-release = <0>; qcom,vdc-slice-height = <256>; qcom,vdc-slice-width = <720>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d1d64720a59a..a132a3a8e1a1 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -115,7 +115,7 @@ qcom,sde-vdc-off = <0x7C000>; qcom,sde-vdc-size = <0x10>; - qcom,sde-vdc-hw-rev = "vdc_1_1"; + qcom,sde-vdc-hw-rev = "vdc_1_2"; qcom,sde-vdc-enc = <0x200>; qcom,sde-vdc-enc-size = <0x1C8>; qcom,sde-vdc-ctl = <0xf00>; From 0ea4570d7b7f339339ebceceb7007c567bf334e6 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Sun, 5 Apr 2020 22:42:35 -0400 Subject: [PATCH 083/362] ARM: dts: msm: increase max number of DSCs available for DP use case Increase the maximum number of DSCs available for DP usage to 4. This will allow 4LM topologies requiring more than 2 DSCs to be supported. Change-Id: I9b5c3c9b460a537ccdb84dd7a72d6b7218a4cae0 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d1d64720a59a..801fd5f247dc 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -396,7 +396,7 @@ qcom,widebus-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-blks = <4>; qcom,max-dp-dsc-input-width-pixs = <2048>; vdda-1p2-supply = <&L6B>; From fde81ee3b1dd40852f0b1432b307c4fb8d29708d Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Thu, 9 Apr 2020 16:09:37 -0700 Subject: [PATCH 084/362] bindings: Documentation: update DisplayPort node Update the documentation for the DisplayPort node on Lahaina. Change-Id: I22e8751db2f9b47fbdc433a2687aee41e4e746af --- bindings/sde-dp.txt | 244 ++++++++++++++++++++++++-------------------- 1 file changed, 136 insertions(+), 108 deletions(-) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index 78812304b887..75bd9a52355f 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -4,28 +4,30 @@ DP Controller: Required properties: - compatible: Should be "qcom,dp-display". - reg: Base address and length of DP hardware's memory mapped regions. - reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. - "dp_phy" - DP PHY memory region. + "dp_ahb" - AHB memory region. + "dp_aux" - AUX memory region. + "dp_link" - LINK memory region. + "dp_p0" - PCLK0 memory region. + "dp_phy" - PHY memory region. "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. "dp_mmss_cc" - Display Clock Control memory region. - "qfprom_physical" - QFPROM Phys memory region. "dp_pll" - USB3 DP combo PLL memory region. "usb3_dp_com" - USB3 DP PHY combo memory region. "hdcp_physical" - DP HDCP memory region. + "dp_p1" - DP PCLK1 memory region. + "gdsc" - DISPCC GDSC memory region. - cell-index: Specifies the controller instance. +- #clock-cells: Denotes the DP driver as a clock producer (has one or more clock outputs) - clocks: Clocks required for Display Port operation. - clock-names: Names of the clocks corresponding to handles. Following clocks are required: - "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", - "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", - "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". -- gdsc-supply: phandle to gdsc regulator node. + "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", + "strm0_pixel_clk", "strm1_pixel_clk". - vdda-1p2-supply: phandle to vdda 1.2V regulator node. - vdda-0p9-supply: phandle to vdda 0.9V regulator node. - interrupt-parent phandle to the interrupt parent device node. - interrupts: The interrupt signal from the DSI block. -- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. -- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. -- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. - qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first entry in this array corresponds to the register offset within DP AUX, while the remaining entries indicate the @@ -72,12 +74,14 @@ DP Controller: Required properties: - qcom,fec-feature-enable: FEC feature enable control node. - qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port. - qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block. -- qcom,dp-usbpd-detection: Phandle for the PMI regulator node for USB PHY PD detection. +- qcom,altmode-dev: Phandle for the AltMode GLink driver. +- usb-controller: Phandle for the USB controller. +- qcom,pll-revision: PLL hardware revision. - qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. - qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. - qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. -- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types" - can be "core", "ctrl", and "phy". Within the same type, +- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types" + can be "core", "ctrl", "pll" and "phy". Within the same type, there can be more than one instance of this binding, in which case the entry would be appended with the supply entry index. @@ -96,6 +100,10 @@ msm_ext_disp is a device which manages the interaction between external display interfaces, e.g. Display Port, and the audio subsystem. Optional properties: +- vdd_mx-supply: phandle to vdda MX regulator node +- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. +- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. +- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. - qcom,ext-disp: phandle for msm-ext-display module - compatible: Must be "qcom,msm-ext-disp" - qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node @@ -117,121 +125,141 @@ these devices will be disabled as well. Ex. Audio Codec device. - compatible : "qcom,msm-ext-disp-audio-codec-rx"; Example: - ext_disp: qcom,msm-ext-disp { - compatible = "qcom,msm-ext-disp"; - ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - }; + +ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; }; +}; - sde_dp: qcom,dp_display@0{ - cell-index = <0>; - compatible = "qcom,dp-display"; +sde_dp: qcom,dp_display@0 { + cell-index = <0>; + compatible = "qcom,dp-display"; - gdsc-supply = <&mdss_core_gdsc>; - vdda-1p2-supply = <&pm8998_l26>; - vdda-0p9-supply = <&pm8998_l1>; + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; - reg = <0xae90000 0xa84>, + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, <0x88eaa00 0x200>, <0x88ea200 0x200>, <0x88ea600 0x200>, <0xaf02000 0x1a0>, - <0x780000 0x621c>, - <0x88ea030 0x10>, - <0x88e8000 0x621c>, - <0x0aee1000 0x034>; - reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "qfprom_physical", "dp_pll", - "usb3_dp_com", "hdcp_physical"; + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>, + <0xaf03000 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>; - clock-names = "core_aux_clk", "core_usb_ref_clk_src", - "core_usb_ref_clk", "core_usb_cfg_ahb_clk", - "core_usb_pipe_clk", "ctrl_link_clk", - "ctrl_link_iface_clk", "ctrl_crypto_clk", - "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent"; + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", + "strm0_pixel_clk", "strm1_pixel_clk"; - qcom,dp-usbpd-detection = <&pm8150b_pdphy>; - qcom,ext-disp = <&ext_disp>; - qcom,phy-version = <0x420>; - qcom,dp-aux-switch = <&fsa4480>; + qcom,pll-revision = "5nm-v1"; + qcom,phy-version = <0x420>; + qcom,dp-aux-switch = <&fsa4480>; - qcom,aux-cfg0-settings = [1c 00]; - qcom,aux-cfg1-settings = [20 13 23 1d]; - qcom,aux-cfg2-settings = [24 00]; - qcom,aux-cfg3-settings = [28 00]; - qcom,aux-cfg4-settings = [2c 0a]; - qcom,aux-cfg5-settings = [30 26]; - qcom,aux-cfg6-settings = [34 0a]; - qcom,aux-cfg7-settings = [38 03]; - qcom,aux-cfg8-settings = [3c bb]; - qcom,aux-cfg9-settings = [40 03]; - qcom,max-pclk-frequency-khz = <593470>; - qcom,mst-enable; - qcom,dsc-feature-enable; - qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; - qcom,max-dp-dsc-input-width-pixs = <2048>; - pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; - pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; - pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; - qcom,aux-en-gpio = <&tlmm 43 0>; - qcom,aux-sel-gpio = <&tlmm 51 0>; - qcom,usbplug-cc-gpio = <&tlmm 38 0>; - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + qcom,aux-cfg0-settings = [1c 00]; + qcom,aux-cfg1-settings = [20 13 23 1d]; + qcom,aux-cfg2-settings = [24 00]; + qcom,aux-cfg3-settings = [28 00]; + qcom,aux-cfg4-settings = [2c 0a]; + qcom,aux-cfg5-settings = [30 26]; + qcom,aux-cfg6-settings = [34 0a]; + qcom,aux-cfg7-settings = [38 03]; + qcom,aux-cfg8-settings = [3c bb]; + qcom,aux-cfg9-settings = [40 03]; + qcom,max-pclk-frequency-khz = <593470>; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-input-width-pixs = <2048>; - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; }; + }; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <21800>; - qcom,supply-disable-load = <4>; - }; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; }; + }; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <36000>; - qcom,supply-disable-load = <32>; - }; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; }; }; }; From dc8d2605555d1e3648493bfe686d6fc990596eaa Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Wed, 8 Apr 2020 12:57:10 -0700 Subject: [PATCH 085/362] ARM: dts: msm: add device node for MSM HDCP driver on Lahaina Add device node for the MSM HDCP driver which manages communication between HLOS and TZ for HDCP related operations. Change-Id: I7b37814f1ade7f62cf73e196c834da400abba5fe --- display/lahaina-sde.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index a132a3a8e1a1..c1aa1506d31b 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -332,6 +332,10 @@ }; }; + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + sde_dp: qcom,dp_display@ae90000 { cell-index = <0>; compatible = "qcom,dp-display"; From 9023c5746e6b82e67b2b6bc7bfa51c51482fb29e Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Wed, 29 Apr 2020 18:53:45 -0700 Subject: [PATCH 086/362] ARM: dts: msm: add 144FPS configuration for sim panel on lahaina Change adds 144 FPS configuration for FHD resolution DSI simulation panel on lahaina target. Change-Id: I1cc3032fa432940af854d0990f18250a16cfb38e --- .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 52 +++++++++++++++++++ display/lahaina-sde-display.dtsi | 7 +++ 2 files changed, 59 insertions(+) diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index 118d1e935460..0d48d49b21ca 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -1433,6 +1433,58 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@17 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index b3b1589841c9..8e9cc9977dc2 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -839,6 +839,13 @@ qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; + + timing@17 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; }; }; From fb08b9d6c92f82de11bc589536bbda14b60668ba Mon Sep 17 00:00:00 2001 From: Rajkumar Subbiah Date: Wed, 6 May 2020 18:59:22 -0400 Subject: [PATCH 087/362] ARM: dts: msm: enable DP MST support on Lahaina This change enables DP MST support on Lahaina. Change-Id: Ifae606ae3b3a5402a703b147aa0701f6b13713a1 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d1d64720a59a..a995d3ab04c2 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -394,6 +394,7 @@ qcom,max-pclk-frequency-khz = <675000>; qcom,widebus-enable; + qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; qcom,max-dp-dsc-blks = <2>; From 3584180ee17618e819b8d95a4dbe5cdc9f2272b9 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 5 May 2020 11:26:32 -0700 Subject: [PATCH 088/362] ARM: dts: msm: remove load for lab/ibb supplies for lahaina While voting for LAB/IBB supplies there is no need for setting a load value. The change updates enable load property to zero so that no load value is set on these regulators for lahaina target. Change-Id: Ifb6a69b337e2e5eb8dcef853daf122db67c2059e --- display/lahaina-sde-display.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 47efdcc7d8e4..a12a242456f8 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -72,8 +72,8 @@ qcom,supply-name = "lab"; qcom,supply-min-voltage = <4600000>; qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <363000>; - qcom,supply-disable-load = <100>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; }; qcom,panel-supply-entry@3 { @@ -81,8 +81,8 @@ qcom,supply-name = "ibb"; qcom,supply-min-voltage = <4600000>; qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <363000>; - qcom,supply-disable-load = <100>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <20>; }; }; From 16e29f5526edf55bddaeac25b277b16263978253 Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Tue, 7 Apr 2020 13:51:10 -0700 Subject: [PATCH 089/362] ARM: dts: msm: add altmode device for DisplayPort client on Lahaina Add a reference to the altmode device for use in the DisplayPort driver. This update is necessitated by a change in the API for altmode client registration. Change-Id: Idaef5fab963b4c280873d30bb424cbe3e26c7419 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index f05698696aee..8960a50c342a 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -342,7 +342,7 @@ qcom,dp-aux-switch = <&fsa4480>; qcom,ext-disp = <&ext_disp>; - qcom,altmode-parent = "altmode_0"; + qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; reg = <0xae90000 0x0dc>, From 0c9c554f740c880c1d3926343d1b3d75bc59e5ca Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 15:41:26 +0800 Subject: [PATCH 090/362] ARM: dts: msm: update clock entries to support CPHY for Lahaina Add cphy specific clock entries for both the DSI controller nodes. Change-Id: I9694595cc079249ad2e4ed58d353f0cc8e3692e4 --- display/lahaina-sde-display.dtsi | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 47efdcc7d8e4..0008a22e9303 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -132,10 +132,16 @@ clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -163,10 +169,16 @@ clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; From 1f1b0dabb82d881709daedea4e1ddc5fe04d3690 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 15:48:10 +0800 Subject: [PATCH 091/362] dt-bindings: add new property to specify PHY type Add new boolean property that specifies whether the panel is using DSI CPHY. If this property is not set, default PHY type i.e. DPHY will be used. Change-Id: I82e1738e64027e74a7752996c28b10ebdfdf3e15 --- bindings/mdss-dsi-panel.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 3810bb221e3a..73cf79d6611e 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -504,7 +504,7 @@ Optional properties: - qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel for any commands that we send. - qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. - +- qcom,panel-cphy-mode: Boolean to specify whether panel is using cphy. - qcom,compression-mode: Select compression mode for panel. "fbc" - frame buffer compression "dsc" - display stream compression. From b73db2e05491d57d1001a6fbab7405698e86f7ce Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 21:37:11 +0800 Subject: [PATCH 092/362] ARM: dts: msm: add r66451 cphy panel support for lahaina Add DDIC R66451 Visionox panel CPHY cmd and video mode support. Change-Id: I1952f26dd0437816a5f367f09c4664fb6420966c --- ...si-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi | 100 ++++++++++++++++++ ...-panel-r66451-dsc-fhd-plus-video-cphy.dtsi | 83 +++++++++++++++ display/lahaina-sde-display-cdp.dtsi | 19 ++++ display/lahaina-sde-display-mtp.dtsi | 19 ++++ display/lahaina-sde-display-qrd.dtsi | 19 ++++ display/lahaina-sde-display.dtsi | 28 +++++ 6 files changed, 268 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi new file mode 100644 index 000000000000..8b540370ae41 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi @@ -0,0 +1,100 @@ +&mdss_mdp { + dsi_r66451_amoled_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-mdp-transfer-time-us = <15300>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 03 eb 00 00 + 39 01 00 00 00 00 02 f7 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 06 B6 6c 00 06 23 a6 + 39 01 00 00 00 00 02 B4 20 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi new file mode 100644 index 000000000000..4e898a61b030 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi @@ -0,0 +1,83 @@ +&mdss_mdp { + dsi_r66451_amoled_video_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_vid { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 06 B6 6c 00 06 23 a6 + 39 01 00 00 00 00 02 B4 20 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 876780b10608..3597392d094b 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -41,6 +41,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sharp_4k_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 8594b9d3d0b5..67eab860d2d8 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -38,6 +38,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sharp_4k_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index cee3ab009b04..913eb806336b 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -19,6 +19,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sw43404_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 0008a22e9303..a2a1caf972ab 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -13,6 +13,8 @@ #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" #include "dsi-panel-r66451-dsc-qhd-cmd.dtsi" #include "dsi-panel-r66451-dsc-qhd-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" @@ -294,6 +296,32 @@ }; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; From e6b74221c0a1023ffd38acccfd0dfde820c9c717 Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Mon, 20 Apr 2020 17:43:45 -0700 Subject: [PATCH 093/362] ARM: dts: msm: reduce the minimum vote on ahb bus This change ensures that voltage on CNOC does not scale to a higher voltage corner than intended. Display driver only intends to enable the CNOC on power collapse restore. When display really needs higher performance i.e. at first commit it votes for the real bandwidth required. Change-Id: Ib9d9786aed0315fe0457ccb6dbcb73a5a8ad2917 --- display/lahaina-sde.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8960a50c342a..499c0aeb019d 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -250,9 +250,9 @@ interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", "qcom,sde-reg-bus"; qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 76800>, - <0 150000>, - <0 300000>; + <0 74000>, + <0 148000>, + <0 265000>; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; From cec7bba2f9138774c8befe3aeb557c29373daa86 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 11 May 2020 16:06:46 -0700 Subject: [PATCH 094/362] ARM: dts: msm: ensure display GPIO regulator is on during boot Change adds regulator-boot-on property to the GPIO controlled regulator so that the GPIO doesn't get toggeled during boot from UEFI to kernel. Change-Id: Ib0600ff5177de467e27f9efd09da623dc1c238a4 --- display/lahaina-sde-display.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 47efdcc7d8e4..d04261009f13 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -119,6 +119,7 @@ regulator-enable-ramp-delay = <233>; gpio = <&tlmm 12 0>; enable-active-high; + regulator-boot-on; pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; From 75c18d2d7993b2155ebf039c1d9bc3c320cb4ca7 Mon Sep 17 00:00:00 2001 From: Divya Sharma Date: Wed, 13 May 2020 12:17:56 -0700 Subject: [PATCH 095/362] Revert "ARM: dts: msm: add ebi bus for split vote on APPS RSC" This reverts commit 0c4d032cb0c95b98ba1f7e7c6acc598f737992e8. Change-Id: I4a5f0320abe3932d4e0cb991a722b85e0410ea3a --- display/lahaina-sde.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6c4fbc48afa0..d4607746dc98 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -241,13 +241,12 @@ /* data and reg bus scale settings */ interconnects = - <&mmss_noc MASTER_MDP0 &gem_noc SLAVE_LLCC>, - <&mmss_noc MASTER_MDP1 &gem_noc SLAVE_LLCC>, - <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; + &config_noc SLAVE_DISPLAY_CFG>; interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + "qcom,sde-reg-bus"; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; From 6ee7552fd34fb0f384982126a4fa895abc395842 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 13 May 2020 13:45:07 -0700 Subject: [PATCH 096/362] bindings: Documentation: add MDSS HW version Add documentation for the MDSS HW version parameter. Change-Id: I573c885057f98843037d06278600e3b07683872e --- bindings/sde.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index a2b2fba88cb7..1aeb4b45759d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -98,6 +98,7 @@ Optional properties: -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off +- qcom,sde-hw-version: A u32 value indicates the MDSS hw version - qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. - qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. - qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. @@ -578,6 +579,7 @@ Example: iommus = <&mdp_smmu 0>; #power-domain-cells = <0>; + qcom,sde-hw-version = <0x70000000>; qcom,sde-off = <0x1000>; qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 0x00002600 0x00002800>; From 3066fde623074e51a2ffcfd6072f6e639588a5d1 Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Fri, 15 May 2020 08:10:47 -0700 Subject: [PATCH 097/362] ARM: dts: msm: make smmu devices as separated device on lahaina This change adds smmu devices as separate devices so that driver waits for these devices to bind before using any smmu operation. This fixes recent stability issues where devices were not probed during the dpu hw initialization. Change-Id: If605ae258b0fc4a314e142b185d6d4553ed30b07 --- display/lahaina-sde-display.dtsi | 3 ++- display/lahaina-sde.dtsi | 32 ++++++++++++++++---------------- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index c67153317aec..2f92a01650bf 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -205,7 +205,8 @@ }; &mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi + &sde_dsi1 &sde_rscc>; }; /* PHY TIMINGS REVISION YC with reduced margins*/ diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8960a50c342a..688a1454baef 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -306,22 +306,6 @@ }; }; - smmu_sde_unsec: qcom,smmu_sde_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&apps_smmu 0x820 0x402>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-earlymap; /* for cont-splash */ - }; - - smmu_sde_sec: qcom,smmu_sde_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x821 0x400>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-vmid = <0xa>; - }; - }; ext_disp: qcom,msm-ext-disp { @@ -669,4 +653,20 @@ }; }; + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + }; From af515c56bc55d6ac8e9d5a61967252bced6f27b9 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Sat, 9 May 2020 15:13:02 +0800 Subject: [PATCH 098/362] ARM: dts: msm: add memory region for pll_codes on Lahaina Add memory region for pll_codes on Lahaina, and the pll_codes are used as trim_codes for RFI. Change-Id: Ib1f8d59cc0c3e17a4c9f21894504e1be897a0480 Signed-off-by: Bruce Hoo --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8960a50c342a..237bf948b08a 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -605,6 +605,7 @@ vdda-0p9-supply = <&L5B>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; qcom,platform-strength-ctrl = [55 03 55 03 55 03 From 495f1e2dfc4761c4208e2271f90286156ee3b70a Mon Sep 17 00:00:00 2001 From: Manoj Kumar Amara Date: Wed, 6 May 2020 19:53:51 +0800 Subject: [PATCH 099/362] ARM: dts: msm: enable RFI on lahaina Add clock settings to enable RFI on lahaina. Change-Id: I40f1e89d3e6d40691c58ab25a0278808ec70506a --- display/lahaina-sde-display.dtsi | 34 ++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index c67153317aec..515b2ae44c91 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -134,17 +134,29 @@ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1"; + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -218,6 +230,8 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; qcom,mdss-dsi-display-timings { timing@0 { @@ -239,7 +253,11 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-qsync-min-refresh-rate = <55>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; qcom,mdss-dsi-display-timings { timing@0 { From 2b50793dc29013f7c7e82bf185ebe5e1049a573d Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 21 May 2020 14:13:39 -0700 Subject: [PATCH 100/362] ARM: dts: msm: fix compilation error for lahaina Change fixes compilation error introduced by merGing commit 1f7eae5101a9 ("ARM: dts: msm: enable RFI on lahaina"). Change-Id: I1cbf7f3069228d3af1ae56ea05043819ac472814 --- display/lahaina-sde-display.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 05492eeeaf7b..616b9d2347d0 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -144,7 +144,7 @@ <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, @@ -154,7 +154,7 @@ "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; + "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", "shadow_byte_clk1", "shadow_pixel_clk1"; From e90f44aec82af31c1f934d81afbdb9bd34f4c1c4 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 7 May 2020 12:38:55 -0700 Subject: [PATCH 101/362] ARM: dts: msm: remove qsync property for BOE command mode panel for lahaina QSYNC is not supported by the BOE WQHD command mode panel. The change removes the property from the panel device tree. Change-Id: I8f771f3547aabd4b516f17cf2506ebef901ea3d4 --- display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi index a46f4e80548b..5c1f1e284eea 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi @@ -36,7 +36,6 @@ 17000 15500 30000 8000 3000>; qcom,mdss-dsi-panel-peak-brightness = <4200000>; qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,mdss-dsi-qsync-min-refresh-rate = <55>; qcom,mdss-dsi-display-timings { timing@0 { @@ -98,14 +97,6 @@ qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 5a 01]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_lp_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 5a 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_lp_mode"; qcom,mdss-dsi-lp1-command = [ 05 01 00 00 00 00 02 39 00 ]; From ee156a0aeae2281ba9720ea36163137dd5060f5c Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 14 May 2020 10:36:11 -0700 Subject: [PATCH 102/362] ARM: dts: msm: add 60 FPS for Sharp qhd plus panel for lahaina Change adds 60 FPS timing node and switch command for Sharp QHD plus command mode panel for lahaina target. Change-Id: I1bd7720a9d6be4f66418886dd7efeb7236e86a19 --- display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi | 183 ++++++++++++++++++ display/lahaina-sde-display.dtsi | 9 +- 2 files changed, 191 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi index 06c9b92e86d6..90fb731fbb88 100644 --- a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi +++ b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi @@ -38,6 +38,14 @@ qcom,mdss-dsi-v-front-porch = <39>; qcom,mdss-dsi-v-pulse-width = <2>; qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + ]; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 04 df 97 51 e8 39 01 00 00 00 00 02 de 00 @@ -194,6 +202,181 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@1 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 34 c6 00 12 8a 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 8a 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 4f5920b47a68..9ca4fb4a028a 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -504,12 +504,19 @@ &dsi_sharp_qhd_plus_dsc_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { - timing@0 { + timing@0 { /* 120 FPS */ qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 06 06 02 04 00 13 0a]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; + + timing@1 { /* 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; }; }; From 7b4ad6435cf4585cd3d464c94bbf538e6525f632 Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Tue, 19 May 2020 13:55:29 -0700 Subject: [PATCH 103/362] bindings: Documentation: add documentation for wb linear line width This change adds documentation for device tree entry to specify writeback maximum supported line width in case of linear formats. Change-Id: I7c68404cd066eec55b6114d84cc4fefdda94c03c --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 1aeb4b45759d..18e8bc6b76b5 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -119,6 +119,8 @@ Optional properties: for scaling purposes. - qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. - qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. +- qcom,sde-wb-linewidth-linear: A u32 value indicates the max line width + supported by WB for linear color formats. - qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. - qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for alpha blending. @@ -683,6 +685,7 @@ Example: qcom,sde-dest-scaler-size = <0x800>; qcom,sde-len = <0x100>; qcom,sde-wb-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <5120>; qcom,sde-sspp-scale-size = <0x100>; qcom,sde-mixer-blendstages = <0x8>; qcom,sde-qseed-type = "qseedv2"; From bc5a54da545096e7a1af610ad60fadb6d0dbaadf Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Tue, 19 May 2020 13:49:27 -0700 Subject: [PATCH 104/362] ARM: dts: msm: add wb max width for linear formats on lahaina This change adds maximum line width supported by WB for linear color formats on lahaina target. Change-Id: I0ef7a2a725053d69205f42744e2e732de4c1f257 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6f122c8748c6..81d823581b43 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -161,6 +161,7 @@ qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <4096>; qcom,sde-wb-linewidth = <4096>; + qcom,sde-wb-linewidth-linear = <5120>; qcom,sde-mixer-blendstages = <0xb>; qcom,sde-highest-bank-bit = <0x3>; qcom,sde-ubwc-version = <0x400>; From 1c9a75cd986a59feab9d6dadfab3ad6a47350fc9 Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Tue, 26 May 2020 14:30:43 -0700 Subject: [PATCH 105/362] bindings: Documentation: add USB PHY device for DisplayPort client Add a reference to the usb_qmp_dp_phy device for use in the DisplayPort driver. This will be used to register for USB cable connect and disconnect events. Change-Id: I7d15dc04bde4e54c1007ee078d56c623b3453339 --- bindings/sde-dp.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index 75bd9a52355f..fe55491f448d 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -77,6 +77,7 @@ DP Controller: Required properties: - qcom,altmode-dev: Phandle for the AltMode GLink driver. - usb-controller: Phandle for the USB controller. - qcom,pll-revision: PLL hardware revision. +- usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events. - qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. - qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. - qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. From 77f29ceb0e61776a682e447d65bb30d1579b8111 Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Fri, 22 May 2020 12:41:34 -0700 Subject: [PATCH 106/362] ARM: dts: msm: add USB PHY device for DisplayPort client on Lahaina Add a reference to the usb_qmp_dp_phy device for use in the DisplayPort driver. This will be used to register for USB cable connect and disconnect events. Change-Id: I0bb05815ccf17eca4f5148a48af20bac5b91e5fb --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6f122c8748c6..3e32041de76a 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -324,6 +324,7 @@ cell-index = <0>; compatible = "qcom,dp-display"; + usb-phy = <&usb_qmp_dp_phy>; qcom,dp-aux-switch = <&fsa4480>; qcom,ext-disp = <&ext_disp>; qcom,altmode-dev = <&altmode 0>; From 0e1855112a02851f229a966c4319815c2c2fe865 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Fri, 29 May 2020 14:22:38 -0700 Subject: [PATCH 107/362] ARM: dts: msm: add proxy supply property to GPIO controlled regulator The change adds proxy supply entries to the GPIO controlled regulator display_panel_avdd. It is necessary to add the regulator to the proxy consumer list along with the regulator-boot-on property as this is the only way to ensure that the vote on the regulator stays on till the display driver is probed. Change-Id: I955834dcd0ee93646c5700f7d174931d1b0f5ba7 --- display/lahaina-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 9ca4fb4a028a..11a2d8ef4db6 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -122,6 +122,8 @@ gpio = <&tlmm 12 0>; enable-active-high; regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; From 4f0e53e6dfd6a2f1aa9bed7b00b3eb51f1f89091 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 30 Apr 2020 15:50:12 +0800 Subject: [PATCH 108/362] ARM: dts: msm: update brightness setting for panels on Lahaina In general brightness value, the first parameter is low byte and the second is high byte, but some DDIC invert, so add brightness setting for inverted display brightness value for r66451 display panel. Change-Id: I2662e449b8902fce8e696661e1400893ab532b9a --- display/lahaina-sde-display-cdp.dtsi | 2 ++ display/lahaina-sde-display-mtp.dtsi | 2 ++ display/lahaina-sde-display-qrd.dtsi | 2 ++ 3 files changed, 6 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 3597392d094b..2061e5db40b0 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -27,6 +27,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-sec-reset-gpio = <&tlmm 25 0>; @@ -38,6 +39,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 67eab860d2d8..dfae6039ca0f 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -25,6 +25,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -35,6 +36,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 913eb806336b..bb711e419e3c 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -6,6 +6,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -16,6 +17,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; From 24548d86239f997ee3315fc28dea471b1ee8f9fd Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 30 Apr 2020 15:54:22 +0800 Subject: [PATCH 109/362] dt-bindings: Add documentation for display brightness property setting Add a boolean to specify whether to invert the display brightness value. Change-Id: I28de475db2be036c441a6af5f9becc425eba991f --- bindings/mdss-dsi-panel.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 73cf79d6611e..9fee318fbeb2 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -199,6 +199,8 @@ Optional properties: 0 = default value. - qcom,mdss-dsi-bl-max-level: Specifies the max backlight level supported by the panel. 255 = default value. +- qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value. + When this boolean is set, will inverted display brightness value. - qcom,mdss-brightness-max-level: Specifies the max brightness level supported. 255 = default value. - qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. From 0ac26560859e0338571735dbb2e057c72714e09b Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Mon, 11 May 2020 16:22:03 +0800 Subject: [PATCH 110/362] ARM: dts: msm: rename the panel dtsi file for qrd lahaina This panel is a FHD+, not a QHD, so rename the file name. Change-Id: Ied238ffadb9c454510f773bf4a8cab873151056c --- ...sc-qhd-cmd.dtsi => dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi} | 2 +- ...hd-video.dtsi => dsi-panel-r66451-dsc-fhd-plus-video.dtsi} | 2 +- display/lahaina-sde-display.dtsi | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) rename display/{dsi-panel-r66451-dsc-qhd-cmd.dtsi => dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi} (99%) rename display/{dsi-panel-r66451-dsc-qhd-video.dtsi => dsi-panel-r66451-dsc-fhd-plus-video.dtsi} (97%) diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi similarity index 99% rename from display/dsi-panel-r66451-dsc-qhd-cmd.dtsi rename to display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index c1caaf5afd7a..fd53d15d6390 100644 --- a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_r66451_amoled_cmd: qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd { qcom,mdss-dsi-panel-name = - "r66451 amoled cmd mode dsi visionx panel with DSC"; + "r66451 amoled cmd mode dsi visionox panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,mdss-dsi-virtual-channel-id = <0>; diff --git a/display/dsi-panel-r66451-dsc-qhd-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi similarity index 97% rename from display/dsi-panel-r66451-dsc-qhd-video.dtsi rename to display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 9b86cfa0323c..2201ce22808e 100644 --- a/display/dsi-panel-r66451-dsc-qhd-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_r66451_amoled_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_video { qcom,mdss-dsi-panel-name = - "r66451 amoled video mode dsi visionx panel with DSC"; + "r66451 amoled video mode dsi visionox panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 9ca4fb4a028a..e02e4c5167e0 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -11,10 +11,10 @@ #include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" -#include "dsi-panel-r66451-dsc-qhd-cmd.dtsi" -#include "dsi-panel-r66451-dsc-qhd-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" From 51404aaf358bf18f569f421fa8bb06cfb997c24d Mon Sep 17 00:00:00 2001 From: Rajkumar Subbiah Date: Tue, 2 Jun 2020 18:48:51 -0400 Subject: [PATCH 111/362] ARM: dts: msm: reduce dsc count to 2 for DP DP driver currently uses this value for number of DSCs available for external displays without allowing for DSI concurrency. This causes mode validation failures if DSI also needs to use DSCs. Limiting the DSC count to 2 for external display to allow for concurrencies. Change-Id: If760c609c1f304af77f825e211343277ff8d3fe2 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 24e47646458b..8d61e93d2d65 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -387,7 +387,7 @@ qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <4>; + qcom,max-dp-dsc-blks = <2>; qcom,max-dp-dsc-input-width-pixs = <2048>; vdda-1p2-supply = <&L6B>; From fa5b2b1838bdae96751743880a147fb875ab5966 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Tue, 24 Mar 2020 17:52:21 -0400 Subject: [PATCH 112/362] ARM: dts: msm: Uprev DSPP IGC to version 4.0 on Lahaina target Update the DSPP IGC version to 4.0 for Lahaina family Change-Id: I13ba4b9a9160a6ff4b5f64d1fcaf8f33c16a1328 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 24e47646458b..e2114c3078f1 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -281,7 +281,7 @@ }; qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x1260 0x00030002>; + qcom,sde-dspp-igc = <0x1260 0x00040000>; qcom,sde-dspp-hsic = <0x800 0x00010007>; qcom,sde-dspp-memcolor = <0x880 0x00010007>; qcom,sde-dspp-hist = <0x800 0x00010007>; From 2477bc6ba2f74d62510224b949346ef6ad455ad1 Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Thu, 4 Jun 2020 10:17:16 -0700 Subject: [PATCH 113/362] ARM: dts: msm: enable io coherency on unsecure cb for Lahaina Enable io coherency for non-secure context bank for lahaina target. This support is not needed for secure context bank because secure cb only maps secure buffers which are not cpu accessible. Change-Id: If693842c68fa714c6eee5c62437432ffbe80f749 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 24e47646458b..5204abeb9c49 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -662,6 +662,7 @@ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent-hint-cached; }; smmu_sde_sec: qcom,smmu_sde_sec_cb { From fd56398bdf7437044f7c1e89c18161377b56cd08 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Mon, 1 Jun 2020 15:02:31 +0800 Subject: [PATCH 114/362] ARM: dts: msm: change init sequence for r66451 panel DDIC R66451 cmd mode dynamic fps switch only can work based on 120hz initial parameters. Changed 60hz and 90hz initial parameters based on 120hz, so that DFPS can work on all the FPS. Change-Id: I94c377c605c2eb50fb9ec494f5987272297e6a1e --- .../dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi | 90 ++++++++++++++++--- 1 file changed, 80 insertions(+), 10 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index fd53d15d6390..dc7a7f908ba1 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -62,17 +62,46 @@ qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 13 d8 00 00 00 00 00 - 00 00 00 00 5b 00 5b 00 5b 00 5b 00 - 5b + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 @@ -83,6 +112,10 @@ 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; @@ -129,14 +162,47 @@ ]; qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 @@ -147,6 +213,10 @@ 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; From 0866bc4e8b60d5a322e2fd580c4df7d88df23633 Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Mon, 8 Jun 2020 12:08:52 -0700 Subject: [PATCH 115/362] ARM: dts: msm: set nom MDP clock during cont-splash Set nominal MDP clock during cont-splash usecase to support higher FPS usecases. Change-Id: Iabcb5ab01a2cd3b227cee2d80ef6fee14b257c2d --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8d61e93d2d65..e162628d6adb 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -29,7 +29,7 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; - clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>; + clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>; clock-max-rate = <0 0 0 0 460000000 19200000 460000000 460000000>; From c7186ef74d46684e08e8c99803f3de7f166acc6e Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Wed, 27 May 2020 09:45:45 -0400 Subject: [PATCH 116/362] dt-bindings: Move documentation for DSC line width to SDE node Add an u32 value to specify the DSC maximum linewidth hardware restriction in SDE node and remove unused DSC nodes from DP driver. Change-Id: I7439efba350c6a70c371f9aaec7cf61b9c15b3c8 --- bindings/sde-dp.txt | 4 ---- bindings/sde.txt | 2 ++ 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index fe55491f448d..567cbd7dd81b 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -72,8 +72,6 @@ DP Controller: Required properties: - qcom,mst-enable: MST feature enable control node. - qcom,dsc-feature-enable: DSC feature enable control node. - qcom,fec-feature-enable: FEC feature enable control node. -- qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port. -- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block. - qcom,altmode-dev: Phandle for the AltMode GLink driver. - usb-controller: Phandle for the USB controller. - qcom,pll-revision: PLL hardware revision. @@ -199,8 +197,6 @@ sde_dp: qcom,dp_display@0 { qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; - qcom,max-dp-dsc-input-width-pixs = <2048>; vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; diff --git a/bindings/sde.txt b/bindings/sde.txt index 18e8bc6b76b5..cf824c15d47d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -236,6 +236,7 @@ Optional properties: - qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc block can support native 422 and native 420 encoding. +- qcom,sde-dsc-linewidth: A u32 value indicates the max dsc line width. - qcom,sde-vdc-off: A u32 offset address for the available vdc blocks. This offset is calculated from register "mdp_phys" defined in reg property. @@ -661,6 +662,7 @@ Example: qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <2560>; qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-dsc-linewidth = <2048>; qcom,sde-highest-bank-bit = <0x2>; qcom,sde-ubwc-version = <0x100>; qcom,sde-ubwc-static = <0x100>; From 96052ad9db09022094dcfa089068939948a69dac Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Thu, 28 May 2020 12:58:52 -0400 Subject: [PATCH 117/362] ARM: dts: msm: Move DSC hardware properties to SDE node Move DSC related hardware properties to SDE node since DSC block is managed by SDE driver. Change-Id: I4d923bdc6fa8f53e5f2eeb49657ef03b8ef8c352 --- display/lahaina-sde.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8d61e93d2d65..dde5951caedb 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -107,6 +107,7 @@ qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>; qcom,sde-dsc-ctl-size = <0x10>; qcom,sde-dsc-native422-supp = <0 0 1 1>; + qcom,sde-dsc-linewidth = <2048>; qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; @@ -387,8 +388,6 @@ qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; - qcom,max-dp-dsc-input-width-pixs = <2048>; vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; From cb4272c79d43d31a9aab9ce92dce659fb1d85372 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Thu, 11 Jun 2020 14:37:41 -0700 Subject: [PATCH 118/362] bindings: Documentation: rename qseed_type binding Rename sde-qseed-type property to sde-qseed-sw-lib-rev to indicate that it represents the sw library version supporting the qseed hw. Change-Id: I0f29c6e99d9e7f0dc322dddb516cdc6938b33eb2 --- bindings/sde.txt | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index cf824c15d47d..dc5649953226 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -124,10 +124,11 @@ Optional properties: - qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. - qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for alpha blending. -- qcom,sde-qseed-type: A string entry indiates qseed support on sspp and wb. - It supports "qssedv3" and "qseedv2" entries for qseed - type. By default "qseedv2" is used if this optional property - is not defined. +- qcom,sde-qseed-sw-lib-rev: A string entry indicates qseed sw library revision + supporting the qseed HW block. It supports + "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed + revision. By default "qseedv2" is used if this + optional property is not defined. - qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. It supports "csc" and "csc-10bit" entries for csc type. @@ -690,7 +691,7 @@ Example: qcom,sde-wb-linewidth-linear = <5120>; qcom,sde-sspp-scale-size = <0x100>; qcom,sde-mixer-blendstages = <0x8>; - qcom,sde-qseed-type = "qseedv2"; + qcom,sde-qseed-sw-lib-rev = "qseedv2"; qcom,sde-csc-type = "csc-10bit"; qcom,sde-highest-bank-bit = <15>; qcom,sde-has-mixer-gc; From a96a8d819a5bb6ce968cca9fdb30810a8ff5535c Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 2 Jun 2020 12:22:27 -0700 Subject: [PATCH 119/362] ARM: dts: msm: rename qseed type property Rename sde-qseed-type property to sde-qseed-sw-lib-rev to indicate that it represents the sw library version supporting the qseed hw. Change-Id: Ie5dfd00714381d2ccdc319932562b5e25f4b781c --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 80451ce012c8..523452d24cfa 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -157,7 +157,7 @@ <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; qcom,sde-sspp-csc-off = <0x1a00>; qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; qcom,sde-sspp-qseed-off = <0xa00>; qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <4096>; From 71ed21b1505883efc1a1b6a418845b8179539874 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 2 Jun 2020 13:17:34 -0700 Subject: [PATCH 120/362] bindings: Documentation: add a property for QSEED HW revision Add a SDE property for QSEED HW block revision. Change-Id: I1380c76a9f631267a9726f3b4d86fe3b2560c04c --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index dc5649953226..8c1ec8cf4bcf 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -129,6 +129,8 @@ Optional properties: "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed revision. By default "qseedv2" is used if this optional property is not defined. +- qcom,sde-qseed-scalar-version: A u32 value indicating the HW version of the + QSEED hardware block - qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. It supports "csc" and "csc-10bit" entries for csc type. @@ -692,6 +694,7 @@ Example: qcom,sde-sspp-scale-size = <0x100>; qcom,sde-mixer-blendstages = <0x8>; qcom,sde-qseed-sw-lib-rev = "qseedv2"; + qcom,sde-qseed-scalar-version = <0x3000>; qcom,sde-csc-type = "csc-10bit"; qcom,sde-highest-bank-bit = <15>; qcom,sde-has-mixer-gc; From 278cff5a67437b5b4823097242eb4ba949f5210a Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Thu, 11 Jun 2020 14:42:42 -0700 Subject: [PATCH 121/362] ARM: dts: msm: add a property for QSEED HW revision Add a SDE property for QSEED HW block revision for lahaina. Change-Id: Ie8623d013a623427a2318c537097c2a109f73768 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 523452d24cfa..e222e35f2b30 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -158,6 +158,7 @@ qcom,sde-sspp-csc-off = <0x1a00>; qcom,sde-csc-type = "csc-10bit"; qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; qcom,sde-sspp-qseed-off = <0xa00>; qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <4096>; From ff94236a3ab5b04c73c0b4cc465d9cfd34eb4582 Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Mon, 15 Jun 2020 10:14:50 -0700 Subject: [PATCH 122/362] ARM: dts: msm: update irq latency for mdss irq on lahaina target Update irq latency node for lahaina target in SDE driver for mdss irq. Change-Id: Id19d3abd34454d1a8d1e43a7a0bc62daa750011c --- bindings/sde.txt | 2 ++ display/lahaina-sde.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index cf824c15d47d..423532d1ac04 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -473,6 +473,7 @@ Optional properties: 0xf represents 4 cpu cores. These cores can be silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. +- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, @@ -740,6 +741,7 @@ Example: qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-id = <0 1>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index a48726e69e2f..66286ea86fee 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -232,6 +232,7 @@ qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; /* offsets are relative to "mdp_phys + qcom,sde-off */ From db7763cf5d1833a1bb5d4ca374ae5fcf8caedf6f Mon Sep 17 00:00:00 2001 From: Gopikrishnaiah Anandan Date: Mon, 15 Jun 2020 16:38:28 -0700 Subject: [PATCH 123/362] ARM: dts: msm: Add hdr capabilities to r66451 panel Add hdr capabilities to the panel dtsi so that DPU can support the tone mapping for HDR video playback use-cases. Change-Id: I3a121b54861e882bb93a1735a9f39cdafe5144f6 --- display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index dc7a7f908ba1..9f31efd5478f 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -35,6 +35,9 @@ qcom,mdss-dsi-te-dcs-command = <1>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-framerate = <60>; From 658ad44fed55fd45ef4ef060830e9e36821df02e Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Wed, 17 Jun 2020 15:48:15 -0700 Subject: [PATCH 124/362] ARM: dts: msm: add clk status register for lahaina target Add sspp and wb2 clock active status register and bit offset index for lahaina target. This is required to check hw blocks' idle vs busy status. Change-Id: I0834a267e8c4f007a92da0852e33b1e0e02de226 --- bindings/sde.txt | 12 ++++++++++-- display/lahaina-sde.dtsi | 4 ++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index a29dc87f2b61..93e968a01ab9 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -178,10 +178,10 @@ Optional properties: match the number of offsets defined in property: qcom,sde-sspp-off - qcom,sde-sspp-clk-status: Array of offsets describing clk status - offsets for dynamic clock gating. 1st value + offsets for clock active state. 1st value in the array represents offset of the status register. 2nd value represents bit offset within - control register. Number of offsets defined should + status register. Number of offsets defined should match the number of offsets defined in property: qcom,sde-sspp-off. - qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle @@ -359,6 +359,13 @@ Optional properties: control register. Number of offsets defined should match the number of offsets defined in property: qcom,sde-wb-off +- qcom,sde-wb-clk-status: Array of 2 cell property describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off - qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks, relative to "regdma_phys" defined in reg property. - qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the @@ -724,6 +731,7 @@ Example: qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 90de1c6c2365..e7d0bc65d019 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -79,6 +79,7 @@ qcom,sde-wb-xin-id = <6>; qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; @@ -155,6 +156,9 @@ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>, + <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>; qcom,sde-sspp-csc-off = <0x1a00>; qcom,sde-csc-type = "csc-10bit"; qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; From 3104096ce82a0cc9b0a48cc0b9c340a0933ebc39 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Fri, 19 Jun 2020 23:59:29 -0700 Subject: [PATCH 125/362] ARM: dts: msm: create sde-common device tree on lahaina target Separate and maintain common SDE bindings in sde-common dt file(s). It avoids unwanted duplications between VM variants of the SDE files. It also helps developers with single-dt update for bindings applicable to all the VM's for Lahaina target. For easy maintenance, the recommendation would be to add any VM specific bindings in VM DT files instead of adding them to common DT and use "delete-property" operator to update the VM DT file. Change-Id: I8eaae7355b1c44138d6e032e3cf26f44069bc843 --- display/lahaina-sde-common.dtsi | 370 +++++++++++ display/lahaina-sde-display-common.dtsi | 718 +++++++++++++++++++++ display/lahaina-sde-display.dtsi | 787 +++--------------------- display/lahaina-sde.dtsi | 627 +++++-------------- 4 files changed, 1305 insertions(+), 1197 deletions(-) create mode 100644 display/lahaina-sde-common.dtsi create mode 100644 display/lahaina-sde-display-common.dtsi diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi new file mode 100644 index 000000000000..8dd8954df0c3 --- /dev/null +++ b/display/lahaina-sde-common.dtsi @@ -0,0 +1,370 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000 + 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000 0x1a000 0x1b000>; + qcom,sde-ctl-size = <0x1e8>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "cwb", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800 0x14c00>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x35000 0x36000 + 0x37000 0x38000>; + qcom,sde-intf-size = <0x2c0>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 + 0x6c000 0x6d000 0x6e000 0x6f000>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>; + qcom,sde-merge-3d-size = <0x10>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>; + qcom,sde-dsc-size = <0x10>; + qcom,sde-dsc-pair-mask = <2 1 4 3>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>; + qcom,sde-dsc-ctl-size = <0x10>; + qcom,sde-dsc-native422-supp = <0 0 1 1>; + qcom,sde-dsc-linewidth = <2048>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 + 0xe0 0xe0 0xe0>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-vdc-off = <0x7C000>; + qcom,sde-vdc-size = <0x10>; + qcom,sde-vdc-hw-rev = "vdc_1_2"; + qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-enc-size = <0x1C8>; + qcom,sde-vdc-ctl = <0xf00>; + qcom,sde-vdc-ctl-size = <0x10>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 4 8 12 + 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000 + 3900000 3900000 + 3900000 3900000 + 3900000 3900000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000 + 5200000 5200000 + 5200000 5200000 + 5200000 5200000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>, + <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-wb-linewidth-linear = <5120>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x3>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <11800000>; + qcom,sde-max-bw-high-kbps = <15500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>; + + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x4000821>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.5"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.5"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi new file mode 100644 index 000000000000..7059407c5de6 --- /dev/null +++ b/display/lahaina-sde-display-common.dtsi @@ -0,0 +1,718 @@ +#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" +#include "dsi-panel-sharp-qsync-wqhd-video.dtsi" +#include "dsi-panel-sharp-1080p-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include +#include "dsi-panel-sim-vdc-vid.dtsi" +#include "dsi-panel-sim-vdc-cmd.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <182000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + qcom,mdp = <&mdss_mdp>; + }; +}; + +/* PHY TIMINGS REVISION YC with reduced margins*/ +&dsi_sw43404_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; + }; +}; + +&dsi_sw43404_amoled_video { + qcom,mdss-dsi-qsync-min-refresh-rate = <55>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_1080_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 00 1a 0c]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-panel-clockrate = <900000000>; + }; + }; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03 + 03 02 02 04 00 0b 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* WQHD 60FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* FHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* WQHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04 + 04 03 02 04 00 0e 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* WQHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* WQHD 120FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 10 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* FHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + /* DPHY regular margins */ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06 + 06 07 02 04 00 17 16 ]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_video { + qcom,dsi-supported-dfps-list = <60 57 55>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <53>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + /* DPHY regular margins */ + qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07 + 07 07 02 04 00 18 16]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 + 06 04 02 04 00 12 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 + 06 04 02 04 00 12 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 + 06 04 02 04 00 12 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 0d 0c 08 + 08 05 02 04 00 17 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@4 { /* HD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 09 10 0e 0a + 0a 07 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vdc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vdc_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 00 04 04 08 07 05 + 05 03 02 04 00 0e 09]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 + 02 01 02 04 00 08 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 1080 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 11 10 1b 17 11 + 11 0c 02 04 00 30 15]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 + 04 02 02 04 00 0c 08]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 03 03 05 05 03 + 03 01 02 04 00 0a 08]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 05 09 08 05 + 05 03 02 04 00 10 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 + 07 07 04 02 00 14 0b]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 + 05 03 02 04 00 10 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08 + 08 05 02 04 00 16 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4k 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a + 0a 07 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01 + 01 01 02 04 00 05 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 + 02 01 02 04 00 08 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 + 04 02 02 04 00 0c 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02 + 01 00 02 04 00 06 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04 + 04 02 02 04 00 0c 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 + 05 03 02 04 00 0f 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 + 07 04 02 04 00 14 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01 + 01 00 02 04 00 04 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02 + 02 01 02 04 00 07 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03 + 03 01 02 04 00 08 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index b1408df87ce8..4e0465985d59 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -1,32 +1,4 @@ -#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" -#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" -#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" -#include "dsi-panel-sharp-dsc-4k-video.dtsi" -#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" -#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" -#include "dsi-panel-sharp-qsync-wqhd-video.dtsi" -#include "dsi-panel-sharp-1080p-cmd.dtsi" -#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" -#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" -#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" -#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-ext-bridge-1080p.dtsi" -#include "dsi-panel-sim-cmd.dtsi" -#include "dsi-panel-sim-video.dtsi" -#include "dsi-panel-sim-dsc375-cmd.dtsi" -#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" -#include "dsi-panel-sim-dualmipi-cmd.dtsi" -#include "dsi-panel-sim-dualmipi-video.dtsi" -#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" -#include "dsi-panel-sim-sec-hd-cmd.dtsi" -#include -#include "dsi-panel-sim-vdc-vid.dtsi" -#include "dsi-panel-sim-vdc-cmd.dtsi" +#include "lahaina-sde-display-common.dtsi" &tlmm { display_panel_avdd_default: display_panel_avdd_default { @@ -45,74 +17,6 @@ }; &soc { - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <60700>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <10000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - - qcom,panel-supply-entry@3 { - reg = <3>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <182000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "avdd"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - }; - }; - display_panel_avdd: display_gpio_regulator@1 { compatible = "regulator-fixed"; regulator-name = "display_panel_avdd"; @@ -128,89 +32,6 @@ pinctrl-0 = <&display_panel_avdd_default>; }; - sde_dsi: qcom,dsi-display-primary { - compatible = "qcom,dsi-display"; - label = "primary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1", - "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 82 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - avdd-supply = <&display_panel_avdd>; - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; - - qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; - }; - - sde_dsi1: qcom,dsi-display-secondary { - compatible = "qcom,dsi-display"; - label = "secondary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; - - qcom,platform-te-gpio = <&tlmm 83 0>; - qcom,panel-te-source = <1>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - avdd-supply = <&display_panel_avdd>; - - qcom,mdp = <&mdss_mdp>; - }; - sde_wb: qcom,wb-display@0 { compatible = "qcom,wb-display"; cell-index = <0>; @@ -218,30 +39,88 @@ }; }; +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + avdd-supply = <&display_panel_avdd>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + avdd-supply = <&display_panel_avdd>; +}; + &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; -/* PHY TIMINGS REVISION YC with reduced margins*/ &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + qcom,esd-check-enabled; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05 - 05 06 02 04 00 12 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 180 180 180 1440 180>; }; @@ -249,236 +128,86 @@ }; &dsi_sw43404_amoled_video { - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-qsync-min-refresh-rate = <55>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 - 05 06 02 04 00 12 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_r66451_amoled_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_r66451_amoled_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 - 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 - 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_r66451_amoled_cmd_cphy { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 - 19 03 02 04 00 00 00]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_r66451_amoled_video_cphy { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 - 19 03 02 04 00 00 00]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x77>; qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sharp_4k_dsc_video { - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x77>; qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06 - 06 07 02 04 00 15 0b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sharp_1080_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 - 08 08 02 04 00 1a 0c]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - qcom,mdss-dsi-panel-clockrate = <900000000>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sharp_qsync_wqhd_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,esd-check-enabled; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03 - 03 02 02 04 00 0b 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 8 8 8 1440 8>; }; - - timing@1 { /* WQHD 60FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@2 { /* FHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 - 02 01 02 04 00 09 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 8 8 8 1080 8>; }; - timing@3 { /* WQHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04 - 04 03 02 04 00 0e 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 8 8 8 1440 8>; }; - timing@4 { /* WQHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 8 8 8 1440 8>; }; - - timing@5 { /* WQHD 120FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@6 { /* FHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 10 03 - 03 02 02 04 00 0c 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 8 8 8 1080 8>; }; - timing@7 { /* FHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 - 02 02 02 04 00 0a 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 8 8 8 1080 8>; }; @@ -486,448 +215,88 @@ }; &dsi_sharp_qsync_wqhd_video { - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qhd_plus_dsc_cmd { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 - 06 06 02 04 00 13 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 - 07 07 02 04 00 17 0b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_dual_nt35597_truly_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - /* - * DPHY regular margins - */ - qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06 - 06 07 02 04 00 17 16 ]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_dual_nt35597_truly_video { - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-supported-dfps-list = <60 57 55>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-min-refresh-rate = <53>; - qcom,mdss-dsi-max-refresh-rate = <60>; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 - 07 08 02 04 00 18 0c]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_nt35695b_truly_fhd_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - /* - * DPHY regular margins - */ - qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07 - 07 07 02 04 00 18 16]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sim_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,poms-align-panel-vsync; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 - 06 04 02 04 00 12 0a]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; qcom,panel-roi-alignment = <720 40 720 40 720 40>; qcom,partial-update-enabled = "single_roi"; }; - - timing@1 { /* WQHD 60FPS vid mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 - 06 04 02 04 00 12 0a]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - }; - timing@2 { /* WQHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 - 06 04 02 04 00 12 0b]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; qcom,panel-roi-alignment = <720 40 720 40 720 40>; qcom,partial-update-enabled = "single_roi"; }; - timing@3 { /* FHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 0d 0c 08 - 08 05 02 04 00 17 0c]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; qcom,panel-roi-alignment = <540 40 540 40 540 40>; qcom,partial-update-enabled = "single_roi"; }; - timing@4 { /* HD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 24 0a 09 10 0e 0a - 0a 07 02 04 00 1d 0e]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; qcom,panel-roi-alignment = <360 40 360 40 360 40>; qcom,partial-update-enabled = "single_roi"; }; }; }; -&dsi_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <1 0 1>, - <2 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_vdc_cmd { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <2 1 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_vdc_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <2 1 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - &dsi_sim_dsc_375_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* 1080p */ - qcom,mdss-dsi-panel-phy-timings = [00 00 04 04 08 07 05 - 05 03 02 04 00 0e 09]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* qhd */ - qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 - 02 01 02 04 00 08 07]; - qcom,display-topology = <1 1 1>, - <2 2 1>, /* dsc merge */ - <2 1 1>; /* 3d mux */ - qcom,default-topology-index = <0>; - }; - }; }; &dsi_sim_dsc_10b_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* QHD 60fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 1080 60fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <1 1 1>, - <2 2 1>, /* dsc merge */ - <2 1 1>; /* 3d mux */ - qcom,default-topology-index = <0>; - }; - - timing@2 { /* QHD 90fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_dual_sim_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,mdss-dsi-display-timings { - timing@0 { /* 5K 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 3d 11 10 1b 17 11 - 11 0c 02 04 00 30 15]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* FHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 - 04 02 02 04 00 0c 08]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* WQHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 0a 03 03 05 05 03 - 03 01 02 04 00 0a 08]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4K 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 05 09 08 05 - 05 03 02 04 00 10 0a]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_dual_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 - 07 07 04 02 00 14 0b]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_dual_sim_dsc_375_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* 4k 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 4k 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 - 05 03 02 04 00 10 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* 4k 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08 - 08 05 02 04 00 16 0c]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4k 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a - 0a 07 02 04 00 1d 0e]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@4 { /* 1080 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01 - 01 01 02 04 00 05 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@5 { /* 1080 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 - 02 01 02 04 00 08 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@6 { /* 1080 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@7 { /* 1080 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 - 04 02 02 04 00 0c 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@8 { /* qhd 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02 - 01 00 02 04 00 06 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@9 { /* qhd 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@10 { /* qhd 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04 - 04 02 02 04 00 0c 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@11 { /* qhd 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 - 05 03 02 04 00 0f 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@12 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 - 07 04 02 04 00 14 0b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@13 { /* 720p 30 FPS */ - qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01 - 01 00 02 04 00 04 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@14 { /* 720p 60 FPS */ - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@15 { /* 720p 90 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02 - 02 01 02 04 00 07 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@16 { /* 720 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03 - 03 01 02 04 00 08 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@17 { /* 1080 144FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 - 06 06 02 04 00 13 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_sim_sec_hd_cmd { qcom,ulps-enabled; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 - 08 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; qcom,panel-roi-alignment = <720 40 720 40 720 40>; qcom,partial-update-enabled = "single_roi"; }; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index f57ce9ddca21..4aa15c2d2e45 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -1,3 +1,4 @@ +#include "lahaina-sde-common.dtsi" #include &soc { @@ -6,316 +7,6 @@ label = "disp_rdump_region"; }; - mdss_mdp: qcom,mdss_mdp@ae00000 { - compatible = "qcom,sde-kms"; - reg = <0x0ae00000 0x84000>, - <0x0aeb0000 0x2008>, - <0x0aeac000 0x800>, - <0x0af50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "swfuse_phys"; - - clocks = - <&clock_gcc GCC_DISP_AHB_CLK>, - <&clock_gcc GCC_DISP_HF_AXI_CLK>, - <&clock_gcc GCC_DISP_SF_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk", "rot_clk"; - clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>; - clock-max-rate = <0 0 0 0 460000000 19200000 460000000 - 460000000>; - - mmcx-supply = <&VDD_MMCX_LEVEL>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x16000 0x17000 0x18000 - 0x19000 0x1a000 0x1b000>; - qcom,sde-ctl-size = <0x1e8>; - qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none", "none"; - - qcom,sde-mixer-off = <0x45000 0x46000 0x47000 - 0x48000 0x49000 0x4a000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "primary", "none", - "none", "none", "none"; - - qcom,sde-mixer-cwb-pref = "none", "none", "cwb", - "cwb", "cwb", "cwb"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-dspp-rc-version = <0x00010000>; - qcom,sde-dspp-rc-off = <0x15800 0x14c00>; - qcom,sde-dspp-rc-size = <0x100>; - qcom,sde-dspp-rc-mem-size = <2720>; - - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-top-size = <0x1c>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-dest-scaler-size = <0x800>; - - qcom,sde-wb-off = <0x66000>; - qcom,sde-wb-size = <0x2c8>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-intf-off = <0x35000 0x36000 - 0x37000 0x38000>; - qcom,sde-intf-size = <0x2c0>; - qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; - qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; - - qcom,sde-pp-off = <0x6a000 0x6b000 - 0x6c000 0x6d000 0x6e000 0x6f000>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; - qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; - - qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>; - qcom,sde-merge-3d-size = <0x10>; - - qcom,sde-cdm-off = <0x7a200>; - qcom,sde-cdm-size = <0x224>; - - qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>; - qcom,sde-dsc-size = <0x10>; - qcom,sde-dsc-pair-mask = <2 1 4 3>; - qcom,sde-dsc-hw-rev = "dsc_1_2"; - qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>; - qcom,sde-dsc-enc-size = <0x100>; - qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>; - qcom,sde-dsc-ctl-size = <0x10>; - qcom,sde-dsc-native422-supp = <0 0 1 1>; - qcom,sde-dsc-linewidth = <2048>; - - qcom,sde-dither-off = <0xe0 0xe0 0xe0 - 0xe0 0xe0 0xe0>; - qcom,sde-dither-version = <0x00020000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-vdc-off = <0x7C000>; - qcom,sde-vdc-size = <0x10>; - qcom,sde-vdc-hw-rev = "vdc_1_2"; - qcom,sde-vdc-enc = <0x200>; - qcom,sde-vdc-enc-size = <0x1C8>; - qcom,sde-vdc-ctl = <0xf00>; - qcom,sde-vdc-ctl-size = <0x10>; - - qcom,sde-sspp-type = "vig", "vig", "vig", "vig", - "dma", "dma", "dma", "dma"; - - qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 - 0x25000 0x27000 0x29000 0x2b000>; - qcom,sde-sspp-src-size = <0x1f8>; - - qcom,sde-sspp-xin-id = <0 4 8 12 - 1 5 9 13>; - qcom,sde-sspp-excl-rect = <1 1 1 1 - 1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0 0xf8 0x110>; - - qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000 - 3900000 3900000 - 3900000 3900000 - 3900000 3900000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000 - 5200000 5200000 - 5200000 5200000 - 5200000 5200000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = - <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, - <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; - qcom,sde-sspp-clk-status = - <0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>, - <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <4096>; - qcom,sde-wb-linewidth = <4096>; - qcom,sde-wb-linewidth-linear = <5120>; - qcom,sde-mixer-blendstages = <0xb>; - qcom,sde-highest-bank-bit = <0x3>; - qcom,sde-ubwc-version = <0x400>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1>; - qcom,sde-macrotile-mode = <0x1>; - qcom,sde-smart-panel-align-mode = <0xc>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; - qcom,sde-has-idle-pc; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <11800000>; - qcom,sde-max-bw-high-kbps = <15500000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <800000>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-ltm-version = <0x00010001>; - /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x15300 0x14300>; - - qcom,sde-dspp-spr-off = <0x15400 0x14400>; - qcom,sde-dspp-spr-size = <0x200>; - qcom,sde-dspp-spr-version = <0x00010000>; - - qcom,sde-dspp-demura-off = <0x15600 0x14800>; - qcom,sde-dspp-demura-size = <0x200>; - qcom,sde-dspp-demura-version = <0x00010000>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x1040>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>; - - qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff - 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - - qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; - - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; - qcom,sde-qos-refresh-rates = <60 120>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - - qcom,sde-reg-dma-off = <0 0x400>; - qcom,sde-reg-dma-id = <0 1>; - qcom,sde-reg-dma-version = <0x00020000>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-secure-sid-mask = <0x4000821>; - - /* data and reg bus scale settings */ - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 74000>, - <0 148000>, - <0 265000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060001>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x1260 0x00040000>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040003>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "mmcx"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - - }; - ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; @@ -483,184 +174,6 @@ "qcom,sde-ebi-bus"; }; - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.5"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <800>; - reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.5"; - label = "dsi-ctrl-1"; - cell-index = <1>; - frame-threshold-time-us = <800>; - reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <5 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L5B>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - memory-region = <&dfps_data_memory>; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-1"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96400 0x800>, - <0xae96900 0x27c>, - <0xaf03000 0x8>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L5B>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - smmu_sde_unsec: qcom,smmu_sde_unsec_cb { compatible = "qcom,smmu_sde_unsec"; iommus = <&apps_smmu 0x820 0x402>; @@ -677,5 +190,143 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; +}; + +&mdss_mdp { + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + + mmcx-supply = <&VDD_MMCX_LEVEL>; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010001>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L5B>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L5B>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; From 11bd8cf2207e8b139d5dec74c781924dda8cb3e7 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Tue, 7 Jul 2020 12:44:07 +0800 Subject: [PATCH 126/362] ARM: dts: msm: fix the ESD check error for r66451 panel 60hz could not display and took ESD check failed on some qrd devices. Changed the panel init sequence, doing 60hz and 90hz fps switch after ddic power on(29 command). Change-Id: I00316ab9dbecf7394cba309c33d10bec96e170d1 --- display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index 9f31efd5478f..64b941df0e09 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -115,12 +115,12 @@ 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 ]; qcom,mdss-dsi-off-command = [ @@ -216,12 +216,12 @@ 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 ]; qcom,mdss-dsi-off-command = [ @@ -318,7 +318,7 @@ 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 + 05 01 00 00 14 00 01 29 ]; qcom,mdss-dsi-off-command = [ From 03761dcef2bb76fb2d73c3d265e919b833ddc083 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Wed, 27 May 2020 11:13:37 -0700 Subject: [PATCH 127/362] ARM: dts: msm: batch timing switch commands together for qsync panel Batch the timing switch commands, to be triggered all at once for Sharp qsync command mode panel for lahaina target. Change-Id: Ife397d3e73c2872b77ee5a44e843846747292c26 --- display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi | 168 ++++++++++---------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi index 215b3ab46dde..d553b8711a6c 100644 --- a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi +++ b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi @@ -53,21 +53,21 @@ qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 83 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 0a + 39 00 00 00 00 00 02 17 30 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 01 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -274,21 +274,21 @@ qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 85 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 0a + 39 00 00 00 00 00 02 17 30 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 01 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -383,21 +383,21 @@ qcom,mdss-dsi-panel-framerate = <90>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 83 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 03 - 39 01 00 00 00 00 02 17 70 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 02 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 03 + 39 00 00 00 00 00 02 17 70 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 02 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -491,21 +491,21 @@ qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 83 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 00 - 39 01 00 00 00 00 02 17 10 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 03 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 00 + 39 00 00 00 00 00 02 17 10 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 03 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -712,21 +712,21 @@ qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 85 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 00 - 39 01 00 00 00 00 02 17 10 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 00 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 00 + 39 00 00 00 00 00 02 17 10 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 00 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -821,21 +821,21 @@ qcom,mdss-dsi-panel-framerate = <90>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 85 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 03 - 39 01 00 00 00 00 02 17 70 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 02 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 03 + 39 00 00 00 00 00 02 17 70 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 02 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; From 7a28499cbe8486a70c98b32366d5642ec77662f1 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Tue, 30 Jun 2020 17:18:22 +0800 Subject: [PATCH 128/362] ARM: dts: msm: Complement hdr capabilities to r66451 panel Complement hdr capabilities to the panel dtsi for both cmd and vid mode so that DPU can support the tone mapping for HDR video playback use-cases. Change-Id: I711311027d47be71f9625289d7f8b8f8c60c14f2 --- display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi | 2 ++ display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index 9f31efd5478f..e407253e7f16 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -38,6 +38,8 @@ qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-framerate = <60>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 2201ce22808e..c67a33b57cc8 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -22,6 +22,11 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-width = <1080>; From c281587f39a588a9bdc2e6f48e29bc9bb81799be Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 10 Jul 2020 11:29:02 +0530 Subject: [PATCH 129/362] bindings: Documentation: modify documentation for hbb This changes modifies the documentation for highest bank bit used for UBWC configuration. Change-Id: I4a35bf2330402b3d6680aa74344ea088cd6b2866 --- bindings/sde.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 93e968a01ab9..367633a93d3a 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -134,8 +134,10 @@ Optional properties: - qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. It supports "csc" and "csc-10bit" entries for csc type. -- qcom,sde-highest-bank-bit: A u32 property to indicate GPU/Camera/Video highest memory - bank bit used for tile format buffers. +- qcom,sde-highest-bank-bit: Property to specify GPU/Camera/Video highest memory + bank bit used for tile format buffers. First value + in the array represents the ddr type and the second + value is the hbb value corresponding to the ddr type. - qcom,sde-ubwc-version: Property to specify the UBWC feature version. - qcom,sde-ubwc-static: Property to specify the default UBWC static configuration value. @@ -674,7 +676,7 @@ Example: qcom,sde-sspp-linewidth = <2560>; qcom,sde-mixer-blendstages = <0x7>; qcom,sde-dsc-linewidth = <2048>; - qcom,sde-highest-bank-bit = <0x2>; + qcom,sde-highest-bank-bit = <0x7 0x2>; qcom,sde-ubwc-version = <0x100>; qcom,sde-ubwc-static = <0x100>; qcom,sde-ubwc-swizzle = <0>; From f61e031323e0eddda1b6477c121ced630be61964 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Mon, 13 Jul 2020 18:24:24 +0530 Subject: [PATCH 130/362] ARM: dts: msm: add ddr type and hbb for lahaina target Add supported ddr types and corresponding hbb values for lahaina target. Change-Id: Ib4dd7781ce9ac8f0a1e66ae2d7528d897e348cc3 --- display/lahaina-sde-common.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 8dd8954df0c3..56b7f71adbee 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -148,7 +148,8 @@ qcom,sde-wb-linewidth = <4096>; qcom,sde-wb-linewidth-linear = <5120>; qcom,sde-mixer-blendstages = <0xb>; - qcom,sde-highest-bank-bit = <0x3>; + qcom,sde-highest-bank-bit = <0x8 0x3>, + <0x7 0x2>; qcom,sde-ubwc-version = <0x400>; qcom,sde-ubwc-swizzle = <0x6>; qcom,sde-ubwc-bw-calc-version = <0x1>; From d895e79e35430d3c284e4d90dc06965345f3dd6b Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 14:52:00 -0700 Subject: [PATCH 131/362] ARM: dts: msm: move dsi ctrl power nodes to common dt for Lahaina Move DSI ctrl power handles nodes from lahaina HLOS dt to common dt file as they are needed by all the vm's. Change-Id: Id59f51e1e9e821bb5b02dd26ec41aff71950c306 --- display/lahaina-sde-common.dtsi | 54 ++++++++++++++++++++++++++++++++ display/lahaina-sde.dtsi | 55 --------------------------------- 2 files changed, 54 insertions(+), 55 deletions(-) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 8dd8954df0c3..bd93fb5130b3 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -280,6 +280,33 @@ reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { @@ -292,6 +319,33 @@ reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 4aa15c2d2e45..870528fae30e 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -247,33 +247,6 @@ <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi1 { @@ -287,34 +260,6 @@ <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi_phy0 { From b765705d9b0a348dd4a89b04ef75add12420be1a Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Sat, 20 Jun 2020 00:15:04 -0700 Subject: [PATCH 132/362] ARM: dts: msm: add trusted vm dtsi files for Lahaina target Add trusted VM device tree files for Lahaina. These files inherit common Lahaina target bindings and overrides with needed bindings with VM specific values. Change-Id: Icb3090d1dfa6afe7eb993064e4493140708b658e --- display/trustedvm-lahaina-sde-display.dtsi | 33 +++++++++++ display/trustedvm-lahaina-sde.dtsi | 68 ++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 display/trustedvm-lahaina-sde-display.dtsi create mode 100644 display/trustedvm-lahaina-sde.dtsi diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi new file mode 100644 index 000000000000..036205f97d18 --- /dev/null +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -0,0 +1,33 @@ +#include "lahaina-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_MUX_1_CLK>, + <&clock_cpucc PCLK_MUX_1_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_1_CLK>, + <&clock_cpucc BYTECLK_SRC_1_CLK>, + <&clock_cpucc PCLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + qcom,panel-te-source = <0>; +}; + +&mdss_mdp { + connectors = <&sde_dsi>; +}; diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi new file mode 100644 index 000000000000..005a82796a64 --- /dev/null +++ b/display/trustedvm-lahaina-sde.dtsi @@ -0,0 +1,68 @@ +#include "lahaina-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>, + <0x0ae8f000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-hw-version =<0x70000000>; + + clocks = + <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_cpucc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From 5f6afd05b66ce7beb6356c3626807a0126ffb8d8 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 14:59:41 -0700 Subject: [PATCH 133/362] bindings: Documentation: add property to indicate trusted VM execution Add a property in SDE device to indicate the executing environment is the trusted VM. Change-Id: Id4650d60f582b2058b166e69c2b0c66cdfce36e0 --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 93e968a01ab9..6bad2544b4c9 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -517,6 +517,8 @@ Optional properties: ordering block 0: lower priority pipe has to be on the left for a given pair of pipes. 1: priority have to be explicitly configured for a given pair of pipes. +- qcom,sde-trusted-vm-env: Boolean property to indicate if the device + driver is executing in a trusted VM Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -728,6 +730,7 @@ Example: qcom,sde-te2-off = <0x100>; qcom,sde-te-size = <0xffff>; qcom,sde-te2-size = <0xffff>; + qcom,sde-trusted-vm-env; qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; From 1e8e95a8c684ba12f2579d1288e5989bbb9dfa71 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Mon, 1 Jun 2020 17:17:02 -0700 Subject: [PATCH 134/362] ARM: dts: msm: add property for trusted VM execution for Lahaina Add a property in the display device to indicate the executing environment being a trusted VM for Lahaina target. Change-Id: Iaeeba1b83b8167accfdcb6bbe4f3fd930b891e52 --- display/trustedvm-lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi index 005a82796a64..8ee259e82f95 100644 --- a/display/trustedvm-lahaina-sde.dtsi +++ b/display/trustedvm-lahaina-sde.dtsi @@ -35,6 +35,7 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; + qcom,sde-trusted-vm-env; }; &mdss_dsi0 { From b979bfcf70827c0d77cbec6c3454c130cdaf21fd Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:07:29 -0700 Subject: [PATCH 135/362] bindings: Documentation: add property to specify max trusted vm displays Add documentation for the property to specify the maximum number of concurrent displays supported in the trusted vm environment. Change-Id: I84c0408686e816a6498931949b7391209c9f9640 --- bindings/sde.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 6bad2544b4c9..635cefcd2ad7 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -519,6 +519,9 @@ Optional properties: 1: priority have to be explicitly configured for a given pair of pipes. - qcom,sde-trusted-vm-env: Boolean property to indicate if the device driver is executing in a trusted VM +- qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum + number of concurrent displays supported in the + trusted vm environment Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -711,6 +714,7 @@ Example: qcom,sde-has-idle-pc; qcom,fullsize-va-map; qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-max-dest-scaler-input-linewidth = <2048>; qcom,sde-max-dest-scaler-output-linewidth = <2560>; qcom,sde-sspp-max-rects = <1 1 1 1 From 5e9e5360be53220678a0dc7f61cc38583c41e89a Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:05:35 -0700 Subject: [PATCH 136/362] ARM: dts: msm: specify max trusted vm displays for Lahaina Specify maximum number of concurrent displays supported in trusted vm. This value will be used by both the vm's to validate the TUI start request. For Lahaina, we support one display in trusted vm. Change-Id: I643bacea09f1eead26c0165bf00590afeda67569 --- display/lahaina-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index bd93fb5130b3..fc2d7fa27bf7 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -161,6 +161,7 @@ qcom,sde-pipe-order-version = <0x1>; qcom,sde-has-dim-layer; qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-max-dest-scaler-input-linewidth = <2048>; qcom,sde-max-dest-scaler-output-linewidth = <2560>; From fea122aaca93225b4a371edcb02f4a222cadf8f3 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:12:50 -0700 Subject: [PATCH 137/362] bindings: Documentation: add a property to exclude reg-names In trusted vm, register ranges that need to be mapped need to exactly be the same as that of HLOS vm. But the DT provided register ranges are used to validate the IO memory assign from HLOS vm. So this change introduces a separate property to specify the register names which need to be excluded from the IO memory validation list but still need to be mapped to the vm. Change-Id: I8c5c194254ae260f7a8878bb5492f5a039203fc9 --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 635cefcd2ad7..d6cf76c02dd7 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -522,6 +522,9 @@ Optional properties: - qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum number of concurrent displays supported in the trusted vm environment +- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which + should be excluded from IO memory validation list + in trusted vm environment Bus Scaling: - interconnects An array of 4 cell properties with the format of From dda146f52c9d7f779735a9480ff1a4574c5e9e3a Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Mon, 13 Jul 2020 14:56:12 -0700 Subject: [PATCH 138/362] ARM: dts: msm: populate the property to exclude reg-names for validation Populate the property to exclude reg-names in trusted vm for Lahaina target while validating the IO memory assign from primary vm. Change-Id: I9dc92be7d11862f9af3c083939e82fa8a705b9e3 --- display/trustedvm-lahaina-sde.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi index 8ee259e82f95..dfebcb3a869f 100644 --- a/display/trustedvm-lahaina-sde.dtsi +++ b/display/trustedvm-lahaina-sde.dtsi @@ -21,6 +21,8 @@ "regdma_phys", "sid_phys"; + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version =<0x70000000>; clocks = From f773f85330ac8dedf5eb99c8f7ae90d40360348a Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 15 Jul 2020 13:53:45 +0800 Subject: [PATCH 139/362] ARM: dts: msm: Enable PWM backlight for sharp qhd plus panel Set the backlight control mode to PWM for this panel. Change-Id: I1ac9a35d775f38510aa9Montana59aca940dc76ea40c --- display/lahaina-sde-display-cdp.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 2061e5db40b0..c393be6f19ee 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -111,7 +111,9 @@ &dsi_sharp_qhd_plus_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-te-gpio = <&tlmm 82 0>; @@ -215,5 +217,7 @@ &sde_dsi { + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-2 = <&lcd_backlight_ctrl_default>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; From 53407142407b6254675aaf2992040e1f5f748b82 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Mon, 13 Jul 2020 19:09:43 +0530 Subject: [PATCH 140/362] ARM: dts: msm: add display dt node for shima target Add display related dt nodes for shima target. Change-Id: I4726c57f338667183d50fe937c57767334fe1f21 --- display/shima-sde-display-idp.dtsi | 32 ++ display/shima-sde-display.dtsi | 204 ++++++++++++ display/shima-sde.dtsi | 491 +++++++++++++++++++++++++++++ 3 files changed, 727 insertions(+) create mode 100644 display/shima-sde-display-idp.dtsi create mode 100644 display/shima-sde-display.dtsi create mode 100644 display/shima-sde.dtsi diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi new file mode 100644 index 000000000000..7fd9d2bc172f --- /dev/null +++ b/display/shima-sde-display-idp.dtsi @@ -0,0 +1,32 @@ +#include "shima-sde-display.dtsi" + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; +}; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi new file mode 100644 index 000000000000..03e5cc9147a1 --- /dev/null +++ b/display/shima-sde-display.dtsi @@ -0,0 +1,204 @@ +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + + qcom,mdp = <&mdss_mdp>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi + &sde_dsi1>; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi new file mode 100644 index 000000000000..3a2e89c22c39 --- /dev/null +++ b/display/shima-sde.dtsi @@ -0,0 +1,491 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 460000000 19200000 460000000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none"; + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + + qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x84000 0x84100>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + qcom,sde-sspp-xin-id = <0 4 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, + <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2880>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x7 0x1>, + <0x8 0x2>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-has-idle-pc; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <5900000>; + qcom,sde-max-bw-high-kbps = <13500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + /* creq LUTs */ + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-id = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801 0xC01>; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + sde_rscc: qcom,sde_rscc { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + status = "disabled"; + reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <4>; + + qcom,sde-dram-channels = <2>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + qcom,msm-bus,active-only; + interconnects = + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mmss_noc MASTER_MDP1_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-ebi-bus"; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent-hint-cached; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>, + <&apps_smmu 0xC01 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; From b3ef957d19fe2f96daf66c978ebd74469985f3e4 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Fri, 19 Jun 2020 15:36:55 -0700 Subject: [PATCH 141/362] ARM: dts: msm: add VRAM size to lahaina trusted vm Add the size of VRAM available in trusted vm. Change-Id: Ibe5cbc78b679fdce7293a6ae4ebd9b0947582023 --- bindings/sde.txt | 3 +++ display/trustedvm-lahaina-sde.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 3628b8a4ec55..69430faef8d1 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -527,6 +527,7 @@ Optional properties: - qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which should be excluded from IO memory validation list in trusted vm environment +- qcom,vram-size: A u32 value indicating the size of the VRAM in bytes Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -806,6 +807,8 @@ Example: qcom,sde-amortizable-threshold = <11>; qcom,sde-secure-sid-mask = <0x200801 0x200c01>; + qcom,vram-size = <0x200000>; + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi index dfebcb3a869f..1a363cd7cb2f 100644 --- a/display/trustedvm-lahaina-sde.dtsi +++ b/display/trustedvm-lahaina-sde.dtsi @@ -38,6 +38,7 @@ "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; qcom,sde-trusted-vm-env; + qcom,vram-size = <0x200000>; }; &mdss_dsi0 { From da1af832e2f76a06cba04816da07f28890ca1024 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Wed, 24 Jun 2020 17:57:17 +0530 Subject: [PATCH 142/362] ARM: dts: msm: add display DT node for Holi target Add all display related DT nodes for the Holi target. Change-Id: I30de0a892a8da34c7aa854e686a3dc1879d05a40 --- display/holi-sde-display-cdp.dtsi | 21 ++ display/holi-sde-display-mtp.dtsi | 21 ++ display/holi-sde-display.dtsi | 133 +++++++++++ display/holi-sde.dtsi | 376 ++++++++++++++++++++++++++++++ 4 files changed, 551 insertions(+) create mode 100644 display/holi-sde-display-cdp.dtsi create mode 100644 display/holi-sde-display-mtp.dtsi create mode 100644 display/holi-sde-display.dtsi create mode 100644 display/holi-sde.dtsi diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi new file mode 100644 index 000000000000..9fe8f90c81f4 --- /dev/null +++ b/display/holi-sde-display-cdp.dtsi @@ -0,0 +1,21 @@ +#include "holi-sde-display.dtsi" + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi new file mode 100644 index 000000000000..9fe8f90c81f4 --- /dev/null +++ b/display/holi-sde-display-mtp.dtsi @@ -0,0 +1,21 @@ +#include "holi-sde-display.dtsi" + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi new file mode 100644 index 000000000000..22d402536458 --- /dev/null +++ b/display/holi-sde-display.dtsi @@ -0,0 +1,133 @@ +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include + +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_te_active &disp_pins_default>; + pinctrl-1 = <&sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L1E>; + vdd-supply = <&L8A>; + + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dsi>; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi new file mode 100644 index 000000000000..a19a85b4781f --- /dev/null +++ b/display/holi-sde.dtsi @@ -0,0 +1,376 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@5e00000 { + compatible = "qcom,sde-kms"; + reg = <0x05e00000 0x8f030>, + <0x05eb0000 0x2008>, + <0x05e8f000 0x030>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + "div_clk", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; + clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 + 560000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2c0>; + qcom,sde-intf-type = "none", "dsi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800>; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dsc-off = <0x81000>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + qcom,sde-mixer-stage-base-layer; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; + qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-sspp-linewidth = <2160>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-highest-bank-bit = <0x0 0x1>; + qcom,sde-ubwc-version = <0x200>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1e>; + qcom,sde-macrotile-mode = <0x0>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + qcom,sde-max-bw-low-kbps = <5200000>; + qcom,sde-max-bw-high-kbps = <6200000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <1>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + qcom,sde-qos-refresh-rates = <60 120>; + qcom,sde-danger-lut = <0xffff 0xffff 0x0 + 0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0 + 0x0 0x3ffff 0x3ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + + qcom,sde-secure-sid-mask = <0x821>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <32>; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_rotator: qcom,mdss_rotator { + status = "disabled"; + compatible = "qcom,sde_rotator"; + reg = <0x5e00000 0xac000>, + <0x5eb0000 0x2008>; + + reg-names = "mdp_phys", + "rot_vbif_phys"; + + #list-cells = <1>; + qcom,mdss-rot-mode = <1>; + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>; + + /*Offline rotator RT setting */ + qcom,mdss-rot-parent = <&mdss_mdp 0>; + qcom,mdss-rot-xin-id = <10 11>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x83C 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0x83D 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <1000>; + reg = <0x05e94000 0x400>, + <0x05f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L22A>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 { + compatible = "qcom,dsi-phy-v3.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x05e94400 0x800>, + <0x05e94a00 0x1e0>, + <0x05f01004 0x8>, + <0x05e94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_10nm"; + vdda-0p9-supply = <&S5A_LEVEL>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 80]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + +}; From f06897afe61aab112ecfc966aeb4cf8b234110be Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 22 Jul 2020 14:40:26 +0530 Subject: [PATCH 143/362] ARM: dts: msm: add display node for Holi ATP platform This change adds display node for ATP platform of Holi. Change-Id: Ia52de9a1d24f40058636baf3139aa511f2a94c86 --- display/holi-sde-display-atp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 display/holi-sde-display-atp.dtsi diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi new file mode 100644 index 000000000000..9fe8f90c81f4 --- /dev/null +++ b/display/holi-sde-display-atp.dtsi @@ -0,0 +1,21 @@ +#include "holi-sde-display.dtsi" + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; From b3d611e8644f5e9a801b2738e78dccca8f78aa80 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 11 Jun 2020 15:41:18 +0800 Subject: [PATCH 144/362] ARM: dts: msm: change r66451 video mode fps to 120hz for lahaina Set r66451 panel video mode default fps to 120hz, and enable DFPS. Change-Id: I52409209a379945ff70355cf93e8c1259324327b --- .../dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 33 ++++++++++++++++--- display/lahaina-sde-display-common.dtsi | 9 +++-- 2 files changed, 35 insertions(+), 7 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index c67a33b57cc8..182038f97fab 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -38,18 +38,41 @@ qcom,mdss-dsi-v-back-porch = <4>; qcom,mdss-dsi-v-front-porch = <25>; qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 01 - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 7059407c5de6..f9efbd122ba9 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -156,10 +156,15 @@ &dsi_r66451_amoled_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <60>; + qcom,mdss-dsi-max-refresh-rate = <120>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From ebfca202cfc96740dfd00caede5c0b866c0f5d5d Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 16 Jul 2020 06:19:06 -0700 Subject: [PATCH 145/362] ARM: dts: msm: add display device tree files for lahaina MTP v2.1 Add display device-tree support for Lahaina's MTP v2.1 platform. Change-Id: Ibc90d2e8109e38a120b61d8df800cf41fab3f00e --- display/lahaina-sde-display-mtp-v2.1.dtsi | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 display/lahaina-sde-display-mtp-v2.1.dtsi diff --git a/display/lahaina-sde-display-mtp-v2.1.dtsi b/display/lahaina-sde-display-mtp-v2.1.dtsi new file mode 100644 index 000000000000..e4b362c150f1 --- /dev/null +++ b/display/lahaina-sde-display-mtp-v2.1.dtsi @@ -0,0 +1,3 @@ +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From 2519d8af0ec3da2bf560f0e8dc6663e78f4eacd5 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 23 Jul 2020 22:19:29 -0700 Subject: [PATCH 146/362] ARM: dts: msm: add cmd to vid switch commands for qsync panel Add DCS commands that would be sent during a panel operating mode switch from command mode to video mode. The switch command sets the full frame width and height as the horizontal address and vertical address for the DDIC on switching to video mode. If this is not done and the switch occurs during a partial frame update corruption can be observed post switch. Change-Id: I0b12eb24e4fdac5b0e4bbf42493d8bc0081cc361 --- display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi index 215b3ab46dde..7d766b6bebc6 100644 --- a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi +++ b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi @@ -139,6 +139,10 @@ 05 01 00 00 32 00 01 10 ]; qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,cmd-to-video-mode-switch-commands = [ + 39 01 00 00 00 00 05 2a 00 00 02 cf + 39 01 00 00 00 00 05 2b 00 00 09 ff + ]; qcom,cmd-to-video-mode-post-switch-commands = [ 39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 @@ -569,6 +573,10 @@ 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29 ]; + qcom,cmd-to-video-mode-switch-commands = [ + 39 01 00 00 00 00 05 2a 00 00 02 cf + 39 01 00 00 00 00 05 2b 00 00 09 ff + ]; qcom,cmd-to-video-mode-post-switch-commands = [ 39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 From c9edbd85c975c3ddbbeb2fcbcd4ae7908c2942d3 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Fri, 24 Jul 2020 11:25:57 -0700 Subject: [PATCH 147/362] ARM: dts: msm: add 144FPS for WQHD resolution on sim panel Change adds 144FPS refresh rate timing node with WQHD resolution for simulation panel. Change-Id: I9dc7c7d0d255a12948082955632f6cf65d7178bf --- .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 52 +++++++++++++++++++ display/lahaina-sde-display-common.dtsi | 7 +++ 2 files changed, 59 insertions(+) diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index 0d48d49b21ca..6b5a5b7f04f9 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -1485,6 +1485,58 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@18 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index f9efbd122ba9..79bd533246cb 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -707,6 +707,13 @@ qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; + + timing@18 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a + 0a 07 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; }; }; From 6fbdc3fa35912af5d808873b98a0e1ac9f341dac Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Thu, 9 Jul 2020 13:47:16 +0530 Subject: [PATCH 148/362] ARM: dts: msm: add dp dt node for shima target Add the DP DT node for Shima target. DP SST POR resolution of 4K@60 can be supported without DSC and widebus support. So, the support for DSC, FEC and widebus is not required. Change-Id: Ife3e4806fd116fce3eb1709fd8c73f03446b074c --- display/shima-sde.dtsi | 142 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 3a2e89c22c39..0b991af1c804 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -269,6 +269,148 @@ }; }; + ext_disp: qcom,msm-ext-disp { + status = "disabled"; + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + status = "disabled"; + compatible = "qcom,msm-hdcp"; + }; + + sde_dp: qcom,dp_display@ae90000 { + status = "disabled"; + cell-index = <0>; + compatible = "qcom,dp-display"; + + /* usb-phy = <&usb_qmp_dp_phy>; */ + /* qcom,dp-aux-switch = <&fsa4480>; */ + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02004 0x1a0>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>, + <0xaf03000 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", + "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,pll-revision = "5nm-v1"; + qcom,phy-version = <0x420>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,mst-enable; + + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + sde_rscc: qcom,sde_rscc { cell-index = <0>; compatible = "qcom,sde-rsc"; From 3f20e86250f242117bb6c73f431509b7ea1ab5dd Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 28 Jul 2020 20:35:00 -0700 Subject: [PATCH 149/362] dt-bindings: update dma scheduling bindings for DSI panels Change updates qcom,mdss-dsi-dma-schedule-line and qcom,mdss-dsi-dma-schedule-window bindings which are used to specify parameters for scheduling DSI commands. Change-Id: Ic0c567475639e5db96fc314e9a717666a2b44b56 --- bindings/mdss-dsi-panel.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 9fee318fbeb2..47db5592f747 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -576,7 +576,10 @@ Optional properties: value 0. - qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. - qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active - region, at which command DMA needs to be triggered. + region for video mode panels and line number after TE for command mode + panels, at which command DMA needs to be triggered. +- qcom,mdss-dsi-dma-schedule-window: An integer value indicates the width of the DMA window during which a + DCS command will be triggered for command mode panels Required properties for sub-nodes: None Optional properties: @@ -851,5 +854,6 @@ Example: qcom,src-color-space = <0>; qcom,src-chroma-format = <0>; qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,mdss-dsi-dma-schedule-window = <50>; }; }; From 34e5e7dbf38d87875c35f3aea15c5d3a473211cd Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Fri, 31 Jul 2020 18:37:07 +0530 Subject: [PATCH 150/362] ARM: dts: msm: update dp dt properties for shima Update the DP DT node properties for Shima target. Change-Id: I7eaea8148756d39f67491a418432173fa2f8b758 --- display/shima-sde.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 0b991af1c804..8705b8ab8a46 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -288,8 +288,8 @@ cell-index = <0>; compatible = "qcom,dp-display"; - /* usb-phy = <&usb_qmp_dp_phy>; */ - /* qcom,dp-aux-switch = <&fsa4480>; */ + usb-phy = <&usb_qmp_dp_phy>; + qcom,dp-aux-switch = <&fsa4480>; qcom,ext-disp = <&ext_disp>; qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; @@ -316,16 +316,16 @@ interrupts = <12 0>; #clock-cells = <1>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", From c90c7405f7530f38a56b9cdbe8fca0f6d295af6d Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 16 Jul 2020 06:19:06 -0700 Subject: [PATCH 151/362] ARM: dts: msm: add display device tree files for lahaina MTP v2.1 Add display device-tree support for Lahaina's MTP v2.1 platform Change-Id: Ibc90d2e8109e38a120b61d8df800cf41fab3f00e --- display/lahaina-sde-display-mtp-v2.1.dtsi | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 display/lahaina-sde-display-mtp-v2.1.dtsi diff --git a/display/lahaina-sde-display-mtp-v2.1.dtsi b/display/lahaina-sde-display-mtp-v2.1.dtsi new file mode 100644 index 000000000000..e4b362c150f1 --- /dev/null +++ b/display/lahaina-sde-display-mtp-v2.1.dtsi @@ -0,0 +1,3 @@ +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From 94bad0bdcf5a89b76aa00f5c7bbafde76554bbb3 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 26 May 2020 10:03:36 -0700 Subject: [PATCH 152/362] ARM: dts: msm: update transfer time for sharp qhd panel for lahaina This change updates transfer time fpr Sharp QHD plus panel for 120 FPS timing node to 7933us. Change-Id: I02b65370acf76c4905ad3e4c81cc25185667bf09 --- display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi index 90fb731fbb88..3263d8ff8c74 100644 --- a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi +++ b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi @@ -38,6 +38,7 @@ qcom,mdss-dsi-v-front-porch = <39>; qcom,mdss-dsi-v-pulse-width = <2>; qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-mdp-transfer-time-us = <7933>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 From e760c954d77a2abfaff9ccfb937525f472c2fd02 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 31 Jul 2020 15:12:53 +0800 Subject: [PATCH 153/362] ARM: dts: msm: add display panel support for qrd holi Add qrd holi display initial changes. Change-Id: I4f55787ef5c37937004e749eb96561ebce8c5d96 --- display/holi-sde-display-qrd.dtsi | 31 +++++++++++++++++ display/holi-sde-display.dtsi | 57 +++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 display/holi-sde-display-qrd.dtsi diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi new file mode 100644 index 000000000000..de64faa435fc --- /dev/null +++ b/display/holi-sde-display-qrd.dtsi @@ -0,0 +1,31 @@ +#include "holi-sde-display.dtsi" + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 22d402536458..f68e8e82ab7a 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,5 +1,7 @@ #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include &pm6150l_gpios { @@ -131,3 +133,58 @@ }; }; +&dsi_r66451_amoled_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0B>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + From 85279187d140c9442ba3190fd555eed0f09929b6 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Mon, 6 Apr 2020 10:27:37 -0700 Subject: [PATCH 154/362] ARM: dts: msm: add poms pm_qos cpu mask for silver cores on Lahaina target This change adds pm_qos cpu mask for all silver/performance cores. Change-Id: I628d0731b04b20049bb87ebf75d90197001c4263 --- display/lahaina-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 3bc51fc6b856..738a141a3dc2 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -214,6 +214,7 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From b873dc226c8329c37714f69c10d7dac693d990c7 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 6 Aug 2020 18:23:40 +0530 Subject: [PATCH 155/362] ARM: dts: msm: add r66451 video mode 60hz panel support This change adds visionox r66451 amoled video mode 60Hz dsi panel for Shima target. Change-Id: Iaf673170b6930ea8c58b31474630473108f7bb67 --- ...-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 87 +++++++++++++++++++ display/shima-sde-display-idp.dtsi | 12 ++- display/shima-sde-display.dtsi | 13 +++ 3 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi new file mode 100644 index 000000000000..50e11b87af55 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi @@ -0,0 +1,87 @@ +&mdss_mdp { + dsi_r66451_amoled_60hz_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_video { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox 60Hz panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 7fd9d2bc172f..8049e9d4a014 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +} + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -28,5 +38,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_video>; }; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 03e5cc9147a1..d7bf5f96c7eb 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,4 +1,5 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -158,6 +159,18 @@ }; }; +&dsi_r66451_amoled_60hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From 1126114c747f2fba3bdd9c655dbb74ef151b7ebb Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 31 Jul 2020 12:22:51 +0800 Subject: [PATCH 156/362] ARM: dts: msm: enable LP mode DCS brightness setting for 5K sim panel Used LP mode for DCS brightness command transfer for this 5K sim panel. Change-Id: I1d2b9dfe212dc13e1a4403b56d8c72888df95750 --- display/lahaina-sde-display-cdp.dtsi | 1 + display/lahaina-sde-display-mtp.dtsi | 1 + display/lahaina-sde-display-qrd.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index c393be6f19ee..c53c7af3cac5 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -178,6 +178,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index dfae6039ca0f..167f6866c3f6 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -170,6 +170,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index bb711e419e3c..9080fd8022cd 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -170,6 +170,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { From a5d6febf52c26266891521e9c3969c810be4c838 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 31 Jul 2020 12:20:30 +0800 Subject: [PATCH 157/362] bindings: Documentation: add documentation for DCS transfer mode/state Add a property for DCS brightness commands transfer mode selected. When set the property, will use LP mode for commands transfer, while the default mode is HS mode. Change-Id: I256812b2a3766d1bd31b0eb901ae02f2c0b15211 --- bindings/mdss-dsi-panel.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 47db5592f747..f6c67e5727cd 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -201,6 +201,10 @@ Optional properties: 255 = default value. - qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value. When this boolean is set, will inverted display brightness value. +- qcom,bl-dsc-cmd-state: String that specifies the ctrl state for sending dcs brightness commands. + "dsi_hs_mode" = DSI high speed mode (default) + "dsi_lp_mode" = DSI low power mode + If the string was not set, dsi_hs_mode will be set as default mode. - qcom,mdss-brightness-max-level: Specifies the max brightness level supported. 255 = default value. - qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. From 88722606d735897b7ba455e69c1733a3b9b37deb Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Thu, 13 Aug 2020 16:52:53 +0800 Subject: [PATCH 158/362] ARM: dts: msm: add display panel support for qrd shima Add display panel support for qrd shima. Change-Id: I432ece75d018a29da22d26b6524d677a989dd01d --- display/shima-sde-display-qrd.dtsi | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 display/shima-sde-display-qrd.dtsi diff --git a/display/shima-sde-display-qrd.dtsi b/display/shima-sde-display-qrd.dtsi new file mode 100644 index 000000000000..72107b66065a --- /dev/null +++ b/display/shima-sde-display-qrd.dtsi @@ -0,0 +1,32 @@ +#include "shima-sde-display.dtsi" + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From 183e126f9a0b0b5f1ec4e675165111c71bae3130 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 14:22:30 +0530 Subject: [PATCH 159/362] ARM: dts: msm: Fix compilation error for 60Hz panel on shima This change fixes compilation error with 60Hz panel support on shima idp platform. Change-Id: Ia70fde134829bdb8509d3b65fb471bae8fd6a902 --- display/shima-sde-display-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 8049e9d4a014..a19da7346b70 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -18,7 +18,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; -} +}; &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; From 837a9194cee0f7242d2c70c40d6f7a6ce2d276be Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Tue, 11 Aug 2020 15:10:33 -0700 Subject: [PATCH 160/362] ARM: dts: msm: add display related SPMI address Add SPMI reference node along with the display related SPMI address. This will be used during the trusted-ui usecase where the VMs uses SPMI api to get the physical address, which will be lent/validated during the usecase. Change-Id: Ic3173410790443e87c0584681ec1f0c160fc04a2 --- bindings/sde.txt | 3 +++ display/lahaina-sde-common.dtsi | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 69430faef8d1..9fa9bfc70aba 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -528,6 +528,8 @@ Optional properties: should be excluded from IO memory validation list in trusted vm environment - qcom,vram-size: A u32 value indicating the size of the VRAM in bytes +- qcom,pmic-arb-address: A u32 array of display related SPMI address + bit mask, which is a combination of SID and pheripheral id's. Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -808,6 +810,7 @@ Example: qcom,sde-secure-sid-mask = <0x200801 0x200c01>; qcom,vram-size = <0x200000>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 738a141a3dc2..3730cc8d6dd7 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -228,6 +228,10 @@ qcom,sde-secure-sid-mask = <0x4000821>; + /* SPMI address related to display */ + qcom,pmic-arb = <&spmi_bus>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + qcom,sde-reg-bus,vectors-KBps = <0 0>, <0 74000>, <0 148000>, From ce3b61edb9c1b539c184f099dd9b13b1852a4628 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Tue, 11 Aug 2020 15:10:40 -0700 Subject: [PATCH 161/362] ARM: dts: msm: add gpio pins/address used for BOE cmd panel Add the TLMM base address & size of each GPIO register space along with all the GPIO pins used to drive the DSI host and the BOE panel. Change-Id: Ifabc0713de8c893fdd8b8a0fc38898898ec3c571 --- bindings/mdss-dsi-panel.txt | 9 +++++++++ display/lahaina-sde-display-common.dtsi | 3 +++ 2 files changed, 12 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index f6c67e5727cd..69bdd72ee00e 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -578,6 +578,11 @@ Optional properties: to identify the default topology for the display. The first set is indexed by the value 0. +- qcom,dsi-panel-gpio-address: An u32 pair consisting of base address of the + TLMM register space and size of each GPIO pin. +- qcom,dsi-panel-gpio-pins: An u32 array consisting of all the GPIO pins used + for driving the DSI host and the panels + connected to the host. - qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. - qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active region for video mode panels and line number after TE for command mode @@ -759,6 +764,10 @@ Example: qcom,mdss-dsi-force-clock-lane-hs; qcom,compression-mode = "dsc"; qcom,adjust-timer-wakeup-ms = <1>; + + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,mdss-dsi-display-timings { wqhd { qcom,mdss-dsi-cmd-mode; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 79bd533246cb..db0de1573d19 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -124,6 +124,9 @@ qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05 From 95230a8236dfbf41c4de662e279029fb96ed8759 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 14 Aug 2020 18:03:21 +0530 Subject: [PATCH 162/362] ARM: dts: msm: add rm69299 cmd mode panel support on Holi This change adds visionox rm69299 amoled command mode 60Hz FHD+ dsi panel on Holi target. Change-Id: Iaeb030a7b9fd55dbce4f903223ad1029c63f6c67 --- ...i-panel-rm69299-visionox-fhd-plus-cmd.dtsi | 64 +++++++++++++++++++ display/holi-sde-display-atp.dtsi | 10 +++ display/holi-sde-display-cdp.dtsi | 11 ++++ display/holi-sde-display-mtp.dtsi | 10 +++ display/holi-sde-display.dtsi | 21 ++++++ 5 files changed, 116 insertions(+) create mode 100644 display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi diff --git a/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi b/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi new file mode 100644 index 000000000000..e898151080a6 --- /dev/null +++ b/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi @@ -0,0 +1,64 @@ +&mdss_mdp { + dsi_rm69299_visionox_amoled_cmd: + qcom,mdss_dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-panel-name = + "rm69299 amoled fhd+ cmd mode dsi visionox panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2248>; + qcom,mdss-dsi-h-front-porch = <26>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <56>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 02 C2 08 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 51 FF + 05 01 00 00 96 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi index 9fe8f90c81f4..5efaab6d6cf2 100644 --- a/display/holi-sde-display-atp.dtsi +++ b/display/holi-sde-display-atp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 9fe8f90c81f4..f3b4ef6925c2 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -10,6 +10,17 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi index 9fe8f90c81f4..5efaab6d6cf2 100644 --- a/display/holi-sde-display-mtp.dtsi +++ b/display/holi-sde-display-mtp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index f68e8e82ab7a..33e94bd589da 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,5 +1,6 @@ #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include @@ -133,6 +134,26 @@ }; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; From 261180796d5f7a3f0c59e9515cb7dbb370c209c3 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 19:12:28 +0530 Subject: [PATCH 163/362] ARM: dts: msm: enable esd check for visionox panel on Holi This change enables esd check for rm69299 visionox video and command mode panel in Holi target. Change-Id: I8cca8bccf1b8be46e45ab0379ddb629be7aac3cb --- display/holi-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 33e94bd589da..8c4e1c4c2ab6 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -115,6 +115,7 @@ }; &dsi_rm69299_visionox_amoled_video { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -135,6 +136,7 @@ }; &dsi_rm69299_visionox_amoled_cmd { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; From 12cfdf4061a7b1a47fa0f2f70baff532c73aedfb Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 19:16:53 +0530 Subject: [PATCH 164/362] ARM: dts: msm: enable dfps support for visionox panel on Holi This change enables dynamic fps support for rm6929 visionox video mode panel on Holi target. Change-Id: I3c22b2afa93242f0d224545bcca7452d8df3a7d4 --- display/holi-sde-display.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 8c4e1c4c2ab6..0c39119ce036 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -122,6 +122,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 55 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-t-clk-post = <0x0E>; qcom,mdss-dsi-t-clk-pre = <0x31>; From 2b69c09ab3327128bdb7d0d498e3e63ec31f6978 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Mon, 17 Aug 2020 13:44:51 +0800 Subject: [PATCH 165/362] bindings: Documentation: add documentation for display touch event Add the documentation for configuring the display input touch event feature. Change-Id: Id4236460219038fa644387e2fd8fe97f97554c5e --- bindings/sde.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 69430faef8d1..610cb0ca1e40 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -158,6 +158,9 @@ Optional properties: feature is available or not. - qcom,sde-has-idle-pc: Boolean property to indicate if target has idle power collapse feature available or not. +- qcom,sde-wakeup-with-touch: Boolean property to indicate if command mode display + will exit from power collapse based on display input + touch event or not. - qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction feature available or not. - qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler @@ -718,6 +721,7 @@ Example: qcom,sde-highest-bank-bit = <15>; qcom,sde-has-mixer-gc; qcom,sde-has-idle-pc; + qcom,sde-wakeup-with-touch; qcom,fullsize-va-map; qcom,sde-has-dest-scaler; qcom,sde-max-trusted-vm-displays = <1>; From 096bf87a1d343c1e045cb03161556b5e6ad36e73 Mon Sep 17 00:00:00 2001 From: Divya Sharma Date: Wed, 19 Aug 2020 13:59:30 -0700 Subject: [PATCH 166/362] Revert "ARM: dts: msm: add display device tree files for lahaina MTP v2.1" This reverts commit ce4adee6db2369ac95ae58159f88af250680606f. Change-Id: I68f693b594222e0cf6957ae6908f34c35e39f40c --- display/lahaina-sde-display-mtp-v2.1.dtsi | 3 --- 1 file changed, 3 deletions(-) delete mode 100644 display/lahaina-sde-display-mtp-v2.1.dtsi diff --git a/display/lahaina-sde-display-mtp-v2.1.dtsi b/display/lahaina-sde-display-mtp-v2.1.dtsi deleted file mode 100644 index e4b362c150f1..000000000000 --- a/display/lahaina-sde-display-mtp-v2.1.dtsi +++ /dev/null @@ -1,3 +0,0 @@ -&sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; -}; From 66911e3950133d12f83b1aee52e081154d035aba Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Thu, 16 Jul 2020 17:47:11 +0800 Subject: [PATCH 167/362] ARM: dts: msm: Remove unused property from panel nodes Remove unused property te-gpio from panel nodes, and this property is defined in dsi_display node. Change-Id: Ie6fd4c4f73dbf292bcc58757898fb91468d88ade --- display/lahaina-sde-display-cdp.dtsi | 9 --------- display/lahaina-sde-display-mtp.dtsi | 9 --------- display/lahaina-sde-display-qrd.dtsi | 9 --------- 3 files changed, 27 deletions(-) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index c53c7af3cac5..23695a28dd3a 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -6,7 +6,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -28,7 +27,6 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; @@ -58,7 +56,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -67,7 +64,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -86,7 +82,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -95,7 +90,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -116,7 +110,6 @@ qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -126,7 +119,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -145,7 +137,6 @@ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 167f6866c3f6..804bb6a26c7d 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -6,7 +6,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -26,7 +25,6 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -46,7 +44,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -64,7 +61,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -83,7 +79,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -92,7 +87,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -111,7 +105,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -121,7 +114,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -138,7 +130,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 9080fd8022cd..365e13e7fa43 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -7,7 +7,6 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -27,7 +26,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -46,7 +44,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -64,7 +61,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -83,7 +79,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -92,7 +87,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -111,7 +105,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -121,7 +114,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -138,7 +130,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; From 9d76a1d937af4481e16c35526ae5dda360de6815 Mon Sep 17 00:00:00 2001 From: Vara Reddy Date: Tue, 18 Aug 2020 10:22:52 -0700 Subject: [PATCH 168/362] ARM: dts: msm: enable constant FPS with RFI for BOE panel on Lahaina Enable dynamic refresh with constant FPS feature for BOE video mode panel Change-Id: I1eac76b9d1936982b67fff9d6cd80fc209f1d3e8 --- display/lahaina-sde-display-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 7059407c5de6..6344481ea165 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -143,6 +143,7 @@ "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; qcom,mdss-dsi-display-timings { timing@0 { From a5b27c571910b6e76b5b04266e80ca80a11b9382 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Sun, 16 Aug 2020 17:30:27 +0530 Subject: [PATCH 169/362] ARM: dts: msm: enable offline rotator in Holi target This changes enables sde offline rotator in holi target. Change-Id: I54a947707466a7c561a825404d18bb53c8188e2f --- display/holi-sde.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index a19a85b4781f..4d932ada8d92 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -199,7 +199,6 @@ }; mdss_rotator: qcom,mdss_rotator { - status = "disabled"; compatible = "qcom,sde_rotator"; reg = <0x5e00000 0xac000>, <0x5eb0000 0x2008>; @@ -227,7 +226,7 @@ interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", + interconnect-names = "qcom,rot-data-bus0", "qcom,sde-reg-bus"; qcom,sde-reg-bus,vectors-KBps = <0 0>, <0 76800>; From ffee67ea1ce26f7ab949df4100544ea369258368 Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Sun, 23 Aug 2020 00:18:23 +0530 Subject: [PATCH 170/362] ARM: dts: msm: Extend DP and phy registers to correct size Extend DP and phy registers to correct size. Change-Id: Ia6304d9f4e097e0a7eb429446b87184b62830d7f --- display/shima-sde.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 8705b8ab8a46..e7a9fa86ef15 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -294,18 +294,18 @@ qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; - reg = <0xae90000 0x0dc>, + reg = <0xae90000 0x0f4>, <0xae90200 0x0c0>, - <0xae90400 0x508>, - <0xae91000 0x094>, - <0x88eaa00 0x200>, - <0x88ea200 0x200>, - <0x88ea600 0x200>, - <0xaf02004 0x1a0>, - <0x88ea000 0x200>, - <0x88e8000 0x20>, - <0x0aee1000 0x034>, - <0xae91400 0x094>, + <0xae90400 0x72c>, + <0xae91000 0x098>, + <0x88eaa00 0x198>, + <0x88ea200 0x160>, + <0x88ea600 0x160>, + <0xaf02004 0x1d4>, + <0x88ea000 0x1c8>, + <0x88e8000 0x3c>, + <0x0aee1000 0x02c>, + <0xae91400 0x098>, <0xaf03000 0x8>; reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", From 2b4957d8f7fca45eb13435b4db5441c834cddbeb Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 21 Aug 2020 19:49:48 +0530 Subject: [PATCH 171/362] ARM: dts: msm: change display supply enable load on Shima This change updates the vdd supply enable load to 30mA on Shima target. Minimum 30mA enable load is recommended to bring the regulator out of Low Power Mode. Change-Id: Ibead207dd44123add6858e3a0a1e9e4c67eda6f9 --- display/shima-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index d7bf5f96c7eb..6a72d6a23c56 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -24,7 +24,7 @@ qcom,supply-name = "vdd"; qcom,supply-min-voltage = <3000000>; qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <10000>; + qcom,supply-enable-load = <30000>; qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <0>; }; From 82ea6416b38e2d8784ff10fd8d8dde60c5b42042 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Sat, 22 Aug 2020 14:49:52 +0530 Subject: [PATCH 172/362] ARM: dts: msm: create sde-display-common device tree on Holi Separate common SDE display bindings in sde-display-common dt file to avoid unwanted duplications between VM variants of the SDE display files on Holi target. Change-Id: Id86e414207a9874c6ddcc2855f01e774d49f1fff --- display/holi-sde-display-common.dtsi | 148 +++++++++++++++++++++++ display/holi-sde-display.dtsi | 174 +++------------------------ 2 files changed, 168 insertions(+), 154 deletions(-) create mode 100644 display/holi-sde-display-common.dtsi diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi new file mode 100644 index 000000000000..808738871503 --- /dev/null +++ b/display/holi-sde-display-common.dtsi @@ -0,0 +1,148 @@ +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,dsi-supported-dfps-list = <60 55 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0B>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 0c39119ce036..026318b53148 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,9 +1,4 @@ -#include "dsi-panel-sim-video.dtsi" -#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" -#include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" -#include +#include "holi-sde-display-common.dtsi" &pm6150l_gpios { disp_pins { @@ -18,102 +13,35 @@ }; }; -&soc { - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <62000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_te_active &disp_pins_default>; + pinctrl-1 = <&sde_te_suspend>; - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <857000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; - }; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,panel-te-source = <0>; - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; + vddio-supply = <&L1E>; + vdd-supply = <&L8A>; - qcom,panel-supply-entry@3 { - reg = <3>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - sde_dsi: qcom,dsi-display-primary { - compatible = "qcom,dsi-display"; - label = "primary"; - - qcom,dsi-ctrl = <&mdss_dsi0>; - qcom,dsi-phy = <&mdss_dsi_phy0>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_te_active &disp_pins_default>; - pinctrl-1 = <&sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 23 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&L1E>; - vdd-supply = <&L8A>; - - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; - - qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; - }; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; }; &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dsi>; }; -&dsi_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - &dsi_rm69299_visionox_amoled_video { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -122,20 +50,6 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-supported-dfps-list = <60 55 48>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0E>; - qcom,mdss-dsi-t-clk-pre = <0x31>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 - 08 05 02 04 00]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_rm69299_visionox_amoled_cmd { @@ -146,17 +60,6 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0E>; - qcom,mdss-dsi-t-clk-pre = <0x31>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 - 08 05 02 04 00]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_r66451_amoled_cmd { @@ -167,31 +70,6 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0A>; - qcom,mdss-dsi-t-clk-pre = <0x1D>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 - 04 03 02 04 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 - 07 08 02 04 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_r66451_amoled_video { @@ -201,16 +79,4 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0B>; - qcom,mdss-dsi-t-clk-pre = <0x27>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - }; }; - From a3cc91d1851abe5944fed3c72a335531a790d647 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Tue, 26 May 2020 12:02:18 +0800 Subject: [PATCH 173/362] ARM: dts: msm: add 144hz panel support for lahaina Add DDIC R66451 144hz panel dtsi support for lahaina. Change-Id: Id3d39b94ab3d189d8a6703e4042f607256403dae --- ...i-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi | 134 ++++++++++++++++++ display/lahaina-sde-display-cdp.dtsi | 12 ++ display/lahaina-sde-display-common.dtsi | 14 ++ display/lahaina-sde-display-mtp.dtsi | 12 ++ display/lahaina-sde-display-qrd.dtsi | 12 ++ display/lahaina-sde-display.dtsi | 9 ++ 6 files changed, 193 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi new file mode 100644 index 000000000000..a959920b50ca --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi @@ -0,0 +1,134 @@ +&mdss_mdp { + dsi_r66451_amoled_144hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 B0 04 + 39 01 00 00 00 00 03 E8 00 02 + 39 01 00 00 00 00 03 E4 00 08 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 32 C4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0C 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 CF 64 0B 00 00 00 + 00 00 00 08 00 0B 77 01 01 01 01 01 + 01 02 02 02 02 02 03 00 00 00 00 00 + 00 00 00 00 00 00 00 02 C9 02 C9 02 + C9 03 FF 03 FF 03 FF 00 00 00 00 00 + 00 00 00 00 00 00 00 02 C9 02 C9 02 + C9 03 FF 03 FF 03 FF 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 0F F6 0F + F6 0F F6 0F F6 0F F6 19 + 39 01 00 00 00 00 0D D0 44 44 B2 28 00 + 28 5A 00 5A 0D 17 01 + 39 01 00 00 00 00 15 D3 49 00 00 01 1A + 15 00 15 07 0F 77 77 77 37 B2 11 00 + A0 3C 9A + 39 01 00 00 00 00 1A D7 00 B9 40 00 40 + 04 00 F0 0F 00 40 00 00 00 00 00 00 + 19 40 00 40 04 00 F0 0F + 39 01 00 00 00 00 34 D8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0F + 00 0F 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0F 00 2F 00 0F 00 20 + 39 01 00 00 00 00 2B DF 50 42 58 81 2D + 00 00 00 00 00 00 6B 00 00 00 00 00 + 00 00 00 01 0F FF D4 0E 00 00 00 00 + 00 00 0F 53 18 00 0F 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 F7 01 + 39 01 00 00 00 00 02 B0 80 + 39 01 00 00 00 00 0a E4 34 B4 00 00 00 + 30 04 0C E2 + 39 01 00 00 00 00 02 E6 00 + 39 01 00 00 00 00 02 B0 04 + 39 01 00 00 00 00 03 DF 50 40 + 39 01 00 00 00 00 06 F3 50 00 00 00 00 + 39 01 00 00 00 00 02 F2 11 + 39 01 00 00 00 00 06 F3 01 00 00 00 01 + 39 01 00 00 00 00 03 F4 00 02 + 39 01 00 00 00 00 02 F2 19 + 39 01 00 00 00 00 03 DF 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 23695a28dd3a..58ebc3bec606 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -47,6 +47,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -56,6 +57,17 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index e8d923ee4a08..923309e61b86 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -15,6 +15,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" @@ -228,6 +229,19 @@ }; }; +&dsi_r66451_amoled_144hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 804bb6a26c7d..ad1eb186123b 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -44,6 +44,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -53,6 +54,17 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 365e13e7fa43..6792ded59c5e 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -26,6 +26,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -35,6 +36,17 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 4e0465985d59..60e9663d7420 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -145,6 +145,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; qcom,esd-check-enabled; }; +&dsi_r66451_amoled_144hz_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; From 9d7cdad4617f3137f1ed52a9282c55e441f87aca Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Tue, 25 Aug 2020 10:23:24 +0530 Subject: [PATCH 174/362] ARM: dts: msm: add display ramdump support for holi target This change adds dt support for display during ramdump in holi target. Change-Id: I3e5ff5d6be7813b8f06ba2213f67d98b65e16a66 --- display/holi-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index a19a85b4781f..79854a6e01de 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -1,6 +1,11 @@ #include &soc { + disp_rdump_memory: disp_rdump_region@85200000 { + reg = <0x0 0x85200000 0x0 0x00c00000>; + label = "disp_rdump_region"; + }; + mdss_mdp: qcom,mdss_mdp@5e00000 { compatible = "qcom,sde-kms"; reg = <0x05e00000 0x8f030>, From 42facf71b0d514cb4fb2554b7ce682fa9cce4a4a Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Mon, 24 Aug 2020 16:14:45 +0800 Subject: [PATCH 175/362] ARM: dts: msm: modify VFP & VBP value for nt35597 panel Increase VFP and VBP value to get higer performance. Default prefill lines is 40 for lahaina, if VFP + VBP + VSYNC_PULSE is lower than 40, may lead to perf issues in some cases. Change-Id: I9d2a39cf9cbf14adc06eee03c7b79433bf498ef3 --- display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi index 090c75f8b90d..417d22e3c8b5 100644 --- a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi +++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi @@ -39,8 +39,8 @@ qcom,mdss-dsi-h-back-porch = <32>; qcom,mdss-dsi-h-pulse-width = <16>; qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-back-porch = <17>; + qcom,mdss-dsi-v-front-porch = <23>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-on-command = [ From d087180fe44cd9794e624179c8e79f2dacaeef74 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 27 Aug 2020 12:12:11 +0530 Subject: [PATCH 176/362] ARM: dts: msm: create sde-common device tree for holi target Separate common SDE bindings in sde-common-dt file to avoid unwanted duplications between VM variants of the SDE files for holi target. Change-Id: I45cab5017c296ec8669892b5edd0a742b59011f4 --- display/holi-sde-common.dtsi | 246 +++++++++++++++++++++++ display/holi-sde.dtsi | 375 +++++++---------------------------- 2 files changed, 317 insertions(+), 304 deletions(-) create mode 100644 display/holi-sde-common.dtsi diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi new file mode 100644 index 000000000000..95e9c2d00abf --- /dev/null +++ b/display/holi-sde-common.dtsi @@ -0,0 +1,246 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@5e00000 { + compatible = "qcom,sde-kms"; + reg = <0x05e00000 0x8f030>, + <0x05eb0000 0x2008>, + <0x05e8f000 0x030>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys"; + + clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; + clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 + 560000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2c0>; + qcom,sde-intf-type = "none", "dsi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800>; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dsc-off = <0x81000>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + qcom,sde-mixer-stage-base-layer; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; + qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-sspp-linewidth = <2160>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-highest-bank-bit = <0x0 0x1>; + qcom,sde-ubwc-version = <0x200>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1e>; + qcom,sde-macrotile-mode = <0x0>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-dim-layer; + qcom,sde-max-bw-low-kbps = <5200000>; + qcom,sde-max-bw-high-kbps = <6200000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <1>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + qcom,sde-qos-refresh-rates = <60 120>; + qcom,sde-danger-lut = <0xffff 0xffff 0x0 + 0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0 + 0x0 0x3ffff 0x3ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + + qcom,sde-secure-sid-mask = <0x821>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <32>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <1000>; + reg = <0x05e94000 0x400>, + <0x05f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 { + compatible = "qcom,dsi-phy-v3.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x05e94400 0x800>, + <0x05e94a00 0x1e0>, + <0x05f01004 0x8>, + <0x05e94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_10nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 80]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + +}; diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index 7c7a92e67ff9..2f9a7371774b 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -1,3 +1,4 @@ +#include "holi-sde-common.dtsi" #include &soc { @@ -6,201 +7,20 @@ label = "disp_rdump_region"; }; - mdss_mdp: qcom,mdss_mdp@5e00000 { - compatible = "qcom,sde-kms"; - reg = <0x05e00000 0x8f030>, - <0x05eb0000 0x2008>, - <0x05e8f000 0x030>; - reg-names = "mdp_phys", - "vbif_phys", - "sid_phys"; + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; - clocks = - <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_THROTTLE_CORE_CLK>, - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "throttle_clk", - "div_clk", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk", "rot_clk"; - clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; - clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 - 560000000>; - - sde-vdd-supply = <&mdss_core_gdsc>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - #power-domain-cells = <0>; - - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x2000>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary"; - - qcom,sde-mixer-off = <0x45000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-intf-off = <0x0 0x6b800>; - qcom,sde-intf-size = <0x2c0>; - qcom,sde-intf-type = "none", "dsi"; - qcom,sde-intf-tear-irq-off = <0 0x6e800>; - - qcom,sde-pp-off = <0x71000>; - qcom,sde-pp-size = <0xd4>; - - qcom,sde-dsc-off = <0x81000>; - qcom,sde-dsc-size = <0x140>; - - qcom,sde-dither-off = <0x30e0>; - qcom,sde-dither-version = <0x00010000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-sspp-type = "vig", "dma"; - - qcom,sde-sspp-off = <0x5000 0x25000>; - qcom,sde-sspp-src-size = <0x1f8>; - - qcom,sde-sspp-xin-id = <0 1>; - qcom,sde-sspp-excl-rect = <1 1>; - qcom,sde-sspp-smart-dma-priority = <2 1>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <0>; - qcom,sde-mixer-stage-base-layer; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0 0xf8 0x110>; - - qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; - qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-sspp-linewidth = <2160>; - qcom,sde-vig-sspp-linewidth = <4096>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-mixer-linewidth = <2048>; - qcom,sde-mixer-blendstages = <0x4>; - qcom,sde-highest-bank-bit = <0x0 0x1>; - qcom,sde-ubwc-version = <0x200>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1e>; - qcom,sde-macrotile-mode = <0x0>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-dim-layer; - qcom,sde-has-idle-pc; - qcom,sde-max-bw-low-kbps = <5200000>; - qcom,sde-max-bw-high-kbps = <6200000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <1600000>; - qcom,sde-dram-channels = <1>; - qcom,sde-num-nrt-paths = <0>; - - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x2008>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - - qcom,sde-qos-refresh-rates = <60 120>; - qcom,sde-danger-lut = <0xffff 0xffff 0x0 - 0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0 - 0x0 0x3ffff 0x3ffff>; - - qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>; - - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - - qcom,sde-secure-sid-mask = <0x821>; - qcom,sde-num-mnoc-ports = <1>; - qcom,sde-axi-bus-width = <32>; - - /* data and reg bus scale settings */ - interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, - <&bimc MASTER_AMPSS_M0 - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", - "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 76800>, - <0 150000>, - <0 300000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "sde-vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; }; mdss_rotator: qcom,mdss_rotator { @@ -267,114 +87,61 @@ qcom,iommu-vmid = <0xa>; }; }; - - mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <1000>; - reg = <0x05e94000 0x400>, - <0x05f08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&L22A>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <21800>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 { - compatible = "qcom,dsi-phy-v3.0"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0x05e94400 0x800>, - <0x05e94a00 0x1e0>, - <0x05f01004 0x8>, - <0x05e94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_10nm"; - vdda-0p9-supply = <&S5A_LEVEL>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 80]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = - ; - qcom,supply-max-voltage = - ; - qcom,supply-off-min-voltage = - ; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - smmu_sde_unsec: qcom,smmu_sde_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&apps_smmu 0x820 0x2>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-earlymap; /* for cont-splash */ - }; - - smmu_sde_sec: qcom,smmu_sde_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x821 0x0>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-vmid = <0xa>; - }; - +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + "div_clk", "iface_clk", "core_clk", + "vsync_clk", "lut_clk", "rot_clk"; + sde-vdd-supply = <&mdss_core_gdsc>; + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + qcom,sde-has-idle-pc; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L22A>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&S5A_LEVEL>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; }; From e19f7a9a69fdc031135459783dc06d2fb8ad7a83 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Sat, 22 Aug 2020 15:49:42 +0530 Subject: [PATCH 177/362] ARM: dts: msm: enable esd check for visionox panel on Shima This change enables esd check for r66451 visionox video and command mode panels on Shima target. Change-Id: I99b48f8f25241e6f6e8d8c9d9148e7caa9c83233 --- display/shima-sde-display.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 6a72d6a23c56..62c18c390559 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -143,6 +143,7 @@ }; &dsi_r66451_amoled_video { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -160,6 +161,12 @@ }; &dsi_r66451_amoled_60hz_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -172,6 +179,7 @@ }; &dsi_r66451_amoled_cmd { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; From 549d5d75e4ab3933c239a0a7b4598f8bafb2ea21 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 27 Aug 2020 14:45:11 +0530 Subject: [PATCH 178/362] ARM: dts: msm: change max backlight level of visionox panel on Holi Change max backlight level of visionox rm69299 panel to 255 on Holi target. Change-Id: I8a28102119e65f446c16c2780dcf3d7e47adc332 --- display/holi-sde-display-atp.dtsi | 6 ++---- display/holi-sde-display-cdp.dtsi | 6 ++---- display/holi-sde-display-mtp.dtsi | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi index 5efaab6d6cf2..50e6d5d948d1 100644 --- a/display/holi-sde-display-atp.dtsi +++ b/display/holi-sde-display-atp.dtsi @@ -4,8 +4,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; @@ -14,8 +13,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index f3b4ef6925c2..045a79255a76 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -4,8 +4,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; @@ -14,8 +13,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi index 5efaab6d6cf2..50e6d5d948d1 100644 --- a/display/holi-sde-display-mtp.dtsi +++ b/display/holi-sde-display-mtp.dtsi @@ -4,8 +4,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; @@ -14,8 +13,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; From e662a6cdee40debf1ee21fcf12f1e3cc68e4f643 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 26 Aug 2020 11:00:08 +0530 Subject: [PATCH 179/362] ARM: dts: msm: enable 120fps panel support on Shima This change enables 120fps support for r66451 visionox video mode panel on Shima target. Change-Id: Ic184dd9c2013f7ee9f149782f5b127e94cf0a0d5 --- display/shima-sde-display.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 6a72d6a23c56..71d4e35bad51 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -94,7 +94,6 @@ ibb-supply = <&ibb_vreg>; qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; }; sde_dsi1: qcom,dsi-display-secondary { @@ -151,8 +150,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From dab7edef646740885170aa3f83bd6caffcb81537 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Mon, 31 Aug 2020 15:21:07 -0400 Subject: [PATCH 180/362] ARM: dts: msm: Add Rounded Corner DTSI nodes to Holi target Add Rounded Corner feature DTSI nodes to Holi target. Change-Id: I355a14c0cf6d531ba5706c35a74c881746e4d8c9 --- display/holi-sde-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index 95e9c2d00abf..1fe879f007be 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -38,6 +38,11 @@ qcom,sde-dspp-off = <0x55000>; qcom,sde-dspp-size = <0x1800>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-intf-off = <0x0 0x6b800>; qcom,sde-intf-size = <0x2c0>; qcom,sde-intf-type = "none", "dsi"; From e2a651de1e81a87203103a9d668a5b3b22d53eb6 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 31 Aug 2020 20:06:18 +0530 Subject: [PATCH 181/362] ARM: dts: msm: Update default panel to 120Hz for shima Update default panel to 120Hz configuration for shima target. Change-Id: I1e5a50db0de9ff23579f6c2a2d821e158f55d623 --- display/shima-sde-display-idp.dtsi | 2 +- display/shima-sde-display.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index a19da7346b70..1f7dd6e22ca5 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -38,5 +38,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 915fcb443d56..72fa08d93e6d 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -12,8 +12,8 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; + qcom,supply-min-voltage = <1920000>; + qcom,supply-max-voltage = <1920000>; qcom,supply-enable-load = <60700>; qcom,supply-disable-load = <80>; qcom,supply-post-on-sleep = <20>; From 8e2d7426c1306ad54f66cb4f90b9d85091e60d1e Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Sat, 22 Aug 2020 15:44:08 +0530 Subject: [PATCH 182/362] ARM: dts: msm: enable dfps support for visionox panel on Shima This change enables dynamic fps support for r66451 visionox video mode panel on Shima target. Change-Id: I54d71bee57562ef920e58485abc42554e09536a9 --- display/shima-sde-display.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 72fa08d93e6d..a4d84a3f6033 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -148,6 +148,11 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <120 90 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <120>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { From 4e556f7dbcc503241dd14237418927a68c4a9a76 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 28 Aug 2020 16:22:47 +0530 Subject: [PATCH 183/362] ARM: dts: msm: create sde-display-common device tree on Shima Separate common SDE display bindings in sde-display-common dt file to avoid unwanted duplications between VM variants of the SDE display files on Shima target. Change-Id: Ibcb285e855a5474f9308f55032389c63d4725357 --- display/shima-sde-display-common.dtsi | 140 ++++++++++++++ display/shima-sde-display.dtsi | 255 +++++++------------------- 2 files changed, 206 insertions(+), 189 deletions(-) create mode 100644 display/shima-sde-display-common.dtsi diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi new file mode 100644 index 000000000000..6b1baacf6a4f --- /dev/null +++ b/display/shima-sde-display-common.dtsi @@ -0,0 +1,140 @@ +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1920000>; + qcom,supply-max-voltage = <1920000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + qcom,mdp = <&mdss_mdp>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + qcom,mdp = <&mdss_mdp>; + }; +}; + +&dsi_r66451_amoled_video { + qcom,dsi-supported-dfps-list = <120 90 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <120>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index a4d84a3f6033..b2e706c34a36 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,134 +1,6 @@ -#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-sim-video.dtsi" -#include +#include "shima-sde-display-common.dtsi" &soc { - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1920000>; - qcom,supply-max-voltage = <1920000>; - qcom,supply-enable-load = <60700>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <30000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - - qcom,panel-supply-entry@3 { - reg = <3>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - sde_dsi: qcom,dsi-display-primary { - compatible = "qcom,dsi-display"; - label = "primary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1", - "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 82 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; - - qcom,mdp = <&mdss_mdp>; - }; - - sde_dsi1: qcom,dsi-display-secondary { - compatible = "qcom,dsi-display"; - label = "secondary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; - - qcom,platform-te-gpio = <&tlmm 83 0>; - qcom,panel-te-source = <1>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - - qcom,mdp = <&mdss_mdp>; - }; - sde_wb: qcom,wb-display@0 { compatible = "qcom,wb-display"; cell-index = <0>; @@ -136,6 +8,71 @@ }; }; +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; +}; + + &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_dsi1>; @@ -148,20 +85,6 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-supported-dfps-list = <120 90 60 48>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-min-refresh-rate = <48>; - qcom,mdss-dsi-max-refresh-rate = <120>; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 - 08 05 02 04 00 17 0c]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_r66451_amoled_60hz_video { @@ -171,15 +94,6 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 - 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_r66451_amoled_cmd { @@ -189,41 +103,4 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 - 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 - 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <1 0 1>, - <2 0 1>; - qcom,default-topology-index = <0>; - }; - }; }; From 24f69624b7a9d427c8e0510c818f0a7d67075c37 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 2 Sep 2020 12:36:50 +0530 Subject: [PATCH 184/362] ARM: dts: msm: create sde-common device tree for shima target Separate common SDE bindings in sde-common dt file so that unwanted duplications between VM variants of SDE files can be avoided. Change-Id: I78563c64f1b505e42669e6680fed64f85d513f25 --- display/shima-sde-common.dtsi | 389 ++++++++++++++++++++++++++ display/shima-sde.dtsi | 513 +++++----------------------------- 2 files changed, 463 insertions(+), 439 deletions(-) create mode 100644 display/shima-sde-common.dtsi diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi new file mode 100644 index 000000000000..a3a5861c05e4 --- /dev/null +++ b/display/shima-sde-common.dtsi @@ -0,0 +1,389 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + clock-rate = <0 0 0 0 460000000 19200000 460000000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none"; + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + + qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x84000 0x84100>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + qcom,sde-sspp-xin-id = <0 4 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, + <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2880>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x7 0x1>, + <0x8 0x2>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <5900000>; + qcom,sde-max-bw-high-kbps = <13500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + /* creq LUTs */ + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-id = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801 0xC01>; + + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index e7a9fa86ef15..6e5e724c7e6e 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -1,274 +1,7 @@ +#include "shima-sde-common.dtsi" #include &soc { - mdss_mdp: qcom,mdss_mdp@ae00000 { - compatible = "qcom,sde-kms"; - reg = <0xae00000 0x84208>, - <0xaeb0000 0x2008>, - <0xaeac000 0x214>, - <0xaf50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "swfuse_phys"; - clocks = - <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 0 0 460000000 19200000 460000000>; - clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - vdd-supply = <&disp_cc_mdss_core_gdsc>; - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; - - qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "primary", "none", - "none"; - qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000 0x57000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-top-size = <0x1c>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-dest-scaler-size = <0x800>; - - qcom,sde-wb-off = <0x66000>; - qcom,sde-wb-size = <0x2c8>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-intf-off = <0x6b000 0x6b800 - 0x6c000 0x6c800>; - qcom,sde-intf-size = <0x2b8>; - qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; - qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; - - qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; - qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; - - qcom,sde-merge-3d-off = <0x84000 0x84100>; - qcom,sde-merge-3d-size = <0x100>; - - qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; - - qcom,sde-cdm-off = <0x7a200>; - qcom,sde-cdm-size = <0x224>; - - qcom,sde-dsc-off = <0x81000 0x81400>; - qcom,sde-dsc-size = <0x140>; - qcom,sde-dsc-pair-mask = <2 1>; - - qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 - 0x30e0>; - qcom,sde-dither-version = <0x00010000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-sspp-type = "vig", "vig", - "dma", "dma", "dma"; - qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; - qcom,sde-sspp-src-size = <0x1f8>; - qcom,sde-sspp-xin-id = <0 4 1 5 9>; - qcom,sde-sspp-excl-rect = <1 1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <2 1 4 3>; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0>; - - qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, - <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; - qcom,sde-sspp-clk-status = - <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, - <0x2b8 12>, <0x2c8 12>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <2880>; - qcom,sde-vig-sspp-linewidth = <4096>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-wb-linewidth = <4096>; - qcom,sde-mixer-blendstages = <0x9>; - qcom,sde-highest-bank-bit = <0x7 0x1>, - <0x8 0x2>; - qcom,sde-ubwc-version = <0x400>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1>; - qcom,sde-macrotile-mode = <0x1>; - qcom,sde-smart-panel-align-mode = <0xc>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; - qcom,sde-has-idle-pc; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <5900000>; - qcom,sde-max-bw-high-kbps = <13500000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <1600000>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-ltm-version = <0x00010000>; - /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x1040>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - - /* macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff - 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - - qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; - - /* creq LUTs */ - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; - qcom,sde-qos-refresh-rates = <60 120>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-id = <0>; - qcom,sde-reg-dma-version = <0x00010002>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-secure-sid-mask = <0x801 0xC01>; - - /* data and reg bus scale settings */ - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 74000>, - <0 148000>, - <0 265000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040002>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - ext_disp: qcom,msm-ext-disp { status = "disabled"; compatible = "qcom,msm-ext-disp"; @@ -453,181 +186,83 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; +}; - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <800>; - reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + vdd-supply = <&disp_cc_mdss_core_gdsc>; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-1"; - cell-index = <1>; - frame-threshold-time-us = <800>; - reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <5 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-1"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96400 0x800>, - <0xae96900 0x27c>, - <0xaf03000 0x8>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; }; }; }; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; From ac5193ab05fe76cbc17370fafaabea144f65b15e Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 2 Sep 2020 12:33:59 +0530 Subject: [PATCH 185/362] ARM: dts: msm: enable SDE RSC driver on shima Enable sde rscc v4 driver on shima target Change-Id: Ib0d930dfc6837f53edbff41970035ec0165586ae --- display/shima-sde-display.dtsi | 2 +- display/shima-sde.dtsi | 16 ---------------- 2 files changed, 1 insertion(+), 17 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 915fcb443d56..27f33e0b435c 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -138,7 +138,7 @@ &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi - &sde_dsi1>; + &sde_dsi1 &sde_rscc>; }; &dsi_r66451_amoled_video { diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 6e5e724c7e6e..6cbbb353d36f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -147,7 +147,6 @@ sde_rscc: qcom,sde_rscc { cell-index = <0>; compatible = "qcom,sde-rsc"; - status = "disabled"; reg = <0xaf20000 0x4d68>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; @@ -200,7 +199,6 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; - vdd-supply = <&disp_cc_mdss_core_gdsc>; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, @@ -213,20 +211,6 @@ qcom,sde-dspp-ltm-version = <0x00010000>; /* offsets are based off dspp 0 and dspp 1 */ qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi0 { From 90bbe30d7ae8ae43b0418158c58ed19b153841a0 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 3 Sep 2020 13:20:07 +0530 Subject: [PATCH 186/362] ARM: dts: msm: Enable Dynamic clock switch feature on Holi This change enables dynamic dsi clock switch feature for video and command mode visionox panel on Holi target. Change-Id: I6f79e6dfa14f21ca0647330cca3d581271559b9b --- display/holi-sde-display-common.dtsi | 11 ++++++++++- display/holi-sde.dtsi | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 808738871503..285cda97497c 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -78,7 +78,13 @@ qcom,dsi-supported-dfps-list = <60 55 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <952174080 948206688 956141472>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; qcom,mdss-dsi-t-clk-post = <0x0E>; qcom,mdss-dsi-t-clk-pre = <0x31>; qcom,mdss-dsi-display-timings { @@ -93,6 +99,9 @@ &dsi_rm69299_visionox_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <929813440 925939216 922064992>; qcom,mdss-dsi-t-clk-post = <0x0E>; qcom,mdss-dsi-t-clk-pre = <0x31>; qcom,mdss-dsi-display-timings { diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index 2f9a7371774b..fac819edfda5 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -144,4 +144,5 @@ vdda-0p9-supply = <&S5A_LEVEL>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; From eae7d1185fc01fd0d1ed35ca5dfdb189b2e0a8bc Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Wed, 2 Sep 2020 15:07:40 +0530 Subject: [PATCH 187/362] ARM: dts: msm: Enable display port for shima Enable display port feature for shima target. Change-Id: Id62f46940f138ed97e7e0c9950c73b7964a7c763 --- display/shima-sde-display.dtsi | 2 +- display/shima-sde.dtsi | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 27f33e0b435c..4734603d6edf 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -137,7 +137,7 @@ }; &mdss_mdp { - connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 6cbbb353d36f..7b2994593d5f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -3,7 +3,6 @@ &soc { ext_disp: qcom,msm-ext-disp { - status = "disabled"; compatible = "qcom,msm-ext-disp"; ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { @@ -12,12 +11,10 @@ }; qcom_msmhdcp: qcom,msm_hdcp { - status = "disabled"; compatible = "qcom,msm-hdcp"; }; sde_dp: qcom,dp_display@ae90000 { - status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; From 9f7d4d9c75342f963268db1132c5b39fe00b370c Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 18 Aug 2020 13:34:52 -0700 Subject: [PATCH 188/362] ARM: dts: msm: vote for higher VDDIO voltage for MTPv2.1 Change votes for higher VDDIO voltage, as unexpected high IR drops on MTPv2.1 are causing display instability. Change-Id: Ib06609fc2871f998829c0b6e75ba0aa527a8595b --- display/lahaina-sde-display-mtp-v2.1.dtsi | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/display/lahaina-sde-display-mtp-v2.1.dtsi b/display/lahaina-sde-display-mtp-v2.1.dtsi index e4b362c150f1..f7cd6321a220 100644 --- a/display/lahaina-sde-display-mtp-v2.1.dtsi +++ b/display/lahaina-sde-display-mtp-v2.1.dtsi @@ -1,3 +1,47 @@ +&dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <2000000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; From 43a82bf1d13872fe42dcfbe3654b8e3d0a40f420 Mon Sep 17 00:00:00 2001 From: Divya Sharma Date: Thu, 3 Sep 2020 11:35:11 -0700 Subject: [PATCH 189/362] Revert "ARM: dts: msm: Fix compilation error for 60Hz panel on shima" This reverts commit 53d32d47d08300b9cc5d3a81182f8ee8ee5fdcf8. Change-Id: I43d502020c3471e338fcfbd86a0626a62a8d736c --- display/shima-sde-display-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index a19da7346b70..8049e9d4a014 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -18,7 +18,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; -}; +} &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; From ed7785cb1789d36d87ddede3d4a442aaa29a8b09 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 6 Aug 2020 18:23:40 +0530 Subject: [PATCH 190/362] Revert "ARM: dts: msm: add r66451 video mode 60hz panel support" This reverts commit fbd9ab3a3572c057bfeac6a1d2bd1717f988b564. Change-Id: I481f604cc819605d8b3a33122c6cee3a3e15aa55 --- ...-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 87 ------------------- display/shima-sde-display-idp.dtsi | 12 +-- display/shima-sde-display.dtsi | 13 --- 3 files changed, 1 insertion(+), 111 deletions(-) delete mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi deleted file mode 100644 index 50e11b87af55..000000000000 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -&mdss_mdp { - dsi_r66451_amoled_60hz_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_video { - qcom,mdss-dsi-panel-name = - "r66451 amoled video mode dsi visionox 60Hz panel with DSC"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - qcom,mdss-dsi-panel-physical-type = "oled"; - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <95>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <1>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 02 b3 01 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 13 d8 00 00 00 00 00 - 00 00 00 00 5b 00 5b 00 5b 00 5b 00 - 5b - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 19 cf 64 0b 00 00 00 - 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 02 f7 01 - 39 01 00 00 00 00 03 df 50 40 - 39 01 00 00 00 00 06 f3 50 00 00 00 00 - 39 01 00 00 00 00 02 f2 11 - 39 01 00 00 00 00 06 f3 01 00 00 00 01 - 39 01 00 00 00 00 03 f4 00 02 - 39 01 00 00 00 00 02 f2 19 - 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 2a 00 00 04 37 - 39 01 00 00 00 00 05 2b 00 00 09 23 - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 - ]; - - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <20>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 8049e9d4a014..7fd9d2bc172f 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -10,16 +10,6 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; -&dsi_r66451_amoled_60hz_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; - qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 24 0>; -} - &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -38,5 +28,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; }; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index d7bf5f96c7eb..03e5cc9147a1 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,5 +1,4 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -159,18 +158,6 @@ }; }; -&dsi_r66451_amoled_60hz_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 - 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - &dsi_r66451_amoled_cmd { qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From 3b21dd7bf7717d7f72eba5be74f36b67acb934d7 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 4 Sep 2020 09:41:30 +0530 Subject: [PATCH 191/362] ARM: dts: msm: add trusted vm dtsi files for shima target Add trusted vm dt files for shima target. Common device tree bindings for shima are inherited in these files. Change-Id: I67e2191f964e5193c84652c8a2064ff64aadcdff --- display/trustedvm-shima-sde.dtsi | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 display/trustedvm-shima-sde.dtsi diff --git a/display/trustedvm-shima-sde.dtsi b/display/trustedvm-shima-sde.dtsi new file mode 100644 index 000000000000..86166909fcd5 --- /dev/null +++ b/display/trustedvm-shima-sde.dtsi @@ -0,0 +1,68 @@ +#include "shima-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + + qcom,sde-hw-version = <0x60070000>; + clocks = + <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + qcom,sde-trusted-vm-env; + qcom,vram-size = <0x200000>; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From 695c0712eecd24688af59f33fbf251fe5a8787c9 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 8 Sep 2020 19:28:08 +0530 Subject: [PATCH 192/362] ARM: dts: msm: Add 60Hz command mode support on shima This change Add 60Hz command mode panel support on shima idp platform. Change-Id: I15a258debfee22c6a1eed29daf090ddedddd39d7 --- ...si-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi | 95 +++++++++++++++++++ display/shima-sde-display-common.dtsi | 13 +++ display/shima-sde-display-idp.dtsi | 11 +++ display/shima-sde-display.dtsi | 9 ++ 4 files changed, 128 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi new file mode 100644 index 000000000000..8bf39c27e5f5 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi @@ -0,0 +1,95 @@ +&mdss_mdp { + dsi_r66451_amoled_60hz_cmd: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox 60HZ panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 6b1baacf6a4f..17b6881b10e2 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -1,6 +1,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -99,6 +100,18 @@ }; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 03 03 02 04 00 0f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 1f7dd6e22ca5..3cb99c69fa0b 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -20,6 +20,17 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index c9f2324b1aae..c13225ec0af7 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -96,6 +96,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_cmd { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From e4b1a6a48ac7fffeeb9daff62ead4c80f312c4e0 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Tue, 8 Sep 2020 21:17:43 +0530 Subject: [PATCH 193/362] Revert "Revert "ARM: dts: msm: add r66451 video mode 60hz panel support"" This reverts commit 079ae4d2ea92769d9228f23ad5f9bdaba02e1e95. Change-Id: I3186822818abb326858a41c8cc23980b2e68da8e --- ...-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 87 +++++++++++++++++++ display/shima-sde-display-idp.dtsi | 12 ++- display/shima-sde-display.dtsi | 13 +++ 3 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi new file mode 100644 index 000000000000..50e11b87af55 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi @@ -0,0 +1,87 @@ +&mdss_mdp { + dsi_r66451_amoled_60hz_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_video { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox 60Hz panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 7fd9d2bc172f..8049e9d4a014 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +} + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -28,5 +38,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_video>; }; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 03e5cc9147a1..d7bf5f96c7eb 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,4 +1,5 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -158,6 +159,18 @@ }; }; +&dsi_r66451_amoled_60hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From f8f33d32965796ca6d9904c59c21b3908874807a Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Tue, 8 Sep 2020 22:11:15 +0530 Subject: [PATCH 194/362] Revert "Revert "ARM: dts: msm: Fix compilation error for 60Hz panel on shima"" This reverts commit d3688fdd16fa0aa8b65032f11b5326683051a89f. Change-Id: I847ef1785754894f4a2ec235c387879dc5d939cb --- display/shima-sde-display-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 8049e9d4a014..a19da7346b70 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -18,7 +18,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; -} +}; &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; From 3b1adf7e4189273ff4e5e198a39b14aa9535db02 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 2 Sep 2020 12:36:50 +0530 Subject: [PATCH 195/362] ARM: dts: msm: create sde-common device tree for shima target Separate common SDE bindings in sde-common dt file so that unwanted duplications between VM variants of SDE files can be avoided. Change-Id: I78563c64f1b505e42669e6680fed64f85d513f25 --- display/shima-sde-common.dtsi | 389 ++++++++++++++++++++++++++ display/shima-sde.dtsi | 513 +++++----------------------------- 2 files changed, 463 insertions(+), 439 deletions(-) create mode 100644 display/shima-sde-common.dtsi diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi new file mode 100644 index 000000000000..a3a5861c05e4 --- /dev/null +++ b/display/shima-sde-common.dtsi @@ -0,0 +1,389 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + clock-rate = <0 0 0 0 460000000 19200000 460000000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none"; + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + + qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x84000 0x84100>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + qcom,sde-sspp-xin-id = <0 4 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, + <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2880>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x7 0x1>, + <0x8 0x2>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <5900000>; + qcom,sde-max-bw-high-kbps = <13500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + /* creq LUTs */ + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-id = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801 0xC01>; + + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index e7a9fa86ef15..6e5e724c7e6e 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -1,274 +1,7 @@ +#include "shima-sde-common.dtsi" #include &soc { - mdss_mdp: qcom,mdss_mdp@ae00000 { - compatible = "qcom,sde-kms"; - reg = <0xae00000 0x84208>, - <0xaeb0000 0x2008>, - <0xaeac000 0x214>, - <0xaf50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "swfuse_phys"; - clocks = - <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 0 0 460000000 19200000 460000000>; - clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - vdd-supply = <&disp_cc_mdss_core_gdsc>; - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; - - qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "primary", "none", - "none"; - qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000 0x57000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-top-size = <0x1c>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-dest-scaler-size = <0x800>; - - qcom,sde-wb-off = <0x66000>; - qcom,sde-wb-size = <0x2c8>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-intf-off = <0x6b000 0x6b800 - 0x6c000 0x6c800>; - qcom,sde-intf-size = <0x2b8>; - qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; - qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; - - qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; - qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; - - qcom,sde-merge-3d-off = <0x84000 0x84100>; - qcom,sde-merge-3d-size = <0x100>; - - qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; - - qcom,sde-cdm-off = <0x7a200>; - qcom,sde-cdm-size = <0x224>; - - qcom,sde-dsc-off = <0x81000 0x81400>; - qcom,sde-dsc-size = <0x140>; - qcom,sde-dsc-pair-mask = <2 1>; - - qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 - 0x30e0>; - qcom,sde-dither-version = <0x00010000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-sspp-type = "vig", "vig", - "dma", "dma", "dma"; - qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; - qcom,sde-sspp-src-size = <0x1f8>; - qcom,sde-sspp-xin-id = <0 4 1 5 9>; - qcom,sde-sspp-excl-rect = <1 1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <2 1 4 3>; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0>; - - qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, - <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; - qcom,sde-sspp-clk-status = - <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, - <0x2b8 12>, <0x2c8 12>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <2880>; - qcom,sde-vig-sspp-linewidth = <4096>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-wb-linewidth = <4096>; - qcom,sde-mixer-blendstages = <0x9>; - qcom,sde-highest-bank-bit = <0x7 0x1>, - <0x8 0x2>; - qcom,sde-ubwc-version = <0x400>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1>; - qcom,sde-macrotile-mode = <0x1>; - qcom,sde-smart-panel-align-mode = <0xc>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; - qcom,sde-has-idle-pc; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <5900000>; - qcom,sde-max-bw-high-kbps = <13500000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <1600000>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-ltm-version = <0x00010000>; - /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x1040>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - - /* macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff - 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - - qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; - - /* creq LUTs */ - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; - qcom,sde-qos-refresh-rates = <60 120>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-id = <0>; - qcom,sde-reg-dma-version = <0x00010002>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-secure-sid-mask = <0x801 0xC01>; - - /* data and reg bus scale settings */ - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 74000>, - <0 148000>, - <0 265000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040002>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - ext_disp: qcom,msm-ext-disp { status = "disabled"; compatible = "qcom,msm-ext-disp"; @@ -453,181 +186,83 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; +}; - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <800>; - reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + vdd-supply = <&disp_cc_mdss_core_gdsc>; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-1"; - cell-index = <1>; - frame-threshold-time-us = <800>; - reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <5 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-1"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96400 0x800>, - <0xae96900 0x27c>, - <0xaf03000 0x8>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; }; }; }; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; From 7a5ad0fbd5677ebece56ebd437aeea2a80443ba2 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 2 Sep 2020 12:33:59 +0530 Subject: [PATCH 196/362] ARM: dts: msm: enable SDE RSC driver on shima Enable sde rscc v4 driver on shima target Change-Id: Ib0d930dfc6837f53edbff41970035ec0165586ae --- display/shima-sde-display.dtsi | 2 +- display/shima-sde.dtsi | 16 ---------------- 2 files changed, 1 insertion(+), 17 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index a4d84a3f6033..06a63902cd22 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -138,7 +138,7 @@ &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi - &sde_dsi1>; + &sde_dsi1 &sde_rscc>; }; &dsi_r66451_amoled_video { diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 6e5e724c7e6e..6cbbb353d36f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -147,7 +147,6 @@ sde_rscc: qcom,sde_rscc { cell-index = <0>; compatible = "qcom,sde-rsc"; - status = "disabled"; reg = <0xaf20000 0x4d68>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; @@ -200,7 +199,6 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; - vdd-supply = <&disp_cc_mdss_core_gdsc>; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, @@ -213,20 +211,6 @@ qcom,sde-dspp-ltm-version = <0x00010000>; /* offsets are based off dspp 0 and dspp 1 */ qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi0 { From b70153641764df9d154e44bc89b063f3c33bd1d5 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 4 Sep 2020 09:41:30 +0530 Subject: [PATCH 197/362] ARM: dts: msm: add trusted vm dtsi files for shima target Add trusted vm dt files for shima target. Common device tree bindings for shima are inherited in these files. Change-Id: I67e2191f964e5193c84652c8a2064ff64aadcdff --- display/trustedvm-shima-sde.dtsi | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 display/trustedvm-shima-sde.dtsi diff --git a/display/trustedvm-shima-sde.dtsi b/display/trustedvm-shima-sde.dtsi new file mode 100644 index 000000000000..86166909fcd5 --- /dev/null +++ b/display/trustedvm-shima-sde.dtsi @@ -0,0 +1,68 @@ +#include "shima-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + + qcom,sde-hw-version = <0x60070000>; + clocks = + <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + qcom,sde-trusted-vm-env; + qcom,vram-size = <0x200000>; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From b13234ddd237950bcb8e70dcb877e5e365d232bb Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Wed, 2 Sep 2020 15:07:40 +0530 Subject: [PATCH 198/362] ARM: dts: msm: Enable display port for shima Enable display port feature for shima target. Change-Id: Id62f46940f138ed97e7e0c9950c73b7964a7c763 --- display/shima-sde-display.dtsi | 2 +- display/shima-sde.dtsi | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 06a63902cd22..21dfac76d5ae 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -137,7 +137,7 @@ }; &mdss_mdp { - connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 6cbbb353d36f..7b2994593d5f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -3,7 +3,6 @@ &soc { ext_disp: qcom,msm-ext-disp { - status = "disabled"; compatible = "qcom,msm-ext-disp"; ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { @@ -12,12 +11,10 @@ }; qcom_msmhdcp: qcom,msm_hdcp { - status = "disabled"; compatible = "qcom,msm-hdcp"; }; sde_dp: qcom,dp_display@ae90000 { - status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; From 70d0e20030b747aa7166ee498f8d0f650bc1a3e1 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Wed, 9 Sep 2020 15:37:10 +0530 Subject: [PATCH 199/362] ARM: dts: msm: update default mdp clock value in holi This change updates default mdp clock to 448 MHZ for 120fps usecase to prevent underruns during continuous splash handoff. Change-Id: Ie0a4505699e8bb91b5f4d7ffa38a1257017eaa95 --- display/holi-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index 1fe879f007be..ca2ba7d915f7 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -10,7 +10,7 @@ "vbif_phys", "sid_phys"; - clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; + clock-rate = <0 0 0 0 0 448000000 19200000 448000000 200000000>; clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 560000000>; From 9913019e232c31ad588d4273125bbf44c23b9f24 Mon Sep 17 00:00:00 2001 From: Vara Reddy Date: Wed, 9 Sep 2020 12:28:01 -0700 Subject: [PATCH 200/362] dt-bindings: update dynamic clock switch feature nodes Change adds dynamic clock switch feature enabling node "qcom,dsi-dyn-clk-enable", list of all dynamic clocks supported "qcom,dsi-dyn-clk-list" and node subtype with"qcom,dsi-dyn-clk-type". Change-Id: I1b6bc19e502e2d7019da5f569a830c3e05ac82a3 --- bindings/mdss-dsi-panel.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 69bdd72ee00e..01eb6805fb26 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -174,6 +174,22 @@ Optional properties: - qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh rate is not specified, then the frame rate of the panel in qcom,mdss-dsi-panel-framerate is used. +- qcom,dsi-dyn-clk-enable: Boolean to indicate dsi dynamic clock switch feature + is supported. +- qcom,dsi-dyn-clk-list: An u32 array which lists all the supported dsi bit clock + frequencies in Hz for the given panel. +- qcom,dsi-dyn-clk-type: A string that specifies the sub-type for the dynamic + clk feature. If dyn clk type is not specified, default + value "legacy" is used. + "legacy" = FPS is not maintained after dynamic clock switch. + "constant-fps-adjust-hfp" = FPS is maintained even after + dynamic clock switch by changing panel horizontal front + porch values. + "constant-fps-adjust-vfp" = FPS is maintained even after + dynamic clock switch by changing panel vertical front + porch values. + This dyn-clk-type entry is an optional binding which is + contingent on the enabling of dynamic clock switch. - qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight control for this panel. "bl_ctrl_pwm" = Backlight controlled by PWM gpio. From 3d924b9be263837747863354d1e731932a0f7ede Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Sun, 13 Sep 2020 13:42:46 +0530 Subject: [PATCH 201/362] Revert "ARM: dts: msm: Enable display port for shima" This reverts commit ce54f9e8d2210def9885967b5e28a3fb5d31fcd6. Change-Id: Id5c53f8690eda707f948814291a9fcaa7626d42a --- display/shima-sde-display.dtsi | 2 +- display/shima-sde.dtsi | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 21dfac76d5ae..06a63902cd22 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -137,7 +137,7 @@ }; &mdss_mdp { - connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 7b2994593d5f..6cbbb353d36f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -3,6 +3,7 @@ &soc { ext_disp: qcom,msm-ext-disp { + status = "disabled"; compatible = "qcom,msm-ext-disp"; ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { @@ -11,10 +12,12 @@ }; qcom_msmhdcp: qcom,msm_hdcp { + status = "disabled"; compatible = "qcom,msm-hdcp"; }; sde_dp: qcom,dp_display@ae90000 { + status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; From 796d129dd282a7a8fbc060baebf0119e55c57aa5 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Sun, 13 Sep 2020 13:43:15 +0530 Subject: [PATCH 202/362] Revert "ARM: dts: msm: add trusted vm dtsi files for shima target" This reverts commit 97bb160aa76384bc9508d5f900c43accc8ab7dff. Change-Id: I8b209d7e2d190b329c34914baef32c621c49eff7 --- display/trustedvm-shima-sde.dtsi | 68 -------------------------------- 1 file changed, 68 deletions(-) delete mode 100644 display/trustedvm-shima-sde.dtsi diff --git a/display/trustedvm-shima-sde.dtsi b/display/trustedvm-shima-sde.dtsi deleted file mode 100644 index 86166909fcd5..000000000000 --- a/display/trustedvm-shima-sde.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -#include "shima-sde-common.dtsi" -#include - -&soc { - /* dummy display clock provider */ - clock_cpucc: qcom,cpucc { - compatible = "qcom,dummycc"; - clock-output-names = "cpucc_clocks"; - #clock-cells = <1>; - }; -}; - -&mdss_mdp { - reg = <0xae00000 0x84208>, - <0xaeb0000 0x2008>, - <0xaeac000 0x214>, - <0xaf50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "swfuse_phys"; - - qcom,sde-hw-version = <0x60070000>; - clocks = - <&clock_cpucc GCC_DISP_AHB_CLK>, - <&clock_cpucc GCC_DISP_HF_AXI_CLK>, - <&clock_cpucc GCC_DISP_SF_AXI_CLK>, - <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, - <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, - <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, - <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk"; - qcom,sde-trusted-vm-env; - qcom,vram-size = <0x200000>; -}; - -&mdss_dsi0 { - clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, - <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, - <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; -}; - -&mdss_dsi1 { - clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, - <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, - <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; -}; - - -&mdss_dsi_phy0 { - qcom,dsi-pll-in-trusted-vm; -}; - -&mdss_dsi_phy1 { - qcom,dsi-pll-in-trusted-vm; -}; From 7c268c7edfe68827e1753d913e8aaedca520b3a9 Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Sun, 13 Sep 2020 13:44:01 +0530 Subject: [PATCH 203/362] Revert "ARM: dts: msm: enable SDE RSC driver on shima" This reverts commit 48b82acd61f9f89bf4f1399eb33b7e49654bbb0c. Change-Id: Ie73673f035cb9c7bd1608a280f53566b1067abbf --- display/shima-sde-display.dtsi | 2 +- display/shima-sde.dtsi | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 06a63902cd22..a4d84a3f6033 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -138,7 +138,7 @@ &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi - &sde_dsi1 &sde_rscc>; + &sde_dsi1>; }; &dsi_r66451_amoled_video { diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 6cbbb353d36f..6e5e724c7e6e 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -147,6 +147,7 @@ sde_rscc: qcom,sde_rscc { cell-index = <0>; compatible = "qcom,sde-rsc"; + status = "disabled"; reg = <0xaf20000 0x4d68>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; @@ -199,6 +200,7 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; + vdd-supply = <&disp_cc_mdss_core_gdsc>; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, @@ -211,6 +213,20 @@ qcom,sde-dspp-ltm-version = <0x00010000>; /* offsets are based off dspp 0 and dspp 1 */ qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; &mdss_dsi0 { From c113acbc65cc061135e87bc770ce715aa86ad0dc Mon Sep 17 00:00:00 2001 From: Salendarsingh Gaud Date: Sun, 13 Sep 2020 13:45:40 +0530 Subject: [PATCH 204/362] Revert "ARM: dts: msm: create sde-common device tree for shima target" This reverts commit 684a1e386859f4b92dfc8e504388ada7981da099. Change-Id: Iea8c9d06459b1be77b9b25879cff5d8921bb1f4d --- display/shima-sde-common.dtsi | 389 -------------------------- display/shima-sde.dtsi | 513 +++++++++++++++++++++++++++++----- 2 files changed, 439 insertions(+), 463 deletions(-) delete mode 100644 display/shima-sde-common.dtsi diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi deleted file mode 100644 index a3a5861c05e4..000000000000 --- a/display/shima-sde-common.dtsi +++ /dev/null @@ -1,389 +0,0 @@ -#include - -&soc { - mdss_mdp: qcom,mdss_mdp@ae00000 { - compatible = "qcom,sde-kms"; - reg = <0xae00000 0x84208>, - <0xaeb0000 0x2008>, - <0xaeac000 0x214>, - <0xaf50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "swfuse_phys"; - clock-rate = <0 0 0 0 460000000 19200000 460000000>; - clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; - - qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "primary", "none", - "none"; - qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000 0x57000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-top-size = <0x1c>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-dest-scaler-size = <0x800>; - - qcom,sde-wb-off = <0x66000>; - qcom,sde-wb-size = <0x2c8>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-intf-off = <0x6b000 0x6b800 - 0x6c000 0x6c800>; - qcom,sde-intf-size = <0x2b8>; - qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; - qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; - - qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; - qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; - - qcom,sde-merge-3d-off = <0x84000 0x84100>; - qcom,sde-merge-3d-size = <0x100>; - - qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; - - qcom,sde-cdm-off = <0x7a200>; - qcom,sde-cdm-size = <0x224>; - - qcom,sde-dsc-off = <0x81000 0x81400>; - qcom,sde-dsc-size = <0x140>; - qcom,sde-dsc-pair-mask = <2 1>; - - qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 - 0x30e0>; - qcom,sde-dither-version = <0x00010000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-sspp-type = "vig", "vig", - "dma", "dma", "dma"; - qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; - qcom,sde-sspp-src-size = <0x1f8>; - qcom,sde-sspp-xin-id = <0 4 1 5 9>; - qcom,sde-sspp-excl-rect = <1 1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <2 1 4 3>; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0>; - - qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, - <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; - qcom,sde-sspp-clk-status = - <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, - <0x2b8 12>, <0x2c8 12>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <2880>; - qcom,sde-vig-sspp-linewidth = <4096>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-wb-linewidth = <4096>; - qcom,sde-mixer-blendstages = <0x9>; - qcom,sde-highest-bank-bit = <0x7 0x1>, - <0x8 0x2>; - qcom,sde-ubwc-version = <0x400>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1>; - qcom,sde-macrotile-mode = <0x1>; - qcom,sde-smart-panel-align-mode = <0xc>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <5900000>; - qcom,sde-max-bw-high-kbps = <13500000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <1600000>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <0>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x1040>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - - /* macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff - 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - - qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; - - /* creq LUTs */ - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; - qcom,sde-qos-refresh-rates = <60 120>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-id = <0>; - qcom,sde-reg-dma-version = <0x00010002>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-secure-sid-mask = <0x801 0xC01>; - - - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 74000>, - <0 148000>, - <0 265000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040002>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - }; - - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <800>; - reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-1"; - cell-index = <1>; - frame-threshold-time-us = <800>; - reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <5 0>; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-1"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96400 0x800>, - <0xae96900 0x27c>, - <0xaf03000 0x8>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; -}; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 6e5e724c7e6e..e7a9fa86ef15 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -1,7 +1,274 @@ -#include "shima-sde-common.dtsi" #include &soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 460000000 19200000 460000000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none"; + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + + qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x84000 0x84100>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + qcom,sde-sspp-xin-id = <0 4 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, + <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2880>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x7 0x1>, + <0x8 0x2>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-has-idle-pc; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <5900000>; + qcom,sde-max-bw-high-kbps = <13500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + /* creq LUTs */ + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-id = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801 0xC01>; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + ext_disp: qcom,msm-ext-disp { status = "disabled"; compatible = "qcom,msm-ext-disp"; @@ -186,83 +453,181 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; -}; -&mdss_mdp { - clocks = - <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk"; - vdd-supply = <&disp_cc_mdss_core_gdsc>; + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; - /* data and reg bus scale settings */ - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; - qcom,sde-has-idle-pc; - qcom,sde-dspp-ltm-version = <0x00010000>; - /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; }; }; }; - -&mdss_dsi0 { - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; -}; - -&mdss_dsi1 { - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; -}; - -&mdss_dsi_phy0 { - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; -}; - -&mdss_dsi_phy1 { - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; -}; From 4b5e5240636cb8150973a00a2ec347f34f27c9a8 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Fri, 11 Sep 2020 20:05:04 +0530 Subject: [PATCH 205/362] ARM: dts: msm: update display ramdump node in holi Since the address & size cells for display ramdump's parent node(soc) is one, address & size should be defined in the 32-bit format instead of 64-bit. This change modifies them accordingly. Change-Id: I55b206126c2699cc3210a18295d5fa4dc22f145a --- display/holi-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index fac819edfda5..743eeb11844e 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -3,7 +3,7 @@ &soc { disp_rdump_memory: disp_rdump_region@85200000 { - reg = <0x0 0x85200000 0x0 0x00c00000>; + reg = <0x85200000 0x00c00000>; label = "disp_rdump_region"; }; From d0bd3792df6e6bec4dc3fee51c9c950143f9850a Mon Sep 17 00:00:00 2001 From: David Collins Date: Mon, 14 Sep 2020 11:58:33 -0700 Subject: [PATCH 206/362] ARM: dts: msm: update display_panel_avdd regulator type for Lahaina Change the compatible string for the display_panel_avdd regulator from "regulator-fixed" to "qti-regulator-fixed". This ensures that proxy-consumer properties of this regulator are properly handled at runtime. Change-Id: I5f58a0b72968df47503544950c55a785d1681d00 --- display/lahaina-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 60e9663d7420..3e3a389510da 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -18,7 +18,7 @@ &soc { display_panel_avdd: display_gpio_regulator@1 { - compatible = "regulator-fixed"; + compatible = "qti-regulator-fixed"; regulator-name = "display_panel_avdd"; regulator-min-microvolt = <5500000>; regulator-max-microvolt = <5500000>; From 22421eae876ff4144349ea4cc9253398fbb0c525 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Thu, 10 Sep 2020 13:26:24 +0800 Subject: [PATCH 207/362] ARM: dts: msm: add 90hz video and cmd mode panel for holi Add 90hz video and cmd mode for r66451 panel. Change-Id: Ie80d6118e431687c7f10341c0d44a6120b349742 --- ...si-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi | 247 ++++++++++++++++++ ...-panel-r66451-dsc-fhd-plus-90hz-video.dtsi | 83 ++++++ display/holi-sde-display-common.dtsi | 37 +++ display/holi-sde-display-qrd.dtsi | 20 ++ display/holi-sde-display.dtsi | 19 ++ 5 files changed, 406 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi new file mode 100644 index 000000000000..3fedde23bf84 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi @@ -0,0 +1,247 @@ +&mdss_mdp { + dsi_r66451_amoled_90hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_90hz_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi new file mode 100644 index 000000000000..33adf7a3db27 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi @@ -0,0 +1,83 @@ +&mdss_mdp { + dsi_r66451_amoled_90hz_video: qcom,mdss_dsi_r66451_fhd_plus_90hz_video { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 285cda97497c..9d5201d29779 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -3,6 +3,8 @@ #include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi" #include &soc { @@ -155,3 +157,38 @@ }; }; }; + +&dsi_r66451_amoled_90hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0B>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index de64faa435fc..fcd4ddf34555 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -20,6 +20,26 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 026318b53148..a2da472f274f 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -80,3 +80,22 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_90hz_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From f15160e4f3c88fe54d1fcfa5d4072862b6d296ad Mon Sep 17 00:00:00 2001 From: Raviteja Date: Wed, 16 Sep 2020 02:40:39 +0530 Subject: [PATCH 208/362] ARM: dts: msm: update display ramdump node in Lahaina Since the address & size cells for display ramdump's parent node(soc) is one, address & size should be defined in the 32-bit format instead of 64-bit. This change modifies them accordingly. Change-Id: Ib96fa68c494be73fd45049de530aeecd982fb8ef --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 870528fae30e..41286ac19ff8 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -3,7 +3,7 @@ &soc { disp_rdump_memory: disp_rdump_region@e1000000 { - reg = <0x0 0xe1000000 0x0 0x00800000>; + reg = <0xe1000000 0x00800000>; label = "disp_rdump_region"; }; From bac799a5f9eb67e8c41a5d21ac8a86092bc4ba34 Mon Sep 17 00:00:00 2001 From: Raviteja Date: Wed, 16 Sep 2020 02:25:16 +0530 Subject: [PATCH 209/362] ARM: dts: msm: add pm_qos cpu mask for silver cores on Shima target This change adds pm_qos cpu mask for all silver/performance cores which is applied for higher frame rates. Change-Id: Ie6f048af124d8738385e7bbc55f42b90621cff4f --- display/shima-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi index a3a5861c05e4..a03b19ed549a 100644 --- a/display/shima-sde-common.dtsi +++ b/display/shima-sde-common.dtsi @@ -174,6 +174,7 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From 3bdcf5bb635d4a97ed75f46d9dbefd92df099a06 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 17 Sep 2020 10:33:38 +0530 Subject: [PATCH 210/362] ARM: dts: msm: define ramdump buffer reservation node This change defines ramdump buffer reservation node for shima target. Change-Id: Ib43f4690621524b8d55829e056b4cfdde79ef926 --- display/shima-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 7b2994593d5f..d6f9872d200f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -2,6 +2,11 @@ #include &soc { + disp_rdump_memory: disp_rdump_region@e1000000 { + reg = <0xe1000000 0x02300000>; + label = "disp_rdump_region"; + }; + ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; From 0a6be713964fe3b88aa82b3f776bf664693fe30b Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 17 Sep 2020 13:09:56 +0530 Subject: [PATCH 211/362] ARM: dts: msm: define sid_phys for trusted vm in shima target Proper sid for trusted vm is selected via MDP_SID registers. Define sid_phys for trusted vm to support this. Change-Id: Ib2c924184adcf1f30a38f66c4ce6d42cdd79bd5f --- display/trustedvm-shima-sde.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-shima-sde.dtsi b/display/trustedvm-shima-sde.dtsi index 86166909fcd5..2f9f45c350e2 100644 --- a/display/trustedvm-shima-sde.dtsi +++ b/display/trustedvm-shima-sde.dtsi @@ -14,12 +14,15 @@ reg = <0xae00000 0x84208>, <0xaeb0000 0x2008>, <0xaeac000 0x214>, - <0xaf50000 0x038>; + <0xaf50000 0x038>, + <0xae8f000 0x02c>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "swfuse_phys"; + "swfuse_phys", + "sid_phys"; + qcom,sde-vm-exclude-reg-names = "sid_phys"; qcom,sde-hw-version = <0x60070000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, From 814697736b9cd934909978f2fce37f1ba3047006 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 18 Sep 2020 09:34:51 +0530 Subject: [PATCH 212/362] ARM: dts: msm: add trusted vm display dtsi files for shima target Add trusted VM display device tree files for shima. Change-Id: I99cd70f232f941ecf084d225e4817b91b08a0253 --- display/trustedvm-shima-sde-display.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 display/trustedvm-shima-sde-display.dtsi diff --git a/display/trustedvm-shima-sde-display.dtsi b/display/trustedvm-shima-sde-display.dtsi new file mode 100644 index 000000000000..dc497bf18f44 --- /dev/null +++ b/display/trustedvm-shima-sde-display.dtsi @@ -0,0 +1,35 @@ +#include "shima-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_MUX_1_CLK>, + <&clock_cpucc PCLK_MUX_1_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_1_CLK>, + <&clock_cpucc BYTECLK_SRC_1_CLK>, + <&clock_cpucc PCLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + qcom,panel-te-source = <0>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; + +&mdss_mdp { + connectors = <&sde_dsi>; +}; From 780df937c621d3ee3f6853456d799ec77ea8a10f Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 18 Sep 2020 14:45:26 +0530 Subject: [PATCH 213/362] ARM: dts: msm: Add 60Hz cmd mode panel as default panel for trusted vm This change adds 60Hz command mode panel as the default panel for trusted vm in shima target. Change-Id: Ie66ea72eec7fcc8d966e4fd7846040fb8e990a51 --- display/trustedvm-shima-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/trustedvm-shima-sde-display.dtsi b/display/trustedvm-shima-sde-display.dtsi index dc497bf18f44..f70e3fc880cf 100644 --- a/display/trustedvm-shima-sde-display.dtsi +++ b/display/trustedvm-shima-sde-display.dtsi @@ -27,7 +27,7 @@ "shadow_byte_clk1", "shadow_pixel_clk1"; qcom,panel-te-source = <0>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; }; &mdss_mdp { From af2743c4a7d5984fac51c1b4ca55d43d453a6b27 Mon Sep 17 00:00:00 2001 From: David Collins Date: Mon, 14 Sep 2020 11:58:33 -0700 Subject: [PATCH 214/362] ARM: dts: msm: update display_panel_avdd regulator type for Lahaina Change the compatible string for the display_panel_avdd regulator from "regulator-fixed" to "qti-regulator-fixed". This ensures that proxy-consumer properties of this regulator are properly handled at runtime. Change-Id: I5f58a0b72968df47503544950c55a785d1681d00 --- display/lahaina-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 60e9663d7420..3e3a389510da 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -18,7 +18,7 @@ &soc { display_panel_avdd: display_gpio_regulator@1 { - compatible = "regulator-fixed"; + compatible = "qti-regulator-fixed"; regulator-name = "display_panel_avdd"; regulator-min-microvolt = <5500000>; regulator-max-microvolt = <5500000>; From d39c8a385ddcbb4beea5175ae925e55f2ace2433 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sat, 12 Sep 2020 12:47:53 +0530 Subject: [PATCH 215/362] ARM: dts: msm: Enable dynamic clock switch on shima Enable Dynamic DSI clock switch feature for video and command mode panel on shima target. Change-Id: I858589096c938a8dbda857509ac2a3274dda283f --- display/shima-sde-display-common.dtsi | 11 ++++++++++- display/shima-sde.dtsi | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 17b6881b10e2..9a03e141c726 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -77,7 +77,13 @@ qcom,mdss-dsi-min-refresh-rate = <48>; qcom,mdss-dsi-max-refresh-rate = <120>; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <846374400 842847840 844611120>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 @@ -102,6 +108,9 @@ &dsi_r66451_amoled_60hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <327096550 325733640 328459448>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index d6f9872d200f..9f2455f8871a 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -245,6 +245,7 @@ vdda-0p9-supply = <&L10C>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; &mdss_dsi_phy1 { From 96ef9f4bf561a443a211e845060de999bcc37934 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Fri, 18 Sep 2020 14:06:45 +0530 Subject: [PATCH 216/362] ARM: dts: msm: Add LCD Video mode support on holi Add Qsync FHD Video mode support on holi lcd cdp. Change-Id: If4f44ab659dda1c9a755fe63c6b2f9aa849291ef --- display/holi-sde-display-cdp.dtsi | 8 ++ display/holi-sde-display-common.dtsi | 107 +++++++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 045a79255a76..eb0cf7a029f3 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -25,6 +25,14 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_sharp_qsync_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 9d5201d29779..73fbb4cc0efc 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -5,6 +5,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-sharp-qsync-fhd-video.dtsi" #include &soc { @@ -52,6 +53,40 @@ }; }; + dsi_panel_pwr_supply_labibb: dsi_panel_pwr_supply_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; @@ -192,3 +227,75 @@ }; }; }; + +&dsi_sharp_qsync_fhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 + 07 07 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 05 be 00 10 00 10 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + }; + }; +}; From a91a217941055cc1b8f244fd91bfdffeb2b36d07 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 17 Sep 2020 10:33:38 +0530 Subject: [PATCH 217/362] ARM: dts: msm: define ramdump buffer reservation node This change defines ramdump buffer reservation node for shima target. Change-Id: Ib43f4690621524b8d55829e056b4cfdde79ef926 --- display/shima-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 7b2994593d5f..d6f9872d200f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -2,6 +2,11 @@ #include &soc { + disp_rdump_memory: disp_rdump_region@e1000000 { + reg = <0xe1000000 0x02300000>; + label = "disp_rdump_region"; + }; + ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; From 0249688a9ede6bf92aa9277e07d2989652497c38 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Tue, 22 Sep 2020 11:49:52 +0530 Subject: [PATCH 218/362] ARM: dts: msm: define max trusted vm displays for shima Max trusted vm displays dt entry is used by both the vms to validate the TUI start request. Define this value for shima target. Change-Id: Ieef6e9cf184a58cebfcb1b4577c28215c6d28305 --- display/shima-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi index a03b19ed549a..8ed5332e3db4 100644 --- a/display/shima-sde-common.dtsi +++ b/display/shima-sde-common.dtsi @@ -140,6 +140,7 @@ qcom,sde-min-dram-ib-kbps = <1600000>; qcom,sde-dram-channels = <2>; qcom,sde-num-nrt-paths = <0>; + qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-uidle-off = <0x80000>; qcom,sde-uidle-size = <0x70>; From 3bebcb23d9584ff6a0187bebbb596be941ea61f6 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Mon, 21 Sep 2020 13:33:47 +0530 Subject: [PATCH 219/362] ARM: dts: msm: remove regulator supply nodes in offline rotator SDE offline rotator uses mdss_mdp PM domain for regulator power supply. This change removes redundant regulator supply entries. Change-Id: Ia9e365af362b4a76c44faae621c2dfd972ad189b --- display/holi-sde.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index 743eeb11844e..fa0b5a57eb8b 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -33,8 +33,6 @@ #list-cells = <1>; qcom,mdss-rot-mode = <1>; - rot-vdd-supply = <&mdss_core_gdsc>; - qcom,supply-names = "rot-vdd"; clocks = <&gcc GCC_DISP_AHB_CLK>, From f83e3d72f30032899ef9ae9a6dc9d69468e0b1e7 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Mon, 14 Sep 2020 18:03:09 +0800 Subject: [PATCH 220/362] ARM: dts: msm: increase VFP value for video mode panel Low vbp+vfp may lead to perf issues in some cases, so increase vfp for video mode panel. Change-Id: I7f0daaf489fbf1320d0091b3094063daf9702ff0 --- display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 2 +- display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 2 +- display/lahaina-sde-display-common.dtsi | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 182038f97fab..995e4df38122 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -36,7 +36,7 @@ qcom,mdss-dsi-h-pulse-width = <1>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-front-porch = <75>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-on-command = [ diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi index ecac0d4bfc65..d7cd192a4fbd 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi @@ -37,7 +37,7 @@ qcom,mdss-dsi-h-pulse-width = <12>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <10>; - qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-front-porch = <20>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-h-left-border = <0>; qcom,mdss-dsi-panel-framerate = <60>; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 923309e61b86..5e4afa5c83f2 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -151,7 +151,7 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 05 06 02 04 00 12 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; @@ -168,8 +168,8 @@ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 - 08 05 02 04 00 17 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 16 07 + 07 08 02 04 00 19 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From bf2903279af4513f232db1354272474671c8e61d Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Fri, 11 Sep 2020 14:25:46 +0800 Subject: [PATCH 221/362] ARM: dts: msm: fix nt35597 panel video mode ESD check failure Change the VBP and VFP values to fix ESD check failure. Change-Id: I1083c50557fe1e7eb21785691bddec077962443f --- display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi index 417d22e3c8b5..63e65adbcce9 100644 --- a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi +++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi @@ -39,8 +39,8 @@ qcom,mdss-dsi-h-back-porch = <32>; qcom,mdss-dsi-h-pulse-width = <16>; qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <17>; - qcom,mdss-dsi-v-front-porch = <23>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <33>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-on-command = [ From d1107cc7f835c6244e7633339b21b25c9008ea60 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 20 Aug 2020 12:43:24 +0530 Subject: [PATCH 222/362] ARM: dts: msm: enable ulps for visionox panel on Holi This change enables ulps support for visionox panel on Holi target. Change-Id: Ib2258c765fbc0b89169a322274ae16ef785b61aa --- display/holi-sde-display.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index a2da472f274f..e7470d8ab77d 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -53,6 +53,7 @@ }; &dsi_rm69299_visionox_amoled_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From a4d98ea5b7bfe7643468ecb3a7172acfdbdd0d2b Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Mon, 21 Sep 2020 18:51:29 +0800 Subject: [PATCH 223/362] ARM: dts: msm: add r66451 video mode 60hz panel support Adds visionox r66451 amoled video mode 60Hz dsi panel for holi target. Change-Id: I718f004d969a8a3f2c8abb239f789f878b62ce85 --- ...dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi | 2 +- ...i-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 2 +- display/holi-sde-display-common.dtsi | 14 ++++++++++++++ display/holi-sde-display-qrd.dtsi | 18 ++++++++++++++---- display/holi-sde-display.dtsi | 5 +++++ 5 files changed, 35 insertions(+), 6 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi index 8bf39c27e5f5..7674b87a769f 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_r66451_amoled_60hz_cmd: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_cmd { qcom,mdss-dsi-panel-name = - "r66451 amoled cmd mode dsi visionox 60HZ panel with DSC"; + "r66451 amoled cmd mode dsi visionox panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,mdss-dsi-virtual-channel-id = <0>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi index 50e11b87af55..310f28f3ee28 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_r66451_amoled_60hz_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_video { qcom,mdss-dsi-panel-name = - "r66451 amoled video mode dsi visionox 60Hz panel with DSC"; + "r66451 amoled video mode dsi visionox panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 73fbb4cc0efc..78050aea9671 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -5,6 +5,8 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-sharp-qsync-fhd-video.dtsi" #include @@ -228,6 +230,18 @@ }; }; +&dsi_r66451_amoled_60hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_qsync_fhd_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-t-clk-post = <0x0c>; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index fcd4ddf34555..b079622c2f64 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -4,7 +4,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; @@ -14,7 +14,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; @@ -24,7 +24,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; @@ -34,12 +34,22 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index a2da472f274f..94670b7bc95e 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -79,6 +79,11 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <60>; + qcom,mdss-dsi-max-refresh-rate = <120>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; }; &dsi_r66451_amoled_90hz_cmd { From 57d0b87ccef801b68c3d8c874afc61ef335191f9 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 25 Sep 2020 13:13:48 +0530 Subject: [PATCH 224/362] ARM: dts: msm: Change VDDIO and default panel on shima idp Update VDDIO panel power supply to 1.82V and select 60Hz command mode panel as default on shima IDP platform. Change-Id: I7620cddbe0274127dfa5df78baebd1a4bbbb8037 --- display/shima-sde-display-common.dtsi | 4 ++-- display/shima-sde-display-idp.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 9a03e141c726..69fa6501c5f4 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -13,8 +13,8 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1920000>; - qcom,supply-max-voltage = <1920000>; + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; qcom,supply-enable-load = <60700>; qcom,supply-disable-load = <80>; qcom,supply-post-on-sleep = <20>; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 3cb99c69fa0b..151582b85217 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -49,5 +49,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; }; From d4c6dfba5b8f89d20f755b24a98bff00a9fe2389 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 23 Sep 2020 18:54:04 +0530 Subject: [PATCH 225/362] ARM: dts: msm: enable DSI PHY power off when idle on Holi This change adds the feature which disables the DSI PHY hardware while going to idle screen on Holi target. Change-Id: I415bec33f2c7b42d99d783f678ff38948e0ab2a7 --- display/holi-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index fa0b5a57eb8b..c6d3d332a98a 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -140,6 +140,7 @@ &mdss_dsi_phy0 { vdda-0p9-supply = <&S5A_LEVEL>; + qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; memory-region = <&dfps_data_memory>; From ac1bfd70388211807a91d6449901c6b0456fb216 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Wed, 23 Sep 2020 20:39:56 +0530 Subject: [PATCH 226/362] ARM: dts: msm: Add LCD Command mode support on holi Add Qsync FHD Command mode support on holi lcd cdp. Change-Id: I1c79f098a8eb00132faf917287c1b0158a77a878 --- display/holi-sde-display-cdp.dtsi | 11 +- display/holi-sde-display-common.dtsi | 214 +++++++++++++++++++++++++++ 2 files changed, 224 insertions(+), 1 deletion(-) diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index eb0cf7a029f3..501b2a615690 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -29,7 +29,16 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sharp_qsync_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 78050aea9671..4ffa9be16ad1 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -8,6 +8,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-sharp-qsync-fhd-video.dtsi" +#include "dsi-panel-sharp-qsync-fhd-cmd.dtsi" #include &soc { @@ -313,3 +314,216 @@ }; }; }; + +&dsi_sharp_qsync_fhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 1d 1d 03 + 03 02 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 + 05 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 00 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1e 1e 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 03 + 39 01 00 00 00 00 02 17 70 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + }; + }; +}; From fc61f751d5a4d5ad633a747c3f710efcfe08cdf2 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 24 Sep 2020 09:50:00 +0530 Subject: [PATCH 227/362] ARM: dts: msm: Add 144 fps support on shima target Add 144 fps panel display support on shima target. Change-Id: Ic70a4aec92fabb6c284dc5f36783cba9f4d04751 --- display/shima-sde-display-common.dtsi | 13 +++++++++++++ display/shima-sde-display-idp.dtsi | 11 +++++++++++ 2 files changed, 24 insertions(+) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 9a03e141c726..d601cb6cb167 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -2,6 +2,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -121,6 +122,18 @@ }; }; +&dsi_r66451_amoled_144hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 3cb99c69fa0b..9b5ef968a80a 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -42,6 +42,17 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From a76bfd958c4324d44d6ac376adeb7a8bfda67d6f Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Mon, 28 Sep 2020 10:51:34 +0530 Subject: [PATCH 228/362] ARM: dts: msm: Enable ESD for 144 fps panel on shima target Enabling ESD for 144fps panel on shima target. Change-Id: I58e04b573125d058700e75c580e94b5acacfd270 --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index c13225ec0af7..190d87b4dda2 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -113,3 +113,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_144hz_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 988dd0695cd68a1c316ffa04a2a4d8e55415fac0 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Fri, 18 Sep 2020 13:35:04 +0800 Subject: [PATCH 229/362] ARM: dts: msm: update vddio for r66451 panel Panel will dead sometimes because of power consumption high on r66451 panel, but the current max vddio can't reach, so updata max vddio for r66451 panel for holi qrd. Change-Id: I7c32c2fea7dedbeb5264c06a1af1410fbfe740fe --- display/holi-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index b079622c2f64..4d4feddfc61c 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ #include "holi-sde-display.dtsi" +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; + }; +}; + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 96fb974760172b0688d12f872bd103e70487916f Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Mon, 28 Sep 2020 13:24:40 +0800 Subject: [PATCH 230/362] ARM: dts: msm: update r66451 video panel phy-timing for holi update r66451 video panel phy-timing for holi target. Change-Id: Iaae6c5eeee6455143c0155a57547437ecf269d54 --- display/holi-sde-display-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 4ffa9be16ad1..83a1a9196bb9 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -188,8 +188,8 @@ qcom,mdss-dsi-t-clk-pre = <0x27>; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00]; + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 23 22 07 + 07 08 02 04 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; From 8044f4fdef3075a240e578ee31e311e51aeb1ac3 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Fri, 7 Aug 2020 13:49:25 +0800 Subject: [PATCH 231/362] ARM: dts: msm: add ext bridge 1080p config for hdk8350 Add external bridge 1080p panel timing configure. Change-Id: Ib6a7171f9983c2eeb858f0783cc3ba0307dd75af --- display/lahaina-sde-display-common.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 5e4afa5c83f2..c23cc4f3a018 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -746,3 +746,15 @@ }; }; }; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 00 1a 0c]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; From 56da5eab18da64ca568e4fe970a3f35d66763c40 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Tue, 29 Sep 2020 14:32:52 +0530 Subject: [PATCH 232/362] ARM: dts: msm: Enable POMS feature for qsync panel on holi This change enables POMS feature on sharp qsync fhd video mode panel on holi. Change-Id: I843e2bc9908fa147798d1afa05b4ab87d51937f8 --- display/dsi-panel-sharp-qsync-fhd-video.dtsi | 1 + display/holi-sde-display-common.dtsi | 123 +++++++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/display/dsi-panel-sharp-qsync-fhd-video.dtsi b/display/dsi-panel-sharp-qsync-fhd-video.dtsi index 61f6078c69cd..185f32603582 100644 --- a/display/dsi-panel-sharp-qsync-fhd-video.dtsi +++ b/display/dsi-panel-sharp-qsync-fhd-video.dtsi @@ -12,6 +12,7 @@ qcom,mdss-dsi-bpp = <24>; qcom,mdss-dsi-border-color = <0>; qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; qcom,mdss-dsi-bllp-eof-power-mode; qcom,mdss-dsi-lane-0-state; qcom,mdss-dsi-lane-1-state; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 4ffa9be16ad1..bb0c67aed6d3 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -249,8 +249,16 @@ qcom,mdss-dsi-t-clk-pre = <0x2c>; qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-panel-mode-switch; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; qcom,mdss-dsi-display-timings { timing@0 { + qcom,mdss-dsi-video-mode; qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 07 07 02 04 00]; @@ -311,6 +319,121 @@ 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29 ]; + qcom,cmd-to-video-mode-post-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 05 be 00 10 00 10 + ]; + qcom,cmd-to-video-mode-post-switch-commands-state = + "dsi_lp_mode"; + }; + + timing@1 { + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 1d 1d 03 + 03 02 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,video-to-cmd-mode-post-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 bb 10 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 14 00 + 39 00 00 00 00 00 02 15 10 + 39 00 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + ]; + qcom,video-to-cmd-mode-post-switch-commands-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; }; }; }; From 87555af2e9a5dfe816c36993138fac57c11a3804 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 29 Sep 2020 10:04:33 -0700 Subject: [PATCH 233/362] ARM: dts: msm: update init sequence for video mode for sharp qsync panel Change updates the init sequence for the video timing nodes to allow POMS switch to happen successfully even when we turn the panel on in video mode. Change-Id: I2088add09a607f53b1cca82a8f2b9baa6411c120 --- display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi index f8b7496b94cc..c0cba71a1e74 100644 --- a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi +++ b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi @@ -198,7 +198,7 @@ 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 05 be 00 10 00 10 @@ -210,6 +210,12 @@ 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 @@ -640,7 +646,7 @@ 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 05 be 00 10 00 10 @@ -652,6 +658,12 @@ 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 From 5a68bedad52895c138dd36a2336e5d5c39daa216 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 30 Sep 2020 10:29:30 +0530 Subject: [PATCH 234/362] ARM: dts: msm: Enable ULPS feature on Shima Enable ULPS feature for 60Hz and 120Hz command mode panel on shima platform. Change-Id: If9465cd11508d0da4a755fff3cf2358cea0ecc3b --- display/shima-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 190d87b4dda2..d1d9826fe587 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -97,6 +97,7 @@ }; &dsi_r66451_amoled_60hz_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -106,6 +107,7 @@ }; &dsi_r66451_amoled_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From 8b0fdfff8e85f710af4c58c80bb071af47484beb Mon Sep 17 00:00:00 2001 From: Raviteja Tamatam Date: Wed, 30 Sep 2020 17:50:19 +0530 Subject: [PATCH 235/362] bindings: Documentation: add property to specify qsync min fps list Add documentation for the property to specify list of fps that indicates the qsync min fps corresponding to the mode in the dfps list with same index. Change-Id: I1f0c75c7b473f7c5328525e777e13a1a3d916773 --- bindings/mdss-dsi-panel.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 01eb6805fb26..086fb76f0c73 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -170,6 +170,11 @@ Optional properties: "dfps_immediate_porch_mode_vfp" = FPS change request is implemented immediately by changing panel vertical front porch values. +- qcom,dsi-supported-dfps-list: List containing all the supported refresh rates. +- qcom,dsi-supported-qsync-min-fps-list: The fps value in this list indicates the qsync min fps + corresponding to the mode in the qcom,dsi-supported-dfps-list with same index. + qcom,dsi-supported-qsync-min-fps-list cannot be defined along with + qcom,mdss-dsi-qsync-min-refresh-rate. - qcom,min-refresh-rate: Minimum refresh rate supported by the panel. - qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh rate is not specified, then the frame rate of the panel in @@ -731,6 +736,8 @@ Example: qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; + qcom,dsi-supported-dfps-list = <30 45 60>; + qcom,dsi-supported-qsync-min-fps-list = <30 40 55>; qcom,min-refresh-rate = <30>; qcom,max-refresh-rate = <60>; qcom,mdss-dsi-bl-pmic-bank-select = <0>; From c5ebe11f3dd5e8641170ec423e92d6f585e145b0 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 1 Oct 2020 15:39:39 +0530 Subject: [PATCH 236/362] ARM: dts: msm: fix phy timing array size of sim panel on Holi This change fixes the phy timing array size of video sim panel on Holi target. Change-Id: I1d8364cd6d7460219498d812ab5263f29995a41d --- display/holi-sde-display-common.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 83a1a9196bb9..2dc88cc3b208 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -104,10 +104,12 @@ &dsi_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 + 07 05 02 04 00]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; }; From 038c64470672be1b5bec38c1e4ec4c995570e4af Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Wed, 30 Sep 2020 10:52:10 +0530 Subject: [PATCH 237/362] ARM: dts: msm: Add support for dual display on shima This change adds support for 2 independent displays on shima for both video and command modes. Change-Id: Ia61230e5694a93fe115371557ba59de3738b0801 --- display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi | 3 +++ display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 2 ++ display/shima-sde-display-common.dtsi | 2 ++ display/shima-sde-display-idp.dtsi | 6 ++++++ 4 files changed, 13 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi index 7674b87a769f..6f408edc7be9 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi @@ -14,6 +14,9 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; qcom,mdss-dsi-lane-map = "lane_map_0123"; qcom,mdss-dsi-bllp-eof-power-mode; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi index 310f28f3ee28..1b00915032df 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi @@ -6,6 +6,8 @@ qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; qcom,mdss-dsi-bpp = <24>; diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index d601cb6cb167..8dd9fd76391c 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -97,6 +97,7 @@ &dsi_r66451_amoled_60hz_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 @@ -109,6 +110,7 @@ &dsi_r66451_amoled_60hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <327096550 325733640 328459448>; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 9b5ef968a80a..5bbc92e9c622 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -12,23 +12,29 @@ &dsi_r66451_amoled_60hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_r66451_amoled_60hz_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_r66451_amoled_cmd { From 463345dfeaef2711d660be5b54cfdcd2a8a46a86 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 1 Oct 2020 17:17:46 +0530 Subject: [PATCH 238/362] ARM: dts: msm: Enable Partial Update feature on holi Enable partial update feature for sharp qsync fhd 60hz command mode panel on holi target. Change-Id: I47bc60ae60d2b6dbcfbe833c61d90e8577fe4830 --- .../dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi | 131 ++++++++++++++++++ display/holi-sde-display-cdp.dtsi | 9 ++ display/holi-sde-display-common.dtsi | 17 +++ 3 files changed, 157 insertions(+) create mode 100644 display/dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi diff --git a/display/dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi b/display/dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi new file mode 100644 index 000000000000..ff985394e844 --- /dev/null +++ b/display/dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi @@ -0,0 +1,131 @@ +&mdss_mdp { + dsi_sharp_qsync_fhd_60hz_cmd: qcom,mdss_dsi_sharp_qsync_fhd_60hz_cmd { + qcom,mdss-dsi-panel-name = "Sharp qsync fhd cmd mode single dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <134>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 501b2a615690..a1a4df09a9b3 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -42,6 +42,15 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_sharp_qsync_fhd_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 985fafa82d2a..47b651b60bf0 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -9,6 +9,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-sharp-qsync-fhd-video.dtsi" #include "dsi-panel-sharp-qsync-fhd-cmd.dtsi" +#include "dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi" #include &soc { @@ -652,3 +653,19 @@ }; }; }; + +&dsi_sharp_qsync_fhd_60hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 1d 1d 03 + 03 02 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + }; +}; From 7bd87d54c5dafb22aabab00e4cc314675d41108a Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 5 Oct 2020 22:31:24 +0530 Subject: [PATCH 239/362] ARM: dts: msm: add r66451 120Hz DSI panel support on Holi CDP This change adds visionox r66451 120Hz amoled video and command mode dsi panel on Holi CDP platform. Change-Id: Icb4f1c506fd497cc8f05fbd77199ef3072c59287 --- display/holi-sde-display-cdp.dtsi | 20 +++++++++++++ display/holi-sde-display-common.dtsi | 44 ++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index a1a4df09a9b3..4da9c2161107 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -51,6 +51,26 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vddio_182>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vddio_182>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 47b651b60bf0..8796a6e5c02f 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -57,6 +57,50 @@ }; }; + dsi_panel_pwr_supply_vddio_182: dsi_panel_pwr_supply_vddio_182 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + dsi_panel_pwr_supply_labibb: dsi_panel_pwr_supply_labibb { #address-cells = <1>; #size-cells = <0>; From c0024855ea16e3887c5545af64607d5f6e438c21 Mon Sep 17 00:00:00 2001 From: Ashwini Muduganti Date: Tue, 6 Oct 2020 13:46:09 -0700 Subject: [PATCH 240/362] Revert "ARM: dts: msm: define ramdump buffer reservation node" This reverts commit d2024b815e4e7092442049138875458986fe9287. Change-Id: Ic8a5ebf6293d84675ea56846ca6dee95edfe0dc9 --- display/shima-sde.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index d6f9872d200f..7b2994593d5f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -2,11 +2,6 @@ #include &soc { - disp_rdump_memory: disp_rdump_region@e1000000 { - reg = <0xe1000000 0x02300000>; - label = "disp_rdump_region"; - }; - ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; From 7fe6e4f110d0e752d26cdb406d9cf75136188d4c Mon Sep 17 00:00:00 2001 From: Ashwini Muduganti Date: Tue, 6 Oct 2020 13:47:07 -0700 Subject: [PATCH 241/362] Revert "ARM: dts: msm: update display_panel_avdd regulator type for Lahaina" This reverts commit fffe26cecc44dbc829e9ad14c0222e963dc1fdd3. Change-Id: I8ed0efd98cebeb4cf1468474a279829c092d051a --- display/lahaina-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 3e3a389510da..60e9663d7420 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -18,7 +18,7 @@ &soc { display_panel_avdd: display_gpio_regulator@1 { - compatible = "qti-regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "display_panel_avdd"; regulator-min-microvolt = <5500000>; regulator-max-microvolt = <5500000>; From e451ba292235446df1443941c22622273cb99a32 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 25 Sep 2020 13:13:48 +0530 Subject: [PATCH 242/362] ARM: dts: msm: Change VDDIO and default panel on shima idp Update VDDIO panel power supply to 1.82V and select 60Hz command mode panel as default on shima IDP platform. Change-Id: I7620cddbe0274127dfa5df78baebd1a4bbbb8037 --- display/shima-sde-display-common.dtsi | 4 ++-- display/shima-sde-display-idp.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 8dd9fd76391c..277df1f64085 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -14,8 +14,8 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1920000>; - qcom,supply-max-voltage = <1920000>; + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; qcom,supply-enable-load = <60700>; qcom,supply-disable-load = <80>; qcom,supply-post-on-sleep = <20>; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 5bbc92e9c622..6db7f7e5dbf1 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -66,5 +66,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; }; From fc7fa12f99c7a8a307c43815e475c4a75a609137 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Wed, 30 Sep 2020 16:15:01 -0400 Subject: [PATCH 243/362] ARM: dts: msm: Introduce dummy demura panel ID node ABL expects a demura panel ID node to always be present under the DSI display definition. If this node is not present, ABL is unable to insert it and demura continuous splash can not be brought online. Introduce a dummy demura panel ID node into the device tree. This node is given a panel ID of 0 to allow the kernel to specially handle it. Change-Id: I4da25f02152c6410d4e67868f702149a7a81bd4c --- bindings/sde-dsi.txt | 2 ++ display/lahaina-sde-display-common.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt index 8e720f75f1ee..daad29293deb 100644 --- a/bindings/sde-dsi.txt +++ b/bindings/sde-dsi.txt @@ -42,6 +42,8 @@ Required properties: - interrupts: The interrupt signal from the DSI block. - qcom,dsi-default-panel: Specifies the default panel. - qcom,mdp: Specifies the mdp node which can find panel node from this. +- qcom,demura-panel-id: Specifies the u64 demura panel ID as an array <2> + If demura is not used this node must be set to <0,0>. Bus Scaling Data: - qcom,msm-bus,name: String property describing MDSS client. diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index c23cc4f3a018..5e75e63013cd 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -107,6 +107,7 @@ qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + qcom,demura-panel-id = <0x0 0x0>; }; sde_dsi1: qcom,dsi-display-secondary { @@ -116,6 +117,7 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; }; }; From 8e92a765b4a2f4f90203ea4629c66a5fee2d89d8 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Mon, 12 Oct 2020 10:37:35 +0530 Subject: [PATCH 244/362] ARM: dts: msm: Add support for cphy video mode panel on shima This change adds support for cphy video mode panel on shima platform. Change-Id: I5e18853bb8bf8560fbecb8012c550e363adec50c --- display/shima-sde-display-common.dtsi | 14 ++++++++++++++ display/shima-sde-display-idp.dtsi | 10 ++++++++++ 2 files changed, 24 insertions(+) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 277df1f64085..95d7ee0a9079 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -3,6 +3,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -136,6 +137,19 @@ }; }; +&dsi_r66451_amoled_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 6db7f7e5dbf1..fd96a123258d 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -59,6 +59,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 271ba2c99205e4561baa3d995867c42569fad6fa Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Mon, 12 Oct 2020 10:42:57 +0530 Subject: [PATCH 245/362] ARM: dts: msm: Enable ESD for cphy video mode panel on shima This change enables ESD for cphy video mode panel on shima target. Change-Id: Ica177fe8f0d51a43d1b32cb54c736fc29c1d4002 --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index d1d9826fe587..c8b0ed462c34 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -124,3 +124,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_video_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From f95046906705117f2742143ad3a3e93e4a7a2c87 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 8 Oct 2020 15:52:21 +0530 Subject: [PATCH 246/362] ARM: dts: msm: update topology to 111 for 60fps on shima Updating topology to 111 for 60fps on shima target. Change-Id: If64ccb535a46d0aaf9dfc11113dca9f6d7882827 --- display/shima-sde-display-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 95d7ee0a9079..7647aef3b1ac 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -103,7 +103,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -119,7 +119,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 03 03 02 04 00 0f 13]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; }; From 35112fd29557ec0974449b34962f469625beb265 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 11:20:24 +0530 Subject: [PATCH 247/362] ARM: dts: msm: Add support for sharp qhd dual dsi on shima This change adds support for sharp qhd dual dsi panel on shima platform. Change-Id: I258d1718c611433a06244ae95f02afab86b2dbda --- display/shima-sde-display-common.dtsi | 20 ++++++++++++++++++++ display/shima-sde-display-idp.dtsi | 13 +++++++++++++ 2 files changed, 33 insertions(+) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 7647aef3b1ac..d6e548f33235 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -4,6 +4,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -150,6 +151,25 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index fd96a123258d..3c07eaa27ac0 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -68,6 +68,17 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 48 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; +}; &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; @@ -76,5 +87,7 @@ }; &sde_dsi { + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-2 = <&lcd_backlight_ctrl_default>; qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; }; From 3725dc1308722270d93a51cac2acac223851193e Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 11:22:15 +0530 Subject: [PATCH 248/362] ARM: dts: msm: Enable ESD for sharp qhd dual dsi panel on shima This change enables ESD for sharp qhd dual dsi panel on shima target. Change-Id: I3d1b8b3ff09a58fc15d3f09062b8cb02b2a2a8f3 --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index c8b0ed462c34..576da914f8b6 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -133,3 +133,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 42e3759b294e71c1ec96bde16de248228dfbcea3 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Wed, 21 Oct 2020 13:09:09 +0530 Subject: [PATCH 249/362] ARM: dts: msm: enable qsync along with VRR in shima target This change enables qsync support for shima target along with exisiting VRR. The required concurrency changes are already included in the commit 30b1dd339b45 ("disp: msm: sde: support qsync and vrr in same atomic commit"). Change-Id: I699334dc999857a8938bcb84d2ac4ca1386252c2 --- display/shima-sde-display-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index d601cb6cb167..eaef2892003a 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -78,6 +78,7 @@ qcom,mdss-dsi-min-refresh-rate = <48>; qcom,mdss-dsi-max-refresh-rate = <120>; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-qsync-min-refresh-rate = <48>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0"; From 6b498e97393496a21f7c689c608a6ca29d9e2779 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 21 Oct 2020 15:51:42 +0530 Subject: [PATCH 250/362] ARM: dts: msm: change default panel for trusted vm for shima target Use 120 fps command mode panel as the default panel for trusted vm for shima target. Change-Id: Ic7f24ac362a9ca51e8bd3a46b5625965c50901be --- display/trustedvm-shima-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/trustedvm-shima-sde-display.dtsi b/display/trustedvm-shima-sde-display.dtsi index f70e3fc880cf..dc497bf18f44 100644 --- a/display/trustedvm-shima-sde-display.dtsi +++ b/display/trustedvm-shima-sde-display.dtsi @@ -27,7 +27,7 @@ "shadow_byte_clk1", "shadow_pixel_clk1"; qcom,panel-te-source = <0>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; &mdss_mdp { From f034638cbf7632a18642e5134c9ea06a9440ae01 Mon Sep 17 00:00:00 2001 From: Ashwini Muduganti Date: Wed, 21 Oct 2020 12:26:13 -0700 Subject: [PATCH 251/362] Revert "ARM: dts: msm: Change VDDIO and default panel on shima idp" This reverts commit 98b5af0f99e1d8114791337d231bc7d432a52ebe. Change-Id: Id7ae8e18b88014fc1eb79cbd1d721fd14ab74b39 --- display/shima-sde-display-common.dtsi | 4 ++-- display/shima-sde-display-idp.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 277df1f64085..8dd9fd76391c 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -14,8 +14,8 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1820000>; - qcom,supply-max-voltage = <1820000>; + qcom,supply-min-voltage = <1920000>; + qcom,supply-max-voltage = <1920000>; qcom,supply-enable-load = <60700>; qcom,supply-disable-load = <80>; qcom,supply-post-on-sleep = <20>; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 6db7f7e5dbf1..5bbc92e9c622 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -66,5 +66,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; From 4f766763ca7a6770e8610deeb7a4d5e6ca1b9488 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Thu, 22 Oct 2020 10:17:02 +0800 Subject: [PATCH 252/362] ARM: dts: msm: increase vddio for r66451 panel Increase vddio to 1.86v for qrd. Change-Id: I97f9b6b500ba023c01e80274524427d5552b2f90 --- display/holi-sde-display-qrd.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index 4d4feddfc61c..39f497d72ae7 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -2,8 +2,8 @@ &dsi_panel_pwr_supply { qcom,panel-supply-entry@0 { - qcom,supply-min-voltage = <1820000>; - qcom,supply-max-voltage = <1820000>; + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; }; }; From f4f57c08afc945395a9fd23f8dcbd7afc9d325f2 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 8 Oct 2020 15:52:21 +0530 Subject: [PATCH 253/362] ARM: dts: msm: update topology to 111 for 60fps on shima Updating topology to 111 for 60fps on shima target. Change-Id: If64ccb535a46d0aaf9dfc11113dca9f6d7882827 --- display/shima-sde-display-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 95d7ee0a9079..7647aef3b1ac 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -103,7 +103,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -119,7 +119,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 03 03 02 04 00 0f 13]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; }; From 262a75622252e87aa2347d4c6e570333a3a8e029 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 11:04:42 +0530 Subject: [PATCH 254/362] ARM: dts: msm: Add support for cphy command mode panel on shima This change adds support for cphy command mode panel on shima platform. Change-Id: I7ced651418954fa4c644422d59afe7cbe6162cf1 --- .../dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi | 2 +- display/shima-sde-display-common.dtsi | 14 ++++++++++++++ display/shima-sde-display-idp.dtsi | 10 ++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi index 8b540370ae41..443762b291b8 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi @@ -60,7 +60,7 @@ 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 06 B6 6c 00 06 23 a6 + 39 01 00 00 00 00 06 B6 6c 00 06 23 af 39 01 00 00 00 00 02 B4 20 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 27325abd1380..7006dffcdd0b 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -5,6 +5,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" #include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -171,6 +172,19 @@ }; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 3c07eaa27ac0..54c0f4fa4349 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -80,6 +80,16 @@ qcom,platform-en-gpio = <&tlmm 47 0>; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 1ac4db5f57f5f28cdba0369b562b4ea51463f237 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 11:08:19 +0530 Subject: [PATCH 255/362] ARM: dts: msm: Enable ESD for cphy command mode panel on shima This change enables ESD for cphy command mode panel on shima target. Change-Id: Ia70e000f0ac4a3d9cb144b05d8c3b7debece76a5 --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 576da914f8b6..c4ad6d8c83fc 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -142,3 +142,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 970d4a87b3ee797160f00fb848ff5281825a7695 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Thu, 29 Oct 2020 11:43:01 -0700 Subject: [PATCH 256/362] ARM: dts: msm: update INTF HW block size This change updates hardware INTF block size to right size as per Lahaina SWI. Change-Id: I0301c548a537cfd380a845b9e092a6bc8a442d03 --- display/lahaina-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 3730cc8d6dd7..9c009d960baf 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -62,7 +62,7 @@ qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; - qcom,sde-intf-size = <0x2c0>; + qcom,sde-intf-size = <0x2c4>; qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; From 4cb8ea14b1fb2ca1c2bc06f0758b4ebcc60e6be4 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 22 Oct 2020 16:32:34 +0530 Subject: [PATCH 257/362] ARM: dts: msm: Add support for sharp qhd video mode on shima This change adds support for sharp qhd video mode dual dsi panel on shima platform. Change-Id: I291fbf6d860c754f01bdcde29f51d0ef6c26644f --- .../dsi-panel-sharp-dsc-qhd-plus-video.dtsi | 193 ++++++++++++++++++ display/shima-sde-display-common.dtsi | 13 ++ display/shima-sde-display-idp.dtsi | 13 ++ 3 files changed, 219 insertions(+) create mode 100644 display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi new file mode 100644 index 000000000000..d61e11b05c2f --- /dev/null +++ b/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi @@ -0,0 +1,193 @@ +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_video: qcom,mdss_dsi_sharp_qhd_plus_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp qhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 7006dffcdd0b..70fcc069c51d 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -3,6 +3,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" #include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" @@ -140,6 +141,18 @@ }; }; +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_video_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 54c0f4fa4349..1cbc9bc43f7e 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -68,6 +68,19 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 48 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; +}; + &dsi_sharp_qhd_plus_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; From 0ba08f72569540ed5fdffde4981df16bd609c83d Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 22 Oct 2020 16:35:14 +0530 Subject: [PATCH 258/362] ARM: dts: msm: Enable ESD for sharp qhd video mode on shima This change enables ESD for sharp qhd video mode dual dsi panel on shima target. Change-Id: Ibf4a83abdc0c247043d880ac67925905f055042b --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index c4ad6d8c83fc..d7f3efc6ec23 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -125,6 +125,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_sharp_qhd_plus_dsc_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_video_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From 95fc29eec6efed6cfa82af2490d605781c0a1d16 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 26 Oct 2020 00:39:41 -0700 Subject: [PATCH 259/362] ARM: dts: msm: add backlight properties for trusted vm displays Add backlight properties for displays supported in trusted vm environment. Change-Id: I593a9a94a4cd309638eda5b03793d0f5699c1036 --- display/trustedvm-lahaina-sde-display.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi index 036205f97d18..14697d22c7ca 100644 --- a/display/trustedvm-lahaina-sde-display.dtsi +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -31,3 +31,18 @@ &mdss_mdp { connectors = <&sde_dsi>; }; + +&dsi_sw43404_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; +}; + +&dsi_sw43404_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; +}; + From d17ef1f73203687abc27d8b15ddfe3c955da27c7 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Wed, 11 Nov 2020 11:18:54 +0800 Subject: [PATCH 260/362] ARM: dts: msm: enable LP mode DCS brightness setting for r66451 video panel Used LP mode for DCS brightness and power off commands. Change-Id: Id704c2adf0939717368a7de8108a9cecc530af7a --- display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 2 +- display/lahaina-sde-display-qrd.dtsi | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 995e4df38122..68925fcc9311 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -90,7 +90,7 @@ 05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 6792ded59c5e..6613c46cd877 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -13,6 +13,7 @@ &dsi_r66451_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; From 745cefb9c49f519dc3b1d56681e8047b91dccc26 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Wed, 4 Nov 2020 16:56:52 +0530 Subject: [PATCH 261/362] ARM: dts: msm: Add mdp_intf base address in dt This change adds mdp_intf_base address entry for dsi0 and dsi1 on shima, holi and lahaina targets. Change-Id: I56c118884690237e0559e928c4828fe575adf98c --- display/holi-sde-common.dtsi | 5 +++-- display/lahaina-sde-common.dtsi | 10 ++++++---- display/shima-sde-common.dtsi | 10 ++++++---- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index ca2ba7d915f7..3e49e2ac9420 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -173,8 +173,9 @@ cell-index = <0>; frame-threshold-time-us = <1000>; reg = <0x05e94000 0x400>, - <0x05f08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0x05f08000 0x4>, + <0x05e6b800 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 9c009d960baf..66182dd3bc09 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -283,8 +283,9 @@ cell-index = <0>; frame-threshold-time-us = <800>; reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; @@ -322,8 +323,9 @@ cell-index = <1>; frame-threshold-time-us = <800>; reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>; diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi index 8ed5332e3db4..8e003df778e8 100644 --- a/display/shima-sde-common.dtsi +++ b/display/shima-sde-common.dtsi @@ -241,8 +241,9 @@ cell-index = <0>; frame-threshold-time-us = <800>; reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae6b800 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; @@ -281,8 +282,9 @@ cell-index = <1>; frame-threshold-time-us = <800>; reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae6c000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>; From a78012a4c030a63e3e7879570244d2567af1ea77 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 11 Nov 2020 09:49:11 -0800 Subject: [PATCH 262/362] ARM: dts: msm: add backlight properties for visionox panel in TVM Add properties related to backlight for visionox panel in trusted-VM for lahaina target. Change-Id: I1e797ae25b797f29172efe9c22872aaf11194073 --- display/trustedvm-lahaina-sde-display.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi index 14697d22c7ca..f603189ccf1e 100644 --- a/display/trustedvm-lahaina-sde-display.dtsi +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -46,3 +46,19 @@ qcom,mdss-brightness-max-level = <255>; }; +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; +}; + From 7ee17d24d46610efa623f6ce74c1b4f57cdd48fc Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Thu, 12 Nov 2020 11:38:15 +0530 Subject: [PATCH 263/362] bindings: disp: qcom: Update reg and reg-names binding documentation This change updates documentation for reg and reg-names which are used to specify the address & length and names respectively of the memory mapped regions. Change-Id: Id7f1c8f5cd13bdf8791fbcafc7e1b93a0664a914 --- bindings/sde-dsi.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt index 8e720f75f1ee..b05a411e2522 100644 --- a/bindings/sde-dsi.txt +++ b/bindings/sde-dsi.txt @@ -15,11 +15,12 @@ Required properties: qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2 -- reg: Base address and length of DSI controller's memory - mapped regions. +- reg: List of base address and length of memory mapped + regions of DSI controller, disp_cc and mdp_intf. - reg-names: A list of strings that name the list of regs. "dsi_ctrl" - DSI controller memory region. - "mmss_misc" - MMSS misc memory region. + "disp_cc_base" - Base address of disp_cc memory region. + "mdp_intf_base" - Base address of mdp_intf memory region. - cell-index: Specifies the controller instance. - clocks: Clocks required for DSI controller operation. - clock-names: Names of the clocks corresponding to handles. Following From 96404b91b8afa90e651537f43b901b4613df6a8d Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Fri, 13 Nov 2020 10:41:19 -0800 Subject: [PATCH 264/362] ARM: dts: msm: add name property for all display specific GPIOs Add a GPIO name property to capture all the GPIOs specific to display host and panel. The entries correspond to the GPIO pins in the property dsi-panel-gpio-pins. Change-Id: If820a47fcdf72e5ef6e907a92c947ea4d4480690 --- bindings/mdss-dsi-panel.txt | 3 +++ display/lahaina-sde-display-common.dtsi | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 086fb76f0c73..de435b32c172 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -604,6 +604,8 @@ Optional properties: - qcom,dsi-panel-gpio-pins: An u32 array consisting of all the GPIO pins used for driving the DSI host and the panels connected to the host. +- qcom,dsi-panel-gpio-names: A string array consisting of names of all the + GPIO pins used for driving the DSI host and panels. - qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. - qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active region for video mode panels and line number after TE for command mode @@ -790,6 +792,7 @@ Example: qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; qcom,mdss-dsi-display-timings { wqhd { diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index c23cc4f3a018..4aa28560d687 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -127,6 +127,7 @@ qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; qcom,mdss-dsi-display-timings { timing@0 { @@ -149,6 +150,10 @@ qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio"; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 @@ -166,6 +171,11 @@ qcom,mdss-dsi-min-refresh-rate = <60>; qcom,mdss-dsi-max-refresh-rate = <120>; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio"; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 16 07 @@ -179,6 +189,11 @@ &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 From f3c4569ffa4bb8a9998b2f77e00e52f0eef8186d Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 11 Nov 2020 16:16:22 -0800 Subject: [PATCH 265/362] ARM: dts: msm: enable ESD status check for all panels in lahaina TVM Move the ESD entries from lahaina specific device-tree to common device-tree to enable the feature in both VMs for lahaina target. Change-Id: I8fa9f14eb36f79078be16d380db6a213bf822639 --- display/lahaina-sde-display-common.dtsi | 99 +++++++++++++++++++++++++ display/lahaina-sde-display.dtsi | 92 +---------------------- 2 files changed, 100 insertions(+), 91 deletions(-) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 4aa28560d687..b4a2b6f5467c 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -125,6 +125,13 @@ qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; qcom,dsi-panel-gpio-pins = <12 24 82>; qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; @@ -150,6 +157,13 @@ qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; qcom,dsi-panel-gpio-pins = <12 24>; qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio"; @@ -194,6 +208,13 @@ qcom,dsi-panel-gpio-pins = <12 24 82>; qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 @@ -247,6 +268,14 @@ &dsi_r66451_amoled_144hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09 @@ -259,6 +288,15 @@ &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 @@ -272,6 +310,15 @@ &dsi_sharp_4k_dsc_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06 @@ -284,6 +331,15 @@ &dsi_sharp_1080_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 @@ -297,6 +353,14 @@ &dsi_sharp_qsync_wqhd_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03 @@ -358,6 +422,14 @@ &dsi_sharp_qsync_wqhd_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 @@ -389,6 +461,15 @@ &dsi_dual_nt35597_truly_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { /* DPHY regular margins */ @@ -408,6 +489,15 @@ qcom,mdss-dsi-max-refresh-rate = <60>; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 @@ -422,6 +512,15 @@ &dsi_nt35695b_truly_fhd_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { /* DPHY regular margins */ diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 3e3a389510da..f1949c65f7c4 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -112,13 +112,6 @@ &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; - qcom,mdss-dsi-display-timings { timing@0 { qcom,partial-update-enabled = "single_roi"; @@ -127,74 +120,24 @@ }; }; -&dsi_sw43404_amoled_video { - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; -}; - &dsi_r66451_amoled_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x1c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; + &dsi_r66451_amoled_144hz_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x1c>; - qcom,mdss-dsi-panel-status-read-length = <1>; }; &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x77>; - qcom,mdss-dsi-panel-on-check-value = <0x77>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; -}; - -&dsi_sharp_4k_dsc_video { - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x77>; - qcom,mdss-dsi-panel-on-check-value = <0x77>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; &dsi_sharp_1080_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; &dsi_sharp_qsync_wqhd_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ qcom,partial-update-enabled = "single_roi"; @@ -223,45 +166,12 @@ }; }; -&dsi_sharp_qsync_wqhd_video { - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; -}; - &dsi_dual_nt35597_truly_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; &dsi_nt35695b_truly_fhd_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; &dsi_sim_cmd { From 13169aa3940ade1135f9ba1ef1215d7130c88a5f Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Thu, 29 Oct 2020 12:01:46 -0400 Subject: [PATCH 266/362] ARM: dts: msm: add support for secondary display in TVM Add missing DSI clock nodes and dsi connector for secondary display in TVM. Change-Id: I34dab33fc478bcefff67f282cac35694013202ad --- display/trustedvm-lahaina-sde-display.dtsi | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi index 036205f97d18..f3799d5bb242 100644 --- a/display/trustedvm-lahaina-sde-display.dtsi +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -28,6 +28,23 @@ qcom,panel-te-source = <0>; }; -&mdss_mdp { - connectors = <&sde_dsi>; +&sde_dsi1 { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_MUX_1_CLK>, + <&clock_cpucc PCLK_MUX_1_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; + qcom,panel-te-source = <1>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; }; From 6f24ba7786dcbe2556306e5ab3469fbbdebbd896 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Thu, 19 Nov 2020 11:41:59 -0500 Subject: [PATCH 267/362] bindings: Documentation: add DSC continuous PPS command support for DP Add support for DSC continuous PPS command for DP which allows sending PPS during every frame in hardware as per the requirement of some bridge chips. Change-Id: I6c81c08ca386ef7cf636fed0b1328c4e0c029ea3 --- bindings/sde-dp.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index 567cbd7dd81b..5f0c5fc4fba9 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -76,6 +76,8 @@ DP Controller: Required properties: - usb-controller: Phandle for the USB controller. - qcom,pll-revision: PLL hardware revision. - usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events. +- qcom,dsc-continuous-pps: Control node for sending PPS every frame in hardware for DSC over DP. + This is needed by certain bridge chips where there is such a requirement to do so. - qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. - qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. - qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. @@ -197,7 +199,7 @@ sde_dp: qcom,dp_display@0 { qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - + qcom,dsc-continuous-pps; vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; vdd_mx-supply = <&VDD_MXA_LEVEL>; From eb4ea50d8f1eb54e50ae48566581fba7d5cc316d Mon Sep 17 00:00:00 2001 From: Sudarsan Ramesh Date: Thu, 19 Nov 2020 12:03:05 -0500 Subject: [PATCH 268/362] ARM: dts: msm: Enable continuous PPS for DP DSC This change enables continuous PPS for DP DSC so that a PPS is sent via hardware for every frame. This is needed by certain bridge chips where there is a requirement to do so. Change-Id: Id0aa7238816ae888dffdf145f40e3cd03a387f14 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 41286ac19ff8..08aac3611c8d 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -85,6 +85,7 @@ qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; + qcom,dsc-continuous-pps; vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; From c2e76ada04f6165bb522154dde312c3ff8a495b4 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 12 Nov 2020 15:14:05 -0800 Subject: [PATCH 269/362] ARM: dts: msm: enable dynamic clocks for CPHY panels on Lahaina Change enables Dynamic clocks for Visionox CPHY command and video mode panels on lahaina target. Change-Id: I330a8705c6383870ddc1bdf6e893d8c623427f81 --- display/lahaina-sde-display-common.dtsi | 8 +++++++- display/lahaina-sde-display.dtsi | 10 ++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index b4a2b6f5467c..b089d09f0801 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -242,6 +242,8 @@ &dsi_r66451_amoled_cmd_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <195173804 194360579 193547355>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 @@ -254,7 +256,11 @@ &dsi_r66451_amoled_video_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0"; + "cphy_byte_clk0", "cphy_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <394178400 392535990 387608760>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index f1949c65f7c4..685fd53fd828 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -48,6 +48,8 @@ <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, @@ -55,15 +57,19 @@ <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; + "shadow_byte_clk1", "shadow_pixel_clk1", + "shadow_cphybyte_clk1", "shadow_cphypixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; From d7ff5a63600811c9cbd018262d3bb81efd98e9fe Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Wed, 25 Nov 2020 00:16:09 +0530 Subject: [PATCH 270/362] ARM: dts: msm: add backlight properties for visionox panel in TVM Add properties related to backlight for visionox panel in trusted-VM for shima target. Change-Id: I97913526ba38eb74ba4d6ea44ddbcee67a63ff91 --- display/trustedvm-shima-sde-display.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/display/trustedvm-shima-sde-display.dtsi b/display/trustedvm-shima-sde-display.dtsi index dc497bf18f44..c4df4865ec0f 100644 --- a/display/trustedvm-shima-sde-display.dtsi +++ b/display/trustedvm-shima-sde-display.dtsi @@ -33,3 +33,19 @@ &mdss_mdp { connectors = <&sde_dsi>; }; + +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; +}; From 755dd6bc2d1f0ed5073b3cdbc974eb30c85ebdbe Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Sun, 6 Dec 2020 08:46:08 +0530 Subject: [PATCH 271/362] ARM: dts: msm: add wake up on touch support Early wake up by perf hal ioctl is not enabled for holi target. Made changes to enable early wake up by legacy input touch handle method. Change-Id: Ib1efc689ba21a587bf4e32e34a2e55552ab138b9 --- display/holi-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index c6d3d332a98a..6b9b4af31c3f 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -109,6 +109,7 @@ interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; + qcom,sde-wakeup-with-touch; qcom,platform-supply-entries { #address-cells = <1>; From 04185369fe3cf4f68f3c65ac13658fb2e2b7e336 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Mon, 23 Nov 2020 17:33:06 +0800 Subject: [PATCH 272/362] ARM: dts: msm: add 60Hz panel node for holi Add 60Hz cmd mode and video mode support for qrd and cdp holi. Change-Id: I78b188ba95d324bad95da359aa2e7844ebe751d6 --- display/holi-sde-display-cdp.dtsi | 20 ++++++++++++++++++++ display/holi-sde-display-qrd.dtsi | 10 ++++++++++ display/holi-sde-display.dtsi | 20 ++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 4da9c2161107..bf75e6b46050 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -71,6 +71,26 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index 39f497d72ae7..f7f1aae2c61d 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -57,6 +57,16 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index c019341c0970..248d6f4e80f6 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -105,3 +105,23 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_60hz_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + From b64162fec1ad8aa467e66759304d10d3c959ab90 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Tue, 15 Dec 2020 18:18:03 +0800 Subject: [PATCH 273/362] ARM: dts: msm: increase vddio voltage for qrd lahaina panel Since some panels have larger vddio voltage drop, that will lead panel dead. So increase the voltage from 1.8v to 1.86v. Change-Id: I6e6d3cd95c550e976a170d99b7f3d3d311c8bb3e --- display/lahaina-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 6613c46cd877..a82336ce618e 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ #include "lahaina-sde-display.dtsi" +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; + }; +}; + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From adf0b7c1cbf5d894d7a4c4a82ee3a0a6cae0acb7 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Wed, 9 Dec 2020 18:16:33 +0530 Subject: [PATCH 274/362] ARM: dts: msm: Add NT36672E Video mode panel support on holi Add NT36672E 60, 120 and 144 fps fhd plus Video mode panel support on holi platform. Change-Id: I7a25b37ebce9fa9c7877dbd6cdfde2929b394663 --- ...dsi-panel-nt36672e-fhd-plus-120-video.dtsi | 334 ++++++++++++++++ ...dsi-panel-nt36672e-fhd-plus-144-video.dtsi | 376 ++++++++++++++++++ ...si-panel-nt36672e-fhd-plus-60hz-video.dtsi | 313 +++++++++++++++ display/holi-sde-display-cdp.dtsi | 24 ++ display/holi-sde-display-common.dtsi | 46 +++ 5 files changed, 1093 insertions(+) create mode 100644 display/dsi-panel-nt36672e-fhd-plus-120-video.dtsi create mode 100644 display/dsi-panel-nt36672e-fhd-plus-144-video.dtsi create mode 100644 display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi diff --git a/display/dsi-panel-nt36672e-fhd-plus-120-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-120-video.dtsi new file mode 100644 index 000000000000..ddbf609aefa9 --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-120-video.dtsi @@ -0,0 +1,334 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_120_video: qcom,mdss_dsi_nt36672e_fhd_plus_120_video { + qcom,mdss-dsi-panel-name = + "nt36672e fhd plus 120Hz Video panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 B0 00 + 15 01 00 00 00 00 02 C0 03 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 + 0D B7 0C B7 + 39 01 00 00 00 00 03 C2 1B A0 + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 01 66 + 15 01 00 00 00 00 02 06 40 + 15 01 00 00 00 00 02 07 38 + 15 01 00 00 00 00 02 2F 83 + 15 01 00 00 00 00 02 69 91 + 15 01 00 00 00 00 02 95 D1 + 15 01 00 00 00 00 02 96 D1 + 15 01 00 00 00 00 02 F2 64 + 15 01 00 00 00 00 02 F4 64 + 15 01 00 00 00 00 02 F6 64 + 15 01 00 00 00 00 02 F8 64 + + 15 01 00 00 00 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01 00 00 00 00 02 4A F0 + + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 17 00 46 00 63 00 81 00 96 + 00 AB 00 BD + 39 01 00 00 00 00 11 B1 00 CF 01 03 01 2F 01 6E 01 9D 01 E7 + 02 22 02 24 + 39 01 00 00 00 00 11 B2 02 5D 02 9B 02 C4 02 F9 03 1B 03 48 + 03 56 03 65 + 39 01 00 00 00 00 0F B3 03 75 03 87 03 9B 03 B1 03 CA 03 D7 + 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 19 00 4B 00 69 00 87 00 9C + 00 B2 00 C3 + 39 01 00 00 00 00 11 B5 00 D5 01 0B 01 35 01 73 01 A3 01 EC + 02 27 02 29 + 39 01 00 00 00 00 11 B6 02 60 02 9F 02 C7 02 FB 03 1D 03 4C + 03 5A 03 69 + 39 01 00 00 00 00 0F B7 03 7A 03 8C 03 A0 03 B5 03 CB 03 D7 + 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 19 00 4D 00 6A 00 87 00 9C + 00 B1 00 C2 + 39 01 00 00 00 00 11 B9 00 D3 01 08 01 32 01 70 01 9F 01 E8 + 02 23 02 25 + 39 01 00 00 00 00 11 BA 02 5C 02 9B 02 C3 02 F8 03 1A 03 4C + 03 5B 03 6B + 39 01 00 00 00 00 0F BB 03 7D 03 92 03 A7 03 BB 03 CE 03 D7 + 00 00 + + 15 01 00 00 00 00 02 FF 21 + 15 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 17 00 46 00 63 00 81 00 96 + 00 AB 00 BD + 39 01 00 00 00 00 11 B1 00 CF 01 03 01 2F 01 6E 01 9D 01 E7 + 02 22 02 24 + 39 01 00 00 00 00 11 B2 02 5D 02 9B 02 C4 02 F9 03 1B 03 48 + 03 56 03 65 + 39 01 00 00 00 00 0F B3 03 75 03 87 03 9B 03 B1 03 CA 03 D7 + 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 19 00 4B 00 69 00 87 00 9C + 00 B2 00 C3 + 39 01 00 00 00 00 11 B5 00 D5 01 0B 01 35 01 73 01 A3 01 EC + 02 27 02 29 + 39 01 00 00 00 00 11 B6 02 60 02 9F 02 C7 02 FB 03 1D 03 4C + 03 5A 03 69 + 39 01 00 00 00 00 0F B7 03 7A 03 8C 03 A0 03 B5 03 CB 03 D7 + 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 19 00 4D 00 6A 00 87 00 9C + 00 B1 00 C2 + 39 01 00 00 00 00 11 B9 00 D3 01 08 01 32 01 70 01 9F 01 E8 + 02 23 02 25 + 39 01 00 00 00 00 11 BA 02 5C 02 9B 02 C3 02 F8 03 1A 03 4C + 03 5B 03 6B + 39 01 00 00 00 00 0F BB 03 7D 03 92 03 A7 03 BB 03 CE 03 D7 + 00 00 + + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 FF F0 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 FF 10 + + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 FB 01 + + 15 01 00 00 00 00 02 51 FF //CABC + 15 01 00 00 00 00 02 53 2C + 15 01 00 00 00 00 02 55 01 + + 05 01 00 00 C8 00 01 11 + 05 01 00 00 96 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt36672e-fhd-plus-144-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-144-video.dtsi new file mode 100644 index 000000000000..eb5466ffe0d4 --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-144-video.dtsi @@ -0,0 +1,376 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_144_video: qcom,mdss_dsi_nt36672e_fhd_plus_144_video { + qcom,mdss-dsi-panel-name = + "nt36672e fhd plus 144Hz video panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 FF 10 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 29 01 00 00 00 00 03 C2 1B A0 + 29 01 00 00 00 00 02 E9 01 + + 29 01 00 00 00 00 02 FF 20 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 01 66 + 29 01 00 00 00 00 02 06 40 + 29 01 00 00 00 00 02 07 38 + 29 01 00 00 00 00 02 1B 01 + 29 01 00 00 00 00 02 2D 00 + 29 01 00 00 00 00 02 2F 83 + 29 01 00 00 00 00 02 69 91 + 29 01 00 00 00 00 02 95 D1 + 29 01 00 00 00 00 02 96 D1 + 29 01 00 00 00 00 02 F2 64 + 29 01 00 00 00 00 02 F4 64 + 29 01 00 00 00 00 02 F6 64 + 29 01 00 00 00 00 02 F8 64 + + 29 01 00 00 00 00 02 FF 23 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 00 00 + 29 01 00 00 00 00 02 04 05 + 29 01 00 00 00 00 02 05 2D + 29 01 00 00 00 00 02 06 01 + 29 01 00 00 00 00 02 07 60 + 29 01 00 00 00 00 02 08 01 + 29 01 00 00 00 00 02 09 C7 + 29 01 00 00 00 00 02 11 01 + 29 01 00 00 00 00 02 12 95 + 29 01 00 00 00 00 02 15 68 + 29 01 00 00 00 00 02 16 0B + 29 01 00 00 00 00 02 A0 00 + 29 01 00 00 00 00 02 30 FF + 29 01 00 00 00 00 02 31 F0 + 29 01 00 00 00 00 02 32 EB + 29 01 00 00 00 00 02 33 E5 + 29 01 00 00 00 00 02 34 DD + 29 01 00 00 00 00 02 35 DA + 29 01 00 00 00 00 02 36 D5 + 29 01 00 00 00 00 02 37 D0 + 29 01 00 00 00 00 02 38 CE + 29 01 00 00 00 00 02 39 CD + 29 01 00 00 00 00 02 3A CD + 29 01 00 00 00 00 02 3B CD + 29 01 00 00 00 00 02 3D CB + 29 01 00 00 00 00 02 3F CB + 29 01 00 00 00 00 02 40 C6 + 29 01 00 00 00 00 02 41 BF + 29 01 00 00 00 00 02 45 FF + 29 01 00 00 00 00 02 46 F0 + 29 01 00 00 00 00 02 47 E8 + 29 01 00 00 00 00 02 48 CE + 29 01 00 00 00 00 02 49 BC + 29 01 00 00 00 00 02 4A B8 + 29 01 00 00 00 00 02 4B B5 + 29 01 00 00 00 00 02 4C B0 + 29 01 00 00 00 00 02 4D A8 + 29 01 00 00 00 00 02 4E A0 + 29 01 00 00 00 00 02 4F 9B + 29 01 00 00 00 00 02 50 98 + 29 01 00 00 00 00 02 51 98 + 29 01 00 00 00 00 02 52 88 + 29 01 00 00 00 00 02 53 80 + 29 01 00 00 00 00 02 54 7F + 29 01 00 00 00 00 02 58 FF + 29 01 00 00 00 00 02 59 F6 + 29 01 00 00 00 00 02 5A ED + 29 01 00 00 00 00 02 5B E6 + 29 01 00 00 00 00 02 5C DF + 29 01 00 00 00 00 02 5D D8 + 29 01 00 00 00 00 02 5E D3 + 29 01 00 00 00 00 02 5F CE + 29 01 00 00 00 00 02 60 C9 + 29 01 00 00 00 00 02 61 C4 + 29 01 00 00 00 00 02 62 C1 + 29 01 00 00 00 00 02 63 BE + 29 01 00 00 00 00 02 64 BB + 29 01 00 00 00 00 02 65 B8 + 29 01 00 00 00 00 02 66 B6 + 29 01 00 00 00 00 02 67 B5 + + 29 01 00 00 00 00 02 FF 24 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 01 0F + 29 01 00 00 00 00 02 03 0C + 29 01 00 00 00 00 02 05 1D + 29 01 00 00 00 00 02 08 2F + 29 01 00 00 00 00 02 09 2E + 29 01 00 00 00 00 02 0A 2D + 29 01 00 00 00 00 02 0B 2C + 29 01 00 00 00 00 02 11 17 + 29 01 00 00 00 00 02 12 13 + 29 01 00 00 00 00 02 13 15 + 29 01 00 00 00 00 02 15 14 + 29 01 00 00 00 00 02 16 16 + 29 01 00 00 00 00 02 17 18 + 29 01 00 00 00 00 02 1B 01 + 29 01 00 00 00 00 02 1D 1D + 29 01 00 00 00 00 02 20 2F + 29 01 00 00 00 00 02 21 2E + 29 01 00 00 00 00 02 22 2D + 29 01 00 00 00 00 02 23 2C + 29 01 00 00 00 00 02 29 17 + 29 01 00 00 00 00 02 2A 13 + 29 01 00 00 00 00 02 2B 15 + 29 01 00 00 00 00 02 2F 14 + 29 01 00 00 00 00 02 30 16 + 29 01 00 00 00 00 02 31 18 + 29 01 00 00 00 00 02 32 04 + 29 01 00 00 00 00 02 34 10 + 29 01 00 00 00 00 02 35 19 + 29 01 00 00 00 00 02 36 19 + 29 01 00 00 00 00 02 4D 11 + 29 01 00 00 00 00 02 4E 2B + 29 01 00 00 00 00 02 4F 2B + 29 01 00 00 00 00 02 53 2B + 29 01 00 00 00 00 02 71 30 + 29 01 00 00 00 00 02 79 11 + 29 01 00 00 00 00 02 7A 82 + 29 01 00 00 00 00 02 7B 8B + 29 01 00 00 00 00 02 7D 04 + 29 01 00 00 00 00 02 80 04 + 29 01 00 00 00 00 02 81 04 + 29 01 00 00 00 00 02 82 13 + 29 01 00 00 00 00 02 84 31 + 29 01 00 00 00 00 02 85 00 + 29 01 00 00 00 00 02 86 00 + 29 01 00 00 00 00 02 87 00 + 29 01 00 00 00 00 02 90 13 + 29 01 00 00 00 00 02 92 31 + 29 01 00 00 00 00 02 93 00 + 29 01 00 00 00 00 02 94 00 + 29 01 00 00 00 00 02 95 00 + 29 01 00 00 00 00 02 9C F4 + 29 01 00 00 00 00 02 9D 01 + 29 01 00 00 00 00 02 A0 0B + 29 01 00 00 00 00 02 A2 0B + 29 01 00 00 00 00 02 A3 02 + 29 01 00 00 00 00 02 A4 04 + 29 01 00 00 00 00 02 A5 04 + 29 01 00 00 00 00 02 C6 C0 + 29 01 00 00 00 00 02 C9 00 + 29 01 00 00 00 00 02 D9 80 + 29 01 00 00 00 00 02 E9 02 + + 29 01 00 00 00 00 02 FF 25 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 19 E4 + 29 01 00 00 00 00 02 21 00 + 29 01 00 00 00 00 02 66 D8 + 29 01 00 00 00 00 02 68 50 + 29 01 00 00 00 00 02 69 10 + 29 01 00 00 00 00 02 6B 00 + 29 01 00 00 00 00 02 6D 0D + 29 01 00 00 00 00 02 6E 48 + 29 01 00 00 00 00 02 72 41 + 29 01 00 00 00 00 02 73 4A + 29 01 00 00 00 00 02 74 D0 + 29 01 00 00 00 00 02 77 62 + 29 01 00 00 00 00 02 79 81 + 29 01 00 00 00 00 02 7D 03 + 29 01 00 00 00 00 02 7E 15 + 29 01 00 00 00 00 02 7F 00 + 29 01 00 00 00 00 02 84 4D + 29 01 00 00 00 00 02 CF 00 + 29 01 00 00 00 00 02 D6 80 + 29 01 00 00 00 00 02 D7 80 + 29 01 00 00 00 00 02 EF 20 + 29 01 00 00 00 00 02 F0 84 + + 29 01 00 00 00 00 02 FF 26 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 80 05 + 29 01 00 00 00 00 02 81 0B + 29 01 00 00 00 00 02 83 01 + 29 01 00 00 00 00 02 84 03 + 29 01 00 00 00 00 02 85 01 + 29 01 00 00 00 00 02 86 03 + 29 01 00 00 00 00 02 87 01 + 29 01 00 00 00 00 02 88 06 + 29 01 00 00 00 00 02 8A 1A + 29 01 00 00 00 00 02 8B 11 + 29 01 00 00 00 00 02 8C 24 + 29 01 00 00 00 00 02 8E 42 + 29 01 00 00 00 00 02 8F 11 + 29 01 00 00 00 00 02 90 11 + 29 01 00 00 00 00 02 91 11 + 29 01 00 00 00 00 02 9A 80 + 29 01 00 00 00 00 02 9B 04 + 29 01 00 00 00 00 02 9C 00 + 29 01 00 00 00 00 02 9D 00 + 29 01 00 00 00 00 02 9E 00 + + 29 01 00 00 00 00 02 FF 27 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 01 68 + 29 01 00 00 00 00 02 20 81 + 29 01 00 00 00 00 02 21 30 + 29 01 00 00 00 00 02 25 81 + 29 01 00 00 00 00 02 26 67 + 29 01 00 00 00 00 02 6E 00 + 29 01 00 00 00 00 02 6F 00 + 29 01 00 00 00 00 02 70 00 + 29 01 00 00 00 00 02 71 00 + 29 01 00 00 00 00 02 72 00 + 29 01 00 00 00 00 02 75 00 + 29 01 00 00 00 00 02 76 00 + 29 01 00 00 00 00 02 77 00 + 29 01 00 00 00 00 02 7D 09 + 29 01 00 00 00 00 02 7E 67 + 29 01 00 00 00 00 02 80 23 + 29 01 00 00 00 00 02 82 09 + 29 01 00 00 00 00 02 83 67 + 29 01 00 00 00 00 02 88 01 + 29 01 00 00 00 00 02 89 10 + 29 01 00 00 00 00 02 A5 10 + 29 01 00 00 00 00 02 A6 23 + 29 01 00 00 00 00 02 A7 01 + 29 01 00 00 00 00 02 B6 40 + + 29 01 00 00 00 00 02 FF 2A + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 00 91 + 29 01 00 00 00 00 02 03 20 + 29 01 00 00 00 00 02 04 78 + 29 01 00 00 00 00 02 07 60 + 29 01 00 00 00 00 02 0A 70 + 29 01 00 00 00 00 02 0C 04 + 29 01 00 00 00 00 02 0D 40 + 29 01 00 00 00 00 02 0F 01 + 29 01 00 00 00 00 02 11 E0 + 29 01 00 00 00 00 02 15 0F + 29 01 00 00 00 00 02 16 03 + 29 01 00 00 00 00 02 19 0E + 29 01 00 00 00 00 02 1A D7 + 29 01 00 00 00 00 02 1B 14 + 29 01 00 00 00 00 02 1D 2E + 29 01 00 00 00 00 02 1E 33 + 29 01 00 00 00 00 02 1F 33 + 29 01 00 00 00 00 02 20 33 + 29 01 00 00 00 00 02 28 FD + 29 01 00 00 00 00 02 29 0D + 29 01 00 00 00 00 02 2A B7 + 29 01 00 00 00 00 02 2D 09 + 29 01 00 00 00 00 02 2F 02 + 29 01 00 00 00 00 02 30 47 + 29 01 00 00 00 00 02 33 D8 + 29 01 00 00 00 00 02 34 FF + 29 01 00 00 00 00 02 35 40 + 29 01 00 00 00 00 02 36 B8 + 29 01 00 00 00 00 02 37 F9 + 29 01 00 00 00 00 02 38 45 + 29 01 00 00 00 00 02 39 B3 + 29 01 00 00 00 00 02 3A 47 + 29 01 00 00 00 00 02 4A F0 + + 29 01 00 00 00 00 02 FF 20 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 11 B0 00 E2 00 E9 00 F6 01 01 01 0C 01 15 01 20 01 28 + 29 01 00 00 00 00 11 B1 01 33 01 51 01 6E 01 9A 01 C0 01 FD 02 34 02 35 + 29 01 00 00 00 00 11 B2 02 6B 02 A9 02 D1 03 04 03 25 03 51 03 5F 03 6D + 29 01 00 00 00 00 0F B3 03 7D 03 90 03 A7 03 BB 03 D4 03 D8 00 00 + 29 01 00 00 00 00 11 B4 00 AA 00 B3 00 C4 00 D4 00 E2 00 F0 00 FC 01 08 + 29 01 00 00 00 00 11 B5 01 12 01 39 01 58 01 8C 01 B5 01 F7 02 30 02 31 + 29 01 00 00 00 00 11 B6 02 68 02 A6 02 CE 03 01 03 23 03 4E 03 5C 03 6A + 29 01 00 00 00 00 0F B7 03 7B 03 8E 03 A5 03 BB 03 D4 03 D8 00 00 + 29 01 00 00 00 00 11 B8 00 00 00 20 00 47 00 65 00 85 00 99 00 AD 00 C0 + 29 01 00 00 00 00 11 B9 00 D2 01 06 01 30 01 70 01 9F 01 E8 02 25 02 26 + 29 01 00 00 00 00 11 BA 02 5F 02 9F 02 C7 02 FD 03 20 03 52 03 63 03 67 + 29 01 00 00 00 00 0F BB 03 78 03 8B 03 A3 03 B9 03 D4 03 D8 00 00 + 29 01 00 00 00 00 02 FF 21 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 11 B0 00 E2 00 E9 00 F6 01 01 01 0C 01 15 01 20 01 28 + 29 01 00 00 00 00 11 B1 01 33 01 51 01 6E 01 9A 01 C0 01 FD 02 34 02 35 + 29 01 00 00 00 00 11 B2 02 6B 02 A9 02 D1 03 04 03 25 03 51 03 5F 03 6D + 29 01 00 00 00 00 0F B3 03 7D 03 90 03 A7 03 BB 03 D4 03 D8 00 00 + 29 01 00 00 00 00 11 B4 00 AA 00 B3 00 C4 00 D4 00 E2 00 F0 00 FC 01 08 + 29 01 00 00 00 00 11 B5 01 12 01 39 01 58 01 8C 01 B5 01 F7 02 30 02 31 + 29 01 00 00 00 00 11 B6 02 68 02 A6 02 CE 03 01 03 23 03 4E 03 5C 03 6A + 29 01 00 00 00 00 0F B7 03 7B 03 8E 03 A5 03 BB 03 D4 03 D8 00 00 + 29 01 00 00 00 00 11 B8 00 00 00 20 00 47 00 65 00 85 00 99 00 AD 00 C0 + 29 01 00 00 00 00 11 B9 00 D2 01 06 01 30 01 70 01 9F 01 E8 02 25 02 26 + 29 01 00 00 00 00 11 BA 02 5F 02 9F 02 C7 02 FD 03 20 03 52 03 63 03 67 + 29 01 00 00 00 00 0F BB 03 78 03 8B 03 A3 03 B9 03 D4 03 D8 00 00 + + 29 01 00 00 00 00 02 FF C0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 9C 11 + 29 01 00 00 00 00 02 9D 11 + + 29 01 00 00 00 00 02 FF F0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 5A 00 + 29 01 00 00 00 00 02 9F 0C + + 29 01 00 00 00 00 02 FF D0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 53 22 + 29 01 00 00 00 00 02 54 02 + + 29 01 00 00 00 00 02 FF E0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 35 82 + + 29 01 00 00 00 00 02 FF 10 + 29 01 00 00 00 00 02 FB 01 + + 15 01 00 00 00 00 02 35 01 //TE + + 05 01 00 00 C8 00 01 11 + 05 01 00 00 96 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi new file mode 100644 index 000000000000..c9f454a0c27e --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi @@ -0,0 +1,313 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_60_video: qcom,mdss_dsi_nt36672e_fhd_plus_60_video { + qcom,mdss-dsi-panel-name = + "nt36672e 60 Hz fhd plus video mode panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750 + 39800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <56>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 C0 00 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 14 01 00 01 11 00 01 C1 + 39 01 00 00 00 00 03 C2 1B A0 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3A 01 7A 01 A9 01 F2 02 2D 02 2E + 39 01 00 00 00 00 11 B2 02 64 02 A3 02 CA 03 00 03 1E 03 4A 03 59 03 6A + 39 01 00 00 00 00 0F B3 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 1B 00 51 00 71 00 90 00 A7 00 BF 00 D1 + 39 01 00 00 00 00 11 B5 00 E2 01 1A 01 43 01 83 01 B2 01 FA 02 34 02 36 + 39 01 00 00 00 00 11 B6 02 6B 02 A8 02 D0 03 03 03 21 03 4D 03 5B 03 6B + 39 01 00 00 00 00 0F B7 03 7E 03 94 03 AC 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 1B 00 51 00 72 00 92 00 A8 00 BF 00 D1 + 39 01 00 00 00 00 11 B9 00 E2 01 18 01 42 01 81 01 AF 01 F5 02 2F 02 31 + 39 01 00 00 00 00 11 BA 02 68 02 A6 02 CD 03 01 03 1F 03 4A 03 59 03 6A + 39 01 00 00 00 00 0F BB 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 02 FF 21 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 17 00 49 00 6A 00 89 00 9F 00 B6 00 C8 + 39 01 00 00 00 00 11 B1 00 D9 01 10 01 3A 01 7A 01 A9 01 F2 02 2D 02 2E + 39 01 00 00 00 00 11 B2 02 64 02 A3 02 CA 03 00 03 1E 03 4A 03 59 03 6A + 39 01 00 00 00 00 0F B3 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 1B 00 51 00 71 00 90 00 A7 00 BF 00 D1 + 39 01 00 00 00 00 11 B5 00 E2 01 1A 01 43 01 83 01 B2 01 FA 02 34 02 36 + 39 01 00 00 00 00 11 B6 02 6B 02 A8 02 D0 03 03 03 21 03 4D 03 5B 03 6B + 39 01 00 00 00 00 0F B7 03 7E 03 94 03 AC 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 1B 00 51 00 72 00 92 00 A8 00 BF 00 D1 + 39 01 00 00 00 00 11 B9 00 E2 01 18 01 42 01 81 01 AF 01 F5 02 2F 02 31 + 39 01 00 00 00 00 11 BA 02 68 02 A6 02 CD 03 01 03 1F 03 4A 03 59 03 6A + 39 01 00 00 00 00 0F BB 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 02 FF 2C + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 61 1F + 39 01 00 00 00 00 02 62 1F + 39 01 00 00 00 00 02 7E 03 + 39 01 00 00 00 00 02 6A 14 + 39 01 00 00 00 00 02 6B 36 + 39 01 00 00 00 00 02 6C 36 + 39 01 00 00 00 00 02 6D 36 + 39 01 00 00 00 00 02 53 04 + 39 01 00 00 00 00 02 54 04 + 39 01 00 00 00 00 02 55 04 + 39 01 00 00 00 00 02 56 0F + 39 01 00 00 00 00 02 58 0F + 39 01 00 00 00 00 02 59 0F + 39 01 00 00 00 00 02 FF F0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 51 FF + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 55 01 + 05 01 00 00 78 00 01 11 + 05 01 00 00 64 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + }; + }; + }; +}; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index bf75e6b46050..405d99cc5725 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -94,3 +94,27 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 8796a6e5c02f..b4d0bf1d8d88 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -10,6 +10,9 @@ #include "dsi-panel-sharp-qsync-fhd-video.dtsi" #include "dsi-panel-sharp-qsync-fhd-cmd.dtsi" #include "dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include &soc { @@ -713,3 +716,46 @@ }; }; }; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x32>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 + 08 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x34>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + + }; + }; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0F>; + qcom,mdss-dsi-t-clk-pre = <0x39>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 + 0a 09 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; From ff4e1317fadcc5dcdef050a0759f6918bbe06d2d Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Tue, 22 Dec 2020 17:29:45 +0800 Subject: [PATCH 275/362] ARM: dts: msm: increase vddio voltage for qrd shima panel Since some panels have larger vddio voltage drop, that will lead panel dead. So increase the voltage from 1.82v to 1.86v. Change-Id: I129cdbb11e8b7687111f0c9d34c873a40ad15f54 --- display/shima-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/shima-sde-display-qrd.dtsi b/display/shima-sde-display-qrd.dtsi index 72107b66065a..bbd34e09bda6 100644 --- a/display/shima-sde-display-qrd.dtsi +++ b/display/shima-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ #include "shima-sde-display.dtsi" +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; + }; +}; + &dsi_r66451_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 1e0d888b505c106a8a32f2282f2708a5ea82ec34 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 28 Dec 2020 17:49:43 +0530 Subject: [PATCH 276/362] ARM: dts: msm: add display dt node for yupik target Add display related dt nodes for yupik target. Change-Id: I6c703e83fb174c65157fb3b6604e900857abba5c --- display/yupik-sde-common.dtsi | 325 ++++++++++++++++++++++++++ display/yupik-sde-display-common.dtsi | 119 ++++++++++ display/yupik-sde-display-idp.dtsi | 22 ++ display/yupik-sde-display.dtsi | 42 ++++ display/yupik-sde.dtsi | 107 +++++++++ 5 files changed, 615 insertions(+) create mode 100644 display/yupik-sde-common.dtsi create mode 100644 display/yupik-sde-display-common.dtsi create mode 100644 display/yupik-sde-display-idp.dtsi create mode 100644 display/yupik-sde-display.dtsi create mode 100644 display/yupik-sde.dtsi diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi new file mode 100644 index 000000000000..a91404665c0a --- /dev/null +++ b/display/yupik-sde-common.dtsi @@ -0,0 +1,325 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clock-rate = <0 0 0 0 506666667 19200000 506666667 19200000>; + clock-max-rate = <0 0 0 0 608000000 19200000 608000000 + 608000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000 0x1a000 0x1b000>; + qcom,sde-ctl-size = <0x1e8>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", + "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", + "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x35000 0x36000 + 0x3a000>; + qcom,sde-intf-size = <0x2c4>; + qcom,sde-intf-type = "dp", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0>; + + qcom,sde-pp-off = <0x6a000 + 0x6c000 0x6d000>; + qcom,sde-pp-slave = <0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000>; + qcom,sde-dsc-size = <0x10>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00>; + qcom,sde-dsc-ctl-size = <0x10>; + qcom,sde-dsc-native422-supp = <1>; + qcom,sde-dsc-linewidth = <2048>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", + "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 + 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 + 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0 3 2>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, + <0x2b0 12>, <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2400>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-wb-linewidth-linear = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x8 0x2>, + <0x7 0x1>; + qcom,sde-ubwc-version = <0x300>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <4700000>; + qcom,sde-max-bw-high-kbps = <8800000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>; + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x1 0xff00 0xff00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666666 0x66666540>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x4000901>; + + /* SPMI address related to display */ + qcom,pmic-arb = <&spmi_bus>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.5"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.1"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf01004 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi new file mode 100644 index 000000000000..a8c8e500697a --- /dev/null +++ b/display/yupik-sde-display-common.dtsi @@ -0,0 +1,119 @@ +#include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb: dsi_panel_pwr_supply_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_144_video>; + }; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 08 02 04 00 1c 18]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + +&dsi_nt36672e_fhd_plus_60_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 + 0a 09 02 04 00 1f 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi new file mode 100644 index 000000000000..31e06dd7bacc --- /dev/null +++ b/display/yupik-sde-display-idp.dtsi @@ -0,0 +1,22 @@ +#include "yupik-sde-display.dtsi" + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_144_video>; +}; + diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi new file mode 100644 index 000000000000..e85af3a1b632 --- /dev/null +++ b/display/yupik-sde-display.dtsi @@ -0,0 +1,42 @@ +#include "yupik-sde-display-common.dtsi" + +&soc { + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 80 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; +}; + +&mdss_mdp { + connectors = <&sde_wb &sde_dsi>; +}; diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi new file mode 100644 index 000000000000..464d7c34968c --- /dev/null +++ b/display/yupik-sde.dtsi @@ -0,0 +1,107 @@ +#include "yupik-sde-common.dtsi" +#include + +&soc { + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + status = "disabled"; + reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <4>; + + qcom,sde-dram-channels = <2>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + qcom,msm-bus,active-only; + interconnects = + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus"; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x900 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent-hint-cached; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x901 0x400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &cnoc2 SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010001>; + /* offsets are based off dspp 0 */ + qcom,sde-dspp-ltm-off = <0x15300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + +}; From 62c3eea684bdce7ffa0767d280a88760d422874f Mon Sep 17 00:00:00 2001 From: Mitika Dodiya Date: Wed, 30 Dec 2020 20:06:30 +0530 Subject: [PATCH 277/362] ARM: dts: msm: add display dt node for yupik Add display dt node for yupik. Change-Id: I68f4686e670caaf480ed87b4eeb05e8daa289ae3 --- display/yupik-sde-common.dtsi | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index a91404665c0a..5ab33d471d1e 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -147,14 +147,6 @@ qcom,sde-dram-channels = <2>; qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-spr-off = <0x15400 0x14400>; - qcom,sde-dspp-spr-size = <0x200>; - qcom,sde-dspp-spr-version = <0x00010000>; - - qcom,sde-dspp-demura-off = <0x15600 0x14800>; - qcom,sde-dspp-demura-size = <0x200>; - qcom,sde-dspp-demura-version = <0x00010000>; - qcom,sde-uidle-off = <0x80000>; qcom,sde-uidle-size = <0x70>; @@ -187,7 +179,7 @@ qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; - /* offsets are relative to "mdp_phys + qcom,sde-off */ + /* offsets are relative to regdma_phys */ qcom,sde-reg-dma-off = <0 0x400>; qcom,sde-reg-dma-id = <0 1>; qcom,sde-reg-dma-version = <0x00020000>; From 40b591fa5e923e26002dfadbd95371d85aabff40 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Tue, 5 Jan 2021 10:44:14 +0800 Subject: [PATCH 278/362] Revert "ARM: dts: msm: increase VFP value for video mode panel" This reverts commit 82b36f5105464d12e088ea7deac8d4171a488a67. Change-Id: I8fb1eb6b02f9730c2894cfdecf72e2d049361773 --- display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 2 +- display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 2 +- display/lahaina-sde-display-common.dtsi | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 68925fcc9311..7cfc0bd32bd3 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -36,7 +36,7 @@ qcom,mdss-dsi-h-pulse-width = <1>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <75>; + qcom,mdss-dsi-v-front-porch = <25>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-on-command = [ diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi index d7cd192a4fbd..ecac0d4bfc65 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi @@ -37,7 +37,7 @@ qcom,mdss-dsi-h-pulse-width = <12>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <10>; - qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-front-porch = <10>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-h-left-border = <0>; qcom,mdss-dsi-panel-framerate = <60>; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 9ad13ecdeba6..7b54b749014e 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -172,7 +172,7 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 05 06 02 04 00 12 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; @@ -194,8 +194,8 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 16 07 - 07 08 02 04 00 19 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From 6c957cda0d0cb6322fbc8869b22c02ea72a55158 Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Wed, 6 Jan 2021 01:25:12 +0530 Subject: [PATCH 279/362] ARM: dts: msm: Add dp DT node for yupik target Add dp dt node for yupik target. Change-Id: Iba92179e4a9cfb5e5fe51438f69f85f8bb1e97d1 --- display/yupik-sde.dtsi | 116 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 464d7c34968c..ab62f8bc5bab 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -2,6 +2,122 @@ #include &soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp: qcom,dp_display@ae90000 { + status="disabled"; + cell-index = <0>; + compatible = "qcom,dp-display"; + + usb-phy = <&usb_qmp_dp_phy>; + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0fc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x098>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf01068 0x1a0>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xaf01004 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical","gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "pixel_clk_rcg", "pixel_parent","strm0_pixel_clk"; + + qcom,phy-version = <0x420>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; From 5efc7feef013ba132f059496beae92489841940d Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Tue, 12 Jan 2021 13:30:35 +0530 Subject: [PATCH 280/362] ARM: dts: msm: add cwb pingpong and mixer in yupik DT Add pingpong and mixer blocks in yupik dt, which are used only in cwb case. Change-Id: I9e2dd9143b0b45bc5497634ef2ae1a5af3852793 --- display/yupik-sde-common.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index a91404665c0a..5853774a468e 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -29,12 +29,12 @@ qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; - qcom,sde-mixer-off = <0x45000 0x47000 0x48000>; + qcom,sde-mixer-off = <0x45000 0x45000 0x47000 0x48000>; qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", + qcom,sde-mixer-display-pref = "primary", "none", "none", "none"; - qcom,sde-mixer-cwb-pref = "none", + qcom,sde-mixer-cwb-pref = "none", "cwb", "none", "none"; qcom,sde-dspp-top-off = <0x1300>; @@ -60,9 +60,9 @@ qcom,sde-intf-type = "dp", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0 0x36800 0>; - qcom,sde-pp-off = <0x6a000 + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000>; - qcom,sde-pp-slave = <0x0 0x0 0x0>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; qcom,sde-pp-size = <0xd4>; qcom,sde-cdm-off = <0x7a200>; @@ -78,7 +78,7 @@ qcom,sde-dsc-native422-supp = <1>; qcom,sde-dsc-linewidth = <2048>; - qcom,sde-dither-off = <0xe0 0xe0 0xe0>; + qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0>; qcom,sde-dither-version = <0x00020000>; qcom,sde-dither-size = <0x20>; @@ -95,7 +95,7 @@ qcom,sde-sspp-smart-dma-priority = <4 1 2 3>; qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - qcom,sde-mixer-pair-mask = <0 3 2>; + qcom,sde-mixer-pair-mask = <0 0 4 3>; qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; From e486ed34382625a4d00923ba35649d75f8bef2ee Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 13 Jan 2021 11:54:34 +0530 Subject: [PATCH 281/362] ARM: dts: msm: Update lcdb ldo/ncp voltage for yupik Update lcdb ldo and ncp minimum voltage to 5.6V on yupik idp platform. Change-Id: I1fe6a46cd9c549e7b9d4a678ef22a27683635c5f --- display/yupik-sde-display-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index a8c8e500697a..d91b86f042f2 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -64,7 +64,7 @@ qcom,panel-supply-entry@1 { reg = <1>; qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; + qcom,supply-min-voltage = <5600000>; qcom,supply-max-voltage = <6000000>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; @@ -73,7 +73,7 @@ qcom,panel-supply-entry@2 { reg = <2>; qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; + qcom,supply-min-voltage = <5600000>; qcom,supply-max-voltage = <6000000>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; From 919a78827f8633931dec0fd43731a400df3478c7 Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Wed, 13 Jan 2021 14:15:03 +0530 Subject: [PATCH 282/362] ARM: dts: msm: add pll revision for yupik target Add pll revision for yupik target. Change-Id: Ied69469dcb6bc0dec1a64fb050dbaca44c6abff3 --- display/yupik-sde.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index ab62f8bc5bab..9883ea6ae039 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -32,7 +32,7 @@ <0x88eaa00 0x200>, <0x88ea200 0x200>, <0x88ea600 0x200>, - <0xaf01068 0x1a0>, + <0xaf00f98 0x1a0>, <0x88ea000 0x200>, <0x88e8000 0x20>, <0x0aee1000 0x034>, @@ -45,6 +45,7 @@ interrupt-parent = <&mdss_mdp>; interrupts = <12 0>; + qcom,pll-revision = "7nm"; #clock-cells = <1>; clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&clock_rpmh RPMH_CXO_CLK>, From 0a6656e9054e6595ba4e7e97e0f148e2d6ef0043 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Mon, 11 Jan 2021 16:16:06 +0800 Subject: [PATCH 283/362] ARM: dts: msm: add r66451 display cphy panel support for yupik qrd Add r66451 display cphy panel support for yupik qrd. Change-Id: I91b93b54396df275357743df7af9c0659e84f04f --- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 134 ++++++++++++++++++ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 110 ++++++++++++++ display/yupik-sde-display-common.dtsi | 30 +++- display/yupik-sde-display-qrd.dtsi | 36 +++++ 4 files changed, 309 insertions(+), 1 deletion(-) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi create mode 100644 display/yupik-sde-display-qrd.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi new file mode 100644 index 000000000000..6ff943606cce --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -0,0 +1,134 @@ +&mdss_mdp { + dsi_r66451_amoled_144hz_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi new file mode 100644 index 000000000000..a9aa91546d5c --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -0,0 +1,110 @@ +&mdss_mdp { + dsi_r66451_amoled_90hz_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 10 00 00 00 09 40 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index d91b86f042f2..b4cd94c1e229 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,5 +1,7 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" #include &soc { @@ -105,7 +107,6 @@ }; }; - &dsi_nt36672e_fhd_plus_60_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { @@ -117,3 +118,30 @@ }; }; }; + +&dsi_r66451_amoled_90hz_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_144hz_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 21 1f 06 + 19 07 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi new file mode 100644 index 000000000000..71120732ef0f --- /dev/null +++ b/display/yupik-sde-display-qrd.dtsi @@ -0,0 +1,36 @@ +#include "yupik-sde-display.dtsi" + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + }; +}; + +&dsi_r66451_amoled_90hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_r66451_amoled_144hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&sde_dsi { + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_144hz_cmd_cphy >; +}; From f18535b30d3e70116f554f5979626209f2269f8e Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Fri, 15 Jan 2021 11:06:10 +0530 Subject: [PATCH 284/362] ARM: dts: msm: correct the clock references for yupik target Correct the clock references for yupik target. Change-Id: If1ef29498c827d11ab4c56cfff8bbb7505271946 --- display/yupik-sde.dtsi | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index ab62f8bc5bab..3eb918fd9300 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -46,14 +46,14 @@ interrupts = <12 0>; #clock-cells = <1>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_iface_clk", "pixel_clk_rcg", "pixel_parent","strm0_pixel_clk"; @@ -74,7 +74,6 @@ vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; - vdd_mx-supply = <&VDD_MXA_LEVEL>; qcom,ctrl-supply-entries { #address-cells = <1>; From 5ccbee056351822834cb66e27e4ac0bec31dfd8d Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Fri, 15 Jan 2021 15:39:57 +0530 Subject: [PATCH 285/362] ARM: dts: msm: add merge 3d block in yupik target Add 3d merge block in yupik target. Removed scheduler op4 and op5. Change-Id: Id27f756c9d8f6bf1947470ee1f7891413d644e8e --- display/yupik-sde-common.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index 5853774a468e..2a106f69f8bc 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -24,10 +24,10 @@ qcom,sde-len = <0x494>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 - 0x19000 0x1a000 0x1b000>; + 0x19000>; qcom,sde-ctl-size = <0x1e8>; qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none", "none"; + "none"; qcom,sde-mixer-off = <0x45000 0x45000 0x47000 0x48000>; qcom,sde-mixer-size = <0x320>; @@ -64,6 +64,10 @@ 0x6c000 0x6d000>; qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x50000 0x50000>; + qcom,sde-merge-3d-size = <0x10>; qcom,sde-cdm-off = <0x7a200>; qcom,sde-cdm-size = <0x224>; @@ -109,7 +113,7 @@ /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, - <0x2ac 8>, <0x2b4 8>, <0x2bc 8>; + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>, <0x2b8 12>, <0x2c8 12>; From d3c407393863981bc12f22d0bfa9454607e81497 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 19 Jan 2021 04:45:47 +0530 Subject: [PATCH 286/362] ARM: dts: msm: Update lcd setting for yupik Update lcd setting for yupik idp platform. Change-Id: I0a02725e0f57e9c0e4f88481f370c674b156a2ac --- display/yupik-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index e85af3a1b632..7d939b6b3714 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -32,7 +32,7 @@ qcom,platform-te-gpio = <&tlmm 80 0>; qcom,panel-te-source = <0>; - vddio-supply = <&L12C>; + vddio-supply = <&L8C>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; }; From 58b3541cf09b7a9619d7467ff9b28ad4352d6cab Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 19 Jan 2021 04:42:02 +0530 Subject: [PATCH 287/362] ARM: dts: msm: Select 60Hz Video as default panel on yupik Select 60Hz video mode as default panel on yupik idp platform. Change-Id: Icd9f8d43d6cae4d0bda43b4f1e2ff139afec6f2a --- display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi | 1 - display/yupik-sde-display-idp.dtsi | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi index c9f454a0c27e..92f70b56493e 100644 --- a/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi +++ b/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi @@ -45,7 +45,6 @@ 39 01 00 00 00 00 02 B0 00 39 01 00 00 00 00 02 C0 00 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 - 14 01 00 01 11 00 01 C1 39 01 00 00 00 00 03 C2 1B A0 39 01 00 00 00 00 02 FF 20 39 01 00 00 00 00 02 FB 01 diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 31e06dd7bacc..50c7e266a497 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -17,6 +17,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_144_video>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; + vddio-supply = <&L8C>; }; From eceeb6d6c24b276ed7f0209f693dd4b30101d973 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 18 Jan 2021 22:31:41 +0530 Subject: [PATCH 288/362] ARM: dts: msm: remove gcc ahb clock for yupik Clock drivers have moved GCC_DISP_AHB_CLK to their probe and kept it always ON, and are not registering this clock with the framework. Hence, removing GCC_DISP_AHB_CLK from display clock list. Change-Id: Ifc21194814275f65776c642777263d9d37da3637 --- display/yupik-sde-common.dtsi | 4 ++-- display/yupik-sde.dtsi | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index 2a106f69f8bc..ca5e68650d1b 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -10,8 +10,8 @@ "vbif_phys", "regdma_phys"; - clock-rate = <0 0 0 0 506666667 19200000 506666667 19200000>; - clock-max-rate = <0 0 0 0 608000000 19200000 608000000 + clock-rate = <0 0 0 506666667 19200000 506666667 19200000>; + clock-max-rate = <0 0 0 608000000 19200000 608000000 608000000>; /* interrupt config */ diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 464d7c34968c..d3cefc88044b 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -47,7 +47,6 @@ &mdss_mdp { clocks = - <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, @@ -55,7 +54,7 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + clock-names = "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; From 67f4173c849ea2f98b85bb79702eb19f7ababfa6 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 20 Jan 2021 17:15:47 +0800 Subject: [PATCH 289/362] ARM: dts: msm: increase vddio voltage to 1.88v for qrd Some qrd devices vddio voltage have larger drop, need to increase the vddio votage to 1.88v, then they might work well. Change-Id: I951dc1240a84161828dc6a0e79a79aff15fb8d16 --- display/lahaina-sde-display-qrd.dtsi | 4 ++-- display/shima-sde-display-qrd.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index a82336ce618e..f70f7d46176d 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -2,8 +2,8 @@ &dsi_panel_pwr_supply { qcom,panel-supply-entry@0 { - qcom,supply-min-voltage = <1860000>; - qcom,supply-max-voltage = <1860000>; + qcom,supply-min-voltage = <1880000>; + qcom,supply-max-voltage = <1880000>; }; }; diff --git a/display/shima-sde-display-qrd.dtsi b/display/shima-sde-display-qrd.dtsi index bbd34e09bda6..b5a0ab04fa79 100644 --- a/display/shima-sde-display-qrd.dtsi +++ b/display/shima-sde-display-qrd.dtsi @@ -2,8 +2,8 @@ &dsi_panel_pwr_supply { qcom,panel-supply-entry@0 { - qcom,supply-min-voltage = <1860000>; - qcom,supply-max-voltage = <1860000>; + qcom,supply-min-voltage = <1880000>; + qcom,supply-max-voltage = <1880000>; }; }; From cc31e65fbf4be9329c5dd403de32590bd9864fe8 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 22 Jan 2021 10:49:26 +0530 Subject: [PATCH 290/362] ARM: dts: msm: Enable ESD feature on yupik idp Enable ESD feature for video mode panel on yupik idp platform. Change-Id: I25328ef729133865d15ae7427fca0e39a94aa0fa --- display/yupik-sde-display.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7d939b6b3714..5c04e4d978c7 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -40,3 +40,21 @@ &mdss_mdp { connectors = <&sde_wb &sde_dsi>; }; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From d12227bb751803928d524b1a45f42149acfd181d Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Fri, 22 Jan 2021 19:38:44 +0530 Subject: [PATCH 291/362] ARM: dts: msm: enable SDE RSC driver on yupik Enable sde rscc v4 driver on yupik target Change-Id: If3cec83048cb3061cf02c7b9d96256fd9b28d6f8 --- display/yupik-sde-display.dtsi | 2 +- display/yupik-sde.dtsi | 16 ---------------- 2 files changed, 1 insertion(+), 17 deletions(-) diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7d939b6b3714..4c4de67ec5a0 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -38,5 +38,5 @@ }; &mdss_mdp { - connectors = <&sde_wb &sde_dsi>; + connectors = <&sde_wb &sde_dsi &sde_rscc>; }; diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index bc1a0b82e06d..5be02098e827 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -122,7 +122,6 @@ sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; - status = "disabled"; reg = <0xaf20000 0x4d68>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; @@ -180,25 +179,10 @@ &cnoc2 SLAVE_DISPLAY_CFG>; interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; - vdd-supply = <&disp_cc_mdss_core_gdsc>; qcom,sde-has-idle-pc; qcom,sde-dspp-ltm-version = <0x00010001>; /* offsets are based off dspp 0 */ qcom,sde-dspp-ltm-off = <0x15300>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi0 { From ae8c038b44928420c2cb946b144c26ce66b02241 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 25 Jan 2021 18:48:21 +0530 Subject: [PATCH 292/362] ARM: dts: msm: add smmu nodes in mdp connector list for yupik target Add smmu nodes in mdp connector list for yupik target. Change-Id: If66db7aada636ca8d3f1fc9a3a800fe8e38b9d53 --- display/yupik-sde-common.dtsi | 2 +- display/yupik-sde-display.dtsi | 2 +- display/yupik-sde.dtsi | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index 40f403744008..fcdf37a6c5d4 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -191,7 +191,7 @@ qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - qcom,sde-secure-sid-mask = <0x4000901>; + qcom,sde-secure-sid-mask = <0x901 0xD01>; /* SPMI address related to display */ qcom,pmic-arb = <&spmi_bus>; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7adaccbdd5b8..71e495a3ffa5 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -38,7 +38,7 @@ }; &mdss_mdp { - connectors = <&sde_wb &sde_dsi &sde_rscc>; + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_rscc>; }; &dsi_nt36672e_fhd_plus_60_video { diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 5be02098e827..631580dab3dd 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -153,7 +153,8 @@ smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x901 0x400>; + iommus = <&apps_smmu 0x901 0x0>, + <&apps_smmu 0xD01 0x0>; qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; From 152b695e3f4e36a9ba97ce17de27433d8d6e7d60 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sat, 23 Jan 2021 16:17:05 +0530 Subject: [PATCH 293/362] ARM: dts: msm: Enable DFPS feature on yupik idp Enable DFPS feature to support 120, 60 and 48 fps for 144Hz Video mode panel on yupik idp. Change-Id: I2846c65ee43322949980db3c1fdcf46161995b09 --- display/yupik-sde-display-common.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index b4cd94c1e229..80ed70b3527d 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -97,6 +97,9 @@ &dsi_nt36672e_fhd_plus_144_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-supported-dfps-list = <144 120 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 From 5f0221c2e1cc907a5ec5c53612ebb09610ae667b Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sun, 24 Jan 2021 11:08:26 +0530 Subject: [PATCH 294/362] ARM: dts: msm: Add amoled cphy panel support on yupik Add amoled cphy command mode panel support for 90Hz and 144Hz on yupik idp platform. Change-Id: I3d83a2b603a05d213124ea8d7a8dc4122346844a --- display/yupik-sde-display-common.dtsi | 25 +++++++++++++++++++++++++ display/yupik-sde-display-idp.dtsi | 25 ++++++++++++++++++++++--- display/yupik-sde-display.dtsi | 18 ++++++++++++++++++ 3 files changed, 65 insertions(+), 3 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index b4cd94c1e229..71160b50c270 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -83,6 +83,31 @@ }; }; + dsi_panel_pwr_supply_amoled: dsi_panel_pwr_supply_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 50c7e266a497..d3886dad50f1 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -16,8 +16,27 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; -&sde_dsi { - qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; - vddio-supply = <&L8C>; +&dsi_r66451_amoled_90hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_r66451_amoled_144hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; }; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7adaccbdd5b8..2c4cc24f002c 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -58,3 +58,21 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_90hz_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_144hz_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From ce9b994ec2cd6bbcae42ba3ce24348f118d22d22 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Wed, 27 Jan 2021 10:39:28 +0800 Subject: [PATCH 295/362] ARM: dts: msm: enable display external vdd power for qrd yupik Enable a new external vdd power for qrd panel. Change-Id: I6330b3e52e79b535385a46a5aa4854dda7b0c540 --- display/yupik-sde-display-qrd.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi index 71120732ef0f..e7a88a182bea 100644 --- a/display/yupik-sde-display-qrd.dtsi +++ b/display/yupik-sde-display-qrd.dtsi @@ -5,6 +5,15 @@ qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <1800000>; }; + qcom,panel-supply-entry@4 { + reg = <4>; + qcom,supply-name = "extvdd"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <0>; + }; }; &dsi_r66451_amoled_90hz_cmd_cphy { @@ -32,5 +41,6 @@ vdd-supply = <&L13C>; lab-supply = <&ab_vreg>; ibb-supply = <&ibb_vreg>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_144hz_cmd_cphy >; + extvdd-supply = <&pm8350b_l1>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_144hz_cmd_cphy>; }; From 06abcf62a05453f9bc8a1cafed11de678c2d63a9 Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Fri, 22 Jan 2021 15:51:43 +0530 Subject: [PATCH 296/362] ARM: dts: msm: enable dp for yupik target Enable display port for yupik target. Change-Id: I659877278509f1dacb11c440fb6b7a43d7ddf6a8 --- display/yupik-sde-display.dtsi | 2 +- display/yupik-sde.dtsi | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index f79c40f89def..7359e3d9d407 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -38,7 +38,7 @@ }; &mdss_mdp { - connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_rscc>; + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_rscc &sde_dp>; }; &dsi_nt36672e_fhd_plus_60_video { diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 631580dab3dd..5367d035d47c 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -15,7 +15,6 @@ }; sde_dp: qcom,dp_display@ae90000 { - status="disabled"; cell-index = <0>; compatible = "qcom,dp-display"; From e656f3b745f2f6f3c24d98c0229b081fd4da6cf9 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Thu, 28 Jan 2021 17:04:48 +0530 Subject: [PATCH 297/362] ARM: dts: msm: add trusted vm display dtsi files for yupik target Add trusted VM display device tree files for yupik. Change-Id: I3ecef743c38a5751d3db13ee0d4f72fc00b2b15c --- display/trustedvm-yupik-sde-display.dtsi | 26 +++++++++++ display/trustedvm-yupik-sde.dtsi | 55 ++++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 display/trustedvm-yupik-sde-display.dtsi create mode 100644 display/trustedvm-yupik-sde.dtsi diff --git a/display/trustedvm-yupik-sde-display.dtsi b/display/trustedvm-yupik-sde-display.dtsi new file mode 100644 index 000000000000..7919d11a4a16 --- /dev/null +++ b/display/trustedvm-yupik-sde-display.dtsi @@ -0,0 +1,26 @@ +#include "yupik-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + qcom,panel-te-source = <0>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; +}; + + +&mdss_mdp { + connectors = <&sde_dsi>; +}; diff --git a/display/trustedvm-yupik-sde.dtsi b/display/trustedvm-yupik-sde.dtsi new file mode 100644 index 000000000000..a80a08afb696 --- /dev/null +++ b/display/trustedvm-yupik-sde.dtsi @@ -0,0 +1,55 @@ +#include "yupik-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>, + <0x0ae8f000 0x02c>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version = <0x70020000>; + + clocks = + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_cpucc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + qcom,sde-trusted-vm-env; + qcom,vram-size = <0x200000>; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; From 4be40443e86159e44291ba267da60f187b89a5c2 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Fri, 29 Jan 2021 18:16:27 +0800 Subject: [PATCH 298/362] ARM: dts: msm: enable RFI feature for 60hz panel on qrd yupik Add r66451 60hz cphy command mode panel for qrd yupik, and enable RFI and ESD check for this panel. Change-Id: Ibfbb942c4a2747db9b80b0c81cf9cef40803517b --- ...nel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi | 135 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 16 +++ display/yupik-sde-display-qrd.dtsi | 10 ++ display/yupik-sde-display.dtsi | 9 ++ 4 files changed, 170 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi new file mode 100644 index 000000000000..a6564f74dea3 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi @@ -0,0 +1,135 @@ +&mdss_mdp { + dsi_r66451_amoled_60hz_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_60hz_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 d1 0b + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 10 04 a0 00 09 40 + 39 01 00 00 00 00 2c c4 00 00 00 00 00 + 00 00 00 0d 00 00 05 00 00 00 36 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 0d 17 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 95 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3c 00 3c 00 3c 00 3c 00 + 3c 05 00 00 00 00 00 00 00 00 00 0e + 00 0e 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0e 00 36 00 0e 00 30 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 21 00 ff d4 0e 00 00 00 00 + 00 20 00 53 18 20 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 3b 08 04 9a + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 65a61e861a67..01eac6a41f47 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,5 +1,6 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" #include @@ -147,6 +148,21 @@ }; }; +&dsi_r66451_amoled_60hz_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <600652800 598150080 595647360>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1d 13 03 + 19 02 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_90hz_cmd_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi index 71120732ef0f..00b0f2d2a135 100644 --- a/display/yupik-sde-display-qrd.dtsi +++ b/display/yupik-sde-display-qrd.dtsi @@ -7,6 +7,16 @@ }; }; +&dsi_r66451_amoled_60hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_90hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index f79c40f89def..878e64cfb8cd 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -59,6 +59,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_r66451_amoled_60hz_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_90hz_cmd_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From 58aab5f1ceb3d184298a7dfda35d7d15e214307e Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 28 Jan 2021 11:58:47 +0800 Subject: [PATCH 299/362] ARM: dts: msm: add some more display modes for yupik qrd Add 144hz video, 120hz cmd, and video modes for qrd device. And also enable 120hz cmd dynamic fps switch, 144hz, and 120hz video dfps feature. Change-Id: I5a2e896cf0ad9c3ce8bfd8f4de421385ae98c15e --- ...el-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi | 383 ++++++++++++++++++ ...-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi | 121 ++++++ ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 1 - ...-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi | 123 ++++++ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 1 - display/yupik-sde-display-common.dtsi | 61 +++ display/yupik-sde-display-qrd.dtsi | 30 ++ display/yupik-sde-display.dtsi | 27 ++ 8 files changed, 745 insertions(+), 2 deletions(-) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi new file mode 100644 index 000000000000..ba037bc6840b --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi @@ -0,0 +1,383 @@ +&mdss_mdp { + dsi_r66451_amoled_120hz_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 00 00 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi new file mode 100644 index 000000000000..39e2b56a457a --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi @@ -0,0 +1,121 @@ +&mdss_mdp { + dsi_r66451_amoled_120hz_video_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_120hz_vid { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 6ff943606cce..782f933515b7 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -107,7 +107,6 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi new file mode 100644 index 000000000000..d72020ad1f71 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi @@ -0,0 +1,123 @@ +&mdss_mdp { + dsi_r66451_amoled_144hz_video_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi index a9aa91546d5c..1f2857b7c0cd 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -83,7 +83,6 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 65a61e861a67..d88190c5eac3 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,7 +1,10 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi" #include &soc { @@ -160,6 +163,49 @@ }; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1d 13 03 + 19 02 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1b 05 + 19 06 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_120hz_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1b 05 + 19 06 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; @@ -173,3 +219,18 @@ }; }; +&dsi_r66451_amoled_144hz_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi index e7a88a182bea..e8f03feb5565 100644 --- a/display/yupik-sde-display-qrd.dtsi +++ b/display/yupik-sde-display-qrd.dtsi @@ -26,6 +26,26 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_r66451_amoled_120hz_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -36,6 +56,16 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_r66451_amoled_144hz_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &sde_dsi { vddio-supply = <&L12C>; vdd-supply = <&L13C>; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7359e3d9d407..f11298e93a81 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -68,6 +68,24 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_120hz_video_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -76,3 +94,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_144hz_video_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 918e7c679ea72651b498d76c44ae74e888121c0b Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Mon, 1 Feb 2021 12:13:11 +0530 Subject: [PATCH 300/362] ARM: dts: msm: add display ramdump node for yupik target This change adds dt support for display during ramdump in yupik target. Change-Id: I9784e6bcd8ee787af42e9fa6fa30302adba385fa --- display/yupik-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 5367d035d47c..f664f6d65855 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -2,6 +2,11 @@ #include &soc { + disp_rdump_memory: disp_rdump_region@e1000000 { + reg = <0xe1000000 0x02300000>; + label = "disp_rdump_region"; + }; + ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; From 8a47423d1134b21b60f352fbac6f0216cea85893 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Tue, 2 Feb 2021 11:50:23 +0530 Subject: [PATCH 301/362] ARM: dts: msm: remove display related SPMI address for yupik target Remove display related SPMI address for yupik target. Change-Id: Ic42daf564cf9ed2edcd57ccc61d6662e32f8501e --- display/yupik-sde-common.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index fcdf37a6c5d4..16846daaf579 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -193,10 +193,6 @@ qcom,sde-secure-sid-mask = <0x901 0xD01>; - /* SPMI address related to display */ - qcom,pmic-arb = <&spmi_bus>; - qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; - qcom,sde-reg-bus,vectors-KBps = <0 0>, <0 74000>, <0 148000>, From 86798cd792f0a56bfb9c7ee00f8d472442fdea08 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 2 Feb 2021 18:09:12 +0530 Subject: [PATCH 302/362] ARM: dts: msm: Add 120Hz Video mode support on yupik Add 120Hz nt36672e Video mode panel support on yupik idp platform. Also, enable DFPS and ESD feature for the panel. Change-Id: Ic8e0bf998c3ebf83fba917389754326b39bbac96 --- display/yupik-sde-display-common.dtsi | 16 ++++++++++++++++ display/yupik-sde-display-idp.dtsi | 8 ++++++++ display/yupik-sde-display.dtsi | 9 +++++++++ 3 files changed, 33 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 4412e52d98c2..237b335586e3 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,4 +1,5 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" @@ -139,6 +140,21 @@ }; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-supported-dfps-list = <120 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 + 08 08 02 04 00 1b 18]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index d3886dad50f1..4fcaf173b2b8 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -8,6 +8,14 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 6a9ebe422387..82bc6fd4768d 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -59,6 +59,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_60hz_cmd_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From 2cbef2e554e660f17f1be30d590adc9f05213e10 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Wed, 3 Feb 2021 18:22:16 +0530 Subject: [PATCH 303/362] ARM: dts: msm: enable qsync along with VRR in yupik target This change enables qsync support for yupik target along with existing VRR. Change-Id: I6c238fa1bce3102744c10b2b3a2c678773adb922 --- display/yupik-sde-display-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 237b335586e3..4de9ed87f6fa 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -130,6 +130,7 @@ qcom,dsi-supported-dfps-list = <144 120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-qsync-min-refresh-rate = <48>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -145,6 +146,7 @@ qcom,dsi-supported-dfps-list = <120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-qsync-min-refresh-rate = <48>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 From 4fb81e7ec851b51c9137592a297f0cce59abc1cc Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Fri, 5 Feb 2021 17:46:07 +0530 Subject: [PATCH 304/362] ARM: dts: msm: Add display support for r66451 120fps panel Add r66451 120fps display cphy panel support on Yupik target. Change-Id: Ia295e22add42916343e7c12b3fdd64375ebb8d08 --- display/yupik-sde-display-idp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 4fcaf173b2b8..045d7c6ac25f 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -34,6 +34,16 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From eb8600cf9ace74f00ca3647bf24b17bca3fc559c Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 1 Feb 2021 21:00:23 +0530 Subject: [PATCH 305/362] ARM: dts: msm: Enable Dynamic clock on yupik IDP Enable Dynamic clock for 144Hz and 120Hz Video mode panel on yupik IDP platform. Change-Id: Ic1df031247fdcc3782d3a2ce231c02524deba74e --- display/yupik-sde-display-common.dtsi | 16 ++++++++++++++-- display/yupik-sde.dtsi | 1 + 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 4de9ed87f6fa..acb348abab67 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -126,11 +126,17 @@ }; &dsi_nt36672e_fhd_plus_144_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-supported-dfps-list = <144 120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-qsync-min-refresh-rate = <48>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <953341056 946720632 950030848>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -142,11 +148,17 @@ }; &dsi_nt36672e_fhd_plus_120_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-supported-dfps-list = <120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-qsync-min-refresh-rate = <48>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <901327680 893816616 897572152>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index f664f6d65855..43f616b8e540 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -207,5 +207,6 @@ vdda-0p9-supply = <&L10C>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; From 8f91e06a17ad79ac91f833e62844291737fe8938 Mon Sep 17 00:00:00 2001 From: Chandan Uddaraju Date: Fri, 29 Jan 2021 17:35:57 -0800 Subject: [PATCH 306/362] ARM: dts: msm: add dispcc clock reference for dsi-display nodes Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes for cont_splash use case. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I47c458f4f6f2937effdd1212496b41eacab4e052 --- display/lahaina-sde-display.dtsi | 41 ++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 685fd53fd828..c448cca46045 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -1,4 +1,5 @@ #include "lahaina-sde-display-common.dtsi" +#include &tlmm { display_panel_avdd_default: display_panel_avdd_default { @@ -59,7 +60,22 @@ <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", @@ -69,7 +85,8 @@ "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", "shadow_byte_clk1", "shadow_pixel_clk1", - "shadow_cphybyte_clk1", "shadow_cphypixel_clk1"; + "shadow_cphybyte_clk1", "shadow_cphypixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -93,11 +110,27 @@ <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; + "cphy_byte_clk1", "cphy_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; From 7e1423a5592819669cbf79ac054e8ee94d701565 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Tue, 2 Feb 2021 10:51:25 +0530 Subject: [PATCH 307/362] ARM: dts: msm: add dispcc clock reference for dsi-display nodes Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I4c4baf15171a13a066a3383bdc1242279809444d --- display/shima-sde-display.dtsi | 41 ++++++++++++++++++++++++++++++---- display/yupik-sde-display.dtsi | 21 +++++++++++++++-- 2 files changed, 56 insertions(+), 6 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index d7f3efc6ec23..2f3634ba7b7a 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,4 +1,5 @@ #include "shima-sde-display-common.dtsi" +#include &soc { sde_wb: qcom,wb-display@0 { @@ -24,7 +25,22 @@ <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", @@ -32,7 +48,8 @@ "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; + "shadow_byte_clk1", "shadow_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -55,11 +72,27 @@ <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; + "cphy_byte_clk1", "cphy_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7359e3d9d407..d371070af713 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -1,4 +1,5 @@ #include "yupik-sde-display-common.dtsi" +#include &soc { sde_wb: qcom,wb-display@0 { @@ -18,12 +19,28 @@ <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", - "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; From a99804f01a5ff4e18734970941cf39829574900c Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Mon, 15 Feb 2021 18:17:10 +0530 Subject: [PATCH 308/362] ARM: dts: msm: Add 60fps display support on Lahaina MTP 2.1 This change adds display support for r66451 dsc fhd plus 60fps command mode panel on lahaina. Change-Id: Icec5feb452347aef02d69fe15f86717f7b4852fe --- display/lahaina-sde-display-common.dtsi | 24 ++++++++++++++++++++++++ display/lahaina-sde-display-mtp.dtsi | 10 ++++++++++ 2 files changed, 34 insertions(+) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 7b54b749014e..1db49fb02ed8 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -15,6 +15,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" @@ -273,6 +274,29 @@ }; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <327096544 325733641 324370739>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1e 1e 04 + 04 03 02 04 00 10 14]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_144hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index ad1eb186123b..0d39900163fc 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -28,6 +28,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_r66451_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 40974ef71f498bed320388f61566b8011ecaca11 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 19 Feb 2021 19:54:09 +0530 Subject: [PATCH 309/362] ARM: dts: msm: Update 120Hz Video as default on yupik svm Update 120Hz Video mode as default panel on yupik idp LA and LE dtsi. Change-Id: I94f9220ce90bd73a0cc9037934514ea66cfb544e --- display/trustedvm-yupik-sde-display.dtsi | 2 +- display/yupik-sde-display-idp.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-yupik-sde-display.dtsi b/display/trustedvm-yupik-sde-display.dtsi index 7919d11a4a16..be0b4c27acca 100644 --- a/display/trustedvm-yupik-sde-display.dtsi +++ b/display/trustedvm-yupik-sde-display.dtsi @@ -17,7 +17,7 @@ "shadow_byte_clk0", "shadow_pixel_clk0", "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; qcom,panel-te-source = <0>; - qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; }; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 045d7c6ac25f..e27b789918f7 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -55,6 +55,6 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; }; From a34920365b7bc9274a256451d0771aeef4c4830b Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Tue, 2 Feb 2021 10:51:25 +0530 Subject: [PATCH 310/362] ARM: dts: msm: add dispcc clock reference for dsi-display nodes Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I4c4baf15171a13a066a3383bdc1242279809444d --- display/shima-sde-display.dtsi | 41 ++++++++++++++++++++++++++++++---- display/yupik-sde-display.dtsi | 21 +++++++++++++++-- 2 files changed, 56 insertions(+), 6 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index d7f3efc6ec23..2f3634ba7b7a 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,4 +1,5 @@ #include "shima-sde-display-common.dtsi" +#include &soc { sde_wb: qcom,wb-display@0 { @@ -24,7 +25,22 @@ <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", @@ -32,7 +48,8 @@ "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; + "shadow_byte_clk1", "shadow_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -55,11 +72,27 @@ <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; + "cphy_byte_clk1", "cphy_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 82bc6fd4768d..317dee45b7ec 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -1,4 +1,5 @@ #include "yupik-sde-display-common.dtsi" +#include &soc { sde_wb: qcom,wb-display@0 { @@ -18,12 +19,28 @@ <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", - "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; From 1de242e11b0393b134fc9dd406f30b15fa0a15ee Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Mon, 15 Feb 2021 18:17:10 +0530 Subject: [PATCH 311/362] ARM: dts: msm: Add 60fps display support on Lahaina MTP 2.1 This change adds display support for r66451 dsc fhd plus 60fps command mode panel on lahaina. Change-Id: Icec5feb452347aef02d69fe15f86717f7b4852fe --- display/lahaina-sde-display-common.dtsi | 24 ++++++++++++++++++++++++ display/lahaina-sde-display-mtp.dtsi | 10 ++++++++++ 2 files changed, 34 insertions(+) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 7b54b749014e..1db49fb02ed8 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -15,6 +15,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" @@ -273,6 +274,29 @@ }; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <327096544 325733641 324370739>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1e 1e 04 + 04 03 02 04 00 10 14]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_144hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index ad1eb186123b..0d39900163fc 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -28,6 +28,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_r66451_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 525048614fdbcf46b0e841a3e23f82780f804a32 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Fri, 26 Feb 2021 12:55:14 +0530 Subject: [PATCH 312/362] ARM: dts: msm: reduce transfer time by 100 usec in yupik target This change reduces transfer time by 100 usec for 144fps and 120 fps in yupik. Change-Id: Ib92ecba8dcc4779b636c6c8efa926d5af7d1ffc4 --- display/yupik-sde-display-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index acb348abab67..9b6d97247d27 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -232,6 +232,7 @@ 19 06 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,mdss-mdp-transfer-time-us = <7550>; }; }; }; @@ -261,6 +262,7 @@ 19 07 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,mdss-mdp-transfer-time-us = <6210>; }; }; }; From 8788b51f79f0d0de0dec652f78fcffa9f3845f94 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 3 Feb 2021 12:57:11 +0800 Subject: [PATCH 313/362] ARM: dts: msm: Enable fps switch for 144Hz cphy on yupik qrd Enable 144/120/60 Hz fps switch feature for 144Hz cphy command mode panel on yupik qrd platform. Change-Id: I1343c6419c07b80b93f9572d891c005a7c4c8383 --- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 249 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 14 + 2 files changed, 263 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 782f933515b7..5938221c9fcc 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -48,6 +48,18 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 04 00 00 00 09 34 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 @@ -113,7 +125,244 @@ 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + timing@1 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 00 00 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; qcom,mdss-dsi-off-command = [ 05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 9b6d97247d27..fae8e0561940 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -264,6 +264,20 @@ qcom,default-topology-index = <0>; qcom,mdss-mdp-transfer-time-us = <6210>; }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1d 13 03 + 19 02 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1b 05 + 19 06 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; }; }; From 6469430307e6da3a0757934e647f7d382e9203be Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Fri, 26 Feb 2021 12:55:14 +0530 Subject: [PATCH 314/362] ARM: dts: msm: reduce transfer time by 100 usec in yupik target This change reduces transfer time by 100 usec for 144fps and 120 fps in yupik. Change-Id: Ib92ecba8dcc4779b636c6c8efa926d5af7d1ffc4 --- display/yupik-sde-display-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index acb348abab67..9b6d97247d27 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -232,6 +232,7 @@ 19 06 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,mdss-mdp-transfer-time-us = <7550>; }; }; }; @@ -261,6 +262,7 @@ 19 07 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,mdss-mdp-transfer-time-us = <6210>; }; }; }; From 5c0d0ba35b0edfb8165c111c4913d4180095d615 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Mon, 8 Mar 2021 10:59:00 +0530 Subject: [PATCH 315/362] ARM: dts: msm: remove fixed transfer time for cphy panels in yupik This change reverts commit 8198c2b43d6e ("reduce transfer time by 100 usec in yupik target"). The oriGinal issue of unstable fps on cphy panels will be fixed with commit 72f31fb34bc3 ("disp: msm: dsi: update CPHY command mode clock calculation"). Change-Id: I57ab55416c1fd264b49f9097738942c2b9471096 --- display/yupik-sde-display-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index fae8e0561940..fd0475cfcb0b 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -232,7 +232,6 @@ 19 06 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; - qcom,mdss-mdp-transfer-time-us = <7550>; }; }; }; @@ -262,7 +261,6 @@ 19 07 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; - qcom,mdss-mdp-transfer-time-us = <6210>; }; timing@1 { From d210a65f0ec7390781065d25ada7c9089811a474 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Tue, 9 Mar 2021 11:01:12 +0530 Subject: [PATCH 316/362] ARM: dts: msm: add scaler max line width for yupik target This change adds check for max line width for scaling in yupik target. Change-Id: Iec4ca10b7f52cdbedd53c9b0de17cf9d573170a9 --- display/yupik-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index 16846daaf579..e44b556dac4a 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -125,6 +125,7 @@ qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <2400>; qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; qcom,sde-wb-linewidth = <4096>; qcom,sde-wb-linewidth-linear = <4096>; qcom,sde-mixer-blendstages = <0x9>; From 06c5964ad6c49c25fbc17d01da4845d11281d90e Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 10 Mar 2021 16:04:13 +0530 Subject: [PATCH 317/362] ARM: dts: msm: Remove timing nodes from sim panel Remove timing nodes from dual dsi dsc sim panel to reduce dtbo image size. Change-Id: I6cabb57da9b49420f3f731f54eb7ef5ef183dcec --- .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 1448 ----------------- display/kona-sde-display.dtsi | 112 -- display/lahaina-sde-display-common.dtsi | 126 -- 3 files changed, 1686 deletions(-) diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index 6b5a5b7f04f9..4087a2219dd8 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -89,1454 +89,6 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; - - timing@1 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <90>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@3 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@4 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <30>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@5 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@6 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <90>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@7 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@8 { - qcom,mdss-dsi-panel-framerate = <30>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@9 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@10 { - qcom,mdss-dsi-panel-framerate = <90>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@11 { - qcom,mdss-dsi-panel-framerate = <120>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@12 { - qcom,mdss-dsi-panel-width = <2520>; - qcom,mdss-dsi-panel-height = <2160>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <1080>; - qcom,mdss-dsc-slice-width = <1260>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@13 { - qcom,mdss-dsi-panel-width = <360>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <30>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@14 { - qcom,mdss-dsi-panel-width = <360>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@15 { - qcom,mdss-dsi-panel-width = <360>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <90>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@16 { - qcom,mdss-dsi-panel-width = <360>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@17 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <144>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@18 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <144>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; }; }; }; diff --git a/display/kona-sde-display.dtsi b/display/kona-sde-display.dtsi index a477f44fffc0..00c36cf8e166 100644 --- a/display/kona-sde-display.dtsi +++ b/display/kona-sde-display.dtsi @@ -721,118 +721,6 @@ qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; - - timing@1 { /* 4k 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 - 06 04 02 04 00 15 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* 4k 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 09 - 09 06 02 04 00 1c 19]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4k 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 29 27 0c - 0c 08 02 04 00 24 1b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@4 { /* 1080 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 - 01 01 02 04 00 0a 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@5 { /* 1080 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 02 01 02 04 00 0c 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@6 { /* 1080 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 - 03 02 02 04 00 0e 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@7 { /* 1080 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1e 1e 04 - 04 02 02 04 00 10 14]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@8 { /* qhd 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 - 02 01 02 04 00 0b 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@9 { /* qhd 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 1e 1d 04 - 04 02 02 04 00 0f 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@10 { /* qhd 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05 - 05 03 02 04 00 12 15]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@11 { /* qhd 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07 - 06 04 02 04 00 15 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@12 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07 - 07 04 02 04 00 16 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@13 { /* 720p 30 FPS */ - qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1a 1a 01 - 01 00 02 04 00 08 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@14 { /* 720p 60 FPS */ - qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 - 01 01 02 04 00 0a 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@15 { /* 720p 90 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 - 02 01 02 04 00 0b 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@16 { /* 720 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 03 01 02 04 00 0c 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; }; }; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 1db49fb02ed8..35e4b962161f 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -752,132 +752,6 @@ qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; - - timing@1 { /* 4k 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 - 05 03 02 04 00 10 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* 4k 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08 - 08 05 02 04 00 16 0c]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4k 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a - 0a 07 02 04 00 1d 0e]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@4 { /* 1080 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01 - 01 01 02 04 00 05 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@5 { /* 1080 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 - 02 01 02 04 00 08 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@6 { /* 1080 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@7 { /* 1080 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 - 04 02 02 04 00 0c 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@8 { /* qhd 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02 - 01 00 02 04 00 06 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@9 { /* qhd 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@10 { /* qhd 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04 - 04 02 02 04 00 0c 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@11 { /* qhd 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 - 05 03 02 04 00 0f 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@12 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 - 07 04 02 04 00 14 0b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@13 { /* 720p 30 FPS */ - qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01 - 01 00 02 04 00 04 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@14 { /* 720p 60 FPS */ - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@15 { /* 720p 90 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02 - 02 01 02 04 00 07 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@16 { /* 720 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03 - 03 01 02 04 00 08 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@17 { /* 1080 144FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 - 06 06 02 04 00 13 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@18 { /* WQHD 144 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a - 0a 07 02 04 00 1d 0e]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; }; }; From 2990f83b1a6299968e927aac531cbf476061ac48 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Mon, 8 Mar 2021 10:59:00 +0530 Subject: [PATCH 318/362] ARM: dts: msm: remove fixed transfer time for cphy panels in yupik This change reverts commit 8198c2b43d6e ("reduce transfer time by 100 usec in yupik target"). The oriGinal issue of unstable fps on cphy panels will be fixed with commit 72f31fb34bc3 ("disp: msm: dsi: update CPHY command mode clock calculation"). Change-Id: I57ab55416c1fd264b49f9097738942c2b9471096 --- display/yupik-sde-display-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index fae8e0561940..fd0475cfcb0b 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -232,7 +232,6 @@ 19 06 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; - qcom,mdss-mdp-transfer-time-us = <7550>; }; }; }; @@ -262,7 +261,6 @@ 19 07 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; - qcom,mdss-mdp-transfer-time-us = <6210>; }; timing@1 { From 2c3ad79068fb4231ec1c5d83836dbdb20444b57e Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Thu, 18 Mar 2021 19:55:21 -0700 Subject: [PATCH 319/362] Revert "ARM: dts: msm: Enable fps switch for 144Hz cphy on yupik qrd" This reverts commit ec7a16dbf560151872df441c3e4236f71197a379. Change-Id: I04b592bbba95490f87ebade2a36df742cc447e76 --- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 249 ------------------ display/yupik-sde-display-common.dtsi | 14 - 2 files changed, 263 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 5938221c9fcc..782f933515b7 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -48,18 +48,6 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 0d d0 44 44 b2 28 00 - 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 1a c2 09 24 0c 00 00 - 04 00 00 00 09 34 00 00 00 00 00 00 - 00 00 00 00 00 30 00 6c - 39 01 00 00 00 00 34 d8 00 00 00 00 00 - 00 00 00 00 30 00 30 00 30 00 30 00 - 30 05 00 00 00 00 00 00 00 00 00 0f - 00 0f 00 00 00 00 00 00 00 00 00 00 - 00 00 00 0f 00 2f 00 0f 00 20 - ]; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 @@ -125,244 +113,7 @@ 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <20>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - timing@1 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <96>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <32>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 34 d8 00 00 00 00 00 - 00 00 00 00 3a 00 3a 00 3a 00 3a 00 - 3a 05 00 00 00 00 00 00 00 00 00 0f - 00 0f 00 00 00 00 00 00 00 00 00 00 - 00 00 00 0f 00 2f 00 0f 00 20 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 1a c2 09 24 0c 00 00 - 0c 09 3c 00 09 3c 00 00 00 00 00 00 - 00 00 00 00 00 30 00 6c - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 03 e8 00 02 - 39 01 00 00 00 00 03 e4 00 08 - 39 01 00 00 00 00 03 b4 20 1c - 39 01 00 00 00 00 0d b6 6c 00 06 23 af - 13 1a 05 04 fa 05 20 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 32 c4 00 00 00 00 00 - 00 00 00 10 00 00 02 00 00 00 29 00 - 01 00 00 00 00 00 00 00 00 00 00 00 - 22 00 00 00 00 11 00 00 0c 00 00 00 - 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 0d d0 44 44 b2 28 00 - 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d - 39 01 00 00 00 00 15 d3 49 00 00 01 1a - 15 00 15 07 0f 77 77 77 37 b2 11 00 - a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f - 39 01 00 00 00 00 34 d8 00 00 00 00 00 - 00 00 00 00 30 00 30 00 30 00 30 00 - 30 05 00 00 00 00 00 00 00 00 00 0f - 00 0f 00 00 00 00 00 00 00 00 00 00 - 00 00 00 0f 00 2f 00 0f 00 20 - 39 01 00 00 00 00 2b df 50 42 58 81 2d - 00 00 00 00 00 00 6b 00 00 00 00 00 - 00 00 00 01 0f ff d4 0e 00 00 00 00 - 00 00 0f 53 18 00 0f 00 00 00 00 00 - 00 - 39 01 00 00 00 00 03 eb 8b 8b - 39 01 00 00 00 00 02 f7 01 - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 0a e4 34 b4 00 00 00 - 30 04 0c e2 - 39 01 00 00 00 00 02 e6 00 - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 03 df 50 40 - 39 01 00 00 00 00 06 f3 50 00 00 00 00 - 39 01 00 00 00 00 02 f2 11 - 39 01 00 00 00 00 06 f3 01 00 00 00 01 - 39 01 00 00 00 00 03 f4 00 02 - 39 01 00 00 00 00 02 f2 19 - 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 2a 00 00 04 37 - 39 01 00 00 00 00 05 2b 00 00 09 23 - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 - 39 01 00 00 00 00 0d d0 44 44 b2 28 00 - 28 5a 00 5a 03 03 01 - 39 01 00 00 00 00 34 d8 00 00 00 00 00 - 00 00 00 00 3a 00 3a 00 3a 00 3a 00 - 3a 05 00 00 00 00 00 00 00 00 00 0f - 00 0f 00 00 00 00 00 00 00 00 00 00 - 00 00 00 0f 00 2f 00 0f 00 20 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 1a c2 09 24 0c 00 00 - 0c 09 3c 00 09 3c 00 00 00 00 00 00 - 00 00 00 00 00 30 00 6c - ]; - - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <20>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-framerate = <120>; - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <96>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <32>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 0d d0 44 44 b2 28 00 - 28 5a 00 5a 03 03 01 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 1a c2 09 24 0c 00 00 - 0c 00 00 00 09 3c 00 00 00 00 00 00 - 00 00 00 00 00 30 00 6c - 39 01 00 00 00 00 34 d8 00 00 00 00 00 - 00 00 00 00 3a 00 3a 00 3a 00 3a 00 - 3a 05 00 00 00 00 00 00 00 00 00 0f - 00 0f 00 00 00 00 00 00 00 00 00 00 - 00 00 00 0f 00 2f 00 0f 00 20 - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 03 e8 00 02 - 39 01 00 00 00 00 03 e4 00 08 - 39 01 00 00 00 00 03 b4 20 1c - 39 01 00 00 00 00 0d b6 6c 00 06 23 af - 13 1a 05 04 fa 05 20 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 32 c4 00 00 00 00 00 - 00 00 00 10 00 00 02 00 00 00 29 00 - 01 00 00 00 00 00 00 00 00 00 00 00 - 22 00 00 00 00 11 00 00 0c 00 00 00 - 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 0d d0 44 44 b2 28 00 - 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d - 39 01 00 00 00 00 15 d3 49 00 00 01 1a - 15 00 15 07 0f 77 77 77 37 b2 11 00 - a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f - 39 01 00 00 00 00 34 d8 00 00 00 00 00 - 00 00 00 00 30 00 30 00 30 00 30 00 - 30 05 00 00 00 00 00 00 00 00 00 0f - 00 0f 00 00 00 00 00 00 00 00 00 00 - 00 00 00 0f 00 2f 00 0f 00 20 - 39 01 00 00 00 00 2b df 50 42 58 81 2d - 00 00 00 00 00 00 6b 00 00 00 00 00 - 00 00 00 01 0f ff d4 0e 00 00 00 00 - 00 00 0f 53 18 00 0f 00 00 00 00 00 - 00 - 39 01 00 00 00 00 03 eb 8b 8b - 39 01 00 00 00 00 02 f7 01 - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 0a e4 34 b4 00 00 00 - 30 04 0c e2 - 39 01 00 00 00 00 02 e6 00 - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 03 df 50 40 - 39 01 00 00 00 00 06 f3 50 00 00 00 00 - 39 01 00 00 00 00 02 f2 11 - 39 01 00 00 00 00 06 f3 01 00 00 00 01 - 39 01 00 00 00 00 03 f4 00 02 - 39 01 00 00 00 00 02 f2 19 - 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 2a 00 00 04 37 - 39 01 00 00 00 00 05 2b 00 00 09 23 - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 - 39 01 00 00 00 00 0d d0 44 44 b2 28 00 - 28 5a 00 5a 03 03 01 - 39 01 00 00 00 00 34 d8 00 00 00 00 00 - 00 00 00 00 3a 00 3a 00 3a 00 3a 00 - 3a 05 00 00 00 00 00 00 00 00 00 0f - 00 0f 00 00 00 00 00 00 00 00 00 00 - 00 00 00 0f 00 2f 00 0f 00 20 - ]; qcom,mdss-dsi-off-command = [ 05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index fd0475cfcb0b..acb348abab67 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -262,20 +262,6 @@ qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1d 13 03 - 19 02 02 04 00 00 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1b 05 - 19 06 02 04 00 00 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; }; }; From 839a53d7cfddcf86bd4afdc96615b6069bca700a Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Fri, 19 Mar 2021 15:23:17 +0800 Subject: [PATCH 320/362] ARM: dts: msm: Update dsi-on-command to fix brightness issue on yupik qrd Update dsi-on-command to fix low brightness issue on yupik qrd. Change-Id: I29c4747229a16d205b2fe888ac5e954ae5273b4c --- ...el-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi | 57 ++----------------- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 57 ++----------------- ...nel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi | 18 ------ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 17 ------ 4 files changed, 12 insertions(+), 137 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi index ba037bc6840b..a956720ea3b1 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi @@ -79,26 +79,9 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -139,6 +122,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -196,26 +181,9 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -256,6 +224,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -313,26 +283,9 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -369,6 +322,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 5938221c9fcc..408f668ba110 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -73,28 +73,11 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -130,6 +113,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -182,28 +167,11 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -251,6 +219,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -304,28 +274,11 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -368,6 +321,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi index a6564f74dea3..e7b81243224f 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi @@ -62,28 +62,11 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 0d 17 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 95 - 39 01 00 00 00 00 1a d7 00 b9 40 00 40 - 00 00 e0 0e 00 40 00 00 00 00 00 00 - 19 40 00 00 00 00 e0 0e 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3c 00 3c 00 3c 00 3c 00 3c 05 00 00 00 00 00 00 00 00 00 0e @@ -108,7 +91,6 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi index 1f2857b7c0cd..e59208eb7b21 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -57,23 +57,6 @@ 13 1a 05 04 fa 05 20 39 01 00 00 00 00 0c c2 09 24 0c 00 00 10 00 00 00 09 40 - 39 01 00 00 00 00 1a d7 00 b9 40 00 40 - 00 00 e0 0e 00 40 00 00 00 00 00 00 - 19 40 00 00 00 00 e0 0e - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 03 df 50 40 From 6b0496abc17c1172c6fd8c33d1464605b458ab29 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Tue, 6 Apr 2021 18:56:28 +0530 Subject: [PATCH 321/362] ARM: dts: msm: Add support for sim vid panel on Yupik This change adds support for sim vid panel on Yupik. Change-Id: If43074bfd2ffd20e277e2c80a092b6ac27fdaafd --- display/yupik-sde-display-common.dtsi | 13 +++++++++++++ display/yupik-sde-display-idp.dtsi | 6 ++++++ display/yupik-sde-display-qrd.dtsi | 6 ++++++ 3 files changed, 25 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index fd0475cfcb0b..3f1debe20f9b 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -7,6 +7,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi" +#include "dsi-panel-sim-video.dtsi" #include &soc { @@ -294,3 +295,15 @@ }; }; }; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index e27b789918f7..26f690f77de3 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -54,6 +54,12 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; }; diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi index dbd96c47b950..c03b994e5eea 100644 --- a/display/yupik-sde-display-qrd.dtsi +++ b/display/yupik-sde-display-qrd.dtsi @@ -76,6 +76,12 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &sde_dsi { vddio-supply = <&L12C>; vdd-supply = <&L13C>; From 7be7839a4e48e4fd1fa5e2a8e2899d555012b333 Mon Sep 17 00:00:00 2001 From: Thirupathi Reddy R Date: Fri, 9 Apr 2021 17:48:19 +0530 Subject: [PATCH 322/362] ARM: dts: msm: Enable fps switch for 144Hz cphy on yupik qrd Enable 144/120/60 Hz fps switch feature for 144Hz cphy command mode panel on yupik qrd platform Change-Id: I53699bc562215a2bbcd3aa32ae0698a3139caaba Signed-off-by: Thirupathi Reddy R --- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 249 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 14 + 2 files changed, 263 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 782f933515b7..5938221c9fcc 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -48,6 +48,18 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 04 00 00 00 09 34 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 @@ -113,7 +125,244 @@ 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + timing@1 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 00 00 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; qcom,mdss-dsi-off-command = [ 05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index acb348abab67..fd0475cfcb0b 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -262,6 +262,20 @@ qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1d 13 03 + 19 02 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1b 05 + 19 06 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; }; }; From 81989d33da1588c5f9ded208154467a6d8184e78 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 26 Apr 2021 19:06:47 +0530 Subject: [PATCH 323/362] Revert "ARM: dts: msm: Update dsi-on-command to fix brightness issue on yupik qrd" This reverts commit 50b8070a9106ad630e55361bb703ffc953e8fa94. Change-Id: I1656aba5ff0dc3733cc0cf044604Montana8ffab922a --- ...el-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi | 57 +++++++++++++++++-- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 57 +++++++++++++++++-- ...nel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi | 18 ++++++ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 17 ++++++ 4 files changed, 137 insertions(+), 12 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi index a956720ea3b1..ba037bc6840b 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi @@ -79,9 +79,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -122,8 +139,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -181,9 +196,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -224,8 +256,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -283,9 +313,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -322,8 +369,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 408f668ba110..5938221c9fcc 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -73,11 +73,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -113,8 +130,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -167,11 +182,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -219,8 +251,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -274,11 +304,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -321,8 +368,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi index e7b81243224f..a6564f74dea3 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi @@ -62,11 +62,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 0d 17 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 95 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3c 00 3c 00 3c 00 3c 00 3c 05 00 00 00 00 00 00 00 00 00 0e @@ -91,6 +108,7 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi index e59208eb7b21..1f2857b7c0cd 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -57,6 +57,23 @@ 13 1a 05 04 fa 05 20 39 01 00 00 00 00 0c c2 09 24 0c 00 00 10 00 00 00 09 40 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 03 df 50 40 From c0f69efe5472c038290fbd3b54b51f62a730159b Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 26 Apr 2021 19:06:47 +0530 Subject: [PATCH 324/362] Revert "ARM: dts: msm: Update dsi-on-command to fix brightness issue on yupik qrd" This reverts commit 50b8070a9106ad630e55361bb703ffc953e8fa94. Change-Id: I1656aba5ff0dc3733cc0cf044604Montana8ffab922a --- ...el-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi | 57 +++++++++++++++++-- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 57 +++++++++++++++++-- ...nel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi | 18 ++++++ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 17 ++++++ 4 files changed, 137 insertions(+), 12 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi index a956720ea3b1..ba037bc6840b 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi @@ -79,9 +79,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -122,8 +139,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -181,9 +196,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -224,8 +256,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -283,9 +313,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -322,8 +369,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 408f668ba110..5938221c9fcc 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -73,11 +73,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -113,8 +130,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -167,11 +182,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -219,8 +251,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -274,11 +304,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -321,8 +368,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi index e7b81243224f..a6564f74dea3 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi @@ -62,11 +62,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 0d 17 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 95 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3c 00 3c 00 3c 00 3c 00 3c 05 00 00 00 00 00 00 00 00 00 0e @@ -91,6 +108,7 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi index e59208eb7b21..1f2857b7c0cd 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -57,6 +57,23 @@ 13 1a 05 04 fa 05 20 39 01 00 00 00 00 0c c2 09 24 0c 00 00 10 00 00 00 09 40 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 03 df 50 40 From 457d25b65cbd7181e89f4935a72ec2bca0b10eee Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 29 Apr 2021 16:32:25 +0530 Subject: [PATCH 325/362] ARM: dts: msm: Add NT36672E 90hz Video Mode Panel on Yupik IDP Add NT36672E 90fps fhd plus Video mode panel support on yupik platform. Change-Id: Ic1506e239f8d473c8bd005591905429d0ea993d4 --- ...si-panel-nt36672e-fhd-plus-90hz-video.dtsi | 480 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 13 + display/yupik-sde-display-idp.dtsi | 8 + 3 files changed, 501 insertions(+) create mode 100644 display/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi diff --git a/display/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi new file mode 100644 index 000000000000..02f1cee08a1a --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi @@ -0,0 +1,480 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_90hz_video: qcom,mdss_dsi_nt36672e_fhd_plus_90hz_video { + qcom,mdss-dsi-panel-name = + "nt36672e 90Hz fhd plus video mode panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750 + 39800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <68>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 C0 03 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 39 01 00 00 00 00 03 C2 1B A0 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 66 + 39 01 00 00 00 00 02 06 40 + 39 01 00 00 00 00 02 07 38 + 39 01 00 00 00 00 02 18 66 + 39 01 00 00 00 00 02 1B 01 + 39 01 00 00 00 00 02 5C 90 + 39 01 00 00 00 00 02 5E AA + 39 01 00 00 00 00 02 69 91 + + 39 01 00 00 00 00 02 89 0D + 39 01 00 00 00 00 02 8A 0D + 39 01 00 00 00 00 02 8D 0D + 39 01 00 00 00 00 02 8E 0D + 39 01 00 00 00 00 02 8F 0D + 39 01 00 00 00 00 02 91 0D + + 39 01 00 00 00 00 02 95 D1 + 39 01 00 00 00 00 02 96 D1 + 39 01 00 00 00 00 02 F2 65 + 39 01 00 00 00 00 02 F3 64 + 39 01 00 00 00 00 02 F4 65 + 39 01 00 00 00 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20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3 + 39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E + 39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F + 39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1 + 39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28 + 39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63 + 39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3 + 39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26 + 39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61 + 39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00 + + 39 01 00 00 00 00 02 C6 00 + 39 01 00 00 00 00 02 C7 00 + 39 01 00 00 00 00 02 C8 00 + 39 01 00 00 00 00 02 C9 00 + 39 01 00 00 00 00 02 CA 00 + + 39 01 00 00 00 00 02 CB 00 + 39 01 00 00 00 00 02 CC 00 + 39 01 00 00 00 00 02 CD 00 + 39 01 00 00 00 00 02 CE 00 + 39 01 00 00 00 00 02 CF 00 + + 39 01 00 00 00 00 02 D0 00 + 39 01 00 00 00 00 02 D1 00 + 39 01 00 00 00 00 02 D2 00 + 39 01 00 00 00 00 02 D3 00 + 39 01 00 00 00 00 02 D4 00 + + 39 01 00 00 00 00 02 D5 00 + 39 01 00 00 00 00 02 D6 00 + 39 01 00 00 00 00 02 D7 00 + 39 01 00 00 00 00 02 D8 00 + 39 01 00 00 00 00 02 D9 00 + + 39 01 00 00 00 00 02 DA 00 + 39 01 00 00 00 00 02 DB 00 + 39 01 00 00 00 00 02 DC 00 + 39 01 00 00 00 00 02 DD 00 + 39 01 00 00 00 00 02 DE 00 + + 39 01 00 00 00 00 02 DF 00 + 39 01 00 00 00 00 02 E0 00 + 39 01 00 00 00 00 02 E1 00 + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 E3 00 + + 39 01 00 00 00 00 02 E4 00 + 39 01 00 00 00 00 02 E5 00 + 39 01 00 00 00 00 02 E6 00 + 39 01 00 00 00 00 02 E7 00 + 39 01 00 00 00 00 02 E8 00 + 39 01 00 00 00 00 02 E9 00 + + + 39 01 00 00 00 00 02 FF 21 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3 + 39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E + 39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F + 39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1 + 39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28 + 39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63 + 39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3 + 39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26 + 39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61 + 39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00 + + 39 01 00 00 00 00 02 FF E0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 35 82 + 39 01 00 00 00 00 02 85 32 + + 39 01 00 00 00 00 02 FF F0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 1C 01 + 39 01 00 00 00 00 02 33 01 + 39 01 00 00 00 00 02 5A 00 + + 39 01 00 00 00 00 02 FF D0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 53 22 + 39 01 00 00 00 00 02 54 02 + + 39 01 00 00 00 00 02 FF C0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 9C 11 + 39 01 00 00 00 00 02 9D 11 + + 39 01 00 00 00 00 02 FF 2B + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B7 0A + 39 01 00 00 00 00 02 B8 1C + 39 01 00 00 00 00 02 C0 01 + + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 35 01 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 28 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 3f1debe20f9b..5b31658f12e6 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,5 +1,6 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" @@ -170,6 +171,18 @@ }; }; +&dsi_nt36672e_fhd_plus_90hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 + 06 07 02 04 00 16 16]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 26f690f77de3..1b1fcd8a6792 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -16,6 +16,14 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_nt36672e_fhd_plus_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; From d0a1e1f475bfe2fd8c1a3c4d9e8725d1589b9528 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Thu, 22 Apr 2021 13:13:54 +0530 Subject: [PATCH 326/362] ARM: dts: msm: Add display support for yupik IDP with PM7250B Add display support for yupik IDP variant with PM7250B replacing PM7325B. Change-Id: I4275a099fc488648027a7f68cd6655433af924ba --- display/yupik-sde-display-common.dtsi | 15 +++++ display/yupik-sde-display-idp-pm7250b.dtsi | 77 ++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 display/yupik-sde-display-idp-pm7250b.dtsi diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 3f1debe20f9b..7b598d850195 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -114,6 +114,21 @@ }; }; + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; diff --git a/display/yupik-sde-display-idp-pm7250b.dtsi b/display/yupik-sde-display-idp-pm7250b.dtsi new file mode 100644 index 000000000000..4fe3bd0a54a6 --- /dev/null +++ b/display/yupik-sde-display-idp-pm7250b.dtsi @@ -0,0 +1,77 @@ +#include "yupik-sde-display.dtsi" + +&pm7250b_gpios { + disp_lcd_bias_en { + disp_lcd_bias_en_default: disp_lcd_bias_en_default { + pins = "gpio2"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; + +&pm8350c_gpios { + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio8"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + }; +}; + +&sde_dsi { + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-0 = <&sde_dsi_active &sde_te_active &disp_lcd_bias_en_default>; + pinctrl-2 = <&lcd_backlight_ctrl_default>; + + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-en-gpio = <&pm7250b_gpios 2 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-en-gpio = <&pm7250b_gpios 2 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-en-gpio = <&pm7250b_gpios 2 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + From 51db49611488c06b8ba7a3e642105e418dbf28d2 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Sun, 18 Apr 2021 14:17:42 +0530 Subject: [PATCH 327/362] ARM: dts: msm: Add display support for pm6125 platform of Holi This change adds display nodes for MTP & CDP platforms of the Holi target with PM6125 PMIC. Change-Id: I97725d27dc97c2fed7040735ef1ef16d047a67b6 --- display/holi-sde-display-atp.dtsi | 13 ++++ display/holi-sde-display-cdp-pm6125.dtsi | 75 ++++++++++++++++++++++++ display/holi-sde-display-cdp.dtsi | 13 ++++ display/holi-sde-display-common.dtsi | 25 ++++++++ display/holi-sde-display-mtp-pm6125.dtsi | 75 ++++++++++++++++++++++++ display/holi-sde-display-mtp.dtsi | 13 ++++ display/holi-sde-display-qrd.dtsi | 13 ++++ display/holi-sde-display.dtsi | 13 ---- 8 files changed, 227 insertions(+), 13 deletions(-) create mode 100644 display/holi-sde-display-cdp-pm6125.dtsi create mode 100644 display/holi-sde-display-mtp-pm6125.dtsi diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi index 50e6d5d948d1..5c9cca798fbe 100644 --- a/display/holi-sde-display-atp.dtsi +++ b/display/holi-sde-display-atp.dtsi @@ -1,5 +1,18 @@ #include "holi-sde-display.dtsi" +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi new file mode 100644 index 000000000000..8bb2a7fb3e8b --- /dev/null +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -0,0 +1,75 @@ +#include "holi-sde-display.dtsi" + +&pmr735a_gpios { + disp_pins { + disp_pins_reset: disp_pins_reset { + pins = "gpio2"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 24 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + +&sde_dsi { + vddio-supply = <&L13A>; + avdd-supply = <&display_panel_avdd>; + + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-0 = <&sde_te_active &disp_pins_reset>; + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 405d99cc5725..520ee6175071 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -1,5 +1,18 @@ #include "holi-sde-display.dtsi" +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index b4d0bf1d8d88..18078ece180f 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -138,6 +138,31 @@ }; }; + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #size-cells = <0>; + #address-cells = <1>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; diff --git a/display/holi-sde-display-mtp-pm6125.dtsi b/display/holi-sde-display-mtp-pm6125.dtsi new file mode 100644 index 000000000000..8bb2a7fb3e8b --- /dev/null +++ b/display/holi-sde-display-mtp-pm6125.dtsi @@ -0,0 +1,75 @@ +#include "holi-sde-display.dtsi" + +&pmr735a_gpios { + disp_pins { + disp_pins_reset: disp_pins_reset { + pins = "gpio2"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 24 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + +&sde_dsi { + vddio-supply = <&L13A>; + avdd-supply = <&display_panel_avdd>; + + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-0 = <&sde_te_active &disp_pins_reset>; + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi index 50e6d5d948d1..5c9cca798fbe 100644 --- a/display/holi-sde-display-mtp.dtsi +++ b/display/holi-sde-display-mtp.dtsi @@ -1,5 +1,18 @@ #include "holi-sde-display.dtsi" +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index f7f1aae2c61d..dc34ad3fea52 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -1,5 +1,18 @@ #include "holi-sde-display.dtsi" +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + &dsi_panel_pwr_supply { qcom,panel-supply-entry@0 { qcom,supply-min-voltage = <1860000>; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 248d6f4e80f6..19d406208854 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,18 +1,5 @@ #include "holi-sde-display-common.dtsi" -&pm6150l_gpios { - disp_pins { - disp_pins_default: disp_pins_default { - pins = "gpio9"; - function = "func1"; - qcom,drive-strength = <2>; - power-source = <1>; - bias-disable; - output-low; - }; - }; -}; - &sde_dsi { clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, From dd44a05420e4cad0d4c2e4055c0e246796476b1b Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 19 May 2021 12:37:06 +0530 Subject: [PATCH 328/362] ARM: dts: msm: Add display nodes for Blair target Add display DT nodes for Blair target. Change-Id: I858c76262a44fa836bb61348ad82074c7ade381a --- display/blair-sde-display-cdp.dtsi | 88 ++++++++++++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 1 + display/blair-sde.dtsi | 24 ++++++++ display/holi-sde-display-common.dtsi | 15 +++++ 4 files changed, 128 insertions(+) create mode 100644 display/blair-sde-display-cdp.dtsi create mode 100644 display/blair-sde-display-mtp.dtsi create mode 100644 display/blair-sde.dtsi diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi new file mode 100644 index 000000000000..2ed34724f9df --- /dev/null +++ b/display/blair-sde-display-cdp.dtsi @@ -0,0 +1,88 @@ +/* Should extend holi-sde-display-cdp-pm6125.dtsi */ + +&tlmm { + pmx_sde_bias_en: pmx_sde_bias_en { + lcd_bias_en_active: lcd_bias_en_active { + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + lcd_bias_en_suspend: lcd_bias_en_suspend { + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; + +&pm6125_gpios { + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio8"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + }; +}; + +&sde_dsi { + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-0 = <&sde_te_active &disp_pins_reset &lcd_bias_en_active>; + pinctrl-1 = <&sde_te_suspend &lcd_bias_en_suspend>; + pinctrl-2 = <&lcd_backlight_ctrl_default>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; + qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; +}; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; + qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; + qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; +}; diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi new file mode 100644 index 000000000000..11ff69c6b5a2 --- /dev/null +++ b/display/blair-sde-display-mtp.dtsi @@ -0,0 +1 @@ +/* Should extend holi-sde-display-mtp-pm6125.dtsi */ diff --git a/display/blair-sde.dtsi b/display/blair-sde.dtsi new file mode 100644 index 000000000000..1a5e4b575150 --- /dev/null +++ b/display/blair-sde.dtsi @@ -0,0 +1,24 @@ +#include "holi-sde.dtsi" + +&mdss_dsi0 { + vdda-1p2-supply = <&L4A>; +}; + +&mdss_dsi_phy0 { + compatible = "qcom,dsi-phy-v4.1"; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + + vdda-0p9-supply = <&S1E_LEVEL>; +}; + diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 18078ece180f..b9bd7bf572f0 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -163,6 +163,21 @@ }; }; + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #size-cells = <0>; + #address-cells = <1>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; From 41324fa15589735e9563f69f49eab63d78717397 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Wed, 19 May 2021 01:18:19 +0530 Subject: [PATCH 329/362] ARM: dts: msm: add display support for monaco IDP Add panel dtsi for RM69090 truly 1.78" amoled panel. Change-Id: Ifca7f108a6578062f3b186d37a6a9db4187ada34 --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 74 ++++ display/monaco-sde-display.dtsi | 134 ++++++++ display/monaco-sde.dtsi | 318 ++++++++++++++++++ 3 files changed, 526 insertions(+) create mode 100644 display/dsi-panel-rm69090-amoled-178-cmd.dtsi create mode 100644 display/monaco-sde-display.dtsi create mode 100644 display/monaco-sde.dtsi diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi new file mode 100644 index 000000000000..55601b26b6e5 --- /dev/null +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -0,0 +1,74 @@ +&mdss_mdp { + dsi_rm69090_amoled_cmd: qcom,mdss_dsi_rm69090_amoled_178_cmd { + qcom,mdss-dsi-panel-name = + "RM69090 1.78 amoled cmd mode"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <368>; + qcom,mdss-dsi-panel-height = <448>; + qcom,mdss-dsi-h-front-porch = <40>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FE 01 + 15 01 00 00 00 00 02 6A 03 + 15 01 00 00 00 00 02 FE 00 + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 05 2A 00 10 01 7F + 39 01 00 00 00 00 05 2B 00 00 01 BF + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 40 00 02 29 00 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 15 01 00 00 00 00 02 4F 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi new file mode 100644 index 000000000000..96f16f6bede1 --- /dev/null +++ b/display/monaco-sde-display.dtsi @@ -0,0 +1,134 @@ +#include +#include "dsi-panel-rm69090-amoled-178-cmd.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + /*TODO: check if MDP clock WA is required*/ + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 73 0>; + qcom,panel-te-source = <0>; + vddio-supply = <&L21A>; + qcom,mdp = <&mdss_mdp>; + + qcom,dsi-default-panel = + <&dsi_rm69090_amoled_cmd>; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_dsi>; +}; + +&dsi_rm69090_amoled_cmd { + qcom,mdss-dsi-t-clk-post = <0x08>; + qcom,mdss-dsi-t-clk-pre = <0x0B>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", /*TODO: check these*/ + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0C 03 03 10 1D 03 + 03 03 02 02 04 0B 08]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi new file mode 100644 index 000000000000..0c61a0fd7c46 --- /dev/null +++ b/display/monaco-sde.dtsi @@ -0,0 +1,318 @@ +#include + +&soc { + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x420 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x421 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + + mdss_mdp: qcom,mdss_mdp { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x8f030>, + <0x5eb0000 0x2008>, + <0x5e8f000 0x02c>, + <0xc125ba4 0x20>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys", + "sde_imem_phys"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0xfe4>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "none", "dsi"; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-mixer-stage-base-layer; + + qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2ac 8>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <2700000>; + qcom,sde-max-bw-high-kbps = <2700000>; + qcom,sde-min-core-ib-kbps = <1300000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + + /*Pending macrotile & macrotile-qseed has the same configs */ + + qcom,sde-danger-lut = <0x000000ff 0x00000000 + 0x00000000 0x00000000 0x00000000>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + + qcom,sde-cdp-setting = <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-secure-sid-mask = <0x0000421>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-limits { + qcom,sde-linewidth-limits { + qcom,sde-limit-name = "sspp_linewidth_usecases"; + qcom,sde-limit-cases = "vig", "dma"; + qcom,sde-limit-ids= <0x1 0x2>; + qcom,sde-limit-values = <0x1 2160>, + <0x2 2160>; + }; + + qcom,sde-bw-limits { + qcom,sde-limit-name = "sde_bwlimit_usecases"; + qcom,sde-limit-cases = "per_vig_pipe", + "per_dma_pipe", + "total_max_bw", + "camera_concurrency"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2700000>, + <0x9 2700000>, + <0x2 2700000>, + <0xa 2700000>, + <0x4 2700000>, + <0xc 2700000>; + }; + }; + }; + + mdss_dsi0: qcom,mdss_dsi0_ctrl { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L9A>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1312000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x800>, + <0x5e94900 0x27c>, + <0x5e94200 0x100>, + <0x5f03000 0x8>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base", "gdsc_base"; + pll-label = "dsi_pll_5nm"; + memory-region = <&dfps_data_memory>; + vdda-0p9-supply = <&L12A>; + /*TODO: check these*/ + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; From 73350bfaaefeb40204de2e46583d89711b66898e Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 24 May 2021 16:48:34 +0530 Subject: [PATCH 330/362] ARM: dts: qcom: add thermal cooling dev property under mdss_mdp on Holi The display connector_init fails if the thermal cooling device property "#cooling-cells" is not present under the mdss_mdp DT node. Earlier this property used to be defined in "-thermal-overlay.dtsi" file, because of this, sometimes it gets missed. Looking at the code of the sde_connector, it appears the "#cooling-cells" is a mandatory property of the mdss_mdp. Add this property under mdss_mdp DT node. Change-Id: Icd4b076e0c718327df762f0dae10347162fa2299 --- display/holi-sde.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index 6b9b4af31c3f..17db671487d1 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -88,6 +88,9 @@ }; &mdss_mdp { + /* Enable thermal cooling device */ + #cooling-cells = <2>; + clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, From b204f3e69d75a1634a607d83ed1981204557c2e4 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 13 May 2021 16:57:38 +0530 Subject: [PATCH 331/362] ARM: dts: msm: Add NT36672E 144hz C-phy Video Mode Panel on Yupik IDP Add NT36672E 144fps fhd plus Video mode C-Phy panel support on yupik platform. Change-Id: I186eb8b9d92b873781a2ae2652b7c47c95c758c3 --- ...el-nt36672e-fhd-plus-144hz-video-cphy.dtsi | 430 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 14 + display/yupik-sde-display-idp.dtsi | 8 + 3 files changed, 452 insertions(+) create mode 100644 display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi diff --git a/display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi b/display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi new file mode 100644 index 000000000000..d569a87561c8 --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi @@ -0,0 +1,430 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_144hz_video_cphy: qcom,mdss_dsi_nt36672e_fhd_plus_cphy_144hz_video { + qcom,mdss-dsi-panel-name = + "nt36672e 144Hz fhd plus video mode cphy panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750 + 39800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <80>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <54>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 C0 03 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 39 01 00 00 00 00 03 C2 1B A0 + 39 01 00 00 00 00 02 E9 01 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 66 + 39 01 00 00 00 00 02 06 40 + 39 01 00 00 00 00 02 07 38 + 39 01 00 00 00 00 02 18 77 + 39 01 00 00 00 00 02 69 91 + 39 01 00 00 00 00 02 95 D1 + 39 01 00 00 00 00 02 96 D1 + 39 01 00 00 00 00 02 F2 65 + 39 01 00 00 00 00 02 F3 74 + 39 01 00 00 00 00 02 F4 65 + 39 01 00 00 00 00 02 F5 74 + 39 01 00 00 00 00 02 F6 65 + 39 01 00 00 00 00 02 F7 74 + 39 01 00 00 00 00 02 F8 65 + 39 01 00 00 00 00 02 F9 74 + + 39 01 00 00 00 00 02 89 15 + 39 01 00 00 00 00 02 8A 15 + 39 01 00 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C9 + 39 01 00 00 00 00 02 6C 1F + 39 01 00 00 00 00 02 6D E3 + 39 01 00 00 00 00 02 6E C6 + 39 01 00 00 00 00 02 6F 20 + 39 01 00 00 00 00 02 70 E2 + 39 01 00 00 00 00 02 71 04 + 39 01 00 00 00 00 02 7A 04 + 39 01 00 00 00 00 02 7B 40 + 39 01 00 00 00 00 02 7C 01 + 39 01 00 00 00 00 02 7D 01 + 39 01 00 00 00 00 02 7F E0 + 39 01 00 00 00 00 02 83 0F + 39 01 00 00 00 00 02 84 C5 + 39 01 00 00 00 00 02 87 0F + 39 01 00 00 00 00 02 88 42 + 39 01 00 00 00 00 02 89 14 + 39 01 00 00 00 00 02 8B 36 + 39 01 00 00 00 00 02 8C 33 + 39 01 00 00 00 00 02 8D 33 + 39 01 00 00 00 00 02 8E 33 + 39 01 00 00 00 00 02 95 80 + 39 01 00 00 00 00 02 96 FD + 39 01 00 00 00 00 02 97 19 + 39 01 00 00 00 00 02 98 4A + 39 01 00 00 00 00 02 99 07 + 39 01 00 00 00 00 02 9A 0B + 39 01 00 00 00 00 02 9B 03 + 39 01 00 00 00 00 02 9C 8B + 39 01 00 00 00 00 02 9D FF + 39 01 00 00 00 00 02 9F 8B + 39 01 00 00 00 00 02 A0 FF + 39 01 00 00 00 00 02 A2 4E + 39 01 00 00 00 00 02 A3 01 + 39 01 00 00 00 00 02 A4 F8 + 39 01 00 00 00 00 02 A5 52 + 39 01 00 00 00 00 02 A6 FD + 39 01 00 00 00 00 02 A7 4B + + 39 01 00 00 00 00 02 FF 2C + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 00 02 + 39 01 00 00 00 00 02 01 02 + 39 01 00 00 00 00 02 02 02 + 39 01 00 00 00 00 02 03 16 + 39 01 00 00 00 00 02 04 16 + 39 01 00 00 00 00 02 05 16 + 39 01 00 00 00 00 02 0D 1F + 39 01 00 00 00 00 02 0E 1F + 39 01 00 00 00 00 02 16 1B + 39 01 00 00 00 00 02 17 4B + 39 01 00 00 00 00 02 18 4B + 39 01 00 00 00 00 02 19 4B + 39 01 00 00 00 00 02 2A 03 + 39 01 00 00 00 00 02 4D 16 + 39 01 00 00 00 00 02 4E 03 + 39 01 00 00 00 00 02 53 02 + 39 01 00 00 00 00 02 54 02 + 39 01 00 00 00 00 02 55 02 + 39 01 00 00 00 00 02 56 0B + 39 01 00 00 00 00 02 58 0B + 39 01 00 00 00 00 02 59 0B + 39 01 00 00 00 00 02 61 19 + 39 01 00 00 00 00 02 62 19 + 39 01 00 00 00 00 02 6A 10 + 39 01 00 00 00 00 02 6B 2A + 39 01 00 00 00 00 02 6C 2A + 39 01 00 00 00 00 02 6D 2A + 39 01 00 00 00 00 02 7E 03 + 39 01 00 00 00 00 02 9D 0B + 39 01 00 00 00 00 02 9E 04 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 E2 00 E9 00 F6 01 01 01 0C 01 15 01 20 01 28 + 39 01 00 00 00 00 11 B1 01 33 01 51 01 6E 01 9A 01 C0 01 FD 02 34 02 35 + 39 01 00 00 00 00 11 B2 02 6B 02 A9 02 D1 03 04 03 25 03 51 03 5F 03 6D + 39 01 00 00 00 00 0F B3 03 7D 03 90 03 A7 03 BB 03 D4 03 D8 00 00 + 39 01 00 00 00 00 11 B4 00 AA 00 B3 00 C4 00 D4 00 E2 00 F0 00 FC 01 08 + 39 01 00 00 00 00 11 B5 01 12 01 39 01 58 01 8C 01 B5 01 F7 02 30 02 31 + 39 01 00 00 00 00 11 B6 02 68 02 A6 02 CE 03 01 03 23 03 4E 03 5C 03 6A + 39 01 00 00 00 00 0F B7 03 7B 03 8E 03 A5 03 BB 03 D4 03 D8 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 20 00 47 00 65 00 85 00 99 00 AD 00 C0 + 39 01 00 00 00 00 11 B9 00 D2 01 06 01 30 01 70 01 9F 01 E8 02 25 02 26 + 39 01 00 00 00 00 11 BA 02 5F 02 9F 02 C7 02 FD 03 20 03 52 03 63 03 67 + 39 01 00 00 00 00 0F BB 03 78 03 8B 03 A3 03 B9 03 D4 03 D8 00 00 + + 39 01 00 00 00 00 02 FF 21 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 E2 00 E9 00 F6 01 01 01 0C 01 15 01 20 01 28 + 39 01 00 00 00 00 11 B1 01 33 01 51 01 6E 01 9A 01 C0 01 FD 02 34 02 35 + 39 01 00 00 00 00 11 B2 02 6B 02 A9 02 D1 03 04 03 25 03 51 03 5F 03 6D + 39 01 00 00 00 00 0F B3 03 7D 03 90 03 A7 03 BB 03 D4 03 D8 00 00 + 39 01 00 00 00 00 11 B4 00 AA 00 B3 00 C4 00 D4 00 E2 00 F0 00 FC 01 08 + 39 01 00 00 00 00 11 B5 01 12 01 39 01 58 01 8C 01 B5 01 F7 02 30 02 31 + 39 01 00 00 00 00 11 B6 02 68 02 A6 02 CE 03 01 03 23 03 4E 03 5C 03 6A + 39 01 00 00 00 00 0F B7 03 7B 03 8E 03 A5 03 BB 03 D4 03 D8 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 20 00 47 00 65 00 85 00 99 00 AD 00 C0 + 39 01 00 00 00 00 11 B9 00 D2 01 06 01 30 01 70 01 9F 01 E8 02 25 02 26 + 39 01 00 00 00 00 11 BA 02 5F 02 9F 02 C7 02 FD 03 20 03 52 03 63 03 67 + 39 01 00 00 00 00 0F BB 03 78 03 8B 03 A3 03 B9 03 D4 03 D8 00 00 + + 39 01 00 00 00 00 02 FF E0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 35 82 + + 39 01 00 00 00 00 02 FF F0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 5A 00 + 39 01 00 00 00 00 02 D2 52 + 39 01 00 00 00 00 02 9F 12 + + 39 01 00 00 00 00 02 FF D0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 53 22 + 39 01 00 00 00 00 02 54 02 + + 39 01 00 00 00 00 02 FF C0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 9C 11 + 39 01 00 00 00 00 02 9D 11 + + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + + 39 01 00 00 00 00 02 35 01 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 32 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index f04cb048c16c..dc79e9e90769 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -2,6 +2,7 @@ #include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi" @@ -210,6 +211,19 @@ }; }; +&dsi_nt36672e_fhd_plus_144hz_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 22 1F 06 + 19 07 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_60hz_cmd_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 1b1fcd8a6792..942d2f1a263b 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -32,6 +32,14 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_nt36672e_fhd_plus_144hz_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_90hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 45a7f9a795ff0665c95c0171d46c1101685341d4 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 27 May 2021 21:00:47 +0530 Subject: [PATCH 332/362] ARM: dts: msm: Fix backlight pinctrl config for Blair target Fix pinctrl config of LCD backlight PWM enable pin for Blair CDP target. Change-Id: I3091cc4698d69553b24da25608487b28170ff665 --- display/blair-sde-display-cdp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 2ed34724f9df..4ebd9f1a8942 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -36,10 +36,10 @@ pins = "gpio8"; function = "func1"; input-disable; - output-enable; + output-low; bias-disable; - power-source = <1>; /* 1.8V */ - qcom,drive-strength = <2>; + power-source = <0>; + qcom,drive-strength = <3>; }; }; }; From f02c31c4f3fade2a4de95092a2c96f79bc3af23e Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 27 May 2021 19:13:10 +0530 Subject: [PATCH 333/362] ARM: dts: msm: Fix backlight pinctrl config for yupik IDP with PM7250B Fix pinctrl config of lcd_backlight_ctrl_default for yupik IDP with PM7250B. Change-Id: I3acbb2802dfca11186b0eb1936ac52a79d0b8282 --- display/yupik-sde-display-idp-pm7250b.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/display/yupik-sde-display-idp-pm7250b.dtsi b/display/yupik-sde-display-idp-pm7250b.dtsi index 4fe3bd0a54a6..cfe5719a65e6 100644 --- a/display/yupik-sde-display-idp-pm7250b.dtsi +++ b/display/yupik-sde-display-idp-pm7250b.dtsi @@ -20,10 +20,10 @@ pins = "gpio8"; function = "func1"; input-disable; - output-enable; + output-low; bias-disable; - power-source = <1>; /* 1.8V */ - qcom,drive-strength = <2>; + power-source = <0>; + qcom,drive-strength = <3>; }; }; }; From df4682b6028506f05b7e3a5539a688a934c10fb1 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 21 May 2021 13:11:26 +0800 Subject: [PATCH 334/362] ARM: dts: msm: add panel support for qrd pm6125 platform of Holi Add panel support for this qrd device. Change-Id: I17ec0619d69a340e4bb79361ab87b05159a77ce0 --- display/holi-sde-display-qrd-pm6125.dtsi | 121 +++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 display/holi-sde-display-qrd-pm6125.dtsi diff --git a/display/holi-sde-display-qrd-pm6125.dtsi b/display/holi-sde-display-qrd-pm6125.dtsi new file mode 100644 index 000000000000..6ed7c6ad2e0b --- /dev/null +++ b/display/holi-sde-display-qrd-pm6125.dtsi @@ -0,0 +1,121 @@ +#include "holi-sde-display.dtsi" + +&pmr735a_gpios { + disp_pins { + disp_pins_reset: disp_pins_reset { + pins = "gpio2"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 24 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + +&sde_dsi { + vddio-supply = <&L13A>; + avdd-supply = <&display_panel_avdd>; + + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-0 = <&sde_te_active &disp_pins_reset>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; From 8e20ac5b1d2532defc8165fbc71b576c2683176a Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 4 Jun 2021 22:33:30 +0530 Subject: [PATCH 335/362] ARM: dts: msm: Update dsi phy addresses and timings for Blair target Update dsi phy addresses and phy timings of amoled panel for the Blair target as per 6nm-FF. Change-Id: I366d26b0939f9b7fe969b6c503adc1c3c0574ada --- display/blair-sde-display-cdp.dtsi | 18 ++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 18 ++++++++++++++++++ display/blair-sde.dtsi | 8 ++++---- 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 4ebd9f1a8942..7c64312e4db0 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -51,6 +51,24 @@ pinctrl-2 = <&lcd_backlight_ctrl_default>; }; +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index 11ff69c6b5a2..e5e55997454a 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1 +1,19 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ + +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; diff --git a/display/blair-sde.dtsi b/display/blair-sde.dtsi index 1a5e4b575150..dc45549650c4 100644 --- a/display/blair-sde.dtsi +++ b/display/blair-sde.dtsi @@ -6,10 +6,10 @@ &mdss_dsi_phy0 { compatible = "qcom,dsi-phy-v4.1"; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; + reg = <0x05e94400 0x800>, + <0x05e94900 0x264>, + <0x05f01004 0x8>, + <0x05e94200 0x100>; reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; pll-label = "dsi_pll_5nm"; From 56e494c144ce597ba187b4756289603440ba8a77 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Tue, 13 Apr 2021 15:37:56 +0800 Subject: [PATCH 336/362] bindings: Documentation: add documentation for qpic display Add the documentation for configuring the QPIC display block. Change-Id: I03a0f9f4754b8dfe18165ed7c00a9b12de1c9f7a --- bindings/qcom-qpic-lcdc.txt | 69 +++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 bindings/qcom-qpic-lcdc.txt diff --git a/bindings/qcom-qpic-lcdc.txt b/bindings/qcom-qpic-lcdc.txt new file mode 100644 index 000000000000..e6ee71c512e1 --- /dev/null +++ b/bindings/qcom-qpic-lcdc.txt @@ -0,0 +1,69 @@ +Qualcomm Technologies, Inc. QPIC display + +QPIC LCDC Controller: +Mandatory properties: +- compatible: + * "qcom,mdss_qpic" +- reg: Physical base address and length of registers of controller +- reg-names: The names of register regions. The following regions are required: + * "qpic_base" +- interrupts: The interrupt signal from the QPIC LCDC block. +- clocks: It contains list of required clock. List contain core clock. +- clock-names: Must contain "core" for the core clock and "aon" for the + always on clock. +- qcom,panel-name: The panel peripheral name "string" which is used by QPIC display. +- qcom.rst-gpio: Specifies the gpio used to reset panel. +- qcom,cs-gpio: Specifies the gpio used for LCDC chip select signal. +- qcom,ad8-gpio: Specifies the gpio used for LCDC data pin 8. +- qcom,panel-te-gpio: Specifies the gpio used for TE. + +Optional properties: +- vdd-supply: phandle to vdd regulator device node +- vdda-supply: phandle to vdda regulator device node +- pinctrl-names: the pin control state names; should contain "default" +- pinctrl-0: the default pinctrl state (active) +- pinctrl-n: the "sleep" pinctrl state +- qcom,bl-gpio: Specifies the gpio used to enable backlight. +- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for +below optional properties: + - qcom,msm-bus,name + - qcom,msm-bus,num-cases + - qcom,msm-bus,active-only + - qcom,msm-bus,num-paths + - qcom,msm-bus,vectors-KBps + + +Example: + mdss_qpic: qcom,msm_qpic@1b00000 { + compatible = "qcom,mdss_qpic"; + reg = <0x1b00000 0x24000>; + reg-names = "qpic_base"; + interrupts = <0 251 0>; + + qcom,msm-bus,name = "mdss_qpic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = + <91 512 0 0>, + /* Voting for max b/w on PNOC bus for now */ + <91 512 400000 800000>; + + panel-name = "ili_qvga"; + vdd-supply = <&pmxprairie_l6>; + + qcom,rst-gpio = <&tlmm 23 0>; + qcom,cs-gpio = <&tlmm 21 0>; + qcom,ad8-gpio = <&tlmm 20 0>; + qcom,te-gpio = <&tlmm 22 0>; + qcom,bl-gpio = <&pmxprairie_gpios 1 0>; + + clocks = <&clock_rpmh RPMH_QPIC_CLK>; + clock-names = "core_clk"; + + pinctrl-names= "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_cs_active &mdss_te_active + &mdss_rs_active &mdss_ad_active>; + pinctrl-1 = <&mdss_cs_sleep &mdss_te_sleep + &mdss_rs_sleep &mdss_ad_sleep>; + }; From 60524582d2c1c23b5b2a8e7331ade4c06684251a Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Fri, 19 Mar 2021 17:12:58 +0800 Subject: [PATCH 337/362] ARM: dts: msm: add support for QPIC display Add support for QPIC display and ili panel for MDM project. Change-Id: Ia7a4d47d62333867264e4b29fbaa8ead0ab0fe25 --- display/sdxlemur-qpic-display.dtsi | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 display/sdxlemur-qpic-display.dtsi diff --git a/display/sdxlemur-qpic-display.dtsi b/display/sdxlemur-qpic-display.dtsi new file mode 100644 index 000000000000..b6ede6f9fbea --- /dev/null +++ b/display/sdxlemur-qpic-display.dtsi @@ -0,0 +1,40 @@ +&soc { + mdss_qpic: qcom,msm_qpic@1b00000 { + compatible = "qcom,mdss_qpic"; + + reg = <0x1b00000 0x24000>; + reg-names = "qpic_base"; + + interrupts = <0 75 0>; + interrupt-names = "qpic_irq"; + + interconnect-names = "qpic-display-data-bus"; + interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>; + qcom,msm-bus,name = "mdss_qpic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = + <0 0>, + /* Voting for max b/w on PNOC bus for now */ + <400000 800000>; + + qcom,panel-name = "ili_qvga"; + vdd-supply = <&pmx65_l6>; + + qcom,rst-gpio = <&tlmm 85 0>; + qcom,cs-gpio = <&tlmm 90 0>; + qcom,ad8-gpio = <&tlmm 89 0>; + qcom,panel-te-gpio = <&tlmm 84 0>; + qcom,panel-bl-gpio = <&tlmm 97 0>; + + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "core_clk"; + + pinctrl-names= "qpic_display_default", "qpic_display_sleep"; + pinctrl-0 = <&qpic_cs_active &qpic_te_active + &qpic_rs_active &qpic_ad_active>; + pinctrl-1 = <&qpic_cs_sleep &qpic_te_sleep + &qpic_rs_sleep &qpic_ad_sleep>; + }; +}; From 0c38dce0a140544189d44fc3828c576d50fe3819 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Tue, 8 Jun 2021 20:19:41 +0530 Subject: [PATCH 338/362] ARM: dts: msm: update clock list for monaco-sde Remove GCC_DISP_AHB_CLK as this is always ON clk and support for this clk was removed in clk driver. Change-Id: I641f6c0a69b2a4395357519e1fe732a74144052a --- display/monaco-sde.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 0c61a0fd7c46..69ddb0a24925 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -31,14 +31,13 @@ "sde_imem_phys"; clocks = - <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_THROTTLE_CORE_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + clock-names = "gcc_bus", "throttle_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; From c779434e1a50237d3a5476bcb28ec5d077bd383b Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 9 Jun 2021 15:50:13 +0800 Subject: [PATCH 339/362] ARM: dts: msm: add a new display qrd dtsi for Blair Add a new display dtsi file. Change-Id: I1f02b6d4dfbf71b75feb2cfc3ffdeeccc8eb8de5 --- display/blair-sde-display-qrd.dtsi | 61 ++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 display/blair-sde-display-qrd.dtsi diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi new file mode 100644 index 000000000000..e8d21a2f08c7 --- /dev/null +++ b/display/blair-sde-display-qrd.dtsi @@ -0,0 +1,61 @@ +/* Should extend holi-sde-display-qrd-pm6125.dtsi */ + +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00 1a 17]; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00 1a 17]; + }; + }; +}; + +&dsi_r66451_amoled_90hz_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + }; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + }; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + }; +}; From 0a96923db21aa34470db0b9eb37bf76ddd56b7a0 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Tue, 15 Jun 2021 14:44:12 +0530 Subject: [PATCH 340/362] ARM: dts: msm: update lane-config settings for monaco-sde Update the lane config and LDO settings with correct values. Change-Id: I9bf725599abbf6d1850bd658155bc9b4959a84d2 --- display/monaco-sde.dtsi | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 69ddb0a24925..8b595879d446 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -45,6 +45,9 @@ sde-vdd-supply = <&mdss_core_gdsc>; + /* Enable thermal cooling device */ + #cooling-cells = <2>; + /* data and reg bus scale settings */ interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, <&bimc MASTER_AMPSS_M0 @@ -286,17 +289,16 @@ pll-label = "dsi_pll_5nm"; memory-region = <&dfps_data_memory>; vdda-0p9-supply = <&L12A>; - /*TODO: check these*/ qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; - qcom,platform-lane-config = [00 00 10 0f - 00 00 10 0f - 00 00 10 0f - 00 00 10 0f - 00 00 10 8f]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-en; @@ -307,8 +309,8 @@ qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; + qcom,supply-min-voltage = <904000>; + qcom,supply-max-voltage = <904000>; qcom,supply-enable-load = <37550>; qcom,supply-disable-load = <0>; }; From 2cbaedd9c2083d122e50f5b8a052fa75de4b5810 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 7 Jun 2021 14:21:57 +0530 Subject: [PATCH 341/362] bindings: Documentation: LP11 insertion between lines feature This change adds documentation for LP11 insertion between command mode mdp packets feature. Change-Id: Icb6fdd14866cb9768cb735597afb9b989bf5d9c8 --- bindings/mdss-dsi-panel.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index de435b32c172..f2554a75ed98 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -612,6 +612,11 @@ Optional properties: panels, at which command DMA needs to be triggered. - qcom,mdss-dsi-dma-schedule-window: An integer value indicates the width of the DMA window during which a DCS command will be triggered for command mode panels +- qcom,mdss-dsi-mdp-idle-ctrl-en: A boolean to enable LP11 insertion after transmission of every line. + This requires command mdp burst mode to be disabled. +- qcom,mdss-dsi-mdp-idle-ctrl-len: An u32 value indicating the number of dsi pclk cycles of idle time + to insert between command mode mdp packets. This time must be long + enough to cover the time link takes to switch between HS to LP11 mode. Required properties for sub-nodes: None Optional properties: From c70d048b82564d697787b4263dd26551a77a9db0 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 18 Jun 2021 12:13:39 +0530 Subject: [PATCH 342/362] ARM: dts: msm: add support of sim panel for Blair target Add support of video simulation panel for the Blair target. The Blair display DT includes DT of PM6125 variant of Holi, so this change automatically adds the same support there too. Change-Id: I705d08e87025f9accb9abdecab330d3a20c33e9a --- display/blair-sde-display-cdp.dtsi | 9 +++++++++ display/blair-sde-display-mtp.dtsi | 9 +++++++++ display/holi-sde-display-cdp-pm6125.dtsi | 6 ++++++ display/holi-sde-display-mtp-pm6125.dtsi | 6 ++++++ 4 files changed, 30 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 7c64312e4db0..c22aa8d0b7ae 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -51,6 +51,15 @@ pinctrl-2 = <&lcd_backlight_ctrl_default>; }; +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index e5e55997454a..bec02d25e750 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1,5 +1,14 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi index 8bb2a7fb3e8b..4daffd87cf89 100644 --- a/display/holi-sde-display-cdp-pm6125.dtsi +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -57,6 +57,12 @@ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-mtp-pm6125.dtsi b/display/holi-sde-display-mtp-pm6125.dtsi index 8bb2a7fb3e8b..4daffd87cf89 100644 --- a/display/holi-sde-display-mtp-pm6125.dtsi +++ b/display/holi-sde-display-mtp-pm6125.dtsi @@ -57,6 +57,12 @@ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 2fe96c9d4731a7c8b1b5d08eb8b2809b7031f29d Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Thu, 1 Jul 2021 00:47:22 +0530 Subject: [PATCH 343/362] ARM: dts: msm: update sde qos config for monaco Update safe, danger and qos config for 60fps. Change-Id: I28136c73d2156c128c222ea62549028802a9fb34 --- display/monaco-sde.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 8b595879d446..70f5404675c9 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -140,12 +140,13 @@ /*Pending macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x000000ff 0x00000000 + qcom,sde-danger-lut = <0x000000ff 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; - qcom,sde-safe-lut-linear = <0 0xfff0>; + qcom,sde-safe-lut = <0xfff0 0x0000 0x0000 0x0000 + 0x0000 0x0000>; - qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + qcom,sde-qos-lut-linear = <0x00112222 0x22335777>; qcom,sde-cdp-setting = <1 0>; From 6d7bd29c8ccff67518f6ba6e9aac233c39daeee3 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Sat, 3 Jul 2021 18:21:34 +0530 Subject: [PATCH 344/362] ARM: dts: msm: update tear irq offsets for monaco Add tear irq offset for interface 1. Change-Id: I972627be369a14296b055ce48f96ee3c0384587f --- display/monaco-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 70f5404675c9..00150f1a4710 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -82,6 +82,7 @@ qcom,sde-intf-off = <0x0 0x6b800>; qcom,sde-intf-size = <0x2b8>; qcom,sde-intf-type = "none", "dsi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800>; qcom,sde-pp-off = <0x71000>; qcom,sde-pp-size = <0xd4>; From d56f0ddde3096be8e1fe89207feabd00a7494cac Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 5 Jul 2021 18:28:07 +0530 Subject: [PATCH 345/362] ARM: dts: msm: add list-cells property for mdp node Add list-cells property for mdp device node. Which is needed to populate parent device node for rotator device. Change-Id: I679343160c81f6047cb1a3ff207cd386a0f31580 --- display/holi-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index 3e49e2ac9420..8cf5b56c7c9f 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -20,6 +20,7 @@ #interrupt-cells = <1>; #power-domain-cells = <0>; + #list-cells = <1>; /* hw blocks */ qcom,sde-off = <0x1000>; From 7f33608bfc5b177412b2652bc96a27422453c36d Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 8 Jul 2021 17:23:47 +0530 Subject: [PATCH 346/362] ARM: dts: msm: update supply-min-voltage of dsi phy supply for Blair MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In Blair target, the MX Rail supports till SVSL1 mode whereas in Holi target it’s Nominal. Change the qcom,supply-min-voltage of the dsi phy 0p9 power supply to SVSL1. Change-Id: If6bfe3021f27ce844783b586b42ef0edb7db157f --- display/blair-sde.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/display/blair-sde.dtsi b/display/blair-sde.dtsi index dc45549650c4..ba11d88339bc 100644 --- a/display/blair-sde.dtsi +++ b/display/blair-sde.dtsi @@ -20,5 +20,21 @@ 00 00 8a 8a]; vdda-0p9-supply = <&S1E_LEVEL>; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; From a763fa718fa880f0a90b9997f2245fe69c452f31 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Tue, 13 Jul 2021 22:14:07 +0530 Subject: [PATCH 347/362] ARM: dts: msm: Enable NT36672E D-PHY LCD panel for Blair target Enable NT36672E 60/120/144fps D-PHY fhd plus video mode display panel support for the Blair target. Change-Id: Ie5e69943f7b7984f4b625372ce91a6555a1f2467 --- display/blair-sde-display-cdp.dtsi | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index c22aa8d0b7ae..9926d84935a3 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -88,6 +88,20 @@ qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; qcom,platform-en-gpio = <&tlmm 47 0>; qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 + 0a 09 02 04 00 1f 19]; + }; + }; }; &dsi_nt36672e_fhd_plus_120_video { @@ -100,6 +114,20 @@ qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; qcom,platform-en-gpio = <&tlmm 47 0>; qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 + 08 08 02 04 00 1b 18]; + }; + }; }; &dsi_nt36672e_fhd_plus_144_video { @@ -112,4 +140,18 @@ qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; qcom,platform-en-gpio = <&tlmm 47 0>; qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 08 02 04 00 1c 18]; + }; + }; }; From 5f6dc7394fda571473e9792c43d3861665e7d124 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Tue, 13 Jul 2021 22:16:51 +0530 Subject: [PATCH 348/362] ARM: dts: msm: Enable NT36672E C-PHY LCD panel for Blair target Enable NT36672E 144fps C-PHY fhd plus video mode display panel support for the Blair target. Change-Id: Ife56a47baec80b5580f9820f1a7ff689af7bc26b --- display/blair-sde-display-cdp.dtsi | 49 ++++++++++++++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 19 ++++++++++++ 2 files changed, 68 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 9926d84935a3..cad3a0ad1a34 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -1,4 +1,6 @@ /* Should extend holi-sde-display-cdp-pm6125.dtsi */ +#include +#include "dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi" &tlmm { pmx_sde_bias_en: pmx_sde_bias_en { @@ -45,6 +47,22 @@ }; &sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; pinctrl-0 = <&sde_te_active &disp_pins_reset &lcd_bias_en_active>; pinctrl-1 = <&sde_te_suspend &lcd_bias_en_suspend>; @@ -155,3 +173,34 @@ }; }; }; + +&dsi_nt36672e_fhd_plus_144hz_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; + qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 22 1F 06 + 19 07 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index bec02d25e750..f1786f5e53d2 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1,4 +1,23 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; +}; &dsi_sim_vid { qcom,mdss-dsi-display-timings { From c6a2adb14dbd775aa4232de45218fea202d28995 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Tue, 20 Jul 2021 13:12:00 +0530 Subject: [PATCH 349/362] ARM: dts: msm: remove the t-clk-post and t-clk-pre timings from Blair The qcom,mdss-dsi-t-clk-post and qcom,mdss-dsi-t-clk-pre panel properties are not required for DSI ctrl v2.3.0 and above, using DSI phy v4.0.0 and above. As the Blair is reusing the display nodes from the Holi target, these two properties are getting included automatically. If these properties are defined, the DSI ctrl programs the DSI_CLKOUT_TIMING_CTRL register for all the DSI PHY versions, that is not recommended as per the DSI HPG. We don't need these two for the Blair, remove them from Blair CDP and MTP platforms. Change-Id: I81d66c53fabfc389466b0dbf82c8d8678f08868a --- display/blair-sde-display-cdp.dtsi | 21 +++++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 9 +++++++++ 2 files changed, 30 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index cad3a0ad1a34..c373b3910512 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -70,6 +70,9 @@ }; &dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 @@ -79,6 +82,9 @@ }; &dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -88,6 +94,9 @@ }; &dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -114,6 +123,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 @@ -140,6 +152,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 @@ -166,6 +181,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -195,6 +213,9 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 22 1F 06 diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index f1786f5e53d2..bab296d1f4a0 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -20,6 +20,9 @@ }; &dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 @@ -29,6 +32,9 @@ }; &dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -38,6 +44,9 @@ }; &dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 From a51192b3f0cd3137b6c8576dbfab34d2f34d69aa Mon Sep 17 00:00:00 2001 From: Yu Wu Date: Tue, 20 Jul 2021 18:34:22 +0800 Subject: [PATCH 350/362] ARM: dts: msm: remove the t-clk-post and t-clk-pre timings for blair QRD The qcom,mdss-dsi-t-clk-post and qcom,mdss-dsi-t-clk-pre panel properties are not required for DSI ctrl v2.3.0 and above, using DSI phy v4.0.0 and above. As the Blair is reusing the display nodes from the Holi target, these two properties are getting included automatically. If these properties are defined, the DSI ctrl programs the DSI_CLKOUT_TIMING_CTRL register for all the DSI PHY versions, that is not recommended as per the DSI HPG. We don't need these two for the Blair, remove them. Change-Id: Ic4e1a3a306e4aa191cd7cb3b6017cd3b2f226e8e --- display/blair-sde-display-qrd.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi index e8d21a2f08c7..e12529ae97cf 100644 --- a/display/blair-sde-display-qrd.dtsi +++ b/display/blair-sde-display-qrd.dtsi @@ -1,6 +1,8 @@ /* Should extend holi-sde-display-qrd-pm6125.dtsi */ &dsi_r66451_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 @@ -20,6 +22,8 @@ }; &dsi_r66451_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 @@ -29,6 +33,8 @@ }; &dsi_r66451_amoled_90hz_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 @@ -43,6 +49,8 @@ }; &dsi_r66451_amoled_90hz_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 @@ -52,6 +60,8 @@ }; &dsi_r66451_amoled_60hz_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 From e7a560d1e386907d291f35d8c48f5dc78bd52652 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Tue, 20 Jul 2021 19:47:53 +0530 Subject: [PATCH 351/362] ARM: dts: msm: add dummy regulator for ibb supply for Blair When the AMOLED panel is powered from the external power source, the IBB regulator is not needed. In the absence of ibb regulator node we are getting error message (non-fatal) for AMOLED panel's operation on ibb during change in the power states. Using stub regulator for ibb supply to fix this error. The Blair display DT includes DT of PM6125 variant of Holi, so this change applies to both. Change-Id: I851cef3e6c235b8ee2fa334c45c96caa038262bf --- display/holi-sde-display-cdp-pm6125.dtsi | 9 ++++++++- display/holi-sde-display-common.dtsi | 10 ++++++++++ display/holi-sde-display-mtp-pm6125.dtsi | 9 ++++++++- display/holi-sde-display-qrd-pm6125.dtsi | 9 ++++++++- 4 files changed, 34 insertions(+), 3 deletions(-) diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi index 4daffd87cf89..964f8a8ff0d8 100644 --- a/display/holi-sde-display-cdp-pm6125.dtsi +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -44,14 +44,21 @@ pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; + + display_panel_ibb: display_panel_ibb_stub { + compatible = "qcom,stub-regulator"; + regulator-name = "display_panel_ibb"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + }; }; &sde_dsi { vddio-supply = <&L13A>; avdd-supply = <&display_panel_avdd>; + ibb-supply = <&display_panel_ibb>; /delete-property/ lab-supply; - /delete-property/ ibb-supply; pinctrl-0 = <&sde_te_active &disp_pins_reset>; qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index b9bd7bf572f0..7534c0b447a8 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -161,6 +161,16 @@ qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <0>; }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; }; dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { diff --git a/display/holi-sde-display-mtp-pm6125.dtsi b/display/holi-sde-display-mtp-pm6125.dtsi index 4daffd87cf89..964f8a8ff0d8 100644 --- a/display/holi-sde-display-mtp-pm6125.dtsi +++ b/display/holi-sde-display-mtp-pm6125.dtsi @@ -44,14 +44,21 @@ pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; + + display_panel_ibb: display_panel_ibb_stub { + compatible = "qcom,stub-regulator"; + regulator-name = "display_panel_ibb"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + }; }; &sde_dsi { vddio-supply = <&L13A>; avdd-supply = <&display_panel_avdd>; + ibb-supply = <&display_panel_ibb>; /delete-property/ lab-supply; - /delete-property/ ibb-supply; pinctrl-0 = <&sde_te_active &disp_pins_reset>; qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; diff --git a/display/holi-sde-display-qrd-pm6125.dtsi b/display/holi-sde-display-qrd-pm6125.dtsi index 6ed7c6ad2e0b..3ae08c2c7434 100644 --- a/display/holi-sde-display-qrd-pm6125.dtsi +++ b/display/holi-sde-display-qrd-pm6125.dtsi @@ -44,14 +44,21 @@ pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; + + display_panel_ibb: display_panel_ibb_stub { + compatible = "qcom,stub-regulator"; + regulator-name = "display_panel_ibb"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + }; }; &sde_dsi { vddio-supply = <&L13A>; avdd-supply = <&display_panel_avdd>; + ibb-supply = <&display_panel_ibb>; /delete-property/ lab-supply; - /delete-property/ ibb-supply; pinctrl-0 = <&sde_te_active &disp_pins_reset>; qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; From 6c30d2fbb055318f4cbabfe7cde0cce1f311cd49 Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Fri, 23 Jul 2021 14:55:30 +0800 Subject: [PATCH 352/362] ARM: dts: msm: Update phy timings based on Blair revision YK The display panel timings for Blair QRD need to be updated to match with latest timing revision to avoid display issues. Change-Id: I49cd26e2bde2dbc8100580269e06b0e159ecc2ca --- display/blair-sde-display-qrd.dtsi | 32 +++++++++++++++--------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi index e12529ae97cf..a197818eee41 100644 --- a/display/blair-sde-display-qrd.dtsi +++ b/display/blair-sde-display-qrd.dtsi @@ -5,18 +5,18 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 - 04 03 02 04 00 10 14]; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; }; timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00 15 15]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0b]; }; timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 - 07 08 02 04 00 1a 17]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; }; }; }; @@ -26,8 +26,8 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 - 07 08 02 04 00 1a 17]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; }; }; }; @@ -37,13 +37,13 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 - 04 03 02 04 00 10 14]; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; }; timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00 15 15]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0b]; }; }; }; @@ -53,8 +53,8 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00 15 15]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0b]; }; }; }; @@ -64,8 +64,8 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 - 04 03 02 04 00 10 14]; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; }; }; }; From 9ba06e2a19773fc7afbf640f3c1a5a31cbed458a Mon Sep 17 00:00:00 2001 From: osaisruj Date: Thu, 8 Jul 2021 22:06:41 +0530 Subject: [PATCH 353/362] ARM: dts: msm: Add rounded corner dtsi nodes for monaco add rounded corner feature dtsi nodes for monaco target. Change-Id: Ic8c7246dfcda8538285af53ecc69a10a782e0dd0 --- display/monaco-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 00150f1a4710..6a08b33837d0 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -79,6 +79,11 @@ qcom,sde-dspp-off = <0x55000>; qcom,sde-dspp-size = <0xfe4>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-intf-off = <0x0 0x6b800>; qcom,sde-intf-size = <0x2b8>; qcom,sde-intf-type = "none", "dsi"; From 4b45a9f7ef1754a36ca4eebeceb2f8dcaf7bfd42 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 29 Jul 2021 16:10:29 +0530 Subject: [PATCH 354/362] ARM: dts: msm: Add display support for Blair ATP platform Add DSI display support for the Blair ATP platform. Change-Id: I0fbd9e5548e065f12b07f1a070617899f9b0fbbc --- display/blair-sde-display-atp.dtsi | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 display/blair-sde-display-atp.dtsi diff --git a/display/blair-sde-display-atp.dtsi b/display/blair-sde-display-atp.dtsi new file mode 100644 index 000000000000..70996f26740e --- /dev/null +++ b/display/blair-sde-display-atp.dtsi @@ -0,0 +1,59 @@ +/* Should extend holi-sde-display-atp.dtsi */ +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; +}; + +&dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + /delete-property/ qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + /delete-property/ qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + From ed3dd2e2ab27b28d0256d4cc958aac6e65835a0a Mon Sep 17 00:00:00 2001 From: osaisruj Date: Fri, 9 Jul 2021 15:26:24 +0530 Subject: [PATCH 355/362] ARM: dts: msm: add idle mode commands in panel dtsi Add idle mode commands for RM69090 truly 1.78" amoled panel. Change-Id: I5989861547cc2cd83a735512f95c897489f3c19b --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi index 55601b26b6e5..9b5899fe751f 100644 --- a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -68,6 +68,18 @@ 15 01 00 00 00 00 02 4F 01]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-lp2-command = [ + 15 01 00 00 46 00 02 FE 00 + 05 01 00 00 00 00 01 39 + ]; + qcom,mdss-dsi-lp2-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 1f 00 01 38 /* Idle-Mode Off */ + 15 01 00 00 00 00 02 FE 00 + 29 01 00 00 00 00 05 2A 00 10 01 7F + 29 01 00 00 00 00 05 2B 00 00 01 BF + 05 01 00 00 00 00 02 12 00 + ]; }; }; }; From acd06dee63ea2264e03571aa06a6f66093c4cbd4 Mon Sep 17 00:00:00 2001 From: osaisruj Date: Mon, 26 Jul 2021 15:34:27 +0530 Subject: [PATCH 356/362] ARM: dts: msm: add panel dtsi for monaco WDP Add panel dtsi for RM6D030 1.41" amoled panel. Change-Id: Ide0d69cb6685b11910fea78f7c8f7f5e6042a3a5 --- display/dsi-panel-rm6d030-amoled-141-cmd.dtsi | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 display/dsi-panel-rm6d030-amoled-141-cmd.dtsi diff --git a/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi b/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi new file mode 100644 index 000000000000..4299f95bfbba --- /dev/null +++ b/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi @@ -0,0 +1,86 @@ +&mdss_mdp { + dsi_rm6d030_amoled_cmd: qcom,mdss_dsi_rm6d030_amoled_141_cmd { + qcom,mdss-dsi-panel-name = + "RM6D030 1.41 amoled cmd mode"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <320>; + qcom,mdss-dsi-panel-height = <360>; + qcom,mdss-dsi-h-front-porch = <40>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FE 00 + 15 01 00 00 00 00 02 C4 80 + 39 01 00 00 00 00 05 2A 00 06 01 61 + 39 01 00 00 00 00 05 2B 00 00 01 B9 + 39 01 00 00 00 00 05 30 00 01 01 B8 + 39 01 00 00 00 00 05 31 00 07 01 60 + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 51 FF + 05 01 00 00 60 00 02 11 00 + 05 01 00 00 00 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 15 01 00 00 00 00 02 4F 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-lp2-command = [ + 15 01 00 00 00 00 02 FE 00 + 05 01 00 00 00 00 01 39 + ]; + qcom,mdss-dsi-lp2-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 1f 00 01 38 /* Idle-Mode Off */ + 15 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 05 2A 00 06 01 61 + 39 01 00 00 00 00 05 2B 00 00 01 B9 + 05 01 00 00 00 00 02 12 00 + ]; + }; + }; + }; +}; From 4eed2800241bda6a23306bc34161637e03caa789 Mon Sep 17 00:00:00 2001 From: Yu Wu Date: Thu, 12 Aug 2021 18:01:03 +0800 Subject: [PATCH 357/362] ARM: dts: msm: update vddio for r66451 panel Panel dead happen randomly because of high panel power consumption, increase max vddio for r66451 panel to fix panel dead issue. Change-Id: Ib091cbab6ba4e9e1dd3f8a9ca4b6ad9afc36c174 --- display/blair-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi index a197818eee41..9d188f767321 100644 --- a/display/blair-sde-display-qrd.dtsi +++ b/display/blair-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ /* Should extend holi-sde-display-qrd-pm6125.dtsi */ +&dsi_panel_pwr_supply_avdd { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; + }; +}; + &dsi_r66451_amoled_cmd { /delete-property/ qcom,mdss-dsi-t-clk-post; /delete-property/ qcom,mdss-dsi-t-clk-pre; From f05ca8f9955b4151aafb09b5eb73da9e60ccce00 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Tue, 24 Aug 2021 19:08:56 +0530 Subject: [PATCH 358/362] ARM: dts: qcom: update idle mode commands for RM69090 cmd panel Add idle commands to enter 24 bit mode. Change-Id: I3228636ae019e02c1ddc12e8393e31d5496db767 --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi index 9b5899fe751f..760cb09ee2f0 100644 --- a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -69,6 +69,8 @@ qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-lp2-command = [ + 15 01 00 00 00 00 02 FE 01 + 15 01 00 00 00 00 02 2A 03 15 01 00 00 46 00 02 FE 00 05 01 00 00 00 00 01 39 ]; From 4d2df0a14d9351702a7041e782eeeba9e725a720 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Fri, 27 Aug 2021 13:56:21 +0530 Subject: [PATCH 359/362] ARM: dts: msm: add cpu irq latency for display Add recommended QOS settings. Change-Id: I5e419f9355373aaf043c2b047424da720402f5b9 --- display/monaco-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 6a08b33837d0..1518a5165ba5 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -158,6 +158,7 @@ qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-secure-sid-mask = <0x0000421>; qcom,sde-num-mnoc-ports = <1>; From e455ffb9152c77591f218de166f721647286fe19 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Fri, 16 Jul 2021 14:13:03 +0530 Subject: [PATCH 360/362] ARM: dts: msm: add dts of display for qrb2210-rb1 Add sde dts of display and HDMI panel dts for qrb2210-rb1. Change-Id: Iada831811666082ac934037fb1fca7b83263e197 --- display/dsi-panel-ext-bridge-1080p.dtsi | 4 +- display/qrb2210-rb1-sde-display.dtsi | 101 ++++++++ display/qrb2210-rb1-sde.dtsi | 322 ++++++++++++++++++++++++ 3 files changed, 425 insertions(+), 2 deletions(-) create mode 100644 display/qrb2210-rb1-sde-display.dtsi create mode 100644 display/qrb2210-rb1-sde.dtsi diff --git a/display/dsi-panel-ext-bridge-1080p.dtsi b/display/dsi-panel-ext-bridge-1080p.dtsi index 07d398e9e16c..38c25ef0d8fd 100644 --- a/display/dsi-panel-ext-bridge-1080p.dtsi +++ b/display/dsi-panel-ext-bridge-1080p.dtsi @@ -20,8 +20,8 @@ qcom,mdss-dsi-lane-3-state; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-t-clk-post = <0x03>; - qcom,mdss-dsi-t-clk-pre = <0x24>; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; diff --git a/display/qrb2210-rb1-sde-display.dtsi b/display/qrb2210-rb1-sde-display.dtsi new file mode 100644 index 000000000000..8d03ecffe89c --- /dev/null +++ b/display/qrb2210-rb1-sde-display.dtsi @@ -0,0 +1,101 @@ +#include +#include "dsi-panel-ext-bridge-1080p.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>, + <&mdss_dsi_phy0 PIX0_MUX_CLK>, + <&mdss_dsi_phy0 BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 PIX0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + vddio-supply = <&L15A>; + qcom,mdp = <&mdss_mdp>; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_dsi>; +}; diff --git a/display/qrb2210-rb1-sde.dtsi b/display/qrb2210-rb1-sde.dtsi new file mode 100644 index 000000000000..b37deff088c4 --- /dev/null +++ b/display/qrb2210-rb1-sde.dtsi @@ -0,0 +1,322 @@ +#include + +&soc { + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x420 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x421 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + mdss_mdp: qcom,mdss_mdp { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x8f030>, + <0x5eb0000 0x2008>, + <0x5e8f000 0x02c>, + <0xc125ba4 0x20>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys", + "sde_imem_phys"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + "div_clk", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0xfe4>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "none", "dsi"; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-mixer-stage-base-layer; + + qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <2700000>; + qcom,sde-max-bw-high-kbps = <2700000>; + qcom,sde-min-core-ib-kbps = <1300000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + + /*Pending macrotile & macrotile-qseed has the same configs */ + + qcom,sde-danger-lut = <0x000000ff 0x00000000 + 0x00000000 0x00000000 0x00000000>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + + qcom,sde-cdp-setting = <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-secure-sid-mask = <0x0000421>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-limits { + qcom,sde-linewidth-limits { + qcom,sde-limit-name = "sspp_linewidth_usecases"; + qcom,sde-limit-cases = "vig", "dma"; + qcom,sde-limit-ids= <0x1 0x2>; + qcom,sde-limit-values = <0x1 2160>, + <0x2 2160>; + }; + + qcom,sde-bw-limits { + qcom,sde-limit-name = "sde_bwlimit_usecases"; + qcom,sde-limit-cases = "per_vig_pipe", + "per_dma_pipe", + "total_max_bw", + "camera_concurrency"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2700000>, + <0x9 2700000>, + <0x2 2700000>, + <0xa 2700000>, + <0x4 2700000>, + <0xc 2700000>; + }; + }; + }; + + mdss_dsi0: qcom,mdss_dsi0_ctrl { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L5A>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1312000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x588>, + <0x5e01400 0x100>, + <0x5e94200 0x100>, + <0x5e94400 0x588>, + <0x5f03000 0x8>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base", "pll_base", "gdsc_base"; + pll-label = "dsi_pll_14nm"; + memory-region = <&dfps_data_memory>; + vdda-0p9-supply = <&VDD_MX_LEVEL>; + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; From 43ea79256774eafc441aeafe3e59da8cdd0f891f Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Sat, 28 Aug 2021 01:13:18 +0530 Subject: [PATCH 361/362] ARM: dts: msm: update max clk rate for display clocks Update max clk rates for mdp clks. Change-Id: I1732f73d1646d8aa08ffbaebfd6afacda07baaaf --- display/monaco-sde.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 1518a5165ba5..aee56512a059 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -40,8 +40,8 @@ clock-names = "gcc_bus", "throttle_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; - clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; - clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>; + clock-rate = <0 0 0 300000000 19200000 192000000>; + clock-max-rate = <0 0 0 400000000 19200000 400000000>; sde-vdd-supply = <&mdss_core_gdsc>; From daedd7b619731dfdfbef3d0d07a1c9128e2cf729 Mon Sep 17 00:00:00 2001 From: osaisruj Date: Tue, 17 Aug 2021 23:16:36 +0530 Subject: [PATCH 362/362] ARM: dts: msm: add panel support for monaco WDP Add RM6D030 1.41" amoled panel node for monaco. Change-Id: I4dbe5484ed4239a163d3b9d4653686624c5fdbff --- display/monaco-sde-display.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 96f16f6bede1..0bda2f93c0a0 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -1,5 +1,6 @@ #include #include "dsi-panel-rm69090-amoled-178-cmd.dtsi" +#include "dsi-panel-rm6d030-amoled-141-cmd.dtsi" &soc { dsi_panel_pwr_supply: dsi_panel_pwr_supply { @@ -132,3 +133,19 @@ }; }; +&dsi_rm6d030_amoled_cmd { + qcom,mdss-dsi-t-clk-post = <0x07>; + qcom,mdss-dsi-t-clk-pre = <0x0A>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0A 02 02 0F 1D 02 + 02 02 02 02 04 0A 07]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +};