A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-14 08:36:12 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge "dt-bindings: clock: dispcc: Remove mdss dp crypto clocks"

Browse source
This commit is contained in:
qctecmdr 2020-05-18 07:55:00 -07:00 • committed by Gerrit - the friendly Code Review server
commit 29c0add321
1 changed files with 47 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

98
include/dt-bindings/clock/qcom,dispcc-lahaina.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_LAHAINA_H
@ -21,56 +21,52 @@
#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
#define DISP_CC_MDSS_DP_AUX_CLK 12
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13
#define DISP_CC_MDSS_DP_CRYPTO1_CLK 14
#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC 15
#define DISP_CC_MDSS_DP_CRYPTO_CLK 16
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 17
#define DISP_CC_MDSS_DP_LINK1_CLK 18
#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 19
#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 20
#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 21
#define DISP_CC_MDSS_DP_LINK_CLK 22
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 23
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 24
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 25
#define DISP_CC_MDSS_DP_PIXEL1_CLK 26
#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 27
#define DISP_CC_MDSS_DP_PIXEL2_CLK 28
#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 29
#define DISP_CC_MDSS_DP_PIXEL_CLK 30
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 31
#define DISP_CC_MDSS_EDP_AUX_CLK 32
#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 33
#define DISP_CC_MDSS_EDP_LINK_CLK 34
#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 35
#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 36
#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 37
#define DISP_CC_MDSS_EDP_PIXEL_CLK 38
#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 39
#define DISP_CC_MDSS_ESC0_CLK 40
#define DISP_CC_MDSS_ESC0_CLK_SRC 41
#define DISP_CC_MDSS_ESC1_CLK 42
#define DISP_CC_MDSS_ESC1_CLK_SRC 43
#define DISP_CC_MDSS_MDP_CLK 44
#define DISP_CC_MDSS_MDP_CLK_SRC 45
#define DISP_CC_MDSS_MDP_LUT_CLK 46
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 47
#define DISP_CC_MDSS_PCLK0_CLK 48
#define DISP_CC_MDSS_PCLK0_CLK_SRC 49
#define DISP_CC_MDSS_PCLK1_CLK 50
#define DISP_CC_MDSS_PCLK1_CLK_SRC 51
#define DISP_CC_MDSS_ROT_CLK 52
#define DISP_CC_MDSS_ROT_CLK_SRC 53
#define DISP_CC_MDSS_RSCC_AHB_CLK 54
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 55
#define DISP_CC_MDSS_VSYNC_CLK 56
#define DISP_CC_MDSS_VSYNC_CLK_SRC 57
#define DISP_CC_PLL0 58
#define DISP_CC_PLL1 59
#define DISP_CC_SLEEP_CLK 60
#define DISP_CC_SLEEP_CLK_SRC 61
#define DISP_CC_XO_CLK 62
#define DISP_CC_XO_CLK_SRC 63
#define DISP_CC_MDSS_DP_LINK1_CLK 14
#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15
#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16
#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17
#define DISP_CC_MDSS_DP_LINK_CLK 18
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21
#define DISP_CC_MDSS_DP_PIXEL1_CLK 22
#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23
#define DISP_CC_MDSS_DP_PIXEL2_CLK 24
#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25
#define DISP_CC_MDSS_DP_PIXEL_CLK 26
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27
#define DISP_CC_MDSS_EDP_AUX_CLK 28
#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 29
#define DISP_CC_MDSS_EDP_LINK_CLK 30
#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 31
#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 32
#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 33
#define DISP_CC_MDSS_EDP_PIXEL_CLK 34
#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 35
#define DISP_CC_MDSS_ESC0_CLK 36
#define DISP_CC_MDSS_ESC0_CLK_SRC 37
#define DISP_CC_MDSS_ESC1_CLK 38
#define DISP_CC_MDSS_ESC1_CLK_SRC 39
#define DISP_CC_MDSS_MDP_CLK 40
#define DISP_CC_MDSS_MDP_CLK_SRC 41
#define DISP_CC_MDSS_MDP_LUT_CLK 42
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 43
#define DISP_CC_MDSS_PCLK0_CLK 44
#define DISP_CC_MDSS_PCLK0_CLK_SRC 45
#define DISP_CC_MDSS_PCLK1_CLK 46
#define DISP_CC_MDSS_PCLK1_CLK_SRC 47
#define DISP_CC_MDSS_ROT_CLK 48
#define DISP_CC_MDSS_ROT_CLK_SRC 49
#define DISP_CC_MDSS_RSCC_AHB_CLK 50
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 51
#define DISP_CC_MDSS_VSYNC_CLK 52
#define DISP_CC_MDSS_VSYNC_CLK_SRC 53
#define DISP_CC_PLL0 54
#define DISP_CC_PLL1 55
#define DISP_CC_SLEEP_CLK 56
#define DISP_CC_SLEEP_CLK_SRC 57
#define DISP_CC_XO_CLK 58
#define DISP_CC_XO_CLK_SRC 59
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0