From 29c930cf5719a88ec7ec44fef3f73ac8448046d5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 29 Oct 2020 19:39:14 +0530 Subject: [PATCH] interconnect: qcom: Add OSM L3 support on SM8150 Add Operating State Manager (OSM) L3 interconnect provider support on SM8150 SoCs. Change-Id: I0e6c48fd04c16711dfc9a29ad27471e7f5464efc Signed-off-by: Veera Vegivada --- drivers/interconnect/qcom/osm-l3.c | 34 +++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index d5aaaea34dbb..c69f41bc864e 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -25,7 +25,7 @@ #define REG_FREQ_LUT 0x110 #define REG_PERF_STATE 0x920 -#define OSM_L3_MAX_LINKS 1 +#define OSM_L3_MAX_LINKS 6 #define to_qcom_provider(_provider) \ container_of(_provider, struct qcom_osm_l3_icc_provider, provider) @@ -33,6 +33,11 @@ enum { OSM_MASTER_L3_APPS = 5000, OSM_SLAVE_L3, + OSM_SLAVE_L3_CLUSTER0, + OSM_SLAVE_L3_CLUSTER1, + OSM_SLAVE_L3_CLUSTER2, + OSM_SLAVE_L3_GPU, + OSM_SLAVE_L3_MISC, }; struct qcom_osm_l3_icc_provider { @@ -85,6 +90,32 @@ const static struct qcom_icc_desc sdm845_icc_osm_l3 = { .num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes), }; +DEFINE_QNODE(sm8150_osm_apps_l3, OSM_MASTER_L3_APPS, 1, + OSM_SLAVE_L3, OSM_SLAVE_L3_CLUSTER0, + OSM_SLAVE_L3_CLUSTER1, OSM_SLAVE_L3_CLUSTER2, + OSM_SLAVE_L3_MISC, OSM_SLAVE_L3_GPU); +DEFINE_QNODE(sm8150_osm_l3, OSM_SLAVE_L3, 1); +DEFINE_QNODE(sm8150_osm_l3_cluster0, OSM_SLAVE_L3_CLUSTER0, 1); +DEFINE_QNODE(sm8150_osm_l3_cluster1, OSM_SLAVE_L3_CLUSTER1, 1); +DEFINE_QNODE(sm8150_osm_l3_cluster2, OSM_SLAVE_L3_CLUSTER2, 1); +DEFINE_QNODE(sm8150_osm_l3_misc, OSM_SLAVE_L3_MISC, 1); +DEFINE_QNODE(sm8150_osm_l3_gpu, OSM_SLAVE_L3_GPU, 1); + +static struct qcom_icc_node *sm8150_osm_l3_nodes[] = { + [MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3, + [SLAVE_OSM_L3] = &sm8150_osm_l3, + [SLAVE_OSM_L3_CLUSTER0] = &sm8150_osm_l3_cluster0, + [SLAVE_OSM_L3_CLUSTER1] = &sm8150_osm_l3_cluster1, + [SLAVE_OSM_L3_CLUSTER2] = &sm8150_osm_l3_cluster2, + [SLAVE_OSM_L3_MISC] = &sm8150_osm_l3_misc, + [SLAVE_OSM_L3_GPU] = &sm8150_osm_l3_gpu, +}; + +static const struct qcom_icc_desc sm8150_icc_osm_l3 = { + .nodes = sm8150_osm_l3_nodes, + .num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes), +}; + static int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak) { @@ -253,6 +284,7 @@ err: static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, + { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match);