From 2a1379fdfde18c3ec4ab5c62bb5692ca86c09d2d Mon Sep 17 00:00:00 2001 From: houdz1 Date: Fri, 15 Jan 2021 16:30:57 +0800 Subject: [PATCH] display/holi: support the configuration of strength offset in each projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The clock and data lanes have a calibration circuitry feature. To offset the drive strength from the calibrated value in an increasing or decreasing manner, use 6 bit two’s complement values. For some project ,will change the strength offset to reduce the mipi voltage, to fix rf desense issue. By default, there are only two bytes to config the strength of lane. Support the configuration of strength offset in each projects, we must expand to 4 bytes. And the default value is 0. Change-Id: Ifaa2a0024b10176c638d4bc44756f9d09a1927ef Signed-off-by: houdz1 Reviewed-on: https://gerrit.mot.com/1852325 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Yeqing Wang Reviewed-by: Huosheng Liao Submit-Approved: Jira Key --- qcom/holi-moto-common-overlay.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/holi-moto-common-overlay.dtsi b/qcom/holi-moto-common-overlay.dtsi index 46dc407fa39f..996398a2885c 100644 --- a/qcom/holi-moto-common-overlay.dtsi +++ b/qcom/holi-moto-common-overlay.dtsi @@ -584,3 +584,11 @@ &ufshc_mem { spm-level = <3>; }; + +&mdss_dsi_phy0 { + qcom,platform-strength-ctrl = [55 03 00 00 + 55 03 00 00 + 55 03 00 00 + 55 03 00 00 + 55 00 00 00]; +};