From 2aa0a1534eda37e7995135bda346391a2a80df7e Mon Sep 17 00:00:00 2001 From: wangyq13 Date: Sun, 1 Aug 2021 17:42:15 +0800 Subject: [PATCH] arm/dt: corfur: set mipi clk to 1103.16 for rf arm/dt: Set mipi clk to 1103.16 for rf. Change panel ic osc clk. Change power off timing. Change-Id: I75d66866026b827a4a0458d39ba946c955c06feb Signed-off-by: wangyq13 Reviewed-on: https://gerrit.mot.com/2030039 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Huosheng Liao Submit-Approved: Jira Key --- qcom/corfup-display.dtsi | 2 +- qcom/corfuq-display.dtsi | 2 +- qcom/corfur-display.dtsi | 8 ++--- ...anel-mot-visionox-vtdr6110c-fhd-video.dtsi | 32 ++++++++++--------- 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/qcom/corfup-display.dtsi b/qcom/corfup-display.dtsi index 2d8fb2dcaf51..94db6eb18fc7 100644 --- a/qcom/corfup-display.dtsi +++ b/qcom/corfup-display.dtsi @@ -86,7 +86,7 @@ qcom,mdss-dsi-t-clk-pre = <0x3B>; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 09 02 04 00]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; diff --git a/qcom/corfuq-display.dtsi b/qcom/corfuq-display.dtsi index 2a0a7bc2c5da..a39344862ed7 100644 --- a/qcom/corfuq-display.dtsi +++ b/qcom/corfuq-display.dtsi @@ -58,7 +58,7 @@ qcom,mdss-dsi-t-clk-pre = <0x3B>; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 09 02 04 00]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; diff --git a/qcom/corfur-display.dtsi b/qcom/corfur-display.dtsi index 1b06df5a6b30..3f46c737a173 100644 --- a/qcom/corfur-display.dtsi +++ b/qcom/corfur-display.dtsi @@ -54,12 +54,12 @@ qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0E>; - qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-t-clk-pre = <0x1F>; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 - 09 09 02 04 00 1D 0E]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A + 0A 09 02 04 00 1F 1A]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; }; diff --git a/qcom/dsi-panel-mot-visionox-vtdr6110c-fhd-video.dtsi b/qcom/dsi-panel-mot-visionox-vtdr6110c-fhd-video.dtsi index f71b3ab694cb..108497c502bb 100644 --- a/qcom/dsi-panel-mot-visionox-vtdr6110c-fhd-video.dtsi +++ b/qcom/dsi-panel-mot-visionox-vtdr6110c-fhd-video.dtsi @@ -41,9 +41,9 @@ timing@0 { qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <2400>; - qcom,mdss-dsi-h-front-porch = <40>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <88>; + qcom,mdss-dsi-h-pulse-width = <4>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-v-back-porch = <14>; @@ -56,22 +56,24 @@ qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-on-command = [ - 15 01 00 00 00 00 02 35 00 - 15 01 00 00 00 00 02 53 20 - 39 01 00 00 00 00 03 51 00 00 - 15 01 00 00 00 00 02 6F 01 - 15 01 00 00 00 00 02 59 09 - 39 01 00 00 00 00 03 F0 AA 10 - 39 01 00 00 00 00 03 EA 30 00 - 39 01 00 00 00 00 03 F0 AA 11 - 39 01 00 00 00 00 03 BB 10 21 - 39 01 00 00 00 00 03 F0 AA 00 + 15 00 00 00 00 00 02 35 00 + 15 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 15 00 00 00 00 00 02 6F 01 + 15 00 00 00 00 00 02 59 09 + 39 00 00 00 00 00 03 F0 AA 10 + 39 00 00 00 00 00 03 EA 30 00 + 39 00 00 00 00 00 03 F0 AA 11 + 39 00 00 00 00 00 03 BB 10 21 + 39 00 00 00 00 00 03 F0 AA 12 + 15 00 00 00 00 00 02 C8 84 + 39 00 00 00 00 00 03 F0 AA 00 05 01 00 00 78 00 01 11 05 01 00 00 01 00 01 29 ]; qcom,mdss-dsi-off-command = [ - 05 01 00 00 44 00 01 28 - 05 01 00 00 00 00 01 10 + 05 01 00 00 14 00 01 28 + 05 01 00 00 78 00 01 10 ]; qcom,mdss-dsi-t-clk-post = <0x0E>; qcom,mdss-dsi-t-clk-pre = <0x35>;