coresight: ost: Add snapshot of Coresight OST driver

This is a snapshot of the coresight-cti driver as of msm-4.14
commit '7d42028b99d32ad6ec82aa429378fba0280a1c4a'.byte-cntr: Read 64bit rwp
TMC RWP has two 32bit registers which combine to one 64bit register.
Read correct RWP register in byte counter driver.
Make necessary change to adopt coresight framework change.

Change-Id: I4a89b9b041c354093b96e01ee0436a7372ff37fd
Signed-off-by: Rama Aparna Mallavarapu <aparnam@codeaurora.org>
Signed-off-by: Mulu He <muluhe@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
This commit is contained in:
Rama Aparna Mallavarapu 2017-10-12 16:05:08 -07:00 • committed by Tingwei Zhang
commit 2aa23d3acc
9 changed files with 554 additions and 73 deletions

View file

@ -2,9 +2,18 @@
#ifndef __UAPI_CORESIGHT_STM_H_
#define __UAPI_CORESIGHT_STM_H_
#define STM_FLAG_TIMESTAMPED BIT(3)
#define STM_FLAG_GUARANTEED BIT(7)
#define STM_FLAG_NONE 0x00
#define STM_FLAG_TIMESTAMPED 0x08
#define STM_FLAG_GUARANTEED 0x80
#define OST_ENTITY_NONE 0x00
#define OST_ENTITY_FTRACE_EVENTS 0x01
#define OST_ENTITY_TRACE_PRINTK 0x02
#define OST_ENTITY_TRACE_MARKER 0x04
#define OST_ENTITY_DEV_NODE 0x08
#define OST_ENTITY_DIAG 0xEE
#define OST_ENTITY_QVIEW 0xFE
#define OST_ENTITY_MAX 0xFF
/*
* The CoreSight STM supports guaranteed and invariant timing
* transactions. Guaranteed transactions are guaranteed to be