From 2b20b03859ed480f0e1abbd7e43f284bea6b762f Mon Sep 17 00:00:00 2001 From: Satya Durga Srinivasu Prabhala Date: Mon, 13 Jan 2020 15:08:19 -0800 Subject: [PATCH] ARM: dts: msm: update DPC properties for Lahaina Update DPC values for Lahaina as per latest data. Change-Id: I2b079afab7362ecc3e3734fb7fbcc764186ea9e8 --- qcom/lahaina.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 6b8aef464f33..c3493a58d91b 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -133,7 +133,7 @@ cache-size = <0x20000>; cpu-release-addr = <0x0 0x90000000>; capacity-dmips-mhz = <1946>; - dynamic-power-coefficient = <454>; + dynamic-power-coefficient = <515>; cpu-idle-states = <&GOLD_RAIL_OFF>; next-level-cache = <&L2_4>; L2_4: l2-cache { @@ -152,7 +152,7 @@ cache-size = <0x20000>; cpu-release-addr = <0x0 0x90000000>; capacity-dmips-mhz = <1946>; - dynamic-power-coefficient = <454>; + dynamic-power-coefficient = <515>; cpu-idle-states = <&GOLD_RAIL_OFF>; next-level-cache = <&L2_5>; L2_5: l2-cache { @@ -171,7 +171,7 @@ cache-size = <0x20000>; cpu-release-addr = <0x0 0x90000000>; capacity-dmips-mhz = <1946>; - dynamic-power-coefficient = <454>; + dynamic-power-coefficient = <515>; cpu-idle-states = <&GOLD_RAIL_OFF>; next-level-cache = <&L2_6>; L2_6: l2-cache { @@ -190,7 +190,7 @@ cache-size = <0x20000>; cpu-release-addr = <0x0 0x90000000>; capacity-dmips-mhz = <2048>; - dynamic-power-coefficient = <704>; + dynamic-power-coefficient = <845>; cpu-idle-states = <&GOLD_RAIL_OFF>; next-level-cache = <&L2_7>; L2_7: l2-cache {