From 2b2f29cc506d61709ea81ff6bae1dcad548f5b6f Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Wed, 12 Aug 2020 14:35:11 -0600 Subject: [PATCH] msm: kgsl: Fix gmu fence error during slumber There can exist a race where we clear the A6XX_RBBM_INT_0_MASK register while the gpu is going into IFPC. Fix this by clearing this register before clearing the OOB. Change-Id: I08e9dbccbfdbee93ba7ef35fbbc673938ee033da Signed-off-by: Harshdeep Dhatt --- drivers/gpu/msm/adreno_a6xx_gmu.c | 4 +++- drivers/gpu/msm/adreno_a6xx_rgmu.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 92bda0fbac27..3ac50f63588b 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -3069,10 +3069,12 @@ static int a6xx_power_off(struct adreno_device *adreno_dev) if (adreno_is_a630(adreno_dev)) a630_vbif_halt(adreno_dev); + adreno_irqctrl(adreno_dev, 0); + a6xx_gmu_oob_clear(device, oob_gpu); no_gx_power: - a6xx_disable_gpu_irq(adreno_dev); + kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF); a6xx_gmu_power_off(adreno_dev); diff --git a/drivers/gpu/msm/adreno_a6xx_rgmu.c b/drivers/gpu/msm/adreno_a6xx_rgmu.c index 55f1ac8d9c3e..a4b5a4daa8af 100644 --- a/drivers/gpu/msm/adreno_a6xx_rgmu.c +++ b/drivers/gpu/msm/adreno_a6xx_rgmu.c @@ -1056,6 +1056,8 @@ static int a6xx_power_off(struct adreno_device *adreno_dev) /* Save physical performance counter values before GPU power down*/ adreno_perfcounter_save(adreno_dev); + adreno_irqctrl(adreno_dev, 0); + a6xx_rgmu_prepare_stop(device); a6xx_rgmu_oob_clear(device, oob_gpu); @@ -1067,7 +1069,7 @@ no_gx_power: adreno_wait_for_halt_ack(device, ADRENO_REG_GBIF_HALT_ACK, A6XX_GBIF_CLIENT_HALT_MASK); - a6xx_disable_gpu_irq(adreno_dev); + kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF); a6xx_rgmu_power_off(adreno_dev);