mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 08:36:12 -04:00
Merge "ARM: dts: msm: Add clock controllers and gdsc nodes for SM6150"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
2b32c317fb
4 changed files with 487 additions and 0 deletions
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@ -7,3 +7,31 @@
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qcom,msm-name = "SA6155";
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qcom,msm-id = <384 0x10000>;
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};
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&gcc {
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compatible = "qcom,sa6155-gcc", "syscon";
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/delete-property/ protected-clocks;
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};
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&camcc {
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compatible = "qcom,sa6155-camcc", "syscon";
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vdd_mx-supply = <&VDD_CX_LEVEL>;
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};
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&dispcc {
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compatible = "qcom,sa6155-dispcc", "syscon";
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};
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&gpucc {
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compatible = "qcom,sa6155-gpucc", "syscon";
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vdd_mx-supply = <&VDD_CX_LEVEL>;
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};
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&scc {
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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status = "ok"
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};
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&videocc {
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compatible = "qcom,sa6155-videocc", "syscon";
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};
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@ -19,3 +19,31 @@
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/delete-node/ rpmh-regulator-ldoc18;
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/delete-node/ bt_wcn3990;
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};
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&gcc {
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compatible = "qcom,sa6155-gcc", "syscon";
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/delete-property/ protected-clocks;
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};
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&camcc {
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compatible = "qcom,sa6155-camcc", "syscon";
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vdd_mx-supply = <&VDD_CX_LEVEL>;
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};
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&dispcc {
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compatible = "qcom,sa6155-dispcc", "syscon";
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};
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&gpucc {
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compatible = "qcom,sa6155-gpucc", "syscon";
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vdd_mx-supply = <&VDD_CX_LEVEL>;
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};
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&scc {
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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status = "ok"
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};
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&videocc {
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compatible = "qcom,sa6155-videocc", "syscon";
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};
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186
qcom/sm6150-gdsc.dtsi
Normal file
186
qcom/sm6150-gdsc.dtsi
Normal file
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@ -0,0 +1,186 @@
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&soc {
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/* GDSCs in Global CC */
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emac_gdsc: qcom,gdsc@106004 {
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compatible = "qcom,gdsc";
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reg = <0x106004 0x4>;
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regulator-name = "emac_gdsc";
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status = "disabled";
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};
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pcie_0_gdsc: qcom,gdsc@16b004 {
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compatible = "qcom,gdsc";
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reg = <0x16b004 0x4>;
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regulator-name = "pcie_0_gdsc";
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status = "disabled";
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};
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ufs_phy_gdsc: qcom,gdsc@177004 {
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compatible = "qcom,gdsc";
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reg = <0x177004 0x4>;
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regulator-name = "ufs_phy_gdsc";
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status = "disabled";
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};
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usb20_sec_gdsc: qcom,gdsc@1a6004 {
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compatible = "qcom,gdsc";
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reg = <0x1a6004 0x4>;
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regulator-name = "usb20_sec_gdsc";
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status = "disabled";
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};
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usb30_prim_gdsc: qcom,gdsc@10f004 {
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compatible = "qcom,gdsc";
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reg = <0x10f004 0x4>;
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regulator-name = "usb30_prim_gdsc";
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 {
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compatible = "qcom,gdsc";
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reg = <0x17d040 0x4>;
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regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 {
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compatible = "qcom,gdsc";
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reg = <0x17d044 0x4>;
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regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 {
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compatible = "qcom,gdsc";
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reg = <0x17d048 0x4>;
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regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c {
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compatible = "qcom,gdsc";
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reg = <0x17d04c 0x4>;
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regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
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compatible = "qcom,gdsc";
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reg = <0x17d050 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 {
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compatible = "qcom,gdsc";
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reg = <0x17d054 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
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compatible = "qcom,gdsc";
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reg = <0x17d058 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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/* GDSCs in Camera CC */
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bps_gdsc: qcom,gdsc@ad06004 {
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compatible = "qcom,gdsc";
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reg = <0xad06004 0x4>;
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regulator-name = "bps_gdsc";
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status = "disabled";
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};
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ife_0_gdsc: qcom,gdsc@ad09004 {
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compatible = "qcom,gdsc";
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reg = <0xad09004 0x4>;
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regulator-name = "ife_0_gdsc";
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status = "disabled";
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};
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ife_1_gdsc: qcom,gdsc@ad0a004 {
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compatible = "qcom,gdsc";
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reg = <0xad0a004 0x4>;
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regulator-name = "ife_1_gdsc";
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status = "disabled";
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};
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ipe_0_gdsc: qcom,gdsc@ad07004 {
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compatible = "qcom,gdsc";
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reg = <0xad07004 0x4>;
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regulator-name = "ipe_0_gdsc";
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status = "disabled";
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};
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titan_top_gdsc: qcom,gdsc@ad0b134 {
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compatible = "qcom,gdsc";
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reg = <0xad0b134 0x4>;
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regulator-name = "titan_top_gdsc";
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status = "disabled";
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};
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/* GDSCs in Display CC */
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mdss_core_gdsc: qcom,gdsc@af03000 {
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compatible = "qcom,gdsc";
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reg = <0xaf03000 0x4>;
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regulator-name = "mdss_core_gdsc";
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qcom,support-hw-trigger;
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status = "disabled";
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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};
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/* GDSCs in Graphics CC */
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gpu_cx_hw_ctrl: syscon@5091540 {
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compatible = "syscon";
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reg = <0x5091540 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@509106c {
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compatible = "qcom,gdsc";
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reg = <0x509106c 0x4>;
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regulator-name = "gpu_cx_gdsc";
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hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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qcom,clk-dis-wait-val = <8>;
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status = "disabled";
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};
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gpu_gx_gdsc: qcom,gdsc@509100c {
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compatible = "qcom,gdsc";
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reg = <0x509100c 0x4>;
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regulator-name = "gpu_gx_gdsc";
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status = "disabled";
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};
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/* GDSCs in Video CC */
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vcodec0_gdsc: qcom,gdsc@ab00874 {
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compatible = "qcom,gdsc";
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reg = <0xab00874 0x4>;
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regulator-name = "vcodec0_gdsc";
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status = "disabled";
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};
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venus_gdsc: qcom,gdsc@ab00814 {
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compatible = "qcom,gdsc";
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reg = <0xab00814 0x4>;
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regulator-name = "venus_gdsc";
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status = "disabled";
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};
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};
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245
qcom/sm6150.dtsi
245
qcom/sm6150.dtsi
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@ -1,5 +1,11 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,camcc-sm6150.h>
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#include <dt-bindings/clock/qcom,dispcc-sm6150.h>
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#include <dt-bindings/clock/qcom,gpucc-sm6150.h>
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#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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#include <dt-bindings/clock/qcom,scc-sm6150.h>
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#include <dt-bindings/clock/qcom,videocc-sm6150.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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@ -615,6 +621,38 @@
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interrupt-controller;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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scc_pll: scc_pll {
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compatible = "fixed-clock";
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clock-frequency = <600000000>;
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clock-output-names = "scc_pll";
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#clock-cells = <0>;
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};
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scc_pll_out_aux: scc_pll_out_aux {
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compatible = "fixed-factor-clock";
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clock-output-names = "scc_pll_out_aux";
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clocks = <&scc_pll>;
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clock-mult = <1>;
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clock-div = <2>;
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#clock-cells = <0>;
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};
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};
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qcom,msm-imem@146aa000 {
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compatible = "qcom,msm-imem";
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reg = <0x146aa000 0x1000>;
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@ -714,9 +752,216 @@
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<ACTIVE_TCS 2>,
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<CONTROL_TCS 0>;
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};
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gcc: clock-controller@100000 {
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compatible = "qcom,sm6150-gcc", "syscon";
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reg = <0x100000 0x1f0000>;
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reg-name = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>;
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clock-names = "bi_tcxo",
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"bi_tcxo_ao",
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"sleep_clk";
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protected-clocks = <GCC_SDR_CORE_CLK>,
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<GCC_SDR_WR0_MEM_CLK>,
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<GCC_SDR_WR1_MEM_CLK>,
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<GCC_SDR_WR2_MEM_CLK>,
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<GCC_SDR_CSR_HCLK>,
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<GCC_SDR_PRI_MI2S_CLK>,
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<GCC_SDR_SEC_MI2S_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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camcc: clock-controller@ad00000 {
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compatible = "qcom,sm6150-camcc", "syscon";
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reg = <0xad00000 0x10000>;
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reg-name = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "bi_tcxo";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sm6150-dispcc", "syscon";
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reg = <0xaf00000 0x20000>;
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reg-name = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
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clock-names = "bi_tcxo", "gpll0";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpucc: clock-controller@5090000 {
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compatible = "qcom,sm6150-gpucc", "syscon";
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reg = <0x5090000 0x9000>;
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reg-name = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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clock-names = "bi_tcxo", "gpll0";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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scc: clock-controller@62b10000 {
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compatible = "qcom,sa6155-scc", "syscon";
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reg = <0x62b10000 0x30000>;
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reg-name = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>, <&scc_pll>,
|
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<&scc_pll_out_aux>;
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clock-names = "bi_tcxo", "sleep_clk",
|
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"scc_pll", "scc_pll_out_aux";
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#clock-cells = <1>;
|
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#reset-cells = <1>;
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status = "disabled";
|
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};
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|
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videocc: clock-controller@ab00000 {
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compatible = "qcom,sm6150-videocc", "syscon";
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reg = <0xab00000 0x10000>;
|
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reg-name = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
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clock-names = "bi_tcxo", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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||||
};
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|
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apsscc: syscon@182a0000 {
|
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compatible = "syscon";
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reg = <0x182a0000 0x1c>;
|
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};
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|
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mccc: syscon@90b0000 {
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compatible = "syscon";
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reg = <0x90b0000 0x54>;
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};
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|
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debugcc: debug-clock-controller@0 {
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compatible = "qcom,sm6150-debugcc";
|
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qcom,apsscc = <&apsscc>;
|
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qcom,camcc = <&camcc>;
|
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qcom,dispcc = <&dispcc>;
|
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qcom,gcc = <&gcc>;
|
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qcom,gpucc = <&gpucc>;
|
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qcom,mccc = <&mccc>;
|
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qcom,videocc = <&videocc>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo_clk_src";
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#clock-cells = <1>;
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||||
};
|
||||
};
|
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|
||||
#include "sm6150-qupv3.dtsi"
|
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#include "sm6150-pinctrl.dtsi"
|
||||
#include "sm6150-pm.dtsi"
|
||||
#include "sm6150-regulator.dtsi"
|
||||
#include "sm6150-gdsc.dtsi"
|
||||
|
||||
&emac_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&pcie_0_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ufs_phy_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&usb30_prim_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&usb20_sec_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&bps_gdsc {
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ife_0_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ife_1_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ipe_0_gdsc {
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&titan_top_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&mdss_core_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&gpu_cx_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&gpu_gx_gdsc {
|
||||
clock-names = "core_root_clk";
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK_SRC>;
|
||||
qcom,force-enable-root-clk;
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&vcodec0_gdsc {
|
||||
qcom,support-hw-trigger;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&venus_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue