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msm: ep-pcie: Support 16.6 MHz Aux clock for PCIe Gen4 Controller

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If the devicetree property for aux clock is present run the clock
at 16.6 MHz. Otherwise default aux clock value to 19.2 MHz.
Introduced for PCIe Gen4 support but can be used in the
future if controller needs 16.6 MHz clock support.

Change-Id: I8a4b3ab4cbd44938f1c9bf8fa91a791ba289ee10
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
This commit is contained in:
Gauri Joshi 2021-02-09 18:14:58 -08:00
commit 2b66ad4b59
2 changed files with 15 additions and 2 deletions
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1
drivers/platform/msm/ep_pcie/ep_pcie_com.h
View file

@ -367,6 +367,7 @@ struct ep_pcie_dev_t {
u32 rev;
u32 phy_rev;
u32 aux_clk_val;
void *ipc_log_sel;
void *ipc_log_ful;
void *ipc_log_dump;

16
drivers/platform/msm/ep_pcie/ep_pcie_core.c
View file

@ -839,7 +839,7 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)
}
if (dev->active_config) {
ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14);
ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, dev->aux_clk_val);
/* Prevent L1ss wakeup after 100ms */
ep_pcie_write_mask(dev->dm_core + PCIE20_GEN3_RELATED_OFF,
@ -1926,7 +1926,7 @@ checkbme:
ep_pcie_core_toggle_wake_gpio(false);
if (dev->active_config)
ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14);
ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, dev->aux_clk_val);
if (!(opt & EP_PCIE_OPT_ENUM_ASYNC)) {
/* Wait for up to 1000ms for BME to be set */
@ -3310,6 +3310,18 @@ static int ep_pcie_probe(struct platform_device *pdev)
ep_pcie_dev.mhi_soc_reset_en = true;
}
ep_pcie_dev.aux_clk_val = 0x14;
ret = of_property_read_u32((&pdev->dev)->of_node, "qcom,aux-clk",
&ep_pcie_dev.aux_clk_val);
if (ret)
EP_PCIE_DBG(&ep_pcie_dev,
"PCIe V%d: Using default value 19.2 MHz.\n",
ep_pcie_dev.rev);
else
EP_PCIE_DBG(&ep_pcie_dev,
"PCIe V%d: Gen4 using aux_clk = 16.6 MHz\n",
ep_pcie_dev.rev);
memcpy(ep_pcie_dev.vreg, ep_pcie_vreg_info,
sizeof(ep_pcie_vreg_info));
memcpy(ep_pcie_dev.gpio, ep_pcie_gpio_info,