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ARM: dts: msm: Add NFC I3C device node for Lahaina

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Device node changes required on lahaina describing
the GPIO configuration for NFC I3C controller chip.

Modified corresponding NFC device node for
MTP, CDP and QRD platforms.

Change-Id: I93ffc68c70dc0a1a06a1c36c63531be8f0802ffb
This commit is contained in:
Gaurav Singhal 2020-02-29 10:32:23 +05:30
commit 2b91009d30
4 changed files with 146 additions and 0 deletions
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20
qcom/lahaina-cdp.dtsi
View file

@ -76,6 +76,26 @@
};
};
&i3c3 {
se-clock-frequency = <19200000>;
i3c-scl-hz = <3500000>;
i2c-scl-hz = <400000>;
status = "ok"
sn@0,23600000000 {
compatible = "qcom,sn-nci-i3c";
reg = <0x0 0x236 0x00000000>;
qcom,sn-ven = <&tlmm 62 0x00>;
qcom,sn-firm = <&tlmm 86 0x00>;
qcom,sn-clkreq = <&tlmm 63 0x00>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nfc_enable_active &nfc_fwdl_active
&nfc_clk_req_active>;
pinctrl-1 = <&nfc_enable_suspend &nfc_fwdl_suspend
&nfc_clk_req_suspend>;
};
};
&sdhc_2 {
vdd-supply = <&pm8350c_l9>;
qcom,vdd-voltage-level = <2950000 2960000>;

20
qcom/lahaina-mtp.dtsi
View file

@ -78,6 +78,26 @@
};
};
&i3c3 {
se-clock-frequency = <19200000>;
i3c-scl-hz = <3500000>;
i2c-scl-hz = <400000>;
status = "ok"
sn@0,23600000000 {
compatible = "qcom,sn-nci-i3c";
reg = <0x0 0x236 0x00000000>;
qcom,sn-ven = <&tlmm 62 0x00>;
qcom,sn-firm = <&tlmm 86 0x00>;
qcom,sn-clkreq = <&tlmm 63 0x00>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nfc_enable_active &nfc_fwdl_active
&nfc_clk_req_active>;
pinctrl-1 = <&nfc_enable_suspend &nfc_fwdl_suspend
&nfc_clk_req_suspend>;
};
};
&sdhc_2 {
vdd-supply = <&pm8350c_l9>;
qcom,vdd-voltage-level = <2950000 2960000>;

86
qcom/lahaina-pinctrl.dtsi
View file

@ -389,6 +389,92 @@
};
};
nfc {
nfc_enable_active: nfc_enable_active {
mux {
pins = "gpio62";
function = "gpio";
};
config {
pins = "gpio62";
drive-strength = <2>; /* 2 MA */
bias-pull-up;
};
};
nfc_enable_suspend: nfc_enable_suspend {
mux {
pins = "gpio62";
function = "gpio";
};
config {
pins = "gpio62";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
nfc_fwdl_active: nfc_fwdl_active {
mux {
/* 86: Firmware */
pins = "gpio86";
function = "gpio";
};
config {
pins = "gpio86";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
nfc_fwdl_suspend: nfc_fwdl_suspend {
mux {
/*86: Firmware */
pins = "gpio86";
function = "gpio";
};
config {
pins = "gpio86";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
nfc_clk_req_active: nfc_clk_req_active {
/* active state */
mux {
/* GPIO 63: NFC CLOCK REQUEST */
pins = "gpio63";
function = "gpio";
};
config {
pins = "gpio63";
drive-strength = <2>; /* 2 MA */
bias-pull-up;
};
};
nfc_clk_req_suspend: nfc_clk_req_suspend {
/* sleep state */
mux {
/* GPIO 63: NFC CLOCK REQUEST */
pins = "gpio63";
function = "gpio";
};
config {
pins = "gpio63";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
};
/* SPI */
qupv3_se0_spi_pins: qupv3_se0_spi_pins {
qupv3_se0_spi_active: qupv3_se0_spi_active {

20
qcom/lahaina-qrd.dtsi
View file

@ -157,6 +157,26 @@
};
};
&i3c3 {
se-clock-frequency = <19200000>;
i3c-scl-hz = <3500000>;
i2c-scl-hz = <400000>;
status = "ok"
sn@0,23600000000 {
compatible = "qcom,sn-nci-i3c";
reg = <0x0 0x236 0x00000000>;
qcom,sn-ven = <&tlmm 62 0x00>;
qcom,sn-firm = <&tlmm 86 0x00>;
qcom,sn-clkreq = <&tlmm 63 0x00>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nfc_enable_active &nfc_fwdl_active
&nfc_clk_req_active>;
pinctrl-1 = <&nfc_enable_suspend &nfc_fwdl_suspend
&nfc_clk_req_suspend>;
};
};
&dai_mi2s2 {
qcom,msm-mi2s-tx-lines = <1>;
pinctrl-names = "default", "sleep";