mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
This is the bulk of GPIO changes for the v4.12 kernel cycle:
Core changes
- Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
This was a much discussed change. It affects use cases where people
write drivers that might or might not be using GPIO resources.
I have decided that this is the lesser evil right now.
- Make gpiod_count() behave consistently across different hardware
descriptions.
- Fix the syntax around open drain/open source to not infer active
high/low semantics.
New drivers
- A new single-register fixed-direction framework driver for hardware
that have lines controlled by a single register that just work in
one direction (out or in), including IRQ support.
- Support the Fintek F71889A GPIO SuperIO controller.
- Support the National NI 169445 MMIO GPIO.
- Support for the X-Gene derivative of the DWC GPIO controller
- Support for the Rohm BD9571MWV-M PMIC GPIO controller.
- Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
and replace both the Gemini and the Moxa ART custom drivers with
this driver.
Driver improvements
- A whole slew of drivers have their spinlocks chaned to raw spinlocks
as they provide irqchips, and thus we are progressing on realtime
compliance.
- Use devm_irq_alloc_descs() in a slew of drivers, getting managed
resources.
- Support for the embedded PWM controller inside the MVEBU driver.
- Debounce, open source and open drain support for the Aspeed driver.
- Misc smaller fixes like spelling and syntax and whatnot.
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Merge tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.12 kernel cycle.
Core changes:
- Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
This was a much discussed change. It affects use cases where people
write drivers that might or might not be using GPIO resources. I
have decided that this is the lesser evil right now.
- Make gpiod_count() behave consistently across different hardware
descriptions.
- Fix the syntax around open drain/open source to not infer active
high/low semantics.
New drivers:
- A new single-register fixed-direction framework driver for hardware
that have lines controlled by a single register that just work in
one direction (out or in), including IRQ support.
- Support the Fintek F71889A GPIO SuperIO controller.
- Support the National NI 169445 MMIO GPIO.
- Support for the X-Gene derivative of the DWC GPIO controller
- Support for the Rohm BD9571MWV-M PMIC GPIO controller.
- Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
and replace both the Gemini and the Moxa ART custom drivers with
this driver.
Driver improvements:
- A whole slew of drivers have their spinlocks chaned to raw
spinlocks as they provide irqchips, and thus we are progressing on
realtime compliance.
- Use devm_irq_alloc_descs() in a slew of drivers, getting managed
resources.
- Support for the embedded PWM controller inside the MVEBU driver.
- Debounce, open source and open drain support for the Aspeed driver.
- Misc smaller fixes like spelling and syntax and whatnot"
* tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (77 commits)
gpio: f7188x: Add a missing break
gpio: omap: return error if requested debounce time is not possible
gpio: Add ROHM BD9571MWV-M PMIC GPIO driver
gpio: gpio-wcove: fix GPIO IRQ status mask
gpio: DT bindings, move tca9554 from pcf857x to pca953x
gpio: move tca9554 from pcf857x to pca953x
gpio: arizona: Correct check whether the pin is an input
gpio: Add XRA1403 DTS binding documentation
dt-bindings: add exar to vendor prefixes list
gpio: gpio-wcove: fix irq pending status bit width
gpio: dwapb: use dwapb_read instead of readl_relaxed
gpio: aspeed: Add open-source and open-drain support
gpio: aspeed: Add debounce support
gpio: aspeed: dt: Add optional clocks property
gpio: aspeed: dt: Fix description alignment in bindings document
gpio: mvebu: Add limited PWM support
gpio: Use unsigned int for interrupt numbers
gpio: f7188x: Add F71889A GPIO support.
gpio: core: Decouple open drain/source flag with active low/high
gpio: arizona: Correct handling for reading input GPIOs
...
This commit is contained in:
Linus Torvalds
commit
2bd8040174
66 changed files with 1860 additions and 648 deletions
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@ -1,8 +1,11 @@
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Cortina Systems Gemini GPIO Controller
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Faraday Technology FTGPIO010 GPIO Controller
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Required properties:
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- compatible : Must be "cortina,gemini-gpio"
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- compatible : Should be one of
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"cortina,gemini-gpio", "faraday,ftgpio010"
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"moxa,moxart-gpio", "faraday,ftgpio010"
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"faraday,ftgpio010"
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- reg : Should contain registers location and length
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- interrupts : Should contain the interrupt line for the GPIO block
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- gpio-controller : marks this as a GPIO controller
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@ -14,7 +17,7 @@ Required properties:
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Example:
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gpio@4d000000 {
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compatible = "cortina,gemini-gpio";
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4d000000 0x100>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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@ -17,7 +17,8 @@ Required properties:
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Optional properties:
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- interrupt-parent : The parent interrupt controller, optional if inherited
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- interrupt-parent : The parent interrupt controller, optional if inherited
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- clocks : A phandle to the HPLL clock node for debounce timings
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The gpio and interrupt properties are further described in their respective
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bindings documentation:
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@ -38,6 +38,24 @@ Required properties:
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- #gpio-cells: Should be two. The first cell is the pin number. The
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second cell is reserved for flags, unused at the moment.
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Optional properties:
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In order to use the GPIO lines in PWM mode, some additional optional
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properties are required. Only Armada 370 and XP support these properties.
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- compatible: Must contain "marvell,armada-370-xp-gpio"
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- reg: an additional register set is needed, for the GPIO Blink
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Counter on/off registers.
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- reg-names: Must contain an entry "pwm" corresponding to the
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additional register range needed for PWM operation.
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- #pwm-cells: Should be two. The first cell is the GPIO line number. The
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second cell is the period in nanoseconds.
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- clocks: Must be a phandle to the clock for the GPIO controller.
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Example:
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gpio0: gpio@d0018100 {
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@ -51,3 +69,17 @@ Example:
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#interrupt-cells = <2>;
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interrupts = <16>, <17>, <18>, <19>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,armada-370-xp-gpio";
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reg = <0x18140 0x40>, <0x181c8 0x08>;
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reg-names = "gpio", "pwm";
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ngpios = <17>;
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gpio-controller;
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#gpio-cells = <2>;
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#pwm-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>, <88>, <89>;
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clocks = <&coreclk 0>;
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};
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@ -26,6 +26,7 @@ Required properties:
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ti,tca6416
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ti,tca6424
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ti,tca9539
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ti,tca9554
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onsemi,pca9654
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exar,xra1202
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@ -25,7 +25,6 @@ Required Properties:
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- "nxp,pcf8574": For the NXP PCF8574
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- "nxp,pcf8574a": For the NXP PCF8574A
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- "nxp,pcf8575": For the NXP PCF8575
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- "ti,tca9554": For the TI TCA9554
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- reg: I2C slave address.
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27
Documentation/devicetree/bindings/gpio/gpio-thunderx.txt
Normal file
27
Documentation/devicetree/bindings/gpio/gpio-thunderx.txt
Normal file
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@ -0,0 +1,27 @@
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Cavium ThunderX/OCTEON-TX GPIO controller bindings
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Required Properties:
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- reg: The controller bus address.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells: Must be 2.
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- First cell is the GPIO pin number relative to the controller.
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- Second cell is a standard generic flag bitfield as described in gpio.txt.
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Optional Properties:
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- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Must be present and have value of 2 if
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"interrupt-controller" is present.
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- First cell is the GPIO pin number relative to the controller.
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- Second cell is triggering flags as defined in interrupts.txt.
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Example:
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gpio_6_0: gpio@6,0 {
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compatible = "cavium,thunder-8890-gpio";
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reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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46
Documentation/devicetree/bindings/gpio/gpio-xra1403.txt
Normal file
46
Documentation/devicetree/bindings/gpio/gpio-xra1403.txt
Normal file
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@ -0,0 +1,46 @@
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GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
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The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
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- Individually programmable inputs:
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- Internal pull-up resistors
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- Polarity inversion
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- Individual interrupt enable
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- Rising edge and/or Falling edge interrupt
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- Input filter
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- Individually programmable outputs
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- Output Level Control
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- Output Three-State Control
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Properties
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----------
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Check documentation for SPI and GPIO controllers regarding properties needed to configure the node.
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- compatible = "exar,xra1403".
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- reg - SPI id of the device.
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- gpio-controller - marks the node as gpio.
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- #gpio-cells - should be two where the first cell is the pin number
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and the second one is used for optional parameters.
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Optional properties:
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-------------------
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- reset-gpios: in case available used to control the device reset line.
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- interrupt-controller - marks the node as interrupt controller.
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- #interrupt-cells - should be two and represents the number of cells
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needed to encode interrupt source.
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Example
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--------
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gpioxra0: gpio@2 {
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compatible = "exar,xra1403";
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reg = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
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spi-max-frequency = <1000000>;
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};
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@ -1,19 +0,0 @@
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MOXA ART GPIO Controller
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Required properties:
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- #gpio-cells : Should be 2, The first cell is the pin number,
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the second cell is used to specify polarity:
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0 = active high
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1 = active low
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- compatible : Must be "moxa,moxart-gpio"
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- reg : Should contain registers location and length
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Example:
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gpio: gpio@98700000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "moxa,moxart-gpio";
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reg = <0x98700000 0xC>;
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};
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@ -0,0 +1,38 @@
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Bindings for the National Instruments 169445 GPIO NAND controller
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The 169445 GPIO NAND controller has two memory mapped GPIO registers, one
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for input (the ready signal) and one for output (control signals). It is
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intended to be used with the GPIO NAND driver.
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Required properties:
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- compatible: should be "ni,169445-nand-gpio"
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- reg-names: must contain
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"dat" - data register
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- reg: address + size pairs describing the GPIO register sets;
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order must correspond with the order of entries in reg-names
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- #gpio-cells: must be set to 2. The first cell is the pin number and
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the second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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- gpio-controller: Marks the device node as a gpio controller.
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Optional properties:
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- no-output: disables driving output on the pins
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Examples:
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gpio1: nand-gpio-out@1f300010 {
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compatible = "ni,169445-nand-gpio";
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reg = <0x1f300010 0x4>;
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reg-names = "dat";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: nand-gpio-in@1f300014 {
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compatible = "ni,169445-nand-gpio";
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reg = <0x1f300014 0x4>;
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reg-names = "dat";
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gpio-controller;
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#gpio-cells = <2>;
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no-output;
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};
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@ -103,6 +103,7 @@ ettus NI Ettus Research
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eukrea Eukréa Electromatique
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everest Everest Semiconductor Co. Ltd.
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everspin Everspin Technologies, Inc.
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exar Exar Corporation
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excito Excito
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ezchip EZchip Semiconductor
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faraday Faraday Technology Corporation
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