From 8493c5affbff1ad2d6ce5e5daf7793ff28155053 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Tue, 13 Jul 2021 17:28:03 +0530 Subject: [PATCH] clk: qcom: dispcc-blair: Allow config of cdivs for byte clk Change the clk_regmap_div_ro ops to clk_regmap_div ops to allow dynamic configuration of the cdivs. This is required for cphy configuration where the byte intf clock need to be the same frequency as its byte clock. Change-Id: Iddf733697b7287577f690bd5535a60f406b7129a Signed-off-by: BIVASH KUMAR SINGH --- drivers/clk/qcom/dispcc-blair.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-blair.c b/drivers/clk/qcom/dispcc-blair.c index 3a45e9bcd386..4d5ef6412a76 100644 --- a/drivers/clk/qcom/dispcc-blair.c +++ b/drivers/clk/qcom/dispcc-blair.c @@ -333,8 +333,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, + .ops = &clk_regmap_div_ops, }, };