From 01df4aa8198d2f007c48eadb8b6836223d19e9f0 Mon Sep 17 00:00:00 2001 From: Phanindra Babu Pabba Date: Wed, 30 Dec 2020 10:24:18 +0530 Subject: [PATCH] ARM: dts: msm: Enable qsee drivers for yupik Add device node entries on DT include file to enable QSEECOM, SMCINVOKE, QRNG, qcedev, qcrypto, HWKM and tzlog drivers for yupik. Change-Id: I8f72e1d83543797b2dff12583493432fe04f018a --- qcom/yupik-ion.dtsi | 18 ++++++ qcom/yupik.dtsi | 152 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 166 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi index a79bbd58abf5..e22976a73288 100644 --- a/qcom/yupik-ion.dtsi +++ b/qcom/yupik-ion.dtsi @@ -21,6 +21,24 @@ memory-region = <&secure_display_memory>; qcom,ion-heap-type = "HYP_CMA"; }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = ; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@26 { /* USER CONTIG HEAP */ + reg = ; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = ; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 3c19ec45d796..05257ba9b920 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -366,6 +366,30 @@ reg = <0x0 0xd7f80000 0x0 0x80000>; }; + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + secure_display_memory: secure_display_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; @@ -452,6 +476,112 @@ method = "smc"; }; + qcom_tzlog: tz-log@0x146aa720 { + compatible = "qcom,tz-log"; + reg = <0x146aa720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qcom_qseecom: qseecom@c1800000 { + compatible = "qcom,qseecom"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_rng: qrng@10d3000 { + compatible = "qcom,msm-rng"; + reg = <0x10d3000 0x1000>; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_HWKM>; + clock-names = "km_clk_src"; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x04E6 0x0011>; + qcom,iommu-dma = "atomic"; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x4F2 0>, + <&apps_smmu 0x4F8 0>, + <&apps_smmu 0x4F9 0>, + <&apps_smmu 0x4FF 0>; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x4F3 0>, + <&apps_smmu 0x4FC 0>, + <&apps_smmu 0x4FD 0>, + <&apps_smmu 0x4FE 0>; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,secure-context-bank; + }; + }; + + qcom_crypto: qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x04E4 0x0011>; + qcom,iommu-dma = "atomic"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + ipcc_mproc: qcom,ipcc@408000 { compatible = "qcom,ipcc"; reg = <0x408000 0x1000>; @@ -799,6 +929,16 @@ memory-region = <&pil_video_mem>; }; + qcom_hwkm: hwkm@10c0000 { + compatible = "qcom,hwkm"; + reg = <0x10c0000 0x9000>, <0x1d90000 0x9000>; + reg-names = "km_master", "ice_slave"; + qcom,enable-hwkm-clk; + clock-names = "km_clk_src"; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + qcom,op-freq-hz = <75000000>; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; reg-names = "phy_mem"; @@ -859,8 +999,10 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; - reg = <0x1d84000 0x3000>; - reg-names = "ufs_mem"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; @@ -1694,8 +1836,10 @@ sdhc_1: sdhci@7C4000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>; - reg-names = "hc_mem", "cqhci_mem"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, + <0x007c8000 0x8000>, <0x7d0000 0x9000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", + "cqhci_ice_hwkm"; interrupts = , ;