mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 13:49:24 -04:00
cnss2: Use CONFIG_PCI_MSM to protect MSM PCIe APIs
This can ease the complexity to port CNSS2 driver to non-MSM platforms while still be able to maintain the compatibility. Change-Id: I268cdd90c59085b34aa2fe3c3b845d60c4e2a417 Signed-off-by: Yue Ma <yuem@codeaurora.org>
This commit is contained in:
Yue Ma
Gerrit - the friendly Code Review server
parent
dc0ecaca75
commit
2dc22bc62d
2 changed files with 281 additions and 45 deletions
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@ -370,6 +370,232 @@ static struct cnss_misc_reg wlaon_reg_access_seq[] = {
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#define PCIE_REG_SIZE ARRAY_SIZE(pcie_reg_access_seq)
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#define WLAON_REG_SIZE ARRAY_SIZE(wlaon_reg_access_seq)
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#if IS_ENABLED(CONFIG_PCI_MSM)
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/**
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* cnss_pci_enumerate() - Enumerate PCIe endpoints
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* @plat_priv: driver platform context pointer
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* @rc_num: root complex index that an endpoint connects to
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to power on root complex and enumerate the endpoint connected to it.
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*
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* Return: 0 for success, negative value for error
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*/
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static int cnss_pci_enumerate(struct cnss_plat_data *plat_priv, int rc_num)
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{
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return msm_pcie_enumerate(rc_num);
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}
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/**
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* cnss_pci_assert_perst() - Assert PCIe PERST GPIO
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* @pci_priv: driver PCI bus context pointer
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to assert PCIe PERST GPIO.
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*
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* Return: 0 for success, negative value for error
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*/
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static int cnss_pci_assert_perst(struct cnss_pci_data *pci_priv)
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{
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struct pci_dev *pci_dev = pci_priv->pci_dev;
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return msm_pcie_pm_control(MSM_PCIE_HANDLE_LINKDOWN,
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pci_dev->bus->number, pci_dev, NULL,
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PM_OPTIONS_DEFAULT);
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}
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/**
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* cnss_pci_disable_pc() - Disable PCIe link power collapse from RC driver
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* @pci_priv: driver PCI bus context pointer
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* @vote: value to indicate disable (true) or enable (false)
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to disable PCIe power collapse. The purpose of this API is to avoid
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* root complex driver still controlling PCIe link from callbacks of
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* system suspend/resume. Device driver itself should take full control
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* of the link in such cases.
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*
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* Return: 0 for success, negative value for error
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*/
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static int cnss_pci_disable_pc(struct cnss_pci_data *pci_priv, bool vote)
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{
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struct pci_dev *pci_dev = pci_priv->pci_dev;
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return msm_pcie_pm_control(vote ? MSM_PCIE_DISABLE_PC :
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MSM_PCIE_ENABLE_PC,
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pci_dev->bus->number, pci_dev, NULL,
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PM_OPTIONS_DEFAULT);
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}
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/**
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* cnss_pci_set_link_bandwidth() - Update number of lanes and speed of
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* PCIe link
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* @pci_priv: driver PCI bus context pointer
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* @link_speed: PCIe link gen speed
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* @link_width: number of lanes for PCIe link
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to update number of lanes and speed of the link.
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*
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* Return: 0 for success, negative value for error
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*/
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static int cnss_pci_set_link_bandwidth(struct cnss_pci_data *pci_priv,
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u16 link_speed, u16 link_width)
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{
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return msm_pcie_set_link_bandwidth(pci_priv->pci_dev,
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link_speed, link_width);
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}
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/**
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* cnss_pci_set_max_link_speed() - Set the maximum speed PCIe can link up with
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* @pci_priv: driver PCI bus context pointer
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* @rc_num: root complex index that an endpoint connects to
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* @link_speed: PCIe link gen speed
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to update the maximum speed that PCIe can link up with.
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*
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* Return: 0 for success, negative value for error
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*/
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static int cnss_pci_set_max_link_speed(struct cnss_pci_data *pci_priv,
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u32 rc_num, u16 link_speed)
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{
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return msm_pcie_set_target_link_speed(rc_num, link_speed);
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}
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/**
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* _cnss_pci_prevent_l1() - Prevent PCIe L1 and L1 sub-states
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* @pci_priv: driver PCI bus context pointer
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to prevent PCIe link enter L1 and L1 sub-states. The APIs should also
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* bring link out of L1 or L1 sub-states if any and avoid synchronization
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* issues if any.
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*
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* Return: 0 for success, negative value for error
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*/
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static int _cnss_pci_prevent_l1(struct cnss_pci_data *pci_priv)
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{
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return msm_pcie_prevent_l1(pci_priv->pci_dev);
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}
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/**
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* _cnss_pci_allow_l1() - Allow PCIe L1 and L1 sub-states
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* @pci_priv: driver PCI bus context pointer
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to allow PCIe link enter L1 and L1 sub-states. The APIs should avoid
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* synchronization issues if any.
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*
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* Return: 0 for success, negative value for error
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*/
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static void _cnss_pci_allow_l1(struct cnss_pci_data *pci_priv)
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{
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msm_pcie_allow_l1(pci_priv->pci_dev);
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}
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/**
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* cnss_pci_set_link_up() - Power on or resume PCIe link
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* @pci_priv: driver PCI bus context pointer
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to Power on or resume PCIe link.
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*
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* Return: 0 for success, negative value for error
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*/
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static int cnss_pci_set_link_up(struct cnss_pci_data *pci_priv)
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{
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struct pci_dev *pci_dev = pci_priv->pci_dev;
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enum msm_pcie_pm_opt pm_ops = MSM_PCIE_RESUME;
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u32 pm_options = PM_OPTIONS_DEFAULT;
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int ret;
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ret = msm_pcie_pm_control(pm_ops, pci_dev->bus->number, pci_dev,
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NULL, pm_options);
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if (ret)
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cnss_pr_err("Failed to resume PCI link with default option, err = %d\n",
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ret);
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return ret;
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}
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/**
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* cnss_pci_set_link_down() - Power off or suspend PCIe link
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* @pci_priv: driver PCI bus context pointer
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to power off or suspend PCIe link.
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*
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* Return: 0 for success, negative value for error
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*/
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static int cnss_pci_set_link_down(struct cnss_pci_data *pci_priv)
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{
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struct pci_dev *pci_dev = pci_priv->pci_dev;
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enum msm_pcie_pm_opt pm_ops;
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u32 pm_options = PM_OPTIONS_DEFAULT;
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int ret;
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if (pci_priv->drv_connected_last) {
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cnss_pr_vdbg("Use PCIe DRV suspend\n");
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pm_ops = MSM_PCIE_DRV_SUSPEND;
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} else {
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pm_ops = MSM_PCIE_SUSPEND;
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}
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ret = msm_pcie_pm_control(pm_ops, pci_dev->bus->number, pci_dev,
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NULL, pm_options);
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if (ret)
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cnss_pr_err("Failed to suspend PCI link with default option, err = %d\n",
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ret);
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return ret;
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}
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#else
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static int cnss_pci_enumerate(struct cnss_plat_data *plat_priv, int rc_num)
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{
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return -EOPNOTSUPP;
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}
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static int cnss_pci_assert_perst(struct cnss_pci_data *pci_priv)
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{
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return -EOPNOTSUPP;
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}
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static int cnss_pci_disable_pc(struct cnss_pci_data *pci_priv, bool vote)
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{
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return 0;
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}
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static int cnss_pci_set_link_bandwidth(struct cnss_pci_data *pci_priv,
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u16 link_speed, u16 link_width)
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{
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return 0;
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}
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static int cnss_pci_set_max_link_speed(struct cnss_pci_data *pci_priv,
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u32 rc_num, u16 link_speed)
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{
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return 0;
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}
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static int _cnss_pci_prevent_l1(struct cnss_pci_data *pci_priv)
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{
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return 0;
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}
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static void _cnss_pci_allow_l1(struct cnss_pci_data *pci_priv) {}
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static int cnss_pci_set_link_up(struct cnss_pci_data *pci_priv)
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{
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return 0;
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}
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static int cnss_pci_set_link_down(struct cnss_pci_data *pci_priv)
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{
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return 0;
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}
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#endif /* CONFIG_PCI_MSM */
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int cnss_pci_check_link_status(struct cnss_pci_data *pci_priv)
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{
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u16 device_id;
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@ -738,8 +964,7 @@ static int cnss_set_pci_link_status(struct cnss_pci_data *pci_priv,
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return -EINVAL;
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}
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ret = msm_pcie_set_link_bandwidth(pci_priv->pci_dev,
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link_speed, link_width);
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ret = cnss_pci_set_link_bandwidth(pci_priv, link_speed, link_width);
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if (!ret)
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pci_priv->cur_link_speed = link_speed;
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@ -748,43 +973,28 @@ static int cnss_set_pci_link_status(struct cnss_pci_data *pci_priv,
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static int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up)
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{
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int ret = 0;
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struct pci_dev *pci_dev = pci_priv->pci_dev;
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enum msm_pcie_pm_opt pm_ops;
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int retry = 0;
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u32 pm_options = PM_OPTIONS_DEFAULT;
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int ret = 0, retry = 0;
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cnss_pr_vdbg("%s PCI link\n", link_up ? "Resuming" : "Suspending");
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if (link_up) {
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pm_ops = MSM_PCIE_RESUME;
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} else {
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if (pci_priv->drv_connected_last) {
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cnss_pr_vdbg("Use PCIe DRV suspend\n");
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pm_ops = MSM_PCIE_DRV_SUSPEND;
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/* Since DRV suspend cannot be done in Gen 3, set it to
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* Gen 2 if current link speed is larger than Gen 2.
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*/
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if (pci_priv->cur_link_speed >
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PCI_EXP_LNKSTA_CLS_5_0GB)
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cnss_set_pci_link_status(pci_priv, PCI_GEN2);
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} else {
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pm_ops = MSM_PCIE_SUSPEND;
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}
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}
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retry:
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ret = msm_pcie_pm_control(pm_ops, pci_dev->bus->number, pci_dev,
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NULL, pm_options);
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if (ret) {
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cnss_pr_err("Failed to %s PCI link with default option, err = %d\n",
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link_up ? "resume" : "suspend", ret);
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if (link_up && retry++ < LINK_TRAINING_RETRY_MAX_TIMES) {
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ret = cnss_pci_set_link_up(pci_priv);
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if (ret && retry++ < LINK_TRAINING_RETRY_MAX_TIMES) {
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cnss_pr_dbg("Retry PCI link training #%d\n", retry);
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if (pci_priv->pci_link_down_ind)
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msleep(LINK_TRAINING_RETRY_DELAY_MS * retry);
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goto retry;
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}
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} else {
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/* Since DRV suspend cannot be done in Gen 3, set it to
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* Gen 2 if current link speed is larger than Gen 2.
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*/
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if (pci_priv->drv_connected_last &&
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pci_priv->cur_link_speed > PCI_EXP_LNKSTA_CLS_5_0GB)
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cnss_set_pci_link_status(pci_priv, PCI_GEN2);
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ret = cnss_pci_set_link_down(pci_priv);
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}
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if (pci_priv->drv_connected_last) {
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@ -939,7 +1149,7 @@ int cnss_pci_prevent_l1(struct device *dev)
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return -EIO;
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}
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ret = msm_pcie_prevent_l1(pci_dev);
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ret = _cnss_pci_prevent_l1(pci_priv);
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if (ret == -EIO) {
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cnss_pr_err("Failed to prevent PCIe L1, considered as link down\n");
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cnss_pci_link_down(dev);
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@ -969,7 +1179,7 @@ void cnss_pci_allow_l1(struct device *dev)
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return;
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}
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msm_pcie_allow_l1(pci_dev);
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_cnss_pci_allow_l1(pci_priv);
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}
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EXPORT_SYMBOL(cnss_pci_allow_l1);
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@ -1026,9 +1236,7 @@ int cnss_pci_link_down(struct device *dev)
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cnss_pr_err("PCI link down is detected by drivers\n");
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ret = msm_pcie_pm_control(MSM_PCIE_HANDLE_LINKDOWN,
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pci_dev->bus->number, pci_dev, NULL,
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PM_OPTIONS_DEFAULT);
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ret = cnss_pci_assert_perst(pci_priv);
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if (ret)
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cnss_pci_handle_linkdown(pci_priv);
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@ -1461,6 +1669,7 @@ out:
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return ret;
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}
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#if IS_ENABLED(CONFIG_PCI_MSM)
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/**
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* cnss_wlan_adsp_pc_enable: Control ADSP power collapse setup
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* @dev: Platform driver pci private data structure
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@ -1494,6 +1703,13 @@ static int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
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cnss_pr_dbg("%s ADSP power collapse\n", control ? "Enable" : "Disable");
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return 0;
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}
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#else
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static int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
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bool control)
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{
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return 0;
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}
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#endif
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int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv)
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{
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@ -2615,6 +2831,7 @@ int cnss_pci_unregister_driver_hdlr(struct cnss_pci_data *pci_priv)
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return 0;
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}
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#if IS_ENABLED(CONFIG_PCI_MSM)
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static bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv)
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{
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struct pci_dev *root_port = pci_find_pcie_root_port(pci_priv->pci_dev);
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@ -2691,6 +2908,16 @@ static void cnss_pci_event_cb(struct msm_pcie_notify *notify)
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}
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}
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/**
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* cnss_reg_pci_event() - Register for PCIe events
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* @pci_priv: driver PCI bus context pointer
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*
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* This function shall call corresponding PCIe root complex driver APIs
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* to register for PCIe events like link down or WAKE GPIO toggling etc.
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* The events should be based on PCIe root complex driver's capability.
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*
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* Return: 0 for success, negative value for error
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*/
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static int cnss_reg_pci_event(struct cnss_pci_data *pci_priv)
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{
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int ret = 0;
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@ -2722,6 +2949,14 @@ static void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv)
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{
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msm_pcie_deregister_event(&pci_priv->msm_pci_event);
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}
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#else
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static int cnss_reg_pci_event(struct cnss_pci_data *pci_priv)
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{
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return 0;
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}
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static void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv) {}
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#endif
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static int cnss_pci_suspend_driver(struct cnss_pci_data *pci_priv)
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{
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@ -3081,10 +3316,7 @@ int cnss_wlan_pm_control(struct device *dev, bool vote)
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if (!pci_priv)
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return -ENODEV;
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ret = msm_pcie_pm_control(vote ? MSM_PCIE_DISABLE_PC :
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MSM_PCIE_ENABLE_PC,
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pci_dev->bus->number, pci_dev,
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NULL, PM_OPTIONS_DEFAULT);
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ret = cnss_pci_disable_pc(pci_priv, vote);
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if (ret)
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return ret;
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@ -4907,13 +5139,13 @@ static int cnss_mhi_bw_scale(struct mhi_controller *mhi_ctrl,
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* bandwidth getting rejected if requested link speed is higher than
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* current one.
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*/
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ret = msm_pcie_set_target_link_speed(plat_priv->rc_num,
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link_info->target_link_speed);
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ret = cnss_pci_set_max_link_speed(pci_priv, plat_priv->rc_num,
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link_info->target_link_speed);
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if (ret)
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cnss_pr_err("Failed to set target link speed to 0x%x, err = %d\n",
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link_info->target_link_speed, ret);
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ret = msm_pcie_set_link_bandwidth(pci_priv->pci_dev,
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ret = cnss_pci_set_link_bandwidth(pci_priv,
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link_info->target_link_speed,
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link_info->target_link_width);
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@ -5295,15 +5527,15 @@ int cnss_pci_init(struct cnss_plat_data *plat_priv)
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* if requested speed is higher than the one specified in PCIe DT.
|
||||
*/
|
||||
if (plat_priv->device_id == QCA6490_DEVICE_ID) {
|
||||
ret = msm_pcie_set_target_link_speed(rc_num,
|
||||
PCI_EXP_LNKSTA_CLS_5_0GB);
|
||||
ret = cnss_pci_set_max_link_speed(plat_priv->bus_priv, rc_num,
|
||||
PCI_EXP_LNKSTA_CLS_5_0GB);
|
||||
if (ret)
|
||||
cnss_pr_err("Failed to set target PCIe link speed to Gen2, err = %d\n",
|
||||
ret);
|
||||
}
|
||||
|
||||
retry:
|
||||
ret = msm_pcie_enumerate(rc_num);
|
||||
ret = cnss_pci_enumerate(plat_priv, rc_num);
|
||||
if (ret) {
|
||||
cnss_pr_err("Failed to enable PCIe RC%x, err = %d\n",
|
||||
rc_num, ret);
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */
|
||||
/* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
|
||||
|
||||
#ifndef _CNSS_PCI_H
|
||||
#define _CNSS_PCI_H
|
||||
|
||||
#include <linux/iommu.h>
|
||||
#include <linux/mhi.h>
|
||||
#if IS_ENABLED(CONFIG_PCI_MSM)
|
||||
#include <linux/msm_pcie.h>
|
||||
#endif
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include "main.h"
|
||||
|
|
@ -86,7 +88,9 @@ struct cnss_pci_data {
|
|||
u8 pci_link_down_ind;
|
||||
struct pci_saved_state *saved_state;
|
||||
struct pci_saved_state *default_state;
|
||||
#if IS_ENABLED(CONFIG_PCI_MSM)
|
||||
struct msm_pcie_register_event msm_pci_event;
|
||||
#endif
|
||||
struct cnss_pm_stats pm_stats;
|
||||
atomic_t auto_suspended;
|
||||
atomic_t drv_connected;
|
||||
|
|
|
|||
Loading…
Reference in a new issue