mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
Conflicts: arch/sparc64/kernel/pci_psycho.c
This commit is contained in:
commit
2e57572a50
1002 changed files with 34751 additions and 10635 deletions
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@ -447,8 +447,10 @@ config PATA_MARVELL
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tristate "Marvell PATA support via legacy mode"
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depends on PCI
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help
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This option enables limited support for the Marvell 88SE6145 ATA
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controller.
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This option enables limited support for the Marvell 88SE61xx ATA
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controllers. If you wish to use only the SATA ports then select
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the AHCI driver alone. If you wish to the use the PATA port or
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both SATA and PATA include this driver.
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If unsure, say N.
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@ -420,7 +420,7 @@ static const struct ata_port_info ahci_port_info[] = {
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/* board_ahci_mv */
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{
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AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
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AHCI_HFLAG_MV_PATA),
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AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
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.pio_mask = 0x1f, /* pio0-4 */
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@ -487,7 +487,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
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{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
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{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
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{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
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{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
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{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
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/* JMicron 360/1/3/5/6, match class to avoid IDE function */
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{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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@ -610,6 +612,15 @@ module_param(ahci_em_messages, int, 0444);
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MODULE_PARM_DESC(ahci_em_messages,
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"Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
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#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
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static int marvell_enable;
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#else
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static int marvell_enable = 1;
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#endif
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module_param(marvell_enable, int, 0644);
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MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
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static inline int ahci_nr_ports(u32 cap)
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{
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return (cap & 0x1f) + 1;
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@ -732,6 +743,8 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
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"MV_AHCI HACK: port_map %x -> %x\n",
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port_map,
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port_map & mv);
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dev_printk(KERN_ERR, &pdev->dev,
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"Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
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port_map &= mv;
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}
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@ -2533,6 +2546,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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/* The AHCI driver can only drive the SATA ports, the PATA driver
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can drive them all so if both drivers are selected make sure
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AHCI stays out of the way */
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if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
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return -ENODEV;
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/* acquire resources */
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rc = pcim_enable_device(pdev);
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if (rc)
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@ -1499,7 +1499,7 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
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* off.
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*/
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if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
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int rc = piix_disable_ahci(pdev);
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rc = piix_disable_ahci(pdev);
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if (rc)
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return rc;
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}
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@ -1315,11 +1315,6 @@ fsm_start:
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break;
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case HSM_ST_ERR:
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/* make sure qc->err_mask is available to
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* know what's wrong and recover
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*/
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WARN_ON(!(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)));
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ap->hsm_task_state = HSM_ST_IDLE;
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/* complete taskfile transaction */
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@ -20,7 +20,42 @@
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#include <linux/ata.h>
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#define DRV_NAME "pata_marvell"
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#define DRV_VERSION "0.1.4"
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#define DRV_VERSION "0.1.6"
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/**
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* marvell_pata_active - check if PATA is active
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* @pdev: PCI device
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*
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* Returns 1 if the PATA port may be active. We know how to check this
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* for the 6145 but not the other devices
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*/
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static int marvell_pata_active(struct pci_dev *pdev)
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{
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int i;
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u32 devices;
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void __iomem *barp;
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/* We don't yet know how to do this for other devices */
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if (pdev->device != 0x6145)
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return 1;
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barp = pci_iomap(pdev, 5, 0x10);
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if (barp == NULL)
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return -ENOMEM;
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printk("BAR5:");
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for(i = 0; i <= 0x0F; i++)
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printk("%02X:%02X ", i, ioread8(barp + i));
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printk("\n");
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devices = ioread32(barp + 0x0C);
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pci_iounmap(pdev, barp);
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if (devices & 0x10)
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return 1;
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return 0;
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}
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/**
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* marvell_pre_reset - check for 40/80 pin
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@ -34,26 +69,10 @@ static int marvell_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 devices;
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void __iomem *barp;
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int i;
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/* Check if our port is enabled */
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barp = pci_iomap(pdev, 5, 0x10);
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if (barp == NULL)
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return -ENOMEM;
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printk("BAR5:");
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for(i = 0; i <= 0x0F; i++)
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printk("%02X:%02X ", i, ioread8(barp + i));
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printk("\n");
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devices = ioread32(barp + 0x0C);
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pci_iounmap(pdev, barp);
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if ((pdev->device == 0x6145) && (ap->port_no == 0) &&
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(!(devices & 0x10))) /* PATA enable ? */
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return -ENOENT;
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if (pdev->device == 0x6145 && ap->port_no == 0 &&
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!marvell_pata_active(pdev)) /* PATA enable ? */
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return -ENOENT;
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return ata_sff_prereset(link, deadline);
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}
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@ -128,6 +147,12 @@ static int marvell_init_one (struct pci_dev *pdev, const struct pci_device_id *i
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if (pdev->device == 0x6101)
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ppi[1] = &ata_dummy_port_info;
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#if defined(CONFIG_AHCI) || defined(CONFIG_AHCI_MODULE)
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if (!marvell_pata_active(pdev)) {
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printk(KERN_INFO DRV_NAME ": PATA port not active, deferring to AHCI driver.\n");
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return -ENODEV;
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}
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#endif
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return ata_pci_sff_init_one(pdev, ppi, &marvell_sht, NULL);
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}
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@ -322,9 +322,6 @@ static int __devinit sil680_init_one(struct pci_dev *pdev,
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/* Try to acquire MMIO resources and fallback to PIO if
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* that fails
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*/
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
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if (rc)
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goto use_ioports;
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@ -96,6 +96,7 @@ enum {
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PORT_SCR = 0x20,
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/* HOST_CTL bits */
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HCTL_LEDEN = (1 << 3), /* enable LED operation */
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HCTL_IRQOFF = (1 << 8), /* global IRQ off */
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HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
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HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
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@ -540,7 +541,7 @@ static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
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void __iomem *port_base = inic_port_base(ap);
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/* fire up the ADMA engine */
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writew(HCTL_FTHD0, port_base + HOST_CTL);
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writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL);
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writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
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writeb(0, port_base + PORT_CPB_PTQFIFO);
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@ -667,7 +667,8 @@ static const struct pci_device_id mv_pci_tbl[] = {
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{ PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
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{ PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
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{ PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
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/* RocketRAID 1740/174x have different identifiers */
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/* RocketRAID 1720/174x have different identifiers */
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{ PCI_VDEVICE(TTI, 0x1720), chip_6042 },
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{ PCI_VDEVICE(TTI, 0x1740), chip_508x },
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{ PCI_VDEVICE(TTI, 0x1742), chip_508x },
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@ -309,8 +309,6 @@ static void nv_nf2_freeze(struct ata_port *ap);
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static void nv_nf2_thaw(struct ata_port *ap);
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static void nv_ck804_freeze(struct ata_port *ap);
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static void nv_ck804_thaw(struct ata_port *ap);
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static int nv_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline);
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static int nv_adma_slave_config(struct scsi_device *sdev);
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static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
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static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
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@ -407,7 +405,7 @@ static struct scsi_host_template nv_swncq_sht = {
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static struct ata_port_operations nv_generic_ops = {
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.inherits = &ata_bmdma_port_ops,
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.hardreset = nv_hardreset,
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.hardreset = ATA_OP_NULL,
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.scr_read = nv_scr_read,
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.scr_write = nv_scr_write,
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};
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@ -1588,21 +1586,6 @@ static void nv_mcp55_thaw(struct ata_port *ap)
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ata_sff_thaw(ap);
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}
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static int nv_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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int rc;
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/* SATA hardreset fails to retrieve proper device signature on
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* some controllers. Request follow up SRST. For more info,
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* see http://bugzilla.kernel.org/show_bug.cgi?id=3352
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*/
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rc = sata_sff_hardreset(link, class, deadline);
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if (rc)
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return rc;
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return -EAGAIN;
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}
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static void nv_adma_error_handler(struct ata_port *ap)
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{
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struct nv_adma_port_priv *pp = ap->private_data;
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