From dfdd7d28907b4b02feecdf9e34efc7e1c1136997 Mon Sep 17 00:00:00 2001 From: Raghu Ananya Arabolu Date: Thu, 23 Jan 2020 11:12:12 -0800 Subject: [PATCH] msm: kgsl: Override UBWC configuration for A660 based on DDR type The highest bank bit defined in the A660 gpucore structure defaults to DDR type 8. If underlying DDR is type 7, then modify the highest bank bit accordingly. Change-Id: Idd36f69227dca63eef19c1ac1843b88982346edd Signed-off-by: Raghu Ananya Arabolu --- drivers/gpu/msm/adreno_a6xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 507bc290a6a9..df64f94efd4d 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -106,7 +106,9 @@ static void a6xx_init(struct adreno_device *adreno_dev) adreno_dev->highest_bank_bit = a6xx_core->highest_bank_bit; - if (adreno_is_a650(adreno_dev) && of_fdt_get_ddrtype() == 0x7) + /* If the memory type is DDR 4, override the existing configuration */ + if ((adreno_is_a650(adreno_dev) || adreno_is_a660(adreno_dev)) && + of_fdt_get_ddrtype() == 0x7) adreno_dev->highest_bank_bit = 15; a6xx_crashdump_init(adreno_dev);