From 4e6f18d642c2cbdd78afa41b69d59e2f99c4c01e Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Wed, 1 Jul 2020 12:02:06 -0700 Subject: [PATCH] pci: msm: Add support to disable L1SS sleep Read device tree property qcom,l1ss-sleep-disable to prevent sending L1SS sleep enable and disable rpmsg to DRV processor. This support is added to prevent PCIe link down caused due to manually operating phy PLL. Change-Id: I2f96f3dc186d3af0ffad110807204936af58814a Signed-off-by: Hemant Kumar --- drivers/pci/controller/pci-msm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index cf4b9f8fccc8..2a4501d6c49a 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -745,6 +745,7 @@ struct msm_pcie_drv_info { u16 reply_seq; u32 timeout_ms; /* IPC command timeout */ u32 l1ss_timeout_us; + u32 l1ss_sleep_disable; struct completion completion; /* for DRV SSR */ @@ -5317,6 +5318,9 @@ static int msm_pcie_setup_drv(struct msm_pcie_dev_t *pcie_dev, drv_info->dev_id = pcie_dev->rc_idx; + of_property_read_u32(of_node, "qcom,l1ss-sleep-disable", + &drv_info->l1ss_sleep_disable); + ret = of_property_read_u32(of_node, "qcom,phy-manage-pll", &phy_manage_pll); if (!ret && phy_manage_pll) { @@ -6621,7 +6625,7 @@ static int msm_pcie_drv_resume(struct msm_pcie_dev_t *pcie_dev) mutex_lock(&pcie_dev->setup_lock); /* if rpdev is NULL then DRV subsystem is powered down */ - if (rpdev) { + if (!drv_info->l1ss_sleep_disable && rpdev) { ret = msm_pcie_drv_send_rpmsg(pcie_dev, rpdev, &drv_info->drv_disable_l1ss_sleep); if (ret) @@ -6796,7 +6800,8 @@ static int msm_pcie_drv_suspend(struct msm_pcie_dev_t *pcie_dev, msm_pcie_vreg_deinit(pcie_dev); /* enable L1ss sleep if client allows it */ - if (!(options & MSM_PCIE_CONFIG_NO_L1SS_TO)) + if (!drv_info->l1ss_sleep_disable && + !(options & MSM_PCIE_CONFIG_NO_L1SS_TO)) msm_pcie_drv_send_rpmsg(pcie_dev, rpdev, &drv_info->drv_enable_l1ss_sleep);