From 31f1ba62914c0612d5b27cf3a0d448f52331399b Mon Sep 17 00:00:00 2001
From: Pankaj Gupta <gpankaj@qti.qualcomm.com>
Date: Mon, 25 Jan 2021 19:03:54 +0530
Subject: [PATCH] ARM: dts: qcom: Add GPU gaming bin support for Yupik

Add provider bindings in qfprom and consumer bindings for enabling
support to read the gaming bin fuse bit for Yupik GPU.

Change-Id: Id39af50bdc2c26eee0f9a0a48b8c18a36124b7c6
---
 qcom/yupik-gpu.dtsi | 4 ++--
 qcom/yupik.dtsi     | 5 +++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi
index 21701059f411..f6bb660a63ee 100644
--- a/qcom/yupik-gpu.dtsi
+++ b/qcom/yupik-gpu.dtsi
@@ -80,8 +80,8 @@
 			<0>,   /* Off */
 			<100>; /* On */
 
-		nvmem-cells = <&gpu_speed_bin>;
-		nvmem-cell-names = "speed_bin";
+		nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
+		nvmem-cell-names = "speed_bin", "gaming_bin";
 
 		qcom,gpu-mempools {
 			#address-cells = <1>;
diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi
index 29f77964dc3c..9bf7e1470090 100644
--- a/qcom/yupik.dtsi
+++ b/qcom/yupik.dtsi
@@ -3427,6 +3427,11 @@
 			bits = <5 8>;
 		};
 
+		gpu_gaming_bin: gpu_gaming_bin@1f5 {
+			reg = <0x1f5 0x1>;
+			bits = <5 1>;
+		};
+
 		feat_conf_m7: feat_conf_m7@6020 {
 			reg = <0x6020 0x4>;
 		};