From 0ff8097bc0f2b6f96b83ef81de567385228cc555 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 23 Apr 2020 23:45:59 +0530 Subject: [PATCH 1/3] clk: qcom: Add qcom implementation of qcom_clk_set_flags The qcom_clk_set_flags API would be used to set/clear the memory flags for the desired branches. Change-Id: I58b2347f63d382168b61dd04ead57ad114559eb2 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-branch.c | 55 ++++++++++++++++++++++++++++++++++- include/linux/clk/qcom.h | 12 +++++++- 2 files changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 5a29357997cc..ad6de4eebcca 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016-2020, The Linux Foundation. All rights reserved. */ #include @@ -11,6 +11,7 @@ #include #include #include +#include #include "clk-branch.h" #include "clk-debug.h" @@ -272,3 +273,55 @@ const struct clk_ops clk_branch_simple_ops = { .is_enabled = clk_is_enabled_regmap, }; EXPORT_SYMBOL_GPL(clk_branch_simple_ops); + +int qcom_clk_set_flags(struct clk *clk, unsigned long flags) +{ + struct clk_hw *hw; + struct clk_branch *br; + u32 cbcr_val = 0, cbcr_mask; + int ret; + + if (IS_ERR_OR_NULL(clk)) + return 0; + + hw = __clk_get_hw(clk); + if (IS_ERR_OR_NULL(hw)) + return -EINVAL; + + switch (flags) { + case CLKFLAG_PERIPH_OFF_SET: + cbcr_val = cbcr_mask = BIT(12); + break; + case CLKFLAG_PERIPH_OFF_CLEAR: + cbcr_mask = BIT(12); + break; + case CLKFLAG_RETAIN_PERIPH: + cbcr_val = cbcr_mask = BIT(13); + break; + case CLKFLAG_NORETAIN_PERIPH: + cbcr_mask = BIT(13); + break; + case CLKFLAG_RETAIN_MEM: + cbcr_val = cbcr_mask = BIT(14); + break; + case CLKFLAG_NORETAIN_MEM: + cbcr_mask = BIT(14); + break; + default: + return -EINVAL; + } + + br = to_clk_branch(hw); + ret = regmap_update_bits(br->clkr.regmap, br->halt_reg, cbcr_mask, + cbcr_val); + if (ret) + return ret; + + /* Make sure power is enabled/disabled before returning. */ + mb(); + + udelay(1); + + return 0; +} +EXPORT_SYMBOL(qcom_clk_set_flags); diff --git a/include/linux/clk/qcom.h b/include/linux/clk/qcom.h index 8e510b10b987..1ae1f16cca7a 100644 --- a/include/linux/clk/qcom.h +++ b/include/linux/clk/qcom.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ #ifndef __LINUX_CLK_QCOM_H_ @@ -8,6 +8,16 @@ #include +enum branch_mem_flags { + CLKFLAG_RETAIN_PERIPH, + CLKFLAG_NORETAIN_PERIPH, + CLKFLAG_RETAIN_MEM, + CLKFLAG_NORETAIN_MEM, + CLKFLAG_PERIPH_OFF_SET, + CLKFLAG_PERIPH_OFF_CLEAR, +}; + int qcom_clk_get_voltage(struct clk *clk, unsigned long rate); +int qcom_clk_set_flags(struct clk *clk, unsigned long flags); #endif /* __LINUX_CLK_QCOM_H_ */ From f708ea1445d423ae39698e537822807bdc7a1068 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 6 Jun 2020 15:51:48 +0530 Subject: [PATCH 2/3] clk: qcom: clk-branch: Add clock ops for Voltage voting In the cases where the branch clocks requires to vote on a voltage rail add the clock ops callbacks for the same. Change-Id: If7ffbc4fdda1fb71c1d097f56a5eb762859eb2c4 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-branch.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index ad6de4eebcca..2aab7777aaed 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -200,6 +200,10 @@ static void clk_branch2_init(struct clk_hw *hw) } const struct clk_ops clk_branch2_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_branch2_enable, .disable = clk_branch2_disable, .is_enabled = clk_is_enabled_regmap, From fbf704a3b0d14e16b6fa9887ed94e5bf754207cf Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 19 May 2020 13:08:23 +0530 Subject: [PATCH 3/3] bindings: clock: qcom: Update the GPU CC clock IDs Update the clock IDs which are required and supported from the Graphics clock controller on HOLI. Change-Id: I8f16d0ff3ed42500521c8384cd8272ce9d5b9d22 Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,gpucc-holi.h | 48 ++++++++------------- 1 file changed, 17 insertions(+), 31 deletions(-) diff --git a/include/dt-bindings/clock/qcom,gpucc-holi.h b/include/dt-bindings/clock/qcom,gpucc-holi.h index a233fc3081ff..9d7a282238e3 100644 --- a/include/dt-bindings/clock/qcom,gpucc-holi.h +++ b/include/dt-bindings/clock/qcom,gpucc-holi.h @@ -7,38 +7,24 @@ #define _DT_BINDINGS_CLK_QCOM_GPU_CC_HOLI_H /* GPU_CC clocks */ -#define GPU_CC_PLL0 0 -#define GPU_CC_PLL1 1 -#define GPU_CC_ACD_AHB_CLK 2 -#define GPU_CC_ACD_CXO_CLK 3 -#define GPU_CC_AHB_CLK 4 -#define GPU_CC_CRC_AHB_CLK 5 -#define GPU_CC_CX_APB_CLK 6 -#define GPU_CC_CX_GFX3D_CLK 7 -#define GPU_CC_CX_GFX3D_SLV_CLK 8 -#define GPU_CC_CX_GMU_CLK 9 -#define GPU_CC_CX_SNOC_DVM_CLK 10 -#define GPU_CC_CXO_AON_CLK 11 -#define GPU_CC_CXO_CLK 12 -#define GPU_CC_GMU_CLK_SRC 13 -#define GPU_CC_GX_CXO_CLK 14 -#define GPU_CC_GX_GFX3D_CLK 15 -#define GPU_CC_GX_GMU_CLK 16 -#define GPU_CC_GX_QDSS_TSCTR_CLK 17 -#define GPU_CC_GX_VSENSE_CLK 18 -#define GPU_CC_SLEEP_CLK 19 +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 /* GPU_CC power domains */ -#define CX_GDSC 0 -#define GX_GDSC 1 - -/* GPU_CC resets */ -#define GPUCC_GPU_CC_ACD_BCR 0 -#define GPUCC_GPU_CC_CX_BCR 1 -#define GPUCC_GPU_CC_GFX3D_AON_BCR 2 -#define GPUCC_GPU_CC_GMU_BCR 3 -#define GPUCC_GPU_CC_GX_BCR 4 -#define GPUCC_GPU_CC_RBCPR_BCR 5 -#define GPUCC_GPU_CC_XO_BCR 6 +#define CX_GDSC 0 +#define GX_GDSC 1 #endif