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ARM: Device-tree updates

Browse source 
Business as usual -- the bulk of our changes are to devicetree files
 with new hardware support, new SoCs and platforms, and new board types.
 
 New SoCs/platforms:
  - Raspberry Pi Compute Module (CM1) and IO board
  - i.MX6SSL from NXP
  - Renesas RZ/N1D SoC (R9A06G032), Dual Cortex-A7 with Ethernet, CAN and
    PLC interfaces
  - TI AM654 SoC, Quad Cortex-A53, safety subsystem with Cortex-R5
    controllers, communication and PRU subsystem and lots of other
    interfaces (PCIe, USB3, etc).
 
 New boards and systems:
  - Several Atmel at91-based boards from Laird
  - Marvell Armada388-based Helios4 board from SolidRun
  - Samsung Aires-based phones (s5pv210)
  - Allwinner A64-based Pinebook laptop
 
 In addition to the above, there's the usual amount of new devices
 described on existing platforms, fixes and tweaks and new minor variants
 of boards/platforms.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM device-tree updates from Olof Johansson:
 "Business as usual -- the bulk of our changes are to devicetree files
  with new hardware support, new SoCs and platforms, and new board
  types.

  New SoCs/platforms:
   - Raspberry Pi Compute Module (CM1) and IO board
   - i.MX6SSL from NXP
   - Renesas RZ/N1D SoC (R9A06G032), Dual Cortex-A7 with Ethernet, CAN
     and PLC interfaces
   - TI AM654 SoC, Quad Cortex-A53, safety subsystem with Cortex-R5
     controllers, communication and PRU subsystem and lots of other
     interfaces (PCIe, USB3, etc).

  New boards and systems:
   - Several Atmel at91-based boards from Laird
   - Marvell Armada388-based Helios4 board from SolidRun
   - Samsung Aires-based phones (s5pv210)
   - Allwinner A64-based Pinebook laptop

  In addition to the above, there's the usual amount of new devices
  described on existing platforms, fixes and tweaks and new minor
  variants of boards/platforms"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (478 commits)
  arm64: dts: sdm845: Add tsens nodes
  arm64: dts: msm8996: thermal: Initialise via DT and add second controller
  arm64: dts: sprd: Add one suspend timer
  arm64: dts: sprd: Add SC27XX ADC device
  arm64: dts: sprd: Add SC27XX eFuse device
  arm64: dts: sprd: Add SC27XX vibrator device
  arm64: dts: sprd: Add SC27XX breathing light controller device
  arm64: dts: meson-axg: add spdif-dit codec
  arm64: dts: meson-axg: add lineout codec
  arm64: dts: meson-axg: add linein codec
  arm64: dts: meson-axg: add tdm interfaces
  arm64: dts: meson-axg: add tdmout formatters
  arm64: dts: meson-axg: add tdmin formatters
  arm64: dts: meson-axg: add spdifout
  arm64: dts: rockchip: add led support for Firefly-RK3399
  arm64: dts: rockchip: remove deprecated Type-C PHY properties on rk3399
  arm64: dts: rockchip: add power button support for Firefly-RK3399
  ARM: dts: aspeed: Add coprocessor interrupt controller
  arm64: dts: meson-axg: add audio arb reset controller
  arm64: dts: meson-axg: add usb power regulator
  ...
This commit is contained in:
Linus Torvalds 2018-08-23 14:02:22 -07:00
commit 2f34a64aea
581 changed files with 22415 additions and 7095 deletions
Download patch file Download diff file Expand all files Collapse all files

95
include/dt-bindings/memory/mt2712-larb-port.h Normal file
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@ -0,0 +1,95 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#ifndef __DTS_IOMMU_PORT_MT2712_H
#define __DTS_IOMMU_PORT_MT2712_H
#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
#define M4U_LARB2_ID 2
#define M4U_LARB3_ID 3
#define M4U_LARB4_ID 4
#define M4U_LARB5_ID 5
#define M4U_LARB6_ID 6
#define M4U_LARB7_ID 7
#define M4U_LARB8_ID 8
#define M4U_LARB9_ID 9
/* larb0 */
#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7)
/* larb1 */
#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7)
#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9)
#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10)
/* larb2 */
#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0)
#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1)
#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2)
/* larb3 */
#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5)
#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6)
#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7)
#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8)
/* larb4 */
#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0)
#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1)
#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2)
#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3)
#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4)
#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5)
#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6)
/* larb5 */
#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0)
#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1)
#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2)
#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3)
/* larb6 */
#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0)
#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1)
#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2)
#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3)
/* larb7 */
#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0)
#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1)
/* larb8 */
#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0)
#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1)
#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2)
/* larb9 */
#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0)
#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1)
#endif