mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
main drm pull request for 4.12 kernel
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJZCTzvAAoJEAx081l5xIa+9kcQAJsQiija4/7QGx6IzakOMqjx WulJ3zYG/cU/HLwCBcuWRDF6wAj+7iWNeLCPmolHwEazcI8tQVdgMlWtbdMbDh8U ckzD3FBXsEVfIfab+u6tyoUkm3l/VDhMXbjkUK7NTo/+dkRqe5LuFfZPCGN09jft Y+5salkRXzDhXPSFsqmjfzhx1v7PTgf0a5HUenKWEWOv+sJQaW4/iPvcDSIcg5qR l9WjAqro1NpFYhUodnh6DkLeledL1U5whdtp/yvrUAck8y+WP/jwGYmQ7pZ0UkQm f0M3kV6K67ox9eqN++jsGX5o8sB1qF01Uh95kBAnyzYzsw4ZlMCx6pV7PDX+J88M UBNMEqX10hrLkNJA9lGjPWx+/6fudcwg9anKvTRO3Uyx7MbYoJAgjzAM+yBqqtV0 8Otxa4Bw0V2pmUD+0lqJDERRvE77VCXkLb8SaI5lQo0MHpQqT2cZA+GD+B+rZHO6 Ie5LDFY87vM2GG1IECufG+xOa3v6sn2FfQ1ouu1KNGKOAMBKcQCQyQx3kGVuNW2i HDACVXALJgXdRlVLm4jydOCZdRoguX7AWmRjtdwxgaO+lBcGfLhkXdjLQ7Ho+29p 32ArJfkZPfA53vMB6lHxAfbtrs1q2RzyVnPHj/KqeJnGZbABKTsF2HQ5BQc4Xq/J mqXoz6Oubdvk4Pwyx7Ne =UxFF -----END PGP SIGNATURE----- Merge tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux Pull drm u pdates from Dave Airlie: "This is the main drm pull request for v4.12. Apart from two fixes pulls, everything should have been in drm-next for at least 2 weeks. The biggest thing in here is AMD released the public headers for their upcoming VEGA GPUs. These as always are quite a sizeable chunk of header files. They've also added initial non-display support for those GPUs, though they aren't available in production yet. Otherwise it's pretty much normal. New bridge drivers: - megachips-stdpxxxx-ge-b850v3-fw LVDS->DP++ - generic LVDS bridge support. Core: - Displayport link train failure reporting to userspace - debugfs interface cleaned up - subsystem TODO in kerneldoc now - Extended fbdev support (flipping and vblank wait) - drm_platform removed - EDP CRC support in helper - HF-VSDB SCDC support in EDID parser - Lots of code cleanups and header extraction - Thunderbolt external GPU awareness - Atomic helper improvements - Documentation improvements panel: - Sitronix and Samsung new panel support amdgpu: - Preliminary vega10 support - Multi-level page table support - GPU sensor support for userspace - PRT support for sparse buffers - SR-IOV improvements - Non-contig VRAM CPU mapping i915: - Atomic modesetting enabled by default on Gen5+ - LSPCON improvements - Atomic state handling for cdclk - GPU reset improvements - In-kernel unit tests - Geminilake improvements and color manager support - Designware i2c fixes - vblank evasion improvements - Hotplug safe connector iterators - GVT scheduler QoS support - GVT Kabylake support nouveau: - Acceleration support for Pascal (GP10x). - Rearchitecture of code handling proprietary signed firmware - Fix GTX 970 with odd MMU configuration - GP10B support - GP107 acceleration support vmwgfx: - Atomic modesetting support for vmwgfx omapdrm: - Support for render nodes - Refactor omapdss code - Fix some probe ordering issues - Fix too dark RGB565 rendering sunxi: - prelim rework for multiple pipes. mali-dp: - Color management support - Plane scaling - Power management improvements imx-drm: - Prefetch Resolve Engine/Gasket on i.MX6QP - Deferred plane disabling - Separate alpha support mediatek: - Mediatek SoC MT2701 support rcar-du: - Gen3 HDMI support msm: - 4k support for newer chips - OPP bindings for gpu - prep work for per-process pagetables vc4: - HDMI audio support - fixes qxl: - minor fixes. dw-hdmi: - PHY improvements - CSC fixes - Amlogic GX SoC support" * tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux: (1778 commits) drm/nouveau/fb/gf100-: Fix 32 bit wraparound in new ram detection drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr() drm/nouveau/kms: Increase max retries in scanout position queries. drm/nouveau/bios/bitP: check that table is long enough for optional pointers drm/nouveau/fifo/nv40: no ctxsw for pre-nv44 mpeg engine drm: mali-dp: use div_u64 for expensive 64-bit divisions drm/i915: Confirm the request is still active before adding it to the await drm/i915: Avoid busy-spinning on VLV_GLTC_PW_STATUS mmio drm/i915/selftests: Allocate inode/file dynamically drm/i915: Fix system hang with EI UP masked on Haswell drm/i915: checking for NULL instead of IS_ERR() in mock selftests drm/i915: Perform link quality check unconditionally during long pulse drm/i915: Fix use after free in lpe_audio_platdev_destroy() drm/i915: Use the right mapping_gfp_mask for final shmem allocation drm/i915: Make legacy cursor updates more unsynced drm/i915: Apply a cond_resched() to the saturated signaler drm/i915: Park the signaler before sleeping drm: mali-dp: Check the mclk rate and allow up/down scaling drm: mali-dp: Enable image enhancement when scaling drm: mali-dp: Add plane upscaling support ...
This commit is contained in:
Linus Torvalds
commit
2f34c1231b
1060 changed files with 456334 additions and 27130 deletions
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@ -0,0 +1,111 @@
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Amlogic specific extensions to the Synopsys Designware HDMI Controller
|
||||
======================================================================
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||||
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||||
The Amlogic Meson Synopsys Designware Integration is composed of :
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- A Synopsys DesignWare HDMI Controller IP
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||||
- A TOP control block controlling the Clocks and PHY
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- A custom HDMI PHY in order to convert video to TMDS signal
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___________________________________
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| HDMI TOP |<= HPD
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||||
|___________________________________|
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||||
| | |
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||||
| Synopsys HDMI | HDMI PHY |=> TMDS
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| Controller |________________|
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|___________________________________|<=> DDC
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The HDMI TOP block only supports HPD sensing.
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The Synopsys HDMI Controller interrupt is routed through the
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TOP Block interrupt.
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Communication to the TOP Block and the Synopsys HDMI Controller is done
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||||
via a pair of dedicated addr+read/write registers.
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||||
The HDMI PHY is configured by registers in the HHI register block.
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|
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Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux
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selects either the ENCI encoder for the 576i or 480i formats or the ENCP
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encoder for all the other formats including interlaced HD formats.
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|
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The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
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DVI timings for the HDMI controller.
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|
||||
Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
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HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
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audio source interfaces.
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Required properties:
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
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- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
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followed by the common "amlogic,meson-gx-dw-hdmi"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The HDMI interrupt number
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- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
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and the Amlogic Meson venci clocks as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt,
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the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci"
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- resets, resets-names: must have the phandles to the HDMI apb, glue and phy
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resets as described in :
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Documentation/devicetree/bindings/reset/reset.txt,
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the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"
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Required nodes:
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The connections to the HDMI ports are modeled using the OF graph
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bindings specified in Documentation/devicetree/bindings/graph.txt.
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|
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The following table lists for each supported model the port number
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corresponding to each HDMI output and input.
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Port 0 Port 1
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-----------------------------------------
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S905 (GXBB) VENC Input TMDS Output
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S905X (GXL) VENC Input TMDS Output
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S905D (GXL) VENC Input TMDS Output
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S912 (GXM) VENC Input TMDS Output
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|
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Example:
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_tmds_out>;
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};
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};
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};
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hdmi_tx: hdmi-tx@c883a000 {
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compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
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reg = <0x0 0xc883a000 0x0 0x1c>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
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resets = <&reset RESET_HDMITX_CAPB3>,
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<&reset RESET_HDMI_SYSTEM_RESET>,
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<&reset RESET_HDMI_TX>;
|
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reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
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clocks = <&clkc CLKID_HDMI_PCLK>,
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<&clkc CLKID_CLK81>,
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<&clkc CLKID_GCLK_VENCI_INT0>;
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clock-names = "isfr", "iahb", "venci";
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#address-cells = <1>;
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#size-cells = <0>;
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/* VPU VENC Input */
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hdmi_tx_venc_port: port@0 {
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reg = <0>;
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|
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hdmi_tx_in: endpoint {
|
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remote-endpoint = <&hdmi_tx_out>;
|
||||
};
|
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};
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|
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/* TMDS Output */
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hdmi_tx_tmds_port: port@1 {
|
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reg = <1>;
|
||||
|
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hdmi_tx_tmds_out: endpoint {
|
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remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
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||||
|
|
@ -34,6 +34,9 @@ Optional properties for HDMI:
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|||
- hpd-gpios: The GPIO pin for HDMI hotplug detect (if it doesn't appear
|
||||
as an interrupt/status bit in the HDMI controller
|
||||
itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
|
||||
- dmas: Should contain one entry pointing to the DMA channel used to
|
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transfer audio data
|
||||
- dma-names: Should contain "audio-rx"
|
||||
|
||||
Required properties for DPI:
|
||||
- compatible: Should be "brcm,bcm2835-dpi"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,64 @@
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|||
Parallel to LVDS Encoder
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||||
------------------------
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||||
|
||||
This binding supports the parallel to LVDS encoders that don't require any
|
||||
configuration.
|
||||
|
||||
LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
|
||||
incompatible data link layers have been used over time to transmit image data
|
||||
to LVDS panels. This binding targets devices compatible with the following
|
||||
specifications only.
|
||||
|
||||
[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
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1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
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[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
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Semiconductor
|
||||
[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
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Electronics Standards Association (VESA)
|
||||
|
||||
Those devices have been marketed under the FPD-Link and FlatLink brand names
|
||||
among others.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be "lvds-encoder"
|
||||
|
||||
Required nodes:
|
||||
|
||||
This device has two video ports. Their connections are modeled using the OF
|
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graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
- Video port 0 for parallel input
|
||||
- Video port 1 for LVDS output
|
||||
|
||||
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Example
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-------
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lvds-encoder {
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compatible = "lvds-encoder";
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||||
#address-cells = <1>;
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#size-cells = <0>;
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|
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ports {
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#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
|
||||
port@0 {
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reg = <0>;
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||||
|
||||
lvds_enc_in: endpoint {
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remote-endpoint = <&display_out_rgb>;
|
||||
};
|
||||
};
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||||
|
||||
port@1 {
|
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reg = <1>;
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||||
|
||||
lvds_enc_out: endpoint {
|
||||
remote-endpoint = <&lvds_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
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||||
|
|
@ -0,0 +1,94 @@
|
|||
Drivers for the second video output of the GE B850v3:
|
||||
STDP4028-ge-b850v3-fw bridges (LVDS-DP)
|
||||
STDP2690-ge-b850v3-fw bridges (DP-DP++)
|
||||
|
||||
The video processing pipeline on the second output on the GE B850v3:
|
||||
|
||||
Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
|
||||
|
||||
Each bridge has a dedicated flash containing firmware for supporting the custom
|
||||
design. The result is that, in this design, neither the STDP4028 nor the
|
||||
STDP2690 behave as the stock bridges would. The compatible strings include the
|
||||
suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with
|
||||
the firmware specific for the GE B850v3.
|
||||
|
||||
The hardware do not provide control over the video processing pipeline, as the
|
||||
two bridges behaves as a single one. The only interfaces exposed by the
|
||||
hardware are EDID, HPD, and interrupts.
|
||||
|
||||
stdp4028-ge-b850v3-fw required properties:
|
||||
- compatible : "megachips,stdp4028-ge-b850v3-fw"
|
||||
- reg : I2C bus address
|
||||
- interrupt-parent : phandle of the interrupt controller that services
|
||||
interrupts to the device
|
||||
- interrupts : one interrupt should be described here, as in
|
||||
<0 IRQ_TYPE_LEVEL_HIGH>
|
||||
- ports : One input port(reg = <0>) and one output port(reg = <1>)
|
||||
|
||||
stdp2690-ge-b850v3-fw required properties:
|
||||
compatible : "megachips,stdp2690-ge-b850v3-fw"
|
||||
- reg : I2C bus address
|
||||
- ports : One input port(reg = <0>) and one output port(reg = <1>)
|
||||
|
||||
Example:
|
||||
|
||||
&mux2_i2c2 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
stdp4028@73 {
|
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compatible = "megachips,stdp4028-ge-b850v3-fw";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
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reg = <0x73>;
|
||||
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
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ports {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
stdp4028_in: endpoint {
|
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remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
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stdp4028_out: endpoint {
|
||||
remote-endpoint = <&stdp2690_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stdp2690@72 {
|
||||
compatible = "megachips,stdp2690-ge-b850v3-fw";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0x72>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
stdp2690_in: endpoint {
|
||||
remote-endpoint = <&stdp4028_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
stdp2690_out: endpoint {
|
||||
/* Connector for external display */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
Renesas Gen3 DWC HDMI TX Encoder
|
||||
================================
|
||||
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||
following device-specific properties.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Shall contain one or more of
|
||||
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
|
||||
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
|
||||
|
||||
When compatible with generic versions, nodes must list the SoC-specific
|
||||
version corresponding to the platform first, followed by the
|
||||
family-specific version.
|
||||
|
||||
- reg: See dw_hdmi.txt.
|
||||
- interrupts: HDMI interrupt number
|
||||
- clocks: See dw_hdmi.txt.
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
|
||||
corresponding to the video input of the controller and one port numbered 1
|
||||
corresponding to its HDMI output. Each port shall have a single endpoint.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- power-domains: Shall reference the power domain that contains the DWC HDMI,
|
||||
if any.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
hdmi0: hdmi0@fead0000 {
|
||||
compatible = "renesas,r8a7795-dw-hdmi";
|
||||
reg = <0 0xfead0000 0 0x10000>;
|
||||
interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
|
||||
clock-names = "iahb", "isfr";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dw_hdmi0_in: endpoint {
|
||||
remote-endpoint = <&du_out_hdmi0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi0-out {
|
||||
compatible = "hdmi-connector";
|
||||
label = "HDMI0 OUT";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi0_con: endpoint {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -21,13 +21,19 @@ Freescale i.MX IPUv3
|
|||
====================
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,<chip>-ipu"
|
||||
- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
|
||||
- imx51
|
||||
- imx53
|
||||
- imx6q
|
||||
- imx6qp
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- interrupts: Should contain sync interrupt and error interrupt,
|
||||
in this order.
|
||||
- resets: phandle pointing to the system reset controller and
|
||||
reset line index, see reset/fsl,imx-src.txt for details
|
||||
Additional required properties for fsl,imx6qp-ipu:
|
||||
- fsl,prg: phandle to prg node associated with this IPU instance
|
||||
Optional properties:
|
||||
- port@[0-3]: Port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
|
|
@ -53,6 +59,57 @@ ipu: ipu@18000000 {
|
|||
};
|
||||
};
|
||||
|
||||
Freescale i.MX PRE (Prefetch Resolve Engine)
|
||||
============================================
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "fsl,imx6qp-pre"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- clocks : phandle to the PRE axi clock input, as described
|
||||
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
|
||||
Documentation/devicetree/bindings/clock/imx6q-clock.txt.
|
||||
- clock-names: should be "axi"
|
||||
- interrupts: should contain the PRE interrupt
|
||||
- fsl,iram: phandle pointing to the mmio-sram device node, that should be
|
||||
used for the PRE SRAM double buffer.
|
||||
|
||||
example:
|
||||
|
||||
pre@21c8000 {
|
||||
compatible = "fsl,imx6qp-pre";
|
||||
reg = <0x021c8000 0x1000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRE0>;
|
||||
clock-names = "axi";
|
||||
fsl,iram = <&ocram2>;
|
||||
};
|
||||
|
||||
Freescale i.MX PRG (Prefetch Resolve Gasket)
|
||||
============================================
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "fsl,imx6qp-prg"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- clocks : phandles to the PRG ipg and axi clock inputs, as described
|
||||
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
|
||||
Documentation/devicetree/bindings/clock/imx6q-clock.txt.
|
||||
- clock-names: should be "ipg" and "axi"
|
||||
- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
|
||||
PRE as the first entry and the muxable PREs following.
|
||||
|
||||
example:
|
||||
|
||||
prg@21cc000 {
|
||||
compatible = "fsl,imx6qp-prg";
|
||||
reg = <0x021cc000 0x1000>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
|
||||
<&clks IMX6QDL_CLK_PRG0_AXI>;
|
||||
clock-names = "ipg", "axi";
|
||||
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
|
||||
};
|
||||
|
||||
Parallel display support
|
||||
========================
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ Required properties (all function blocks):
|
|||
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
|
||||
"mediatek,<chip>-disp-mutex" - display mutex
|
||||
"mediatek,<chip>-disp-od" - overdrive
|
||||
the supported chips are mt2701 and mt8173.
|
||||
- reg: Physical base address and length of the function block register space
|
||||
- interrupts: The interrupt signal from the function block (required, except for
|
||||
merge and split function blocks).
|
||||
|
|
@ -54,6 +55,7 @@ Required properties (DMA function blocks):
|
|||
"mediatek,<chip>-disp-ovl"
|
||||
"mediatek,<chip>-disp-rdma"
|
||||
"mediatek,<chip>-disp-wdma"
|
||||
the supported chips are mt2701 and mt8173.
|
||||
- larb: Should contain a phandle pointing to the local arbiter device as defined
|
||||
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
|
||||
- iommus: Should point to the respective IOMMU block with master port as
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ channel output.
|
|||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dsi"
|
||||
the supported chips are mt2701 and mt8173.
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
|
|
@ -25,6 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
|
|||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-mipi-tx"
|
||||
the supported chips are mt2701 and mt8173.
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: PLL reference clock
|
||||
- clock-output-names: name of the output clock line to the DSI encoder
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "ampire,am-480272h3tmqw-t01h"
|
||||
|
||||
Optional properties:
|
||||
- power-supply: regulator to provide the supply voltage
|
||||
- enable-gpios: GPIO pin to enable or disable the panel
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
Optional nodes:
|
||||
- Video port for RGB input.
|
||||
|
||||
Example:
|
||||
panel_rgb: panel-rgb {
|
||||
compatible = "ampire,am-480272h3tmqw-t01h";
|
||||
enable-gpios = <&gpioa 8 1>;
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <&controller_out_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
Mitsubishi AA204XD12 LVDS Display Panel
|
||||
=======================================
|
||||
|
||||
The AA104XD12 is a 10.4" XGA TFT-LCD display panel.
|
||||
|
||||
These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
|
||||
with the following device-specific properties.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Shall contain "mitsubishi,aa121td01" and "panel-lvds", in that
|
||||
order.
|
||||
- vcc-supply: Reference to the regulator powering the panel VCC pins.
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
panel {
|
||||
compatible = "mitsubishi,aa104xd12", "panel-lvds";
|
||||
vcc-supply = <&vcc_3v3>;
|
||||
|
||||
width-mm = <210>;
|
||||
height-mm = <158>;
|
||||
|
||||
data-mapping = "jeida-24";
|
||||
|
||||
panel-timing {
|
||||
/* 1024x768 @65Hz */
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hsync-len = <136>;
|
||||
hfront-porch = <20>;
|
||||
hback-porch = <160>;
|
||||
vfront-porch = <3>;
|
||||
vback-porch = <29>;
|
||||
vsync-len = <6>;
|
||||
};
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds_encoder>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
Mitsubishi AA121TD01 LVDS Display Panel
|
||||
=======================================
|
||||
|
||||
The AA121TD01 is a 12.1" WXGA TFT-LCD display panel.
|
||||
|
||||
These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
|
||||
with the following device-specific properties.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Shall contain "mitsubishi,aa121td01" and "panel-lvds", in that
|
||||
order.
|
||||
- vcc-supply: Reference to the regulator powering the panel VCC pins.
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
panel {
|
||||
compatible = "mitsubishi,aa121td01", "panel-lvds";
|
||||
vcc-supply = <&vcc_3v3>;
|
||||
|
||||
width-mm = <261>;
|
||||
height-mm = <163>;
|
||||
|
||||
data-mapping = "jeida-24";
|
||||
|
||||
panel-timing {
|
||||
/* 1280x800 @60Hz */
|
||||
clock-frequency = <71000000>;
|
||||
hactive = <1280>;
|
||||
vactive = <800>;
|
||||
hsync-len = <70>;
|
||||
hfront-porch = <20>;
|
||||
hback-porch = <70>;
|
||||
vsync-len = <5>;
|
||||
vfront-porch = <3>;
|
||||
vback-porch = <15>;
|
||||
};
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds_encoder>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
Common Properties for Display Panel
|
||||
===================================
|
||||
|
||||
This document defines device tree properties common to several classes of
|
||||
display panels. It doesn't constitue a device tree binding specification by
|
||||
itself but is meant to be referenced by device tree bindings.
|
||||
|
||||
When referenced from panel device tree bindings the properties defined in this
|
||||
document are defined as follows. The panel device tree bindings are
|
||||
responsible for defining whether each property is required or optional.
|
||||
|
||||
|
||||
Descriptive Properties
|
||||
----------------------
|
||||
|
||||
- width-mm,
|
||||
- height-mm: The width-mm and height-mm specify the width and height of the
|
||||
physical area where images are displayed. These properties are expressed in
|
||||
millimeters and rounded to the closest unit.
|
||||
|
||||
- label: The label property specifies a symbolic name for the panel as a
|
||||
string suitable for use by humans. It typically contains a name inscribed on
|
||||
the system (e.g. as an affixed label) or specified in the system's
|
||||
documentation (e.g. in the user's manual).
|
||||
|
||||
If no such name exists, and unless the property is mandatory according to
|
||||
device tree bindings, it shall rather be omitted than constructed of
|
||||
non-descriptive information. For instance an LCD panel in a system that
|
||||
contains a single panel shall not be labelled "LCD" if that name is not
|
||||
inscribed on the system or used in a descriptive fashion in system
|
||||
documentation.
|
||||
|
||||
|
||||
Display Timings
|
||||
---------------
|
||||
|
||||
- panel-timing: Most display panels are restricted to a single resolution and
|
||||
require specific display timings. The panel-timing subnode expresses those
|
||||
timings as specified in the timing subnode section of the display timing
|
||||
bindings defined in
|
||||
Documentation/devicetree/bindings/display/display-timing.txt.
|
||||
|
||||
|
||||
Connectivity
|
||||
------------
|
||||
|
||||
- ports: Panels receive video data through one or multiple connections. While
|
||||
the nature of those connections is specific to the panel type, the
|
||||
connectivity is expressed in a standard fashion using ports as specified in
|
||||
the device graph bindings defined in
|
||||
Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
- ddc-i2c-bus: Some panels expose EDID information through an I2C-compatible
|
||||
bus such as DDC2 or E-DDC. For such panels the ddc-i2c-bus contains a
|
||||
phandle to the system I2C controller connected to that bus.
|
||||
|
||||
|
||||
Control I/Os
|
||||
------------
|
||||
|
||||
Many display panels can be controlled through pins driven by GPIOs. The nature
|
||||
and timing of those control signals are device-specific and left for panel
|
||||
device tree bindings to specify. The following GPIO specifiers can however be
|
||||
used for panels that implement compatible control signals.
|
||||
|
||||
- enable-gpios: Specifier for a GPIO connected to the panel enable control
|
||||
signal. The enable signal is active high and enables operation of the panel.
|
||||
This property can also be used for panels implementing an active low power
|
||||
down signal, which is a negated version of the enable signal. Active low
|
||||
enable signals (or active high power down signals) can be supported by
|
||||
inverting the GPIO specifier polarity flag.
|
||||
|
||||
Note that the enable signal control panel operation only and must not be
|
||||
confused with a backlight enable signal.
|
||||
|
||||
- reset-gpios: Specifier for a GPIO coonnected to the panel reset control
|
||||
signal. The reset signal is active low and resets the panel internal logic
|
||||
while active. Active high reset signals can be supported by inverting the
|
||||
GPIO specifier polarity flag.
|
||||
|
||||
|
||||
Backlight
|
||||
---------
|
||||
|
||||
Most display panels include a backlight. Some of them also include a backlight
|
||||
controller exposed through a control bus such as I2C or DSI. Others expose
|
||||
backlight control through GPIO, PWM or other signals connected to an external
|
||||
backlight controller.
|
||||
|
||||
- backlight: For panels whose backlight is controlled by an external backlight
|
||||
controller, this property contains a phandle that references the controller.
|
||||
|
|
@ -9,6 +9,7 @@ Optional properties:
|
|||
- enable-gpios: panel enable gpio
|
||||
- reset-gpios: GPIO to control the RESET pin
|
||||
- vcc-supply: phandle of regulator that will be used to enable power to the display
|
||||
- backlight: phandle of the backlight device
|
||||
|
||||
Required nodes:
|
||||
- "panel-timing" containing video timings
|
||||
|
|
@ -22,6 +23,8 @@ lcd0: display@0 {
|
|||
compatible = "samsung,lte430wq-f0c", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
backlight = <&backlight>;
|
||||
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
|
|
|
|||
120
Documentation/devicetree/bindings/display/panel/panel-lvds.txt
Normal file
120
Documentation/devicetree/bindings/display/panel/panel-lvds.txt
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
LVDS Display Panel
|
||||
==================
|
||||
|
||||
LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
|
||||
incompatible data link layers have been used over time to transmit image data
|
||||
to LVDS panels. This bindings supports display panels compatible with the
|
||||
following specifications.
|
||||
|
||||
[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
|
||||
1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
|
||||
[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
|
||||
Semiconductor
|
||||
[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
|
||||
Electronics Standards Association (VESA)
|
||||
|
||||
Device compatible with those specifications have been marketed under the
|
||||
FPD-Link and FlatLink brands.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Shall contain "panel-lvds" in addition to a mandatory
|
||||
panel-specific compatible string defined in individual panel bindings. The
|
||||
"panel-lvds" value shall never be used on its own.
|
||||
- width-mm: See panel-common.txt.
|
||||
- height-mm: See panel-common.txt.
|
||||
- data-mapping: The color signals mapping order, "jeida-18", "jeida-24"
|
||||
or "vesa-24".
|
||||
|
||||
Optional properties:
|
||||
|
||||
- label: See panel-common.txt.
|
||||
- gpios: See panel-common.txt.
|
||||
- backlight: See panel-common.txt.
|
||||
- data-mirror: If set, reverse the bit order described in the data mappings
|
||||
below on all data lanes, transmitting bits for slots 6 to 0 instead of
|
||||
0 to 6.
|
||||
|
||||
Required nodes:
|
||||
|
||||
- panel-timing: See panel-common.txt.
|
||||
- ports: See panel-common.txt. These bindings require a single port subnode
|
||||
corresponding to the panel LVDS input.
|
||||
|
||||
|
||||
LVDS data mappings are defined as follows.
|
||||
|
||||
- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
|
||||
[VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
|
||||
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
|
||||
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
|
||||
|
||||
- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
|
||||
specifications. Data are transferred as follows on 4 LVDS lanes.
|
||||
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
|
||||
DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
|
||||
DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
|
||||
|
||||
- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
|
||||
Data are transferred as follows on 4 LVDS lanes.
|
||||
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
|
||||
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
|
||||
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
|
||||
|
||||
Control signals are mapped as follows.
|
||||
|
||||
CTL0: HSync
|
||||
CTL1: VSync
|
||||
CTL2: Data Enable
|
||||
CTL3: 0
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
panel {
|
||||
compatible = "mitsubishi,aa121td01", "panel-lvds";
|
||||
|
||||
width-mm = <261>;
|
||||
height-mm = <163>;
|
||||
|
||||
data-mapping = "jeida-24";
|
||||
|
||||
panel-timing {
|
||||
/* 1280x800 @60Hz */
|
||||
clock-frequency = <71000000>;
|
||||
hactive = <1280>;
|
||||
vactive = <800>;
|
||||
hsync-len = <70>;
|
||||
hfront-porch = <20>;
|
||||
hback-porch = <70>;
|
||||
vsync-len = <5>;
|
||||
vfront-porch = <3>;
|
||||
vback-porch = <15>;
|
||||
};
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds_encoder>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
Samsung S6E3HA2 5.7" 1440x2560 AMOLED panel
|
||||
|
||||
Required properties:
|
||||
- compatible: "samsung,s6e3ha2"
|
||||
- reg: the virtual channel number of a DSI peripheral
|
||||
- vdd3-supply: I/O voltage supply
|
||||
- vci-supply: voltage supply for analog circuits
|
||||
- reset-gpios: a GPIO spec for the reset pin (active low)
|
||||
- enable-gpios: a GPIO spec for the panel enable pin (active high)
|
||||
|
||||
Optional properties:
|
||||
- te-gpios: a GPIO spec for the tearing effect synchronization signal
|
||||
gpio pin (active high)
|
||||
|
||||
Example:
|
||||
&dsi {
|
||||
...
|
||||
|
||||
panel@0 {
|
||||
compatible = "samsung,s6e3ha2";
|
||||
reg = <0>;
|
||||
vdd3-supply = <&ldo27_reg>;
|
||||
vci-supply = <&ldo28_reg>;
|
||||
reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
|
||||
enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
|
||||
te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
Sitronix ST7789V RGB panel with SPI control bus
|
||||
|
||||
Required properties:
|
||||
- compatible: "sitronix,st7789v"
|
||||
- reg: Chip select of the panel on the SPI bus
|
||||
- reset-gpios: a GPIO phandle for the reset pin
|
||||
- power-supply: phandle of the regulator that provides the supply voltage
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle to the backlight used
|
||||
|
||||
The generic bindings for the SPI slaves documented in [1] also applies
|
||||
|
||||
The device node can contain one 'port' child node with one child
|
||||
'endpoint' node, according to the bindings defined in [2]. This
|
||||
node should describe panel's video bus.
|
||||
|
||||
[1]: Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
[2]: Documentation/devicetree/bindings/graph.txt
|
||||
|
||||
Example:
|
||||
|
||||
panel@0 {
|
||||
compatible = "sitronix,st7789v";
|
||||
reg = <0>;
|
||||
reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&pwm_bl>;
|
||||
spi-max-frequency = <100000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
|
||||
port {
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&tcon0_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "winstar,wf35ltiacd"
|
||||
- power-supply: regulator to provide the VCC supply voltage (3.3 volts)
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
||||
Example:
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&hlcdc_pwm 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 31 63 95 127 159 191 223 255>;
|
||||
default-brightness-level = <191>;
|
||||
power-supply = <&bl_reg>;
|
||||
};
|
||||
|
||||
bl_reg: backlight_regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "backlight-power-supply";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "winstar,wf35ltiacd", "simple-panel";
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&panel_reg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&hlcdc_panel_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel_reg: panel_regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "panel-power-supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
|
@ -36,6 +36,9 @@ Required Properties:
|
|||
When supplied they must be named "dclkin.x" with "x" being the input
|
||||
clock numerical index.
|
||||
|
||||
- vsps: A list of phandles to the VSP nodes that handle the memory
|
||||
interfaces for the DU channels.
|
||||
|
||||
Required nodes:
|
||||
|
||||
The connections to the DU output video ports are modeled using the OF graph
|
||||
|
|
|
|||
|
|
@ -5,16 +5,24 @@ Required properties:
|
|||
- #address-cells: Should be <1>.
|
||||
- #size-cells: Should be <0>.
|
||||
- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
|
||||
"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
|
||||
- reg: Represent the physical address range of the controller.
|
||||
- interrupts: Represent the controller's interrupt to the CPU(s).
|
||||
- clocks, clock-names: Phandles to the controller's pll reference
|
||||
clock(ref) and APB clock(pclk), as described in [1].
|
||||
clock(ref) and APB clock(pclk). For RK3399, a phy config clock
|
||||
(phy_cfg) and a grf clock(grf) are required. As described in [1].
|
||||
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
|
||||
- ports: contain a port node with endpoint definitions as defined in [2].
|
||||
For vopb,set the reg = <0> and set the reg = <1> for vopl.
|
||||
|
||||
Optional properties:
|
||||
- power-domains: a phandle to mipi dsi power domain node.
|
||||
- resets: list of phandle + reset specifier pairs, as described in [3].
|
||||
- reset-names: string reset name, must be "apb".
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[3] Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
Example:
|
||||
mipi_dsi: mipi@ff960000 {
|
||||
|
|
@ -25,6 +33,8 @@ Example:
|
|||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
|
||||
clock-names = "ref", "pclk";
|
||||
resets = <&cru SRST_MIPIDSI0>;
|
||||
reset-names = "apb";
|
||||
rockchip,grf = <&grf>;
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -179,6 +179,7 @@ maxim Maxim Integrated Products
|
|||
mcube mCube
|
||||
meas Measurement Specialties
|
||||
mediatek MediaTek Inc.
|
||||
megachips MegaChips
|
||||
melexis Melexis N.V.
|
||||
melfas MELFAS Inc.
|
||||
memsic MEMSIC Inc.
|
||||
|
|
@ -337,6 +338,7 @@ wd Western Digital Corp.
|
|||
wetek WeTek Electronics, limited.
|
||||
wexler Wexler
|
||||
winbond Winbond Electronics corp.
|
||||
winstar Winstar Display Corp.
|
||||
wlf Wolfson Microelectronics
|
||||
wm Wondermedia Technologies, Inc.
|
||||
x-powers X-Powers
|
||||
|
|
|
|||
Loading…
Reference in a new issue